xref: /openbmc/qemu/hw/pci/pcie_host.c (revision 502d0f36)
1 /*
2  * pcie_host.c
3  * utility functions for pci express host bridge.
4  *
5  * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
6  *                    VA Linux Systems Japan K.K.
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12 
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17 
18  * You should have received a copy of the GNU General Public License along
19  * with this program; if not, see <http://www.gnu.org/licenses/>.
20  */
21 
22 #include "qemu/osdep.h"
23 #include "hw/hw.h"
24 #include "hw/pci/pci.h"
25 #include "hw/pci/pcie_host.h"
26 #include "exec/address-spaces.h"
27 
28 /* a helper function to get a PCIDevice for a given mmconfig address */
29 static inline PCIDevice *pcie_dev_find_by_mmcfg_addr(PCIBus *s,
30                                                      uint32_t mmcfg_addr)
31 {
32     return pci_find_device(s, PCIE_MMCFG_BUS(mmcfg_addr),
33                            PCIE_MMCFG_DEVFN(mmcfg_addr));
34 }
35 
36 static void pcie_mmcfg_data_write(void *opaque, hwaddr mmcfg_addr,
37                                   uint64_t val, unsigned len)
38 {
39     PCIExpressHost *e = opaque;
40     PCIBus *s = e->pci.bus;
41     PCIDevice *pci_dev = pcie_dev_find_by_mmcfg_addr(s, mmcfg_addr);
42     uint32_t addr;
43     uint32_t limit;
44 
45     if (!pci_dev) {
46         return;
47     }
48     addr = PCIE_MMCFG_CONFOFFSET(mmcfg_addr);
49     limit = pci_config_size(pci_dev);
50     if (limit <= addr) {
51         /* conventional pci device can be behind pcie-to-pci bridge.
52            256 <= addr < 4K has no effects. */
53         return;
54     }
55     pci_host_config_write_common(pci_dev, addr, limit, val, len);
56 }
57 
58 static uint64_t pcie_mmcfg_data_read(void *opaque,
59                                      hwaddr mmcfg_addr,
60                                      unsigned len)
61 {
62     PCIExpressHost *e = opaque;
63     PCIBus *s = e->pci.bus;
64     PCIDevice *pci_dev = pcie_dev_find_by_mmcfg_addr(s, mmcfg_addr);
65     uint32_t addr;
66     uint32_t limit;
67 
68     if (!pci_dev) {
69         return ~0x0;
70     }
71     addr = PCIE_MMCFG_CONFOFFSET(mmcfg_addr);
72     limit = pci_config_size(pci_dev);
73     if (limit <= addr) {
74         /* conventional pci device can be behind pcie-to-pci bridge.
75            256 <= addr < 4K has no effects. */
76         return ~0x0;
77     }
78     return pci_host_config_read_common(pci_dev, addr, limit, len);
79 }
80 
81 static const MemoryRegionOps pcie_mmcfg_ops = {
82     .read = pcie_mmcfg_data_read,
83     .write = pcie_mmcfg_data_write,
84     .endianness = DEVICE_LITTLE_ENDIAN,
85 };
86 
87 static void pcie_host_init(Object *obj)
88 {
89     PCIExpressHost *e = PCIE_HOST_BRIDGE(obj);
90 
91     e->base_addr = PCIE_BASE_ADDR_UNMAPPED;
92     memory_region_init_io(&e->mmio, OBJECT(e), &pcie_mmcfg_ops, e, "pcie-mmcfg-mmio",
93                           PCIE_MMCFG_SIZE_MAX);
94 }
95 
96 void pcie_host_mmcfg_unmap(PCIExpressHost *e)
97 {
98     if (e->base_addr != PCIE_BASE_ADDR_UNMAPPED) {
99         memory_region_del_subregion(get_system_memory(), &e->mmio);
100         e->base_addr = PCIE_BASE_ADDR_UNMAPPED;
101     }
102 }
103 
104 void pcie_host_mmcfg_init(PCIExpressHost *e, uint32_t size)
105 {
106     assert(!(size & (size - 1)));       /* power of 2 */
107     assert(size >= PCIE_MMCFG_SIZE_MIN);
108     assert(size <= PCIE_MMCFG_SIZE_MAX);
109     e->size = size;
110     memory_region_set_size(&e->mmio, e->size);
111 }
112 
113 void pcie_host_mmcfg_map(PCIExpressHost *e, hwaddr addr,
114                          uint32_t size)
115 {
116     pcie_host_mmcfg_init(e, size);
117     e->base_addr = addr;
118     memory_region_add_subregion(get_system_memory(), e->base_addr, &e->mmio);
119 }
120 
121 void pcie_host_mmcfg_update(PCIExpressHost *e,
122                             int enable,
123                             hwaddr addr,
124                             uint32_t size)
125 {
126     memory_region_transaction_begin();
127     pcie_host_mmcfg_unmap(e);
128     if (enable) {
129         pcie_host_mmcfg_map(e, addr, size);
130     }
131     memory_region_transaction_commit();
132 }
133 
134 static const TypeInfo pcie_host_type_info = {
135     .name = TYPE_PCIE_HOST_BRIDGE,
136     .parent = TYPE_PCI_HOST_BRIDGE,
137     .abstract = true,
138     .instance_size = sizeof(PCIExpressHost),
139     .instance_init = pcie_host_init,
140 };
141 
142 static void pcie_host_register_types(void)
143 {
144     type_register_static(&pcie_host_type_info);
145 }
146 
147 type_init(pcie_host_register_types)
148