xref: /openbmc/qemu/hw/pci/pcie_host.c (revision 21f5826a)
1 /*
2  * pcie_host.c
3  * utility functions for pci express host bridge.
4  *
5  * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
6  *                    VA Linux Systems Japan K.K.
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12 
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17 
18  * You should have received a copy of the GNU General Public License along
19  * with this program; if not, see <http://www.gnu.org/licenses/>.
20  */
21 
22 #include "hw/hw.h"
23 #include "hw/pci/pci.h"
24 #include "hw/pci/pcie_host.h"
25 #include "exec/address-spaces.h"
26 
27 /* a helper function to get a PCIDevice for a given mmconfig address */
28 static inline PCIDevice *pcie_dev_find_by_mmcfg_addr(PCIBus *s,
29                                                      uint32_t mmcfg_addr)
30 {
31     return pci_find_device(s, PCIE_MMCFG_BUS(mmcfg_addr),
32                            PCIE_MMCFG_DEVFN(mmcfg_addr));
33 }
34 
35 static void pcie_mmcfg_data_write(void *opaque, hwaddr mmcfg_addr,
36                                   uint64_t val, unsigned len)
37 {
38     PCIExpressHost *e = opaque;
39     PCIBus *s = e->pci.bus;
40     PCIDevice *pci_dev = pcie_dev_find_by_mmcfg_addr(s, mmcfg_addr);
41     uint32_t addr;
42     uint32_t limit;
43 
44     if (!pci_dev) {
45         return;
46     }
47     addr = PCIE_MMCFG_CONFOFFSET(mmcfg_addr);
48     limit = pci_config_size(pci_dev);
49     if (limit <= addr) {
50         /* conventional pci device can be behind pcie-to-pci bridge.
51            256 <= addr < 4K has no effects. */
52         return;
53     }
54     pci_host_config_write_common(pci_dev, addr, limit, val, len);
55 }
56 
57 static uint64_t pcie_mmcfg_data_read(void *opaque,
58                                      hwaddr mmcfg_addr,
59                                      unsigned len)
60 {
61     PCIExpressHost *e = opaque;
62     PCIBus *s = e->pci.bus;
63     PCIDevice *pci_dev = pcie_dev_find_by_mmcfg_addr(s, mmcfg_addr);
64     uint32_t addr;
65     uint32_t limit;
66 
67     if (!pci_dev) {
68         return ~0x0;
69     }
70     addr = PCIE_MMCFG_CONFOFFSET(mmcfg_addr);
71     limit = pci_config_size(pci_dev);
72     if (limit <= addr) {
73         /* conventional pci device can be behind pcie-to-pci bridge.
74            256 <= addr < 4K has no effects. */
75         return ~0x0;
76     }
77     return pci_host_config_read_common(pci_dev, addr, limit, len);
78 }
79 
80 static const MemoryRegionOps pcie_mmcfg_ops = {
81     .read = pcie_mmcfg_data_read,
82     .write = pcie_mmcfg_data_write,
83     .endianness = DEVICE_NATIVE_ENDIAN,
84 };
85 
86 static void pcie_host_init(Object *obj)
87 {
88     PCIExpressHost *e = PCIE_HOST_BRIDGE(obj);
89 
90     e->base_addr = PCIE_BASE_ADDR_UNMAPPED;
91 }
92 
93 void pcie_host_mmcfg_unmap(PCIExpressHost *e)
94 {
95     if (e->base_addr != PCIE_BASE_ADDR_UNMAPPED) {
96         memory_region_del_subregion(get_system_memory(), &e->mmio);
97         e->base_addr = PCIE_BASE_ADDR_UNMAPPED;
98     }
99 }
100 
101 void pcie_host_mmcfg_init(PCIExpressHost *e, uint32_t size)
102 {
103     assert(!(size & (size - 1)));       /* power of 2 */
104     assert(size >= PCIE_MMCFG_SIZE_MIN);
105     assert(size <= PCIE_MMCFG_SIZE_MAX);
106     e->size = size;
107     memory_region_init_io(&e->mmio, OBJECT(e), &pcie_mmcfg_ops, e,
108                           "pcie-mmcfg", e->size);
109 }
110 
111 void pcie_host_mmcfg_map(PCIExpressHost *e, hwaddr addr,
112                          uint32_t size)
113 {
114     pcie_host_mmcfg_init(e, size);
115     e->base_addr = addr;
116     memory_region_add_subregion(get_system_memory(), e->base_addr, &e->mmio);
117 }
118 
119 void pcie_host_mmcfg_update(PCIExpressHost *e,
120                             int enable,
121                             hwaddr addr,
122                             uint32_t size)
123 {
124     pcie_host_mmcfg_unmap(e);
125     if (enable) {
126         pcie_host_mmcfg_map(e, addr, size);
127     }
128 }
129 
130 static const TypeInfo pcie_host_type_info = {
131     .name = TYPE_PCIE_HOST_BRIDGE,
132     .parent = TYPE_PCI_HOST_BRIDGE,
133     .abstract = true,
134     .instance_size = sizeof(PCIExpressHost),
135     .instance_init = pcie_host_init,
136 };
137 
138 static void pcie_host_register_types(void)
139 {
140     type_register_static(&pcie_host_type_info);
141 }
142 
143 type_init(pcie_host_register_types)
144