1 /* 2 * pcie.c 3 * 4 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp> 5 * VA Linux Systems Japan K.K. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu-common.h" 22 #include "hw/pci/pci_bridge.h" 23 #include "hw/pci/pcie.h" 24 #include "hw/pci/msix.h" 25 #include "hw/pci/msi.h" 26 #include "hw/pci/pci_bus.h" 27 #include "hw/pci/pcie_regs.h" 28 #include "qemu/range.h" 29 30 //#define DEBUG_PCIE 31 #ifdef DEBUG_PCIE 32 # define PCIE_DPRINTF(fmt, ...) \ 33 fprintf(stderr, "%s:%d " fmt, __func__, __LINE__, ## __VA_ARGS__) 34 #else 35 # define PCIE_DPRINTF(fmt, ...) do {} while (0) 36 #endif 37 #define PCIE_DEV_PRINTF(dev, fmt, ...) \ 38 PCIE_DPRINTF("%s:%x "fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__) 39 40 41 /*************************************************************************** 42 * pci express capability helper functions 43 */ 44 int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, uint8_t port) 45 { 46 int pos; 47 uint8_t *exp_cap; 48 49 assert(pci_is_express(dev)); 50 51 pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset, 52 PCI_EXP_VER2_SIZEOF); 53 if (pos < 0) { 54 return pos; 55 } 56 dev->exp.exp_cap = pos; 57 exp_cap = dev->config + pos; 58 59 /* capability register 60 interrupt message number defaults to 0 */ 61 pci_set_word(exp_cap + PCI_EXP_FLAGS, 62 ((type << PCI_EXP_FLAGS_TYPE_SHIFT) & PCI_EXP_FLAGS_TYPE) | 63 PCI_EXP_FLAGS_VER2); 64 65 /* device capability register 66 * table 7-12: 67 * roll based error reporting bit must be set by all 68 * Functions conforming to the ECN, PCI Express Base 69 * Specification, Revision 1.1., or subsequent PCI Express Base 70 * Specification revisions. 71 */ 72 pci_set_long(exp_cap + PCI_EXP_DEVCAP, PCI_EXP_DEVCAP_RBER); 73 74 pci_set_long(exp_cap + PCI_EXP_LNKCAP, 75 (port << PCI_EXP_LNKCAP_PN_SHIFT) | 76 PCI_EXP_LNKCAP_ASPMS_0S | 77 PCI_EXP_LNK_MLW_1 | 78 PCI_EXP_LNK_LS_25); 79 80 pci_set_word(exp_cap + PCI_EXP_LNKSTA, 81 PCI_EXP_LNK_MLW_1 | PCI_EXP_LNK_LS_25 |PCI_EXP_LNKSTA_DLLLA); 82 83 pci_set_long(exp_cap + PCI_EXP_DEVCAP2, 84 PCI_EXP_DEVCAP2_EFF | PCI_EXP_DEVCAP2_EETLPP); 85 86 pci_set_word(dev->wmask + pos + PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_EETLPPB); 87 return pos; 88 } 89 90 int pcie_endpoint_cap_init(PCIDevice *dev, uint8_t offset) 91 { 92 uint8_t type = PCI_EXP_TYPE_ENDPOINT; 93 94 /* 95 * Windows guests will report Code 10, device cannot start, if 96 * a regular Endpoint type is exposed on a root complex. These 97 * should instead be Root Complex Integrated Endpoints. 98 */ 99 if (pci_bus_is_express(dev->bus) && pci_bus_is_root(dev->bus)) { 100 type = PCI_EXP_TYPE_RC_END; 101 } 102 103 return pcie_cap_init(dev, offset, type, 0); 104 } 105 106 void pcie_cap_exit(PCIDevice *dev) 107 { 108 pci_del_capability(dev, PCI_CAP_ID_EXP, PCI_EXP_VER2_SIZEOF); 109 } 110 111 uint8_t pcie_cap_get_type(const PCIDevice *dev) 112 { 113 uint32_t pos = dev->exp.exp_cap; 114 assert(pos > 0); 115 return (pci_get_word(dev->config + pos + PCI_EXP_FLAGS) & 116 PCI_EXP_FLAGS_TYPE) >> PCI_EXP_FLAGS_TYPE_SHIFT; 117 } 118 119 /* MSI/MSI-X */ 120 /* pci express interrupt message number */ 121 /* 7.8.2 PCI Express Capabilities Register: Interrupt Message Number */ 122 void pcie_cap_flags_set_vector(PCIDevice *dev, uint8_t vector) 123 { 124 uint8_t *exp_cap = dev->config + dev->exp.exp_cap; 125 assert(vector < 32); 126 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_FLAGS, PCI_EXP_FLAGS_IRQ); 127 pci_word_test_and_set_mask(exp_cap + PCI_EXP_FLAGS, 128 vector << PCI_EXP_FLAGS_IRQ_SHIFT); 129 } 130 131 uint8_t pcie_cap_flags_get_vector(PCIDevice *dev) 132 { 133 return (pci_get_word(dev->config + dev->exp.exp_cap + PCI_EXP_FLAGS) & 134 PCI_EXP_FLAGS_IRQ) >> PCI_EXP_FLAGS_IRQ_SHIFT; 135 } 136 137 void pcie_cap_deverr_init(PCIDevice *dev) 138 { 139 uint32_t pos = dev->exp.exp_cap; 140 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP, 141 PCI_EXP_DEVCAP_RBER); 142 pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL, 143 PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | 144 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE); 145 pci_long_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_DEVSTA, 146 PCI_EXP_DEVSTA_CED | PCI_EXP_DEVSTA_NFED | 147 PCI_EXP_DEVSTA_FED | PCI_EXP_DEVSTA_URD); 148 } 149 150 void pcie_cap_deverr_reset(PCIDevice *dev) 151 { 152 uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL; 153 pci_long_test_and_clear_mask(devctl, 154 PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | 155 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE); 156 } 157 158 static void hotplug_event_update_event_status(PCIDevice *dev) 159 { 160 uint32_t pos = dev->exp.exp_cap; 161 uint8_t *exp_cap = dev->config + pos; 162 uint16_t sltctl = pci_get_word(exp_cap + PCI_EXP_SLTCTL); 163 uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA); 164 165 dev->exp.hpev_notified = (sltctl & PCI_EXP_SLTCTL_HPIE) && 166 (sltsta & sltctl & PCI_EXP_HP_EV_SUPPORTED); 167 } 168 169 static void hotplug_event_notify(PCIDevice *dev) 170 { 171 bool prev = dev->exp.hpev_notified; 172 173 hotplug_event_update_event_status(dev); 174 175 if (prev == dev->exp.hpev_notified) { 176 return; 177 } 178 179 /* Note: the logic above does not take into account whether interrupts 180 * are masked. The result is that interrupt will be sent when it is 181 * subsequently unmasked. This appears to be legal: Section 6.7.3.4: 182 * The Port may optionally send an MSI when there are hot-plug events that 183 * occur while interrupt generation is disabled, and interrupt generation is 184 * subsequently enabled. */ 185 if (msix_enabled(dev)) { 186 msix_notify(dev, pcie_cap_flags_get_vector(dev)); 187 } else if (msi_enabled(dev)) { 188 msi_notify(dev, pcie_cap_flags_get_vector(dev)); 189 } else { 190 pci_set_irq(dev, dev->exp.hpev_notified); 191 } 192 } 193 194 static void hotplug_event_clear(PCIDevice *dev) 195 { 196 hotplug_event_update_event_status(dev); 197 if (!msix_enabled(dev) && !msi_enabled(dev) && !dev->exp.hpev_notified) { 198 pci_irq_deassert(dev); 199 } 200 } 201 202 /* 203 * A PCI Express Hot-Plug Event has occurred, so update slot status register 204 * and notify OS of the event if necessary. 205 * 206 * 6.7.3 PCI Express Hot-Plug Events 207 * 6.7.3.4 Software Notification of Hot-Plug Events 208 */ 209 static void pcie_cap_slot_event(PCIDevice *dev, PCIExpressHotPlugEvent event) 210 { 211 /* Minor optimization: if nothing changed - no event is needed. */ 212 if (pci_word_test_and_set_mask(dev->config + dev->exp.exp_cap + 213 PCI_EXP_SLTSTA, event)) { 214 return; 215 } 216 hotplug_event_notify(dev); 217 } 218 219 static void pcie_cap_slot_hotplug_common(PCIDevice *hotplug_dev, 220 DeviceState *dev, 221 uint8_t **exp_cap, Error **errp) 222 { 223 *exp_cap = hotplug_dev->config + hotplug_dev->exp.exp_cap; 224 uint16_t sltsta = pci_get_word(*exp_cap + PCI_EXP_SLTSTA); 225 226 PCIE_DEV_PRINTF(PCI_DEVICE(dev), "hotplug state: 0x%x\n", sltsta); 227 if (sltsta & PCI_EXP_SLTSTA_EIS) { 228 /* the slot is electromechanically locked. 229 * This error is propagated up to qdev and then to HMP/QMP. 230 */ 231 error_setg_errno(errp, EBUSY, "slot is electromechanically locked"); 232 } 233 } 234 235 void pcie_cap_slot_hotplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, 236 Error **errp) 237 { 238 uint8_t *exp_cap; 239 PCIDevice *pci_dev = PCI_DEVICE(dev); 240 241 pcie_cap_slot_hotplug_common(PCI_DEVICE(hotplug_dev), dev, &exp_cap, errp); 242 243 /* Don't send event when device is enabled during qemu machine creation: 244 * it is present on boot, no hotplug event is necessary. We do send an 245 * event when the device is disabled later. */ 246 if (!dev->hotplugged) { 247 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA, 248 PCI_EXP_SLTSTA_PDS); 249 return; 250 } 251 252 /* To enable multifunction hot-plug, we just ensure the function 253 * 0 added last. When function 0 is added, we set the sltsta and 254 * inform OS via event notification. 255 */ 256 if (pci_get_function_0(pci_dev)) { 257 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA, 258 PCI_EXP_SLTSTA_PDS); 259 pcie_cap_slot_event(PCI_DEVICE(hotplug_dev), 260 PCI_EXP_HP_EV_PDC | PCI_EXP_HP_EV_ABP); 261 } 262 } 263 264 static void pcie_unplug_device(PCIBus *bus, PCIDevice *dev, void *opaque) 265 { 266 object_unparent(OBJECT(dev)); 267 } 268 269 void pcie_cap_slot_hot_unplug_request_cb(HotplugHandler *hotplug_dev, 270 DeviceState *dev, Error **errp) 271 { 272 uint8_t *exp_cap; 273 PCIDevice *pci_dev = PCI_DEVICE(dev); 274 PCIBus *bus = pci_dev->bus; 275 276 pcie_cap_slot_hotplug_common(PCI_DEVICE(hotplug_dev), dev, &exp_cap, errp); 277 278 /* In case user cancel the operation of multi-function hot-add, 279 * remove the function that is unexposed to guest individually, 280 * without interaction with guest. 281 */ 282 if (pci_dev->devfn && 283 !bus->devices[0]) { 284 pcie_unplug_device(bus, pci_dev, NULL); 285 286 return; 287 } 288 289 pcie_cap_slot_push_attention_button(PCI_DEVICE(hotplug_dev)); 290 } 291 292 /* pci express slot for pci express root/downstream port 293 PCI express capability slot registers */ 294 void pcie_cap_slot_init(PCIDevice *dev, uint16_t slot) 295 { 296 uint32_t pos = dev->exp.exp_cap; 297 298 pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_FLAGS, 299 PCI_EXP_FLAGS_SLOT); 300 301 pci_long_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCAP, 302 ~PCI_EXP_SLTCAP_PSN); 303 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP, 304 (slot << PCI_EXP_SLTCAP_PSN_SHIFT) | 305 PCI_EXP_SLTCAP_EIP | 306 PCI_EXP_SLTCAP_HPS | 307 PCI_EXP_SLTCAP_HPC | 308 PCI_EXP_SLTCAP_PIP | 309 PCI_EXP_SLTCAP_AIP | 310 PCI_EXP_SLTCAP_ABP); 311 312 if (dev->cap_present & QEMU_PCIE_SLTCAP_PCP) { 313 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP, 314 PCI_EXP_SLTCAP_PCP); 315 pci_word_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCTL, 316 PCI_EXP_SLTCTL_PCC); 317 pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL, 318 PCI_EXP_SLTCTL_PCC); 319 } 320 321 pci_word_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCTL, 322 PCI_EXP_SLTCTL_PIC | 323 PCI_EXP_SLTCTL_AIC); 324 pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCTL, 325 PCI_EXP_SLTCTL_PIC_OFF | 326 PCI_EXP_SLTCTL_AIC_OFF); 327 pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL, 328 PCI_EXP_SLTCTL_PIC | 329 PCI_EXP_SLTCTL_AIC | 330 PCI_EXP_SLTCTL_HPIE | 331 PCI_EXP_SLTCTL_CCIE | 332 PCI_EXP_SLTCTL_PDCE | 333 PCI_EXP_SLTCTL_ABPE); 334 /* Although reading PCI_EXP_SLTCTL_EIC returns always 0, 335 * make the bit writable here in order to detect 1b is written. 336 * pcie_cap_slot_write_config() test-and-clear the bit, so 337 * this bit always returns 0 to the guest. 338 */ 339 pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL, 340 PCI_EXP_SLTCTL_EIC); 341 342 pci_word_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_SLTSTA, 343 PCI_EXP_HP_EV_SUPPORTED); 344 345 dev->exp.hpev_notified = false; 346 347 qbus_set_hotplug_handler(BUS(pci_bridge_get_sec_bus(PCI_BRIDGE(dev))), 348 DEVICE(dev), NULL); 349 } 350 351 void pcie_cap_slot_reset(PCIDevice *dev) 352 { 353 uint8_t *exp_cap = dev->config + dev->exp.exp_cap; 354 uint8_t port_type = pcie_cap_get_type(dev); 355 356 assert(port_type == PCI_EXP_TYPE_DOWNSTREAM || 357 port_type == PCI_EXP_TYPE_ROOT_PORT); 358 359 PCIE_DEV_PRINTF(dev, "reset\n"); 360 361 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL, 362 PCI_EXP_SLTCTL_EIC | 363 PCI_EXP_SLTCTL_PIC | 364 PCI_EXP_SLTCTL_AIC | 365 PCI_EXP_SLTCTL_HPIE | 366 PCI_EXP_SLTCTL_CCIE | 367 PCI_EXP_SLTCTL_PDCE | 368 PCI_EXP_SLTCTL_ABPE); 369 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL, 370 PCI_EXP_SLTCTL_AIC_OFF); 371 372 if (dev->cap_present & QEMU_PCIE_SLTCAP_PCP) { 373 /* Downstream ports enforce device number 0. */ 374 bool populated = pci_bridge_get_sec_bus(PCI_BRIDGE(dev))->devices[0]; 375 uint16_t pic; 376 377 if (populated) { 378 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL, 379 PCI_EXP_SLTCTL_PCC); 380 } else { 381 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL, 382 PCI_EXP_SLTCTL_PCC); 383 } 384 385 pic = populated ? PCI_EXP_SLTCTL_PIC_ON : PCI_EXP_SLTCTL_PIC_OFF; 386 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL, pic); 387 } 388 389 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA, 390 PCI_EXP_SLTSTA_EIS |/* on reset, 391 the lock is released */ 392 PCI_EXP_SLTSTA_CC | 393 PCI_EXP_SLTSTA_PDC | 394 PCI_EXP_SLTSTA_ABP); 395 396 hotplug_event_update_event_status(dev); 397 } 398 399 void pcie_cap_slot_write_config(PCIDevice *dev, 400 uint32_t addr, uint32_t val, int len) 401 { 402 uint32_t pos = dev->exp.exp_cap; 403 uint8_t *exp_cap = dev->config + pos; 404 uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA); 405 406 if (ranges_overlap(addr, len, pos + PCI_EXP_SLTSTA, 2)) { 407 hotplug_event_clear(dev); 408 } 409 410 if (!ranges_overlap(addr, len, pos + PCI_EXP_SLTCTL, 2)) { 411 return; 412 } 413 414 if (pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL, 415 PCI_EXP_SLTCTL_EIC)) { 416 sltsta ^= PCI_EXP_SLTSTA_EIS; /* toggle PCI_EXP_SLTSTA_EIS bit */ 417 pci_set_word(exp_cap + PCI_EXP_SLTSTA, sltsta); 418 PCIE_DEV_PRINTF(dev, "PCI_EXP_SLTCTL_EIC: " 419 "sltsta -> 0x%02"PRIx16"\n", 420 sltsta); 421 } 422 423 /* 424 * If the slot is polulated, power indicator is off and power 425 * controller is off, it is safe to detach the devices. 426 */ 427 if ((sltsta & PCI_EXP_SLTSTA_PDS) && (val & PCI_EXP_SLTCTL_PCC) && 428 ((val & PCI_EXP_SLTCTL_PIC_OFF) == PCI_EXP_SLTCTL_PIC_OFF)) { 429 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev)); 430 pci_for_each_device(sec_bus, pci_bus_num(sec_bus), 431 pcie_unplug_device, NULL); 432 433 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA, 434 PCI_EXP_SLTSTA_PDS); 435 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA, 436 PCI_EXP_SLTSTA_PDC); 437 } 438 439 hotplug_event_notify(dev); 440 441 /* 442 * 6.7.3.2 Command Completed Events 443 * 444 * Software issues a command to a hot-plug capable Downstream Port by 445 * issuing a write transaction that targets any portion of the Port’s Slot 446 * Control register. A single write to the Slot Control register is 447 * considered to be a single command, even if the write affects more than 448 * one field in the Slot Control register. In response to this transaction, 449 * the Port must carry out the requested actions and then set the 450 * associated status field for the command completed event. */ 451 452 /* Real hardware might take a while to complete requested command because 453 * physical movement would be involved like locking the electromechanical 454 * lock. However in our case, command is completed instantaneously above, 455 * so send a command completion event right now. 456 */ 457 pcie_cap_slot_event(dev, PCI_EXP_HP_EV_CCI); 458 } 459 460 int pcie_cap_slot_post_load(void *opaque, int version_id) 461 { 462 PCIDevice *dev = opaque; 463 hotplug_event_update_event_status(dev); 464 return 0; 465 } 466 467 void pcie_cap_slot_push_attention_button(PCIDevice *dev) 468 { 469 pcie_cap_slot_event(dev, PCI_EXP_HP_EV_ABP); 470 } 471 472 /* root control/capabilities/status. PME isn't emulated for now */ 473 void pcie_cap_root_init(PCIDevice *dev) 474 { 475 pci_set_word(dev->wmask + dev->exp.exp_cap + PCI_EXP_RTCTL, 476 PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE | 477 PCI_EXP_RTCTL_SEFEE); 478 } 479 480 void pcie_cap_root_reset(PCIDevice *dev) 481 { 482 pci_set_word(dev->config + dev->exp.exp_cap + PCI_EXP_RTCTL, 0); 483 } 484 485 /* function level reset(FLR) */ 486 void pcie_cap_flr_init(PCIDevice *dev) 487 { 488 pci_long_test_and_set_mask(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCAP, 489 PCI_EXP_DEVCAP_FLR); 490 491 /* Although reading BCR_FLR returns always 0, 492 * the bit is made writable here in order to detect the 1b is written 493 * pcie_cap_flr_write_config() test-and-clear the bit, so 494 * this bit always returns 0 to the guest. 495 */ 496 pci_word_test_and_set_mask(dev->wmask + dev->exp.exp_cap + PCI_EXP_DEVCTL, 497 PCI_EXP_DEVCTL_BCR_FLR); 498 } 499 500 void pcie_cap_flr_write_config(PCIDevice *dev, 501 uint32_t addr, uint32_t val, int len) 502 { 503 uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL; 504 if (pci_get_word(devctl) & PCI_EXP_DEVCTL_BCR_FLR) { 505 /* Clear PCI_EXP_DEVCTL_BCR_FLR after invoking the reset handler 506 so the handler can detect FLR by looking at this bit. */ 507 pci_device_reset(dev); 508 pci_word_test_and_clear_mask(devctl, PCI_EXP_DEVCTL_BCR_FLR); 509 } 510 } 511 512 /* Alternative Routing-ID Interpretation (ARI) 513 * forwarding support for root and downstream ports 514 */ 515 void pcie_cap_arifwd_init(PCIDevice *dev) 516 { 517 uint32_t pos = dev->exp.exp_cap; 518 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP2, 519 PCI_EXP_DEVCAP2_ARI); 520 pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL2, 521 PCI_EXP_DEVCTL2_ARI); 522 } 523 524 void pcie_cap_arifwd_reset(PCIDevice *dev) 525 { 526 uint8_t *devctl2 = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2; 527 pci_long_test_and_clear_mask(devctl2, PCI_EXP_DEVCTL2_ARI); 528 } 529 530 bool pcie_cap_is_arifwd_enabled(const PCIDevice *dev) 531 { 532 if (!pci_is_express(dev)) { 533 return false; 534 } 535 if (!dev->exp.exp_cap) { 536 return false; 537 } 538 539 return pci_get_long(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2) & 540 PCI_EXP_DEVCTL2_ARI; 541 } 542 543 /************************************************************************** 544 * pci express extended capability list management functions 545 * uint16_t ext_cap_id (16 bit) 546 * uint8_t cap_ver (4 bit) 547 * uint16_t cap_offset (12 bit) 548 * uint16_t ext_cap_size 549 */ 550 551 static uint16_t pcie_find_capability_list(PCIDevice *dev, uint16_t cap_id, 552 uint16_t *prev_p) 553 { 554 uint16_t prev = 0; 555 uint16_t next; 556 uint32_t header = pci_get_long(dev->config + PCI_CONFIG_SPACE_SIZE); 557 558 if (!header) { 559 /* no extended capability */ 560 next = 0; 561 goto out; 562 } 563 for (next = PCI_CONFIG_SPACE_SIZE; next; 564 prev = next, next = PCI_EXT_CAP_NEXT(header)) { 565 566 assert(next >= PCI_CONFIG_SPACE_SIZE); 567 assert(next <= PCIE_CONFIG_SPACE_SIZE - 8); 568 569 header = pci_get_long(dev->config + next); 570 if (PCI_EXT_CAP_ID(header) == cap_id) { 571 break; 572 } 573 } 574 575 out: 576 if (prev_p) { 577 *prev_p = prev; 578 } 579 return next; 580 } 581 582 uint16_t pcie_find_capability(PCIDevice *dev, uint16_t cap_id) 583 { 584 return pcie_find_capability_list(dev, cap_id, NULL); 585 } 586 587 static void pcie_ext_cap_set_next(PCIDevice *dev, uint16_t pos, uint16_t next) 588 { 589 uint32_t header = pci_get_long(dev->config + pos); 590 assert(!(next & (PCI_EXT_CAP_ALIGN - 1))); 591 header = (header & ~PCI_EXT_CAP_NEXT_MASK) | 592 ((next << PCI_EXT_CAP_NEXT_SHIFT) & PCI_EXT_CAP_NEXT_MASK); 593 pci_set_long(dev->config + pos, header); 594 } 595 596 /* 597 * caller must supply valid (offset, size) * such that the range shouldn't 598 * overlap with other capability or other registers. 599 * This function doesn't check it. 600 */ 601 void pcie_add_capability(PCIDevice *dev, 602 uint16_t cap_id, uint8_t cap_ver, 603 uint16_t offset, uint16_t size) 604 { 605 uint32_t header; 606 uint16_t next; 607 608 assert(offset >= PCI_CONFIG_SPACE_SIZE); 609 assert(offset < offset + size); 610 assert(offset + size < PCIE_CONFIG_SPACE_SIZE); 611 assert(size >= 8); 612 assert(pci_is_express(dev)); 613 614 if (offset == PCI_CONFIG_SPACE_SIZE) { 615 header = pci_get_long(dev->config + offset); 616 next = PCI_EXT_CAP_NEXT(header); 617 } else { 618 uint16_t prev; 619 620 /* 0 is reserved cap id. use internally to find the last capability 621 in the linked list */ 622 next = pcie_find_capability_list(dev, 0, &prev); 623 624 assert(prev >= PCI_CONFIG_SPACE_SIZE); 625 assert(next == 0); 626 pcie_ext_cap_set_next(dev, prev, offset); 627 } 628 pci_set_long(dev->config + offset, PCI_EXT_CAP(cap_id, cap_ver, next)); 629 630 /* Make capability read-only by default */ 631 memset(dev->wmask + offset, 0, size); 632 memset(dev->w1cmask + offset, 0, size); 633 /* Check capability by default */ 634 memset(dev->cmask + offset, 0xFF, size); 635 } 636 637 /************************************************************************** 638 * pci express extended capability helper functions 639 */ 640 641 /* ARI */ 642 void pcie_ari_init(PCIDevice *dev, uint16_t offset, uint16_t nextfn) 643 { 644 pcie_add_capability(dev, PCI_EXT_CAP_ID_ARI, PCI_ARI_VER, 645 offset, PCI_ARI_SIZEOF); 646 pci_set_long(dev->config + offset + PCI_ARI_CAP, (nextfn & 0xff) << 8); 647 } 648