1 /* 2 * pcie.c 3 * 4 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp> 5 * VA Linux Systems Japan K.K. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "qemu-common.h" 24 #include "hw/pci/pci_bridge.h" 25 #include "hw/pci/pcie.h" 26 #include "hw/pci/msix.h" 27 #include "hw/pci/msi.h" 28 #include "hw/pci/pci_bus.h" 29 #include "hw/pci/pcie_regs.h" 30 #include "qemu/range.h" 31 32 //#define DEBUG_PCIE 33 #ifdef DEBUG_PCIE 34 # define PCIE_DPRINTF(fmt, ...) \ 35 fprintf(stderr, "%s:%d " fmt, __func__, __LINE__, ## __VA_ARGS__) 36 #else 37 # define PCIE_DPRINTF(fmt, ...) do {} while (0) 38 #endif 39 #define PCIE_DEV_PRINTF(dev, fmt, ...) \ 40 PCIE_DPRINTF("%s:%x "fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__) 41 42 43 /*************************************************************************** 44 * pci express capability helper functions 45 */ 46 47 static void 48 pcie_cap_v1_fill(PCIDevice *dev, uint8_t port, uint8_t type, uint8_t version) 49 { 50 uint8_t *exp_cap = dev->config + dev->exp.exp_cap; 51 uint8_t *cmask = dev->cmask + dev->exp.exp_cap; 52 53 /* capability register 54 interrupt message number defaults to 0 */ 55 pci_set_word(exp_cap + PCI_EXP_FLAGS, 56 ((type << PCI_EXP_FLAGS_TYPE_SHIFT) & PCI_EXP_FLAGS_TYPE) | 57 version); 58 59 /* device capability register 60 * table 7-12: 61 * roll based error reporting bit must be set by all 62 * Functions conforming to the ECN, PCI Express Base 63 * Specification, Revision 1.1., or subsequent PCI Express Base 64 * Specification revisions. 65 */ 66 pci_set_long(exp_cap + PCI_EXP_DEVCAP, PCI_EXP_DEVCAP_RBER); 67 68 pci_set_long(exp_cap + PCI_EXP_LNKCAP, 69 (port << PCI_EXP_LNKCAP_PN_SHIFT) | 70 PCI_EXP_LNKCAP_ASPMS_0S | 71 PCI_EXP_LNK_MLW_1 | 72 PCI_EXP_LNK_LS_25); 73 74 pci_set_word(exp_cap + PCI_EXP_LNKSTA, 75 PCI_EXP_LNK_MLW_1 | PCI_EXP_LNK_LS_25); 76 77 if (dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA) { 78 pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA, 79 PCI_EXP_LNKSTA_DLLLA); 80 } 81 82 /* We changed link status bits over time, and changing them across 83 * migrations is generally fine as hardware changes them too. 84 * Let's not bother checking. 85 */ 86 pci_set_word(cmask + PCI_EXP_LNKSTA, 0); 87 } 88 89 int pcie_cap_init(PCIDevice *dev, uint8_t offset, 90 uint8_t type, uint8_t port, 91 Error **errp) 92 { 93 /* PCIe cap v2 init */ 94 int pos; 95 uint8_t *exp_cap; 96 97 assert(pci_is_express(dev)); 98 99 pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset, 100 PCI_EXP_VER2_SIZEOF, errp); 101 if (pos < 0) { 102 return pos; 103 } 104 dev->exp.exp_cap = pos; 105 exp_cap = dev->config + pos; 106 107 /* Filling values common with v1 */ 108 pcie_cap_v1_fill(dev, port, type, PCI_EXP_FLAGS_VER2); 109 110 /* Filling v2 specific values */ 111 pci_set_long(exp_cap + PCI_EXP_DEVCAP2, 112 PCI_EXP_DEVCAP2_EFF | PCI_EXP_DEVCAP2_EETLPP); 113 114 pci_set_word(dev->wmask + pos + PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_EETLPPB); 115 116 if (dev->cap_present & QEMU_PCIE_EXTCAP_INIT) { 117 /* read-only to behave like a 'NULL' Extended Capability Header */ 118 pci_set_long(dev->wmask + PCI_CONFIG_SPACE_SIZE, 0); 119 } 120 121 return pos; 122 } 123 124 int pcie_cap_v1_init(PCIDevice *dev, uint8_t offset, uint8_t type, 125 uint8_t port) 126 { 127 /* PCIe cap v1 init */ 128 int pos; 129 Error *local_err = NULL; 130 131 assert(pci_is_express(dev)); 132 133 pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset, 134 PCI_EXP_VER1_SIZEOF, &local_err); 135 if (pos < 0) { 136 error_report_err(local_err); 137 return pos; 138 } 139 dev->exp.exp_cap = pos; 140 141 pcie_cap_v1_fill(dev, port, type, PCI_EXP_FLAGS_VER1); 142 143 return pos; 144 } 145 146 static int 147 pcie_endpoint_cap_common_init(PCIDevice *dev, uint8_t offset, uint8_t cap_size) 148 { 149 uint8_t type = PCI_EXP_TYPE_ENDPOINT; 150 Error *local_err = NULL; 151 int ret; 152 153 /* 154 * Windows guests will report Code 10, device cannot start, if 155 * a regular Endpoint type is exposed on a root complex. These 156 * should instead be Root Complex Integrated Endpoints. 157 */ 158 if (pci_bus_is_express(pci_get_bus(dev)) 159 && pci_bus_is_root(pci_get_bus(dev))) { 160 type = PCI_EXP_TYPE_RC_END; 161 } 162 163 if (cap_size == PCI_EXP_VER1_SIZEOF) { 164 return pcie_cap_v1_init(dev, offset, type, 0); 165 } else { 166 ret = pcie_cap_init(dev, offset, type, 0, &local_err); 167 168 if (ret < 0) { 169 error_report_err(local_err); 170 } 171 172 return ret; 173 } 174 } 175 176 int pcie_endpoint_cap_init(PCIDevice *dev, uint8_t offset) 177 { 178 return pcie_endpoint_cap_common_init(dev, offset, PCI_EXP_VER2_SIZEOF); 179 } 180 181 int pcie_endpoint_cap_v1_init(PCIDevice *dev, uint8_t offset) 182 { 183 return pcie_endpoint_cap_common_init(dev, offset, PCI_EXP_VER1_SIZEOF); 184 } 185 186 void pcie_cap_exit(PCIDevice *dev) 187 { 188 pci_del_capability(dev, PCI_CAP_ID_EXP, PCI_EXP_VER2_SIZEOF); 189 } 190 191 void pcie_cap_v1_exit(PCIDevice *dev) 192 { 193 pci_del_capability(dev, PCI_CAP_ID_EXP, PCI_EXP_VER1_SIZEOF); 194 } 195 196 uint8_t pcie_cap_get_type(const PCIDevice *dev) 197 { 198 uint32_t pos = dev->exp.exp_cap; 199 assert(pos > 0); 200 return (pci_get_word(dev->config + pos + PCI_EXP_FLAGS) & 201 PCI_EXP_FLAGS_TYPE) >> PCI_EXP_FLAGS_TYPE_SHIFT; 202 } 203 204 /* MSI/MSI-X */ 205 /* pci express interrupt message number */ 206 /* 7.8.2 PCI Express Capabilities Register: Interrupt Message Number */ 207 void pcie_cap_flags_set_vector(PCIDevice *dev, uint8_t vector) 208 { 209 uint8_t *exp_cap = dev->config + dev->exp.exp_cap; 210 assert(vector < 32); 211 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_FLAGS, PCI_EXP_FLAGS_IRQ); 212 pci_word_test_and_set_mask(exp_cap + PCI_EXP_FLAGS, 213 vector << PCI_EXP_FLAGS_IRQ_SHIFT); 214 } 215 216 uint8_t pcie_cap_flags_get_vector(PCIDevice *dev) 217 { 218 return (pci_get_word(dev->config + dev->exp.exp_cap + PCI_EXP_FLAGS) & 219 PCI_EXP_FLAGS_IRQ) >> PCI_EXP_FLAGS_IRQ_SHIFT; 220 } 221 222 void pcie_cap_deverr_init(PCIDevice *dev) 223 { 224 uint32_t pos = dev->exp.exp_cap; 225 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP, 226 PCI_EXP_DEVCAP_RBER); 227 pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL, 228 PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | 229 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE); 230 pci_long_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_DEVSTA, 231 PCI_EXP_DEVSTA_CED | PCI_EXP_DEVSTA_NFED | 232 PCI_EXP_DEVSTA_FED | PCI_EXP_DEVSTA_URD); 233 } 234 235 void pcie_cap_deverr_reset(PCIDevice *dev) 236 { 237 uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL; 238 pci_long_test_and_clear_mask(devctl, 239 PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | 240 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE); 241 } 242 243 void pcie_cap_lnkctl_init(PCIDevice *dev) 244 { 245 uint32_t pos = dev->exp.exp_cap; 246 pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_LNKCTL, 247 PCI_EXP_LNKCTL_CCC | PCI_EXP_LNKCTL_ES); 248 } 249 250 void pcie_cap_lnkctl_reset(PCIDevice *dev) 251 { 252 uint8_t *lnkctl = dev->config + dev->exp.exp_cap + PCI_EXP_LNKCTL; 253 pci_long_test_and_clear_mask(lnkctl, 254 PCI_EXP_LNKCTL_CCC | PCI_EXP_LNKCTL_ES); 255 } 256 257 static void hotplug_event_update_event_status(PCIDevice *dev) 258 { 259 uint32_t pos = dev->exp.exp_cap; 260 uint8_t *exp_cap = dev->config + pos; 261 uint16_t sltctl = pci_get_word(exp_cap + PCI_EXP_SLTCTL); 262 uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA); 263 264 dev->exp.hpev_notified = (sltctl & PCI_EXP_SLTCTL_HPIE) && 265 (sltsta & sltctl & PCI_EXP_HP_EV_SUPPORTED); 266 } 267 268 static void hotplug_event_notify(PCIDevice *dev) 269 { 270 bool prev = dev->exp.hpev_notified; 271 272 hotplug_event_update_event_status(dev); 273 274 if (prev == dev->exp.hpev_notified) { 275 return; 276 } 277 278 /* Note: the logic above does not take into account whether interrupts 279 * are masked. The result is that interrupt will be sent when it is 280 * subsequently unmasked. This appears to be legal: Section 6.7.3.4: 281 * The Port may optionally send an MSI when there are hot-plug events that 282 * occur while interrupt generation is disabled, and interrupt generation is 283 * subsequently enabled. */ 284 if (msix_enabled(dev)) { 285 msix_notify(dev, pcie_cap_flags_get_vector(dev)); 286 } else if (msi_enabled(dev)) { 287 msi_notify(dev, pcie_cap_flags_get_vector(dev)); 288 } else { 289 pci_set_irq(dev, dev->exp.hpev_notified); 290 } 291 } 292 293 static void hotplug_event_clear(PCIDevice *dev) 294 { 295 hotplug_event_update_event_status(dev); 296 if (!msix_enabled(dev) && !msi_enabled(dev) && !dev->exp.hpev_notified) { 297 pci_irq_deassert(dev); 298 } 299 } 300 301 /* 302 * A PCI Express Hot-Plug Event has occurred, so update slot status register 303 * and notify OS of the event if necessary. 304 * 305 * 6.7.3 PCI Express Hot-Plug Events 306 * 6.7.3.4 Software Notification of Hot-Plug Events 307 */ 308 static void pcie_cap_slot_event(PCIDevice *dev, PCIExpressHotPlugEvent event) 309 { 310 /* Minor optimization: if nothing changed - no event is needed. */ 311 if (pci_word_test_and_set_mask(dev->config + dev->exp.exp_cap + 312 PCI_EXP_SLTSTA, event)) { 313 return; 314 } 315 hotplug_event_notify(dev); 316 } 317 318 static void pcie_cap_slot_hotplug_common(PCIDevice *hotplug_dev, 319 DeviceState *dev, 320 uint8_t **exp_cap, Error **errp) 321 { 322 *exp_cap = hotplug_dev->config + hotplug_dev->exp.exp_cap; 323 uint16_t sltsta = pci_get_word(*exp_cap + PCI_EXP_SLTSTA); 324 325 PCIE_DEV_PRINTF(PCI_DEVICE(dev), "hotplug state: 0x%x\n", sltsta); 326 if (sltsta & PCI_EXP_SLTSTA_EIS) { 327 /* the slot is electromechanically locked. 328 * This error is propagated up to qdev and then to HMP/QMP. 329 */ 330 error_setg_errno(errp, EBUSY, "slot is electromechanically locked"); 331 } 332 } 333 334 void pcie_cap_slot_hotplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, 335 Error **errp) 336 { 337 uint8_t *exp_cap; 338 PCIDevice *pci_dev = PCI_DEVICE(dev); 339 340 pcie_cap_slot_hotplug_common(PCI_DEVICE(hotplug_dev), dev, &exp_cap, errp); 341 342 /* Don't send event when device is enabled during qemu machine creation: 343 * it is present on boot, no hotplug event is necessary. We do send an 344 * event when the device is disabled later. */ 345 if (!dev->hotplugged) { 346 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA, 347 PCI_EXP_SLTSTA_PDS); 348 return; 349 } 350 351 /* To enable multifunction hot-plug, we just ensure the function 352 * 0 added last. When function 0 is added, we set the sltsta and 353 * inform OS via event notification. 354 */ 355 if (pci_get_function_0(pci_dev)) { 356 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA, 357 PCI_EXP_SLTSTA_PDS); 358 pcie_cap_slot_event(PCI_DEVICE(hotplug_dev), 359 PCI_EXP_HP_EV_PDC | PCI_EXP_HP_EV_ABP); 360 } 361 } 362 363 static void pcie_unplug_device(PCIBus *bus, PCIDevice *dev, void *opaque) 364 { 365 object_unparent(OBJECT(dev)); 366 } 367 368 void pcie_cap_slot_hot_unplug_request_cb(HotplugHandler *hotplug_dev, 369 DeviceState *dev, Error **errp) 370 { 371 uint8_t *exp_cap; 372 PCIDevice *pci_dev = PCI_DEVICE(dev); 373 PCIBus *bus = pci_get_bus(pci_dev); 374 375 pcie_cap_slot_hotplug_common(PCI_DEVICE(hotplug_dev), dev, &exp_cap, errp); 376 377 /* In case user cancel the operation of multi-function hot-add, 378 * remove the function that is unexposed to guest individually, 379 * without interaction with guest. 380 */ 381 if (pci_dev->devfn && 382 !bus->devices[0]) { 383 pcie_unplug_device(bus, pci_dev, NULL); 384 385 return; 386 } 387 388 pcie_cap_slot_push_attention_button(PCI_DEVICE(hotplug_dev)); 389 } 390 391 /* pci express slot for pci express root/downstream port 392 PCI express capability slot registers */ 393 void pcie_cap_slot_init(PCIDevice *dev, uint16_t slot) 394 { 395 uint32_t pos = dev->exp.exp_cap; 396 397 pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_FLAGS, 398 PCI_EXP_FLAGS_SLOT); 399 400 pci_long_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCAP, 401 ~PCI_EXP_SLTCAP_PSN); 402 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP, 403 (slot << PCI_EXP_SLTCAP_PSN_SHIFT) | 404 PCI_EXP_SLTCAP_EIP | 405 PCI_EXP_SLTCAP_HPS | 406 PCI_EXP_SLTCAP_HPC | 407 PCI_EXP_SLTCAP_PIP | 408 PCI_EXP_SLTCAP_AIP | 409 PCI_EXP_SLTCAP_ABP); 410 411 if (dev->cap_present & QEMU_PCIE_SLTCAP_PCP) { 412 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP, 413 PCI_EXP_SLTCAP_PCP); 414 pci_word_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCTL, 415 PCI_EXP_SLTCTL_PCC); 416 pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL, 417 PCI_EXP_SLTCTL_PCC); 418 } 419 420 pci_word_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCTL, 421 PCI_EXP_SLTCTL_PIC | 422 PCI_EXP_SLTCTL_AIC); 423 pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCTL, 424 PCI_EXP_SLTCTL_PIC_OFF | 425 PCI_EXP_SLTCTL_AIC_OFF); 426 pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL, 427 PCI_EXP_SLTCTL_PIC | 428 PCI_EXP_SLTCTL_AIC | 429 PCI_EXP_SLTCTL_HPIE | 430 PCI_EXP_SLTCTL_CCIE | 431 PCI_EXP_SLTCTL_PDCE | 432 PCI_EXP_SLTCTL_ABPE); 433 /* Although reading PCI_EXP_SLTCTL_EIC returns always 0, 434 * make the bit writable here in order to detect 1b is written. 435 * pcie_cap_slot_write_config() test-and-clear the bit, so 436 * this bit always returns 0 to the guest. 437 */ 438 pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL, 439 PCI_EXP_SLTCTL_EIC); 440 441 pci_word_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_SLTSTA, 442 PCI_EXP_HP_EV_SUPPORTED); 443 444 dev->exp.hpev_notified = false; 445 446 qbus_set_hotplug_handler(BUS(pci_bridge_get_sec_bus(PCI_BRIDGE(dev))), 447 DEVICE(dev), NULL); 448 } 449 450 void pcie_cap_slot_reset(PCIDevice *dev) 451 { 452 uint8_t *exp_cap = dev->config + dev->exp.exp_cap; 453 uint8_t port_type = pcie_cap_get_type(dev); 454 455 assert(port_type == PCI_EXP_TYPE_DOWNSTREAM || 456 port_type == PCI_EXP_TYPE_ROOT_PORT); 457 458 PCIE_DEV_PRINTF(dev, "reset\n"); 459 460 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL, 461 PCI_EXP_SLTCTL_EIC | 462 PCI_EXP_SLTCTL_PIC | 463 PCI_EXP_SLTCTL_AIC | 464 PCI_EXP_SLTCTL_HPIE | 465 PCI_EXP_SLTCTL_CCIE | 466 PCI_EXP_SLTCTL_PDCE | 467 PCI_EXP_SLTCTL_ABPE); 468 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL, 469 PCI_EXP_SLTCTL_AIC_OFF); 470 471 if (dev->cap_present & QEMU_PCIE_SLTCAP_PCP) { 472 /* Downstream ports enforce device number 0. */ 473 bool populated = pci_bridge_get_sec_bus(PCI_BRIDGE(dev))->devices[0]; 474 uint16_t pic; 475 476 if (populated) { 477 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL, 478 PCI_EXP_SLTCTL_PCC); 479 } else { 480 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL, 481 PCI_EXP_SLTCTL_PCC); 482 } 483 484 pic = populated ? PCI_EXP_SLTCTL_PIC_ON : PCI_EXP_SLTCTL_PIC_OFF; 485 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL, pic); 486 } 487 488 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA, 489 PCI_EXP_SLTSTA_EIS |/* on reset, 490 the lock is released */ 491 PCI_EXP_SLTSTA_CC | 492 PCI_EXP_SLTSTA_PDC | 493 PCI_EXP_SLTSTA_ABP); 494 495 hotplug_event_update_event_status(dev); 496 } 497 498 void pcie_cap_slot_write_config(PCIDevice *dev, 499 uint32_t addr, uint32_t val, int len) 500 { 501 uint32_t pos = dev->exp.exp_cap; 502 uint8_t *exp_cap = dev->config + pos; 503 uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA); 504 505 if (ranges_overlap(addr, len, pos + PCI_EXP_SLTSTA, 2)) { 506 hotplug_event_clear(dev); 507 } 508 509 if (!ranges_overlap(addr, len, pos + PCI_EXP_SLTCTL, 2)) { 510 return; 511 } 512 513 if (pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL, 514 PCI_EXP_SLTCTL_EIC)) { 515 sltsta ^= PCI_EXP_SLTSTA_EIS; /* toggle PCI_EXP_SLTSTA_EIS bit */ 516 pci_set_word(exp_cap + PCI_EXP_SLTSTA, sltsta); 517 PCIE_DEV_PRINTF(dev, "PCI_EXP_SLTCTL_EIC: " 518 "sltsta -> 0x%02"PRIx16"\n", 519 sltsta); 520 } 521 522 /* 523 * If the slot is polulated, power indicator is off and power 524 * controller is off, it is safe to detach the devices. 525 */ 526 if ((sltsta & PCI_EXP_SLTSTA_PDS) && (val & PCI_EXP_SLTCTL_PCC) && 527 ((val & PCI_EXP_SLTCTL_PIC_OFF) == PCI_EXP_SLTCTL_PIC_OFF)) { 528 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev)); 529 pci_for_each_device(sec_bus, pci_bus_num(sec_bus), 530 pcie_unplug_device, NULL); 531 532 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA, 533 PCI_EXP_SLTSTA_PDS); 534 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA, 535 PCI_EXP_SLTSTA_PDC); 536 } 537 538 hotplug_event_notify(dev); 539 540 /* 541 * 6.7.3.2 Command Completed Events 542 * 543 * Software issues a command to a hot-plug capable Downstream Port by 544 * issuing a write transaction that targets any portion of the Port’s Slot 545 * Control register. A single write to the Slot Control register is 546 * considered to be a single command, even if the write affects more than 547 * one field in the Slot Control register. In response to this transaction, 548 * the Port must carry out the requested actions and then set the 549 * associated status field for the command completed event. */ 550 551 /* Real hardware might take a while to complete requested command because 552 * physical movement would be involved like locking the electromechanical 553 * lock. However in our case, command is completed instantaneously above, 554 * so send a command completion event right now. 555 */ 556 pcie_cap_slot_event(dev, PCI_EXP_HP_EV_CCI); 557 } 558 559 int pcie_cap_slot_post_load(void *opaque, int version_id) 560 { 561 PCIDevice *dev = opaque; 562 hotplug_event_update_event_status(dev); 563 return 0; 564 } 565 566 void pcie_cap_slot_push_attention_button(PCIDevice *dev) 567 { 568 pcie_cap_slot_event(dev, PCI_EXP_HP_EV_ABP); 569 } 570 571 /* root control/capabilities/status. PME isn't emulated for now */ 572 void pcie_cap_root_init(PCIDevice *dev) 573 { 574 pci_set_word(dev->wmask + dev->exp.exp_cap + PCI_EXP_RTCTL, 575 PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE | 576 PCI_EXP_RTCTL_SEFEE); 577 } 578 579 void pcie_cap_root_reset(PCIDevice *dev) 580 { 581 pci_set_word(dev->config + dev->exp.exp_cap + PCI_EXP_RTCTL, 0); 582 } 583 584 /* function level reset(FLR) */ 585 void pcie_cap_flr_init(PCIDevice *dev) 586 { 587 pci_long_test_and_set_mask(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCAP, 588 PCI_EXP_DEVCAP_FLR); 589 590 /* Although reading BCR_FLR returns always 0, 591 * the bit is made writable here in order to detect the 1b is written 592 * pcie_cap_flr_write_config() test-and-clear the bit, so 593 * this bit always returns 0 to the guest. 594 */ 595 pci_word_test_and_set_mask(dev->wmask + dev->exp.exp_cap + PCI_EXP_DEVCTL, 596 PCI_EXP_DEVCTL_BCR_FLR); 597 } 598 599 void pcie_cap_flr_write_config(PCIDevice *dev, 600 uint32_t addr, uint32_t val, int len) 601 { 602 uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL; 603 if (pci_get_word(devctl) & PCI_EXP_DEVCTL_BCR_FLR) { 604 /* Clear PCI_EXP_DEVCTL_BCR_FLR after invoking the reset handler 605 so the handler can detect FLR by looking at this bit. */ 606 pci_device_reset(dev); 607 pci_word_test_and_clear_mask(devctl, PCI_EXP_DEVCTL_BCR_FLR); 608 } 609 } 610 611 /* Alternative Routing-ID Interpretation (ARI) 612 * forwarding support for root and downstream ports 613 */ 614 void pcie_cap_arifwd_init(PCIDevice *dev) 615 { 616 uint32_t pos = dev->exp.exp_cap; 617 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP2, 618 PCI_EXP_DEVCAP2_ARI); 619 pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL2, 620 PCI_EXP_DEVCTL2_ARI); 621 } 622 623 void pcie_cap_arifwd_reset(PCIDevice *dev) 624 { 625 uint8_t *devctl2 = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2; 626 pci_long_test_and_clear_mask(devctl2, PCI_EXP_DEVCTL2_ARI); 627 } 628 629 bool pcie_cap_is_arifwd_enabled(const PCIDevice *dev) 630 { 631 if (!pci_is_express(dev)) { 632 return false; 633 } 634 if (!dev->exp.exp_cap) { 635 return false; 636 } 637 638 return pci_get_long(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2) & 639 PCI_EXP_DEVCTL2_ARI; 640 } 641 642 /************************************************************************** 643 * pci express extended capability list management functions 644 * uint16_t ext_cap_id (16 bit) 645 * uint8_t cap_ver (4 bit) 646 * uint16_t cap_offset (12 bit) 647 * uint16_t ext_cap_size 648 */ 649 650 /* Passing a cap_id value > 0xffff will return 0 and put end of list in prev */ 651 static uint16_t pcie_find_capability_list(PCIDevice *dev, uint32_t cap_id, 652 uint16_t *prev_p) 653 { 654 uint16_t prev = 0; 655 uint16_t next; 656 uint32_t header = pci_get_long(dev->config + PCI_CONFIG_SPACE_SIZE); 657 658 if (!header) { 659 /* no extended capability */ 660 next = 0; 661 goto out; 662 } 663 for (next = PCI_CONFIG_SPACE_SIZE; next; 664 prev = next, next = PCI_EXT_CAP_NEXT(header)) { 665 666 assert(next >= PCI_CONFIG_SPACE_SIZE); 667 assert(next <= PCIE_CONFIG_SPACE_SIZE - 8); 668 669 header = pci_get_long(dev->config + next); 670 if (PCI_EXT_CAP_ID(header) == cap_id) { 671 break; 672 } 673 } 674 675 out: 676 if (prev_p) { 677 *prev_p = prev; 678 } 679 return next; 680 } 681 682 uint16_t pcie_find_capability(PCIDevice *dev, uint16_t cap_id) 683 { 684 return pcie_find_capability_list(dev, cap_id, NULL); 685 } 686 687 static void pcie_ext_cap_set_next(PCIDevice *dev, uint16_t pos, uint16_t next) 688 { 689 uint32_t header = pci_get_long(dev->config + pos); 690 assert(!(next & (PCI_EXT_CAP_ALIGN - 1))); 691 header = (header & ~PCI_EXT_CAP_NEXT_MASK) | 692 ((next << PCI_EXT_CAP_NEXT_SHIFT) & PCI_EXT_CAP_NEXT_MASK); 693 pci_set_long(dev->config + pos, header); 694 } 695 696 /* 697 * Caller must supply valid (offset, size) such that the range wouldn't 698 * overlap with other capability or other registers. 699 * This function doesn't check it. 700 */ 701 void pcie_add_capability(PCIDevice *dev, 702 uint16_t cap_id, uint8_t cap_ver, 703 uint16_t offset, uint16_t size) 704 { 705 assert(offset >= PCI_CONFIG_SPACE_SIZE); 706 assert(offset < offset + size); 707 assert(offset + size <= PCIE_CONFIG_SPACE_SIZE); 708 assert(size >= 8); 709 assert(pci_is_express(dev)); 710 711 if (offset != PCI_CONFIG_SPACE_SIZE) { 712 uint16_t prev; 713 714 /* 715 * 0xffffffff is not a valid cap id (it's a 16 bit field). use 716 * internally to find the last capability in the linked list. 717 */ 718 pcie_find_capability_list(dev, 0xffffffff, &prev); 719 assert(prev >= PCI_CONFIG_SPACE_SIZE); 720 pcie_ext_cap_set_next(dev, prev, offset); 721 } 722 pci_set_long(dev->config + offset, PCI_EXT_CAP(cap_id, cap_ver, 0)); 723 724 /* Make capability read-only by default */ 725 memset(dev->wmask + offset, 0, size); 726 memset(dev->w1cmask + offset, 0, size); 727 /* Check capability by default */ 728 memset(dev->cmask + offset, 0xFF, size); 729 } 730 731 /************************************************************************** 732 * pci express extended capability helper functions 733 */ 734 735 /* ARI */ 736 void pcie_ari_init(PCIDevice *dev, uint16_t offset, uint16_t nextfn) 737 { 738 pcie_add_capability(dev, PCI_EXT_CAP_ID_ARI, PCI_ARI_VER, 739 offset, PCI_ARI_SIZEOF); 740 pci_set_long(dev->config + offset + PCI_ARI_CAP, (nextfn & 0xff) << 8); 741 } 742 743 void pcie_dev_ser_num_init(PCIDevice *dev, uint16_t offset, uint64_t ser_num) 744 { 745 static const int pci_dsn_ver = 1; 746 static const int pci_dsn_cap = 4; 747 748 pcie_add_capability(dev, PCI_EXT_CAP_ID_DSN, pci_dsn_ver, offset, 749 PCI_EXT_CAP_DSN_SIZEOF); 750 pci_set_quad(dev->config + offset + pci_dsn_cap, ser_num); 751 } 752 753 void pcie_ats_init(PCIDevice *dev, uint16_t offset) 754 { 755 pcie_add_capability(dev, PCI_EXT_CAP_ID_ATS, 0x1, 756 offset, PCI_EXT_CAP_ATS_SIZEOF); 757 758 dev->exp.ats_cap = offset; 759 760 /* Invalidate Queue Depth 0, Page Aligned Request 0 */ 761 pci_set_word(dev->config + offset + PCI_ATS_CAP, 0); 762 /* STU 0, Disabled by default */ 763 pci_set_word(dev->config + offset + PCI_ATS_CTRL, 0); 764 765 pci_set_word(dev->wmask + dev->exp.ats_cap + PCI_ATS_CTRL, 0x800f); 766 } 767