1 /* 2 * pcie.c 3 * 4 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp> 5 * VA Linux Systems Japan K.K. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu-common.h" 22 #include "hw/pci/pci_bridge.h" 23 #include "hw/pci/pcie.h" 24 #include "hw/pci/msix.h" 25 #include "hw/pci/msi.h" 26 #include "hw/pci/pci_bus.h" 27 #include "hw/pci/pcie_regs.h" 28 #include "qemu/range.h" 29 #include "qapi/qmp/qerror.h" 30 31 //#define DEBUG_PCIE 32 #ifdef DEBUG_PCIE 33 # define PCIE_DPRINTF(fmt, ...) \ 34 fprintf(stderr, "%s:%d " fmt, __func__, __LINE__, ## __VA_ARGS__) 35 #else 36 # define PCIE_DPRINTF(fmt, ...) do {} while (0) 37 #endif 38 #define PCIE_DEV_PRINTF(dev, fmt, ...) \ 39 PCIE_DPRINTF("%s:%x "fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__) 40 41 42 /*************************************************************************** 43 * pci express capability helper functions 44 */ 45 int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, uint8_t port) 46 { 47 int pos; 48 uint8_t *exp_cap; 49 50 assert(pci_is_express(dev)); 51 52 pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset, 53 PCI_EXP_VER2_SIZEOF); 54 if (pos < 0) { 55 return pos; 56 } 57 dev->exp.exp_cap = pos; 58 exp_cap = dev->config + pos; 59 60 /* capability register 61 interrupt message number defaults to 0 */ 62 pci_set_word(exp_cap + PCI_EXP_FLAGS, 63 ((type << PCI_EXP_FLAGS_TYPE_SHIFT) & PCI_EXP_FLAGS_TYPE) | 64 PCI_EXP_FLAGS_VER2); 65 66 /* device capability register 67 * table 7-12: 68 * roll based error reporting bit must be set by all 69 * Functions conforming to the ECN, PCI Express Base 70 * Specification, Revision 1.1., or subsequent PCI Express Base 71 * Specification revisions. 72 */ 73 pci_set_long(exp_cap + PCI_EXP_DEVCAP, PCI_EXP_DEVCAP_RBER); 74 75 pci_set_long(exp_cap + PCI_EXP_LNKCAP, 76 (port << PCI_EXP_LNKCAP_PN_SHIFT) | 77 PCI_EXP_LNKCAP_ASPMS_0S | 78 PCI_EXP_LNK_MLW_1 | 79 PCI_EXP_LNK_LS_25); 80 81 pci_set_word(exp_cap + PCI_EXP_LNKSTA, 82 PCI_EXP_LNK_MLW_1 | PCI_EXP_LNK_LS_25); 83 84 pci_set_long(exp_cap + PCI_EXP_DEVCAP2, 85 PCI_EXP_DEVCAP2_EFF | PCI_EXP_DEVCAP2_EETLPP); 86 87 pci_set_word(dev->wmask + pos, PCI_EXP_DEVCTL2_EETLPPB); 88 return pos; 89 } 90 91 int pcie_endpoint_cap_init(PCIDevice *dev, uint8_t offset) 92 { 93 uint8_t type = PCI_EXP_TYPE_ENDPOINT; 94 95 /* 96 * Windows guests will report Code 10, device cannot start, if 97 * a regular Endpoint type is exposed on a root complex. These 98 * should instead be Root Complex Integrated Endpoints. 99 */ 100 if (pci_bus_is_express(dev->bus) && pci_bus_is_root(dev->bus)) { 101 type = PCI_EXP_TYPE_RC_END; 102 } 103 104 return pcie_cap_init(dev, offset, type, 0); 105 } 106 107 void pcie_cap_exit(PCIDevice *dev) 108 { 109 pci_del_capability(dev, PCI_CAP_ID_EXP, PCI_EXP_VER2_SIZEOF); 110 } 111 112 uint8_t pcie_cap_get_type(const PCIDevice *dev) 113 { 114 uint32_t pos = dev->exp.exp_cap; 115 assert(pos > 0); 116 return (pci_get_word(dev->config + pos + PCI_EXP_FLAGS) & 117 PCI_EXP_FLAGS_TYPE) >> PCI_EXP_FLAGS_TYPE_SHIFT; 118 } 119 120 /* MSI/MSI-X */ 121 /* pci express interrupt message number */ 122 /* 7.8.2 PCI Express Capabilities Register: Interrupt Message Number */ 123 void pcie_cap_flags_set_vector(PCIDevice *dev, uint8_t vector) 124 { 125 uint8_t *exp_cap = dev->config + dev->exp.exp_cap; 126 assert(vector < 32); 127 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_FLAGS, PCI_EXP_FLAGS_IRQ); 128 pci_word_test_and_set_mask(exp_cap + PCI_EXP_FLAGS, 129 vector << PCI_EXP_FLAGS_IRQ_SHIFT); 130 } 131 132 uint8_t pcie_cap_flags_get_vector(PCIDevice *dev) 133 { 134 return (pci_get_word(dev->config + dev->exp.exp_cap + PCI_EXP_FLAGS) & 135 PCI_EXP_FLAGS_IRQ) >> PCI_EXP_FLAGS_IRQ_SHIFT; 136 } 137 138 void pcie_cap_deverr_init(PCIDevice *dev) 139 { 140 uint32_t pos = dev->exp.exp_cap; 141 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP, 142 PCI_EXP_DEVCAP_RBER); 143 pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL, 144 PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | 145 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE); 146 pci_long_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_DEVSTA, 147 PCI_EXP_DEVSTA_CED | PCI_EXP_DEVSTA_NFED | 148 PCI_EXP_DEVSTA_URD | PCI_EXP_DEVSTA_URD); 149 } 150 151 void pcie_cap_deverr_reset(PCIDevice *dev) 152 { 153 uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL; 154 pci_long_test_and_clear_mask(devctl, 155 PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | 156 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE); 157 } 158 159 static void hotplug_event_update_event_status(PCIDevice *dev) 160 { 161 uint32_t pos = dev->exp.exp_cap; 162 uint8_t *exp_cap = dev->config + pos; 163 uint16_t sltctl = pci_get_word(exp_cap + PCI_EXP_SLTCTL); 164 uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA); 165 166 dev->exp.hpev_notified = (sltctl & PCI_EXP_SLTCTL_HPIE) && 167 (sltsta & sltctl & PCI_EXP_HP_EV_SUPPORTED); 168 } 169 170 static void hotplug_event_notify(PCIDevice *dev) 171 { 172 bool prev = dev->exp.hpev_notified; 173 174 hotplug_event_update_event_status(dev); 175 176 if (prev == dev->exp.hpev_notified) { 177 return; 178 } 179 180 /* Note: the logic above does not take into account whether interrupts 181 * are masked. The result is that interrupt will be sent when it is 182 * subsequently unmasked. This appears to be legal: Section 6.7.3.4: 183 * The Port may optionally send an MSI when there are hot-plug events that 184 * occur while interrupt generation is disabled, and interrupt generation is 185 * subsequently enabled. */ 186 if (msix_enabled(dev)) { 187 msix_notify(dev, pcie_cap_flags_get_vector(dev)); 188 } else if (msi_enabled(dev)) { 189 msi_notify(dev, pcie_cap_flags_get_vector(dev)); 190 } else { 191 pci_set_irq(dev, dev->exp.hpev_notified); 192 } 193 } 194 195 static void hotplug_event_clear(PCIDevice *dev) 196 { 197 hotplug_event_update_event_status(dev); 198 if (!msix_enabled(dev) && !msi_enabled(dev) && !dev->exp.hpev_notified) { 199 pci_irq_deassert(dev); 200 } 201 } 202 203 /* 204 * A PCI Express Hot-Plug Event has occurred, so update slot status register 205 * and notify OS of the event if necessary. 206 * 207 * 6.7.3 PCI Express Hot-Plug Events 208 * 6.7.3.4 Software Notification of Hot-Plug Events 209 */ 210 static void pcie_cap_slot_event(PCIDevice *dev, PCIExpressHotPlugEvent event) 211 { 212 /* Minor optimization: if nothing changed - no event is needed. */ 213 if (pci_word_test_and_set_mask(dev->config + dev->exp.exp_cap + 214 PCI_EXP_SLTSTA, event)) { 215 return; 216 } 217 hotplug_event_notify(dev); 218 } 219 220 static void pcie_cap_slot_hotplug_common(PCIDevice *hotplug_dev, 221 DeviceState *dev, 222 uint8_t **exp_cap, Error **errp) 223 { 224 PCIDevice *pci_dev = PCI_DEVICE(dev); 225 *exp_cap = hotplug_dev->config + hotplug_dev->exp.exp_cap; 226 uint16_t sltsta = pci_get_word(*exp_cap + PCI_EXP_SLTSTA); 227 228 PCIE_DEV_PRINTF(pci_dev, "hotplug state: %d\n", state); 229 if (sltsta & PCI_EXP_SLTSTA_EIS) { 230 /* the slot is electromechanically locked. 231 * This error is propagated up to qdev and then to HMP/QMP. 232 */ 233 error_setg_errno(errp, -EBUSY, "slot is electromechanically locked"); 234 } 235 236 /* TODO: multifunction hot-plug. 237 * Right now, only a device of function = 0 is allowed to be 238 * hot plugged/unplugged. 239 */ 240 assert(PCI_FUNC(pci_dev->devfn) == 0); 241 } 242 243 void pcie_cap_slot_hotplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, 244 Error **errp) 245 { 246 uint8_t *exp_cap; 247 248 pcie_cap_slot_hotplug_common(PCI_DEVICE(hotplug_dev), dev, &exp_cap, errp); 249 250 /* Don't send event when device is enabled during qemu machine creation: 251 * it is present on boot, no hotplug event is necessary. We do send an 252 * event when the device is disabled later. */ 253 if (!dev->hotplugged) { 254 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA, 255 PCI_EXP_SLTSTA_PDS); 256 return; 257 } 258 259 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA, 260 PCI_EXP_SLTSTA_PDS); 261 pcie_cap_slot_event(PCI_DEVICE(hotplug_dev), PCI_EXP_HP_EV_PDC); 262 } 263 264 void pcie_cap_slot_hot_unplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, 265 Error **errp) 266 { 267 uint8_t *exp_cap; 268 269 pcie_cap_slot_hotplug_common(PCI_DEVICE(hotplug_dev), dev, &exp_cap, errp); 270 271 object_unparent(OBJECT(dev)); 272 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA, 273 PCI_EXP_SLTSTA_PDS); 274 pcie_cap_slot_event(PCI_DEVICE(hotplug_dev), PCI_EXP_HP_EV_PDC); 275 } 276 277 /* pci express slot for pci express root/downstream port 278 PCI express capability slot registers */ 279 void pcie_cap_slot_init(PCIDevice *dev, uint16_t slot) 280 { 281 uint32_t pos = dev->exp.exp_cap; 282 283 pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_FLAGS, 284 PCI_EXP_FLAGS_SLOT); 285 286 pci_long_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCAP, 287 ~PCI_EXP_SLTCAP_PSN); 288 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP, 289 (slot << PCI_EXP_SLTCAP_PSN_SHIFT) | 290 PCI_EXP_SLTCAP_EIP | 291 PCI_EXP_SLTCAP_HPS | 292 PCI_EXP_SLTCAP_HPC | 293 PCI_EXP_SLTCAP_PIP | 294 PCI_EXP_SLTCAP_AIP | 295 PCI_EXP_SLTCAP_ABP); 296 297 pci_word_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCTL, 298 PCI_EXP_SLTCTL_PIC | 299 PCI_EXP_SLTCTL_AIC); 300 pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCTL, 301 PCI_EXP_SLTCTL_PIC_OFF | 302 PCI_EXP_SLTCTL_AIC_OFF); 303 pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL, 304 PCI_EXP_SLTCTL_PIC | 305 PCI_EXP_SLTCTL_AIC | 306 PCI_EXP_SLTCTL_HPIE | 307 PCI_EXP_SLTCTL_CCIE | 308 PCI_EXP_SLTCTL_PDCE | 309 PCI_EXP_SLTCTL_ABPE); 310 /* Although reading PCI_EXP_SLTCTL_EIC returns always 0, 311 * make the bit writable here in order to detect 1b is written. 312 * pcie_cap_slot_write_config() test-and-clear the bit, so 313 * this bit always returns 0 to the guest. 314 */ 315 pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL, 316 PCI_EXP_SLTCTL_EIC); 317 318 pci_word_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_SLTSTA, 319 PCI_EXP_HP_EV_SUPPORTED); 320 321 dev->exp.hpev_notified = false; 322 323 qbus_set_hotplug_handler(BUS(pci_bridge_get_sec_bus(PCI_BRIDGE(dev))), 324 DEVICE(dev), NULL); 325 } 326 327 void pcie_cap_slot_reset(PCIDevice *dev) 328 { 329 uint8_t *exp_cap = dev->config + dev->exp.exp_cap; 330 331 PCIE_DEV_PRINTF(dev, "reset\n"); 332 333 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL, 334 PCI_EXP_SLTCTL_EIC | 335 PCI_EXP_SLTCTL_PIC | 336 PCI_EXP_SLTCTL_AIC | 337 PCI_EXP_SLTCTL_HPIE | 338 PCI_EXP_SLTCTL_CCIE | 339 PCI_EXP_SLTCTL_PDCE | 340 PCI_EXP_SLTCTL_ABPE); 341 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL, 342 PCI_EXP_SLTCTL_PIC_OFF | 343 PCI_EXP_SLTCTL_AIC_OFF); 344 345 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA, 346 PCI_EXP_SLTSTA_EIS |/* on reset, 347 the lock is released */ 348 PCI_EXP_SLTSTA_CC | 349 PCI_EXP_SLTSTA_PDC | 350 PCI_EXP_SLTSTA_ABP); 351 352 hotplug_event_update_event_status(dev); 353 } 354 355 void pcie_cap_slot_write_config(PCIDevice *dev, 356 uint32_t addr, uint32_t val, int len) 357 { 358 uint32_t pos = dev->exp.exp_cap; 359 uint8_t *exp_cap = dev->config + pos; 360 uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA); 361 362 if (ranges_overlap(addr, len, pos + PCI_EXP_SLTSTA, 2)) { 363 hotplug_event_clear(dev); 364 } 365 366 if (!ranges_overlap(addr, len, pos + PCI_EXP_SLTCTL, 2)) { 367 return; 368 } 369 370 if (pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL, 371 PCI_EXP_SLTCTL_EIC)) { 372 sltsta ^= PCI_EXP_SLTSTA_EIS; /* toggle PCI_EXP_SLTSTA_EIS bit */ 373 pci_set_word(exp_cap + PCI_EXP_SLTSTA, sltsta); 374 PCIE_DEV_PRINTF(dev, "PCI_EXP_SLTCTL_EIC: " 375 "sltsta -> 0x%02"PRIx16"\n", 376 sltsta); 377 } 378 379 hotplug_event_notify(dev); 380 381 /* 382 * 6.7.3.2 Command Completed Events 383 * 384 * Software issues a command to a hot-plug capable Downstream Port by 385 * issuing a write transaction that targets any portion of the Port’s Slot 386 * Control register. A single write to the Slot Control register is 387 * considered to be a single command, even if the write affects more than 388 * one field in the Slot Control register. In response to this transaction, 389 * the Port must carry out the requested actions and then set the 390 * associated status field for the command completed event. */ 391 392 /* Real hardware might take a while to complete requested command because 393 * physical movement would be involved like locking the electromechanical 394 * lock. However in our case, command is completed instantaneously above, 395 * so send a command completion event right now. 396 */ 397 pcie_cap_slot_event(dev, PCI_EXP_HP_EV_CCI); 398 } 399 400 int pcie_cap_slot_post_load(void *opaque, int version_id) 401 { 402 PCIDevice *dev = opaque; 403 hotplug_event_update_event_status(dev); 404 return 0; 405 } 406 407 void pcie_cap_slot_push_attention_button(PCIDevice *dev) 408 { 409 pcie_cap_slot_event(dev, PCI_EXP_HP_EV_ABP); 410 } 411 412 /* root control/capabilities/status. PME isn't emulated for now */ 413 void pcie_cap_root_init(PCIDevice *dev) 414 { 415 pci_set_word(dev->wmask + dev->exp.exp_cap + PCI_EXP_RTCTL, 416 PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE | 417 PCI_EXP_RTCTL_SEFEE); 418 } 419 420 void pcie_cap_root_reset(PCIDevice *dev) 421 { 422 pci_set_word(dev->config + dev->exp.exp_cap + PCI_EXP_RTCTL, 0); 423 } 424 425 /* function level reset(FLR) */ 426 void pcie_cap_flr_init(PCIDevice *dev) 427 { 428 pci_long_test_and_set_mask(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCAP, 429 PCI_EXP_DEVCAP_FLR); 430 431 /* Although reading BCR_FLR returns always 0, 432 * the bit is made writable here in order to detect the 1b is written 433 * pcie_cap_flr_write_config() test-and-clear the bit, so 434 * this bit always returns 0 to the guest. 435 */ 436 pci_word_test_and_set_mask(dev->wmask + dev->exp.exp_cap + PCI_EXP_DEVCTL, 437 PCI_EXP_DEVCTL_BCR_FLR); 438 } 439 440 void pcie_cap_flr_write_config(PCIDevice *dev, 441 uint32_t addr, uint32_t val, int len) 442 { 443 uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL; 444 if (pci_get_word(devctl) & PCI_EXP_DEVCTL_BCR_FLR) { 445 /* Clear PCI_EXP_DEVCTL_BCR_FLR after invoking the reset handler 446 so the handler can detect FLR by looking at this bit. */ 447 pci_device_reset(dev); 448 pci_word_test_and_clear_mask(devctl, PCI_EXP_DEVCTL_BCR_FLR); 449 } 450 } 451 452 /* Alternative Routing-ID Interpretation (ARI) */ 453 /* ari forwarding support for down stream port */ 454 void pcie_cap_ari_init(PCIDevice *dev) 455 { 456 uint32_t pos = dev->exp.exp_cap; 457 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP2, 458 PCI_EXP_DEVCAP2_ARI); 459 pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL2, 460 PCI_EXP_DEVCTL2_ARI); 461 } 462 463 void pcie_cap_ari_reset(PCIDevice *dev) 464 { 465 uint8_t *devctl2 = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2; 466 pci_long_test_and_clear_mask(devctl2, PCI_EXP_DEVCTL2_ARI); 467 } 468 469 bool pcie_cap_is_ari_enabled(const PCIDevice *dev) 470 { 471 if (!pci_is_express(dev)) { 472 return false; 473 } 474 if (!dev->exp.exp_cap) { 475 return false; 476 } 477 478 return pci_get_long(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2) & 479 PCI_EXP_DEVCTL2_ARI; 480 } 481 482 /************************************************************************** 483 * pci express extended capability allocation functions 484 * uint16_t ext_cap_id (16 bit) 485 * uint8_t cap_ver (4 bit) 486 * uint16_t cap_offset (12 bit) 487 * uint16_t ext_cap_size 488 */ 489 490 static uint16_t pcie_find_capability_list(PCIDevice *dev, uint16_t cap_id, 491 uint16_t *prev_p) 492 { 493 uint16_t prev = 0; 494 uint16_t next; 495 uint32_t header = pci_get_long(dev->config + PCI_CONFIG_SPACE_SIZE); 496 497 if (!header) { 498 /* no extended capability */ 499 next = 0; 500 goto out; 501 } 502 for (next = PCI_CONFIG_SPACE_SIZE; next; 503 prev = next, next = PCI_EXT_CAP_NEXT(header)) { 504 505 assert(next >= PCI_CONFIG_SPACE_SIZE); 506 assert(next <= PCIE_CONFIG_SPACE_SIZE - 8); 507 508 header = pci_get_long(dev->config + next); 509 if (PCI_EXT_CAP_ID(header) == cap_id) { 510 break; 511 } 512 } 513 514 out: 515 if (prev_p) { 516 *prev_p = prev; 517 } 518 return next; 519 } 520 521 uint16_t pcie_find_capability(PCIDevice *dev, uint16_t cap_id) 522 { 523 return pcie_find_capability_list(dev, cap_id, NULL); 524 } 525 526 static void pcie_ext_cap_set_next(PCIDevice *dev, uint16_t pos, uint16_t next) 527 { 528 uint32_t header = pci_get_long(dev->config + pos); 529 assert(!(next & (PCI_EXT_CAP_ALIGN - 1))); 530 header = (header & ~PCI_EXT_CAP_NEXT_MASK) | 531 ((next << PCI_EXT_CAP_NEXT_SHIFT) & PCI_EXT_CAP_NEXT_MASK); 532 pci_set_long(dev->config + pos, header); 533 } 534 535 /* 536 * caller must supply valid (offset, size) * such that the range shouldn't 537 * overlap with other capability or other registers. 538 * This function doesn't check it. 539 */ 540 void pcie_add_capability(PCIDevice *dev, 541 uint16_t cap_id, uint8_t cap_ver, 542 uint16_t offset, uint16_t size) 543 { 544 uint32_t header; 545 uint16_t next; 546 547 assert(offset >= PCI_CONFIG_SPACE_SIZE); 548 assert(offset < offset + size); 549 assert(offset + size < PCIE_CONFIG_SPACE_SIZE); 550 assert(size >= 8); 551 assert(pci_is_express(dev)); 552 553 if (offset == PCI_CONFIG_SPACE_SIZE) { 554 header = pci_get_long(dev->config + offset); 555 next = PCI_EXT_CAP_NEXT(header); 556 } else { 557 uint16_t prev; 558 559 /* 0 is reserved cap id. use internally to find the last capability 560 in the linked list */ 561 next = pcie_find_capability_list(dev, 0, &prev); 562 563 assert(prev >= PCI_CONFIG_SPACE_SIZE); 564 assert(next == 0); 565 pcie_ext_cap_set_next(dev, prev, offset); 566 } 567 pci_set_long(dev->config + offset, PCI_EXT_CAP(cap_id, cap_ver, next)); 568 569 /* Make capability read-only by default */ 570 memset(dev->wmask + offset, 0, size); 571 memset(dev->w1cmask + offset, 0, size); 572 /* Check capability by default */ 573 memset(dev->cmask + offset, 0xFF, size); 574 } 575 576 /************************************************************************** 577 * pci express extended capability helper functions 578 */ 579 580 /* ARI */ 581 void pcie_ari_init(PCIDevice *dev, uint16_t offset, uint16_t nextfn) 582 { 583 pcie_add_capability(dev, PCI_EXT_CAP_ID_ARI, PCI_ARI_VER, 584 offset, PCI_ARI_SIZEOF); 585 pci_set_long(dev->config + offset + PCI_ARI_CAP, PCI_ARI_CAP_NFN(nextfn)); 586 } 587