1 /* 2 * pcie.c 3 * 4 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp> 5 * VA Linux Systems Japan K.K. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu-common.h" 22 #include "hw/pci/pci_bridge.h" 23 #include "hw/pci/pcie.h" 24 #include "hw/pci/msix.h" 25 #include "hw/pci/msi.h" 26 #include "hw/pci/pci_bus.h" 27 #include "hw/pci/pcie_regs.h" 28 #include "qemu/range.h" 29 30 //#define DEBUG_PCIE 31 #ifdef DEBUG_PCIE 32 # define PCIE_DPRINTF(fmt, ...) \ 33 fprintf(stderr, "%s:%d " fmt, __func__, __LINE__, ## __VA_ARGS__) 34 #else 35 # define PCIE_DPRINTF(fmt, ...) do {} while (0) 36 #endif 37 #define PCIE_DEV_PRINTF(dev, fmt, ...) \ 38 PCIE_DPRINTF("%s:%x "fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__) 39 40 41 /*************************************************************************** 42 * pci express capability helper functions 43 */ 44 int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, uint8_t port) 45 { 46 int pos; 47 uint8_t *exp_cap; 48 49 assert(pci_is_express(dev)); 50 51 pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset, 52 PCI_EXP_VER2_SIZEOF); 53 if (pos < 0) { 54 return pos; 55 } 56 dev->exp.exp_cap = pos; 57 exp_cap = dev->config + pos; 58 59 /* capability register 60 interrupt message number defaults to 0 */ 61 pci_set_word(exp_cap + PCI_EXP_FLAGS, 62 ((type << PCI_EXP_FLAGS_TYPE_SHIFT) & PCI_EXP_FLAGS_TYPE) | 63 PCI_EXP_FLAGS_VER2); 64 65 /* device capability register 66 * table 7-12: 67 * roll based error reporting bit must be set by all 68 * Functions conforming to the ECN, PCI Express Base 69 * Specification, Revision 1.1., or subsequent PCI Express Base 70 * Specification revisions. 71 */ 72 pci_set_long(exp_cap + PCI_EXP_DEVCAP, PCI_EXP_DEVCAP_RBER); 73 74 pci_set_long(exp_cap + PCI_EXP_LNKCAP, 75 (port << PCI_EXP_LNKCAP_PN_SHIFT) | 76 PCI_EXP_LNKCAP_ASPMS_0S | 77 PCI_EXP_LNK_MLW_1 | 78 PCI_EXP_LNK_LS_25); 79 80 pci_set_word(exp_cap + PCI_EXP_LNKSTA, 81 PCI_EXP_LNK_MLW_1 | PCI_EXP_LNK_LS_25 |PCI_EXP_LNKSTA_DLLLA); 82 83 pci_set_long(exp_cap + PCI_EXP_DEVCAP2, 84 PCI_EXP_DEVCAP2_EFF | PCI_EXP_DEVCAP2_EETLPP); 85 86 pci_set_word(dev->wmask + pos + PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_EETLPPB); 87 return pos; 88 } 89 90 int pcie_endpoint_cap_init(PCIDevice *dev, uint8_t offset) 91 { 92 uint8_t type = PCI_EXP_TYPE_ENDPOINT; 93 94 /* 95 * Windows guests will report Code 10, device cannot start, if 96 * a regular Endpoint type is exposed on a root complex. These 97 * should instead be Root Complex Integrated Endpoints. 98 */ 99 if (pci_bus_is_express(dev->bus) && pci_bus_is_root(dev->bus)) { 100 type = PCI_EXP_TYPE_RC_END; 101 } 102 103 return pcie_cap_init(dev, offset, type, 0); 104 } 105 106 void pcie_cap_exit(PCIDevice *dev) 107 { 108 pci_del_capability(dev, PCI_CAP_ID_EXP, PCI_EXP_VER2_SIZEOF); 109 } 110 111 uint8_t pcie_cap_get_type(const PCIDevice *dev) 112 { 113 uint32_t pos = dev->exp.exp_cap; 114 assert(pos > 0); 115 return (pci_get_word(dev->config + pos + PCI_EXP_FLAGS) & 116 PCI_EXP_FLAGS_TYPE) >> PCI_EXP_FLAGS_TYPE_SHIFT; 117 } 118 119 /* MSI/MSI-X */ 120 /* pci express interrupt message number */ 121 /* 7.8.2 PCI Express Capabilities Register: Interrupt Message Number */ 122 void pcie_cap_flags_set_vector(PCIDevice *dev, uint8_t vector) 123 { 124 uint8_t *exp_cap = dev->config + dev->exp.exp_cap; 125 assert(vector < 32); 126 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_FLAGS, PCI_EXP_FLAGS_IRQ); 127 pci_word_test_and_set_mask(exp_cap + PCI_EXP_FLAGS, 128 vector << PCI_EXP_FLAGS_IRQ_SHIFT); 129 } 130 131 uint8_t pcie_cap_flags_get_vector(PCIDevice *dev) 132 { 133 return (pci_get_word(dev->config + dev->exp.exp_cap + PCI_EXP_FLAGS) & 134 PCI_EXP_FLAGS_IRQ) >> PCI_EXP_FLAGS_IRQ_SHIFT; 135 } 136 137 void pcie_cap_deverr_init(PCIDevice *dev) 138 { 139 uint32_t pos = dev->exp.exp_cap; 140 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP, 141 PCI_EXP_DEVCAP_RBER); 142 pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL, 143 PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | 144 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE); 145 pci_long_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_DEVSTA, 146 PCI_EXP_DEVSTA_CED | PCI_EXP_DEVSTA_NFED | 147 PCI_EXP_DEVSTA_FED | PCI_EXP_DEVSTA_URD); 148 } 149 150 void pcie_cap_deverr_reset(PCIDevice *dev) 151 { 152 uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL; 153 pci_long_test_and_clear_mask(devctl, 154 PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | 155 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE); 156 } 157 158 static void hotplug_event_update_event_status(PCIDevice *dev) 159 { 160 uint32_t pos = dev->exp.exp_cap; 161 uint8_t *exp_cap = dev->config + pos; 162 uint16_t sltctl = pci_get_word(exp_cap + PCI_EXP_SLTCTL); 163 uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA); 164 165 dev->exp.hpev_notified = (sltctl & PCI_EXP_SLTCTL_HPIE) && 166 (sltsta & sltctl & PCI_EXP_HP_EV_SUPPORTED); 167 } 168 169 static void hotplug_event_notify(PCIDevice *dev) 170 { 171 bool prev = dev->exp.hpev_notified; 172 173 hotplug_event_update_event_status(dev); 174 175 if (prev == dev->exp.hpev_notified) { 176 return; 177 } 178 179 /* Note: the logic above does not take into account whether interrupts 180 * are masked. The result is that interrupt will be sent when it is 181 * subsequently unmasked. This appears to be legal: Section 6.7.3.4: 182 * The Port may optionally send an MSI when there are hot-plug events that 183 * occur while interrupt generation is disabled, and interrupt generation is 184 * subsequently enabled. */ 185 if (msix_enabled(dev)) { 186 msix_notify(dev, pcie_cap_flags_get_vector(dev)); 187 } else if (msi_enabled(dev)) { 188 msi_notify(dev, pcie_cap_flags_get_vector(dev)); 189 } else { 190 pci_set_irq(dev, dev->exp.hpev_notified); 191 } 192 } 193 194 static void hotplug_event_clear(PCIDevice *dev) 195 { 196 hotplug_event_update_event_status(dev); 197 if (!msix_enabled(dev) && !msi_enabled(dev) && !dev->exp.hpev_notified) { 198 pci_irq_deassert(dev); 199 } 200 } 201 202 /* 203 * A PCI Express Hot-Plug Event has occurred, so update slot status register 204 * and notify OS of the event if necessary. 205 * 206 * 6.7.3 PCI Express Hot-Plug Events 207 * 6.7.3.4 Software Notification of Hot-Plug Events 208 */ 209 static void pcie_cap_slot_event(PCIDevice *dev, PCIExpressHotPlugEvent event) 210 { 211 /* Minor optimization: if nothing changed - no event is needed. */ 212 if (pci_word_test_and_set_mask(dev->config + dev->exp.exp_cap + 213 PCI_EXP_SLTSTA, event)) { 214 return; 215 } 216 hotplug_event_notify(dev); 217 } 218 219 static void pcie_cap_slot_hotplug_common(PCIDevice *hotplug_dev, 220 DeviceState *dev, 221 uint8_t **exp_cap, Error **errp) 222 { 223 *exp_cap = hotplug_dev->config + hotplug_dev->exp.exp_cap; 224 uint16_t sltsta = pci_get_word(*exp_cap + PCI_EXP_SLTSTA); 225 226 PCIE_DEV_PRINTF(PCI_DEVICE(dev), "hotplug state: 0x%x\n", sltsta); 227 if (sltsta & PCI_EXP_SLTSTA_EIS) { 228 /* the slot is electromechanically locked. 229 * This error is propagated up to qdev and then to HMP/QMP. 230 */ 231 error_setg_errno(errp, EBUSY, "slot is electromechanically locked"); 232 } 233 } 234 235 void pcie_cap_slot_hotplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, 236 Error **errp) 237 { 238 uint8_t *exp_cap; 239 PCIDevice *pci_dev = PCI_DEVICE(dev); 240 241 pcie_cap_slot_hotplug_common(PCI_DEVICE(hotplug_dev), dev, &exp_cap, errp); 242 243 /* Don't send event when device is enabled during qemu machine creation: 244 * it is present on boot, no hotplug event is necessary. We do send an 245 * event when the device is disabled later. */ 246 if (!dev->hotplugged) { 247 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA, 248 PCI_EXP_SLTSTA_PDS); 249 return; 250 } 251 252 /* TODO: multifunction hot-plug. 253 * Right now, only a device of function = 0 is allowed to be 254 * hot plugged/unplugged. 255 */ 256 assert(PCI_FUNC(pci_dev->devfn) == 0); 257 258 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA, 259 PCI_EXP_SLTSTA_PDS); 260 pcie_cap_slot_event(PCI_DEVICE(hotplug_dev), 261 PCI_EXP_HP_EV_PDC | PCI_EXP_HP_EV_ABP); 262 } 263 264 void pcie_cap_slot_hot_unplug_request_cb(HotplugHandler *hotplug_dev, 265 DeviceState *dev, Error **errp) 266 { 267 uint8_t *exp_cap; 268 269 pcie_cap_slot_hotplug_common(PCI_DEVICE(hotplug_dev), dev, &exp_cap, errp); 270 271 pcie_cap_slot_push_attention_button(PCI_DEVICE(hotplug_dev)); 272 } 273 274 /* pci express slot for pci express root/downstream port 275 PCI express capability slot registers */ 276 void pcie_cap_slot_init(PCIDevice *dev, uint16_t slot) 277 { 278 uint32_t pos = dev->exp.exp_cap; 279 280 pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_FLAGS, 281 PCI_EXP_FLAGS_SLOT); 282 283 pci_long_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCAP, 284 ~PCI_EXP_SLTCAP_PSN); 285 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP, 286 (slot << PCI_EXP_SLTCAP_PSN_SHIFT) | 287 PCI_EXP_SLTCAP_EIP | 288 PCI_EXP_SLTCAP_HPS | 289 PCI_EXP_SLTCAP_HPC | 290 PCI_EXP_SLTCAP_PIP | 291 PCI_EXP_SLTCAP_AIP | 292 PCI_EXP_SLTCAP_ABP); 293 294 if (dev->cap_present & QEMU_PCIE_SLTCAP_PCP) { 295 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP, 296 PCI_EXP_SLTCAP_PCP); 297 pci_word_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCTL, 298 PCI_EXP_SLTCTL_PCC); 299 pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL, 300 PCI_EXP_SLTCTL_PCC); 301 } 302 303 pci_word_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCTL, 304 PCI_EXP_SLTCTL_PIC | 305 PCI_EXP_SLTCTL_AIC); 306 pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCTL, 307 PCI_EXP_SLTCTL_PIC_OFF | 308 PCI_EXP_SLTCTL_AIC_OFF); 309 pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL, 310 PCI_EXP_SLTCTL_PIC | 311 PCI_EXP_SLTCTL_AIC | 312 PCI_EXP_SLTCTL_HPIE | 313 PCI_EXP_SLTCTL_CCIE | 314 PCI_EXP_SLTCTL_PDCE | 315 PCI_EXP_SLTCTL_ABPE); 316 /* Although reading PCI_EXP_SLTCTL_EIC returns always 0, 317 * make the bit writable here in order to detect 1b is written. 318 * pcie_cap_slot_write_config() test-and-clear the bit, so 319 * this bit always returns 0 to the guest. 320 */ 321 pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL, 322 PCI_EXP_SLTCTL_EIC); 323 324 pci_word_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_SLTSTA, 325 PCI_EXP_HP_EV_SUPPORTED); 326 327 dev->exp.hpev_notified = false; 328 329 qbus_set_hotplug_handler(BUS(pci_bridge_get_sec_bus(PCI_BRIDGE(dev))), 330 DEVICE(dev), NULL); 331 } 332 333 void pcie_cap_slot_reset(PCIDevice *dev) 334 { 335 uint8_t *exp_cap = dev->config + dev->exp.exp_cap; 336 uint8_t port_type = pcie_cap_get_type(dev); 337 338 assert(port_type == PCI_EXP_TYPE_DOWNSTREAM || 339 port_type == PCI_EXP_TYPE_ROOT_PORT); 340 341 PCIE_DEV_PRINTF(dev, "reset\n"); 342 343 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL, 344 PCI_EXP_SLTCTL_EIC | 345 PCI_EXP_SLTCTL_PIC | 346 PCI_EXP_SLTCTL_AIC | 347 PCI_EXP_SLTCTL_HPIE | 348 PCI_EXP_SLTCTL_CCIE | 349 PCI_EXP_SLTCTL_PDCE | 350 PCI_EXP_SLTCTL_ABPE); 351 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL, 352 PCI_EXP_SLTCTL_AIC_OFF); 353 354 if (dev->cap_present & QEMU_PCIE_SLTCAP_PCP) { 355 /* Downstream ports enforce device number 0. */ 356 bool populated = pci_bridge_get_sec_bus(PCI_BRIDGE(dev))->devices[0]; 357 uint16_t pic; 358 359 if (populated) { 360 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL, 361 PCI_EXP_SLTCTL_PCC); 362 } else { 363 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL, 364 PCI_EXP_SLTCTL_PCC); 365 } 366 367 pic = populated ? PCI_EXP_SLTCTL_PIC_ON : PCI_EXP_SLTCTL_PIC_OFF; 368 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL, pic); 369 } 370 371 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA, 372 PCI_EXP_SLTSTA_EIS |/* on reset, 373 the lock is released */ 374 PCI_EXP_SLTSTA_CC | 375 PCI_EXP_SLTSTA_PDC | 376 PCI_EXP_SLTSTA_ABP); 377 378 hotplug_event_update_event_status(dev); 379 } 380 381 static void pcie_unplug_device(PCIBus *bus, PCIDevice *dev, void *opaque) 382 { 383 object_unparent(OBJECT(dev)); 384 } 385 386 void pcie_cap_slot_write_config(PCIDevice *dev, 387 uint32_t addr, uint32_t val, int len) 388 { 389 uint32_t pos = dev->exp.exp_cap; 390 uint8_t *exp_cap = dev->config + pos; 391 uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA); 392 393 if (ranges_overlap(addr, len, pos + PCI_EXP_SLTSTA, 2)) { 394 hotplug_event_clear(dev); 395 } 396 397 if (!ranges_overlap(addr, len, pos + PCI_EXP_SLTCTL, 2)) { 398 return; 399 } 400 401 if (pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL, 402 PCI_EXP_SLTCTL_EIC)) { 403 sltsta ^= PCI_EXP_SLTSTA_EIS; /* toggle PCI_EXP_SLTSTA_EIS bit */ 404 pci_set_word(exp_cap + PCI_EXP_SLTSTA, sltsta); 405 PCIE_DEV_PRINTF(dev, "PCI_EXP_SLTCTL_EIC: " 406 "sltsta -> 0x%02"PRIx16"\n", 407 sltsta); 408 } 409 410 /* 411 * If the slot is polulated, power indicator is off and power 412 * controller is off, it is safe to detach the devices. 413 */ 414 if ((sltsta & PCI_EXP_SLTSTA_PDS) && (val & PCI_EXP_SLTCTL_PCC) && 415 ((val & PCI_EXP_SLTCTL_PIC_OFF) == PCI_EXP_SLTCTL_PIC_OFF)) { 416 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev)); 417 pci_for_each_device(sec_bus, pci_bus_num(sec_bus), 418 pcie_unplug_device, NULL); 419 420 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA, 421 PCI_EXP_SLTSTA_PDS); 422 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA, 423 PCI_EXP_SLTSTA_PDC); 424 } 425 426 hotplug_event_notify(dev); 427 428 /* 429 * 6.7.3.2 Command Completed Events 430 * 431 * Software issues a command to a hot-plug capable Downstream Port by 432 * issuing a write transaction that targets any portion of the Port’s Slot 433 * Control register. A single write to the Slot Control register is 434 * considered to be a single command, even if the write affects more than 435 * one field in the Slot Control register. In response to this transaction, 436 * the Port must carry out the requested actions and then set the 437 * associated status field for the command completed event. */ 438 439 /* Real hardware might take a while to complete requested command because 440 * physical movement would be involved like locking the electromechanical 441 * lock. However in our case, command is completed instantaneously above, 442 * so send a command completion event right now. 443 */ 444 pcie_cap_slot_event(dev, PCI_EXP_HP_EV_CCI); 445 } 446 447 int pcie_cap_slot_post_load(void *opaque, int version_id) 448 { 449 PCIDevice *dev = opaque; 450 hotplug_event_update_event_status(dev); 451 return 0; 452 } 453 454 void pcie_cap_slot_push_attention_button(PCIDevice *dev) 455 { 456 pcie_cap_slot_event(dev, PCI_EXP_HP_EV_ABP); 457 } 458 459 /* root control/capabilities/status. PME isn't emulated for now */ 460 void pcie_cap_root_init(PCIDevice *dev) 461 { 462 pci_set_word(dev->wmask + dev->exp.exp_cap + PCI_EXP_RTCTL, 463 PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE | 464 PCI_EXP_RTCTL_SEFEE); 465 } 466 467 void pcie_cap_root_reset(PCIDevice *dev) 468 { 469 pci_set_word(dev->config + dev->exp.exp_cap + PCI_EXP_RTCTL, 0); 470 } 471 472 /* function level reset(FLR) */ 473 void pcie_cap_flr_init(PCIDevice *dev) 474 { 475 pci_long_test_and_set_mask(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCAP, 476 PCI_EXP_DEVCAP_FLR); 477 478 /* Although reading BCR_FLR returns always 0, 479 * the bit is made writable here in order to detect the 1b is written 480 * pcie_cap_flr_write_config() test-and-clear the bit, so 481 * this bit always returns 0 to the guest. 482 */ 483 pci_word_test_and_set_mask(dev->wmask + dev->exp.exp_cap + PCI_EXP_DEVCTL, 484 PCI_EXP_DEVCTL_BCR_FLR); 485 } 486 487 void pcie_cap_flr_write_config(PCIDevice *dev, 488 uint32_t addr, uint32_t val, int len) 489 { 490 uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL; 491 if (pci_get_word(devctl) & PCI_EXP_DEVCTL_BCR_FLR) { 492 /* Clear PCI_EXP_DEVCTL_BCR_FLR after invoking the reset handler 493 so the handler can detect FLR by looking at this bit. */ 494 pci_device_reset(dev); 495 pci_word_test_and_clear_mask(devctl, PCI_EXP_DEVCTL_BCR_FLR); 496 } 497 } 498 499 /* Alternative Routing-ID Interpretation (ARI) 500 * forwarding support for root and downstream ports 501 */ 502 void pcie_cap_arifwd_init(PCIDevice *dev) 503 { 504 uint32_t pos = dev->exp.exp_cap; 505 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP2, 506 PCI_EXP_DEVCAP2_ARI); 507 pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL2, 508 PCI_EXP_DEVCTL2_ARI); 509 } 510 511 void pcie_cap_arifwd_reset(PCIDevice *dev) 512 { 513 uint8_t *devctl2 = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2; 514 pci_long_test_and_clear_mask(devctl2, PCI_EXP_DEVCTL2_ARI); 515 } 516 517 bool pcie_cap_is_arifwd_enabled(const PCIDevice *dev) 518 { 519 if (!pci_is_express(dev)) { 520 return false; 521 } 522 if (!dev->exp.exp_cap) { 523 return false; 524 } 525 526 return pci_get_long(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2) & 527 PCI_EXP_DEVCTL2_ARI; 528 } 529 530 /************************************************************************** 531 * pci express extended capability list management functions 532 * uint16_t ext_cap_id (16 bit) 533 * uint8_t cap_ver (4 bit) 534 * uint16_t cap_offset (12 bit) 535 * uint16_t ext_cap_size 536 */ 537 538 static uint16_t pcie_find_capability_list(PCIDevice *dev, uint16_t cap_id, 539 uint16_t *prev_p) 540 { 541 uint16_t prev = 0; 542 uint16_t next; 543 uint32_t header = pci_get_long(dev->config + PCI_CONFIG_SPACE_SIZE); 544 545 if (!header) { 546 /* no extended capability */ 547 next = 0; 548 goto out; 549 } 550 for (next = PCI_CONFIG_SPACE_SIZE; next; 551 prev = next, next = PCI_EXT_CAP_NEXT(header)) { 552 553 assert(next >= PCI_CONFIG_SPACE_SIZE); 554 assert(next <= PCIE_CONFIG_SPACE_SIZE - 8); 555 556 header = pci_get_long(dev->config + next); 557 if (PCI_EXT_CAP_ID(header) == cap_id) { 558 break; 559 } 560 } 561 562 out: 563 if (prev_p) { 564 *prev_p = prev; 565 } 566 return next; 567 } 568 569 uint16_t pcie_find_capability(PCIDevice *dev, uint16_t cap_id) 570 { 571 return pcie_find_capability_list(dev, cap_id, NULL); 572 } 573 574 static void pcie_ext_cap_set_next(PCIDevice *dev, uint16_t pos, uint16_t next) 575 { 576 uint32_t header = pci_get_long(dev->config + pos); 577 assert(!(next & (PCI_EXT_CAP_ALIGN - 1))); 578 header = (header & ~PCI_EXT_CAP_NEXT_MASK) | 579 ((next << PCI_EXT_CAP_NEXT_SHIFT) & PCI_EXT_CAP_NEXT_MASK); 580 pci_set_long(dev->config + pos, header); 581 } 582 583 /* 584 * caller must supply valid (offset, size) * such that the range shouldn't 585 * overlap with other capability or other registers. 586 * This function doesn't check it. 587 */ 588 void pcie_add_capability(PCIDevice *dev, 589 uint16_t cap_id, uint8_t cap_ver, 590 uint16_t offset, uint16_t size) 591 { 592 uint32_t header; 593 uint16_t next; 594 595 assert(offset >= PCI_CONFIG_SPACE_SIZE); 596 assert(offset < offset + size); 597 assert(offset + size < PCIE_CONFIG_SPACE_SIZE); 598 assert(size >= 8); 599 assert(pci_is_express(dev)); 600 601 if (offset == PCI_CONFIG_SPACE_SIZE) { 602 header = pci_get_long(dev->config + offset); 603 next = PCI_EXT_CAP_NEXT(header); 604 } else { 605 uint16_t prev; 606 607 /* 0 is reserved cap id. use internally to find the last capability 608 in the linked list */ 609 next = pcie_find_capability_list(dev, 0, &prev); 610 611 assert(prev >= PCI_CONFIG_SPACE_SIZE); 612 assert(next == 0); 613 pcie_ext_cap_set_next(dev, prev, offset); 614 } 615 pci_set_long(dev->config + offset, PCI_EXT_CAP(cap_id, cap_ver, next)); 616 617 /* Make capability read-only by default */ 618 memset(dev->wmask + offset, 0, size); 619 memset(dev->w1cmask + offset, 0, size); 620 /* Check capability by default */ 621 memset(dev->cmask + offset, 0xFF, size); 622 } 623 624 /************************************************************************** 625 * pci express extended capability helper functions 626 */ 627 628 /* ARI */ 629 void pcie_ari_init(PCIDevice *dev, uint16_t offset, uint16_t nextfn) 630 { 631 pcie_add_capability(dev, PCI_EXT_CAP_ID_ARI, PCI_ARI_VER, 632 offset, PCI_ARI_SIZEOF); 633 pci_set_long(dev->config + offset + PCI_ARI_CAP, (nextfn & 0xff) << 8); 634 } 635