1 /* 2 * pcie.c 3 * 4 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp> 5 * VA Linux Systems Japan K.K. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "hw/pci/pci_bridge.h" 24 #include "hw/pci/pcie.h" 25 #include "hw/pci/msix.h" 26 #include "hw/pci/msi.h" 27 #include "hw/pci/pci_bus.h" 28 #include "hw/pci/pcie_regs.h" 29 #include "hw/pci/pcie_port.h" 30 #include "qemu/range.h" 31 32 //#define DEBUG_PCIE 33 #ifdef DEBUG_PCIE 34 # define PCIE_DPRINTF(fmt, ...) \ 35 fprintf(stderr, "%s:%d " fmt, __func__, __LINE__, ## __VA_ARGS__) 36 #else 37 # define PCIE_DPRINTF(fmt, ...) do {} while (0) 38 #endif 39 #define PCIE_DEV_PRINTF(dev, fmt, ...) \ 40 PCIE_DPRINTF("%s:%x "fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__) 41 42 static bool pcie_sltctl_powered_off(uint16_t sltctl) 43 { 44 return (sltctl & PCI_EXP_SLTCTL_PCC) == PCI_EXP_SLTCTL_PWR_OFF 45 && (sltctl & PCI_EXP_SLTCTL_PIC) == PCI_EXP_SLTCTL_PWR_IND_OFF; 46 } 47 48 /*************************************************************************** 49 * pci express capability helper functions 50 */ 51 52 static void 53 pcie_cap_v1_fill(PCIDevice *dev, uint8_t port, uint8_t type, uint8_t version) 54 { 55 uint8_t *exp_cap = dev->config + dev->exp.exp_cap; 56 uint8_t *cmask = dev->cmask + dev->exp.exp_cap; 57 58 /* capability register 59 interrupt message number defaults to 0 */ 60 pci_set_word(exp_cap + PCI_EXP_FLAGS, 61 ((type << PCI_EXP_FLAGS_TYPE_SHIFT) & PCI_EXP_FLAGS_TYPE) | 62 version); 63 64 /* device capability register 65 * table 7-12: 66 * roll based error reporting bit must be set by all 67 * Functions conforming to the ECN, PCI Express Base 68 * Specification, Revision 1.1., or subsequent PCI Express Base 69 * Specification revisions. 70 */ 71 pci_set_long(exp_cap + PCI_EXP_DEVCAP, PCI_EXP_DEVCAP_RBER); 72 73 pci_set_long(exp_cap + PCI_EXP_LNKCAP, 74 (port << PCI_EXP_LNKCAP_PN_SHIFT) | 75 PCI_EXP_LNKCAP_ASPMS_0S | 76 QEMU_PCI_EXP_LNKCAP_MLW(QEMU_PCI_EXP_LNK_X1) | 77 QEMU_PCI_EXP_LNKCAP_MLS(QEMU_PCI_EXP_LNK_2_5GT)); 78 79 pci_set_word(exp_cap + PCI_EXP_LNKSTA, 80 QEMU_PCI_EXP_LNKSTA_NLW(QEMU_PCI_EXP_LNK_X1) | 81 QEMU_PCI_EXP_LNKSTA_CLS(QEMU_PCI_EXP_LNK_2_5GT)); 82 83 /* We changed link status bits over time, and changing them across 84 * migrations is generally fine as hardware changes them too. 85 * Let's not bother checking. 86 */ 87 pci_set_word(cmask + PCI_EXP_LNKSTA, 0); 88 } 89 90 static void pcie_cap_fill_slot_lnk(PCIDevice *dev) 91 { 92 PCIESlot *s = (PCIESlot *)object_dynamic_cast(OBJECT(dev), TYPE_PCIE_SLOT); 93 uint8_t *exp_cap = dev->config + dev->exp.exp_cap; 94 95 /* Skip anything that isn't a PCIESlot */ 96 if (!s) { 97 return; 98 } 99 100 /* Clear and fill LNKCAP from what was configured above */ 101 pci_long_test_and_clear_mask(exp_cap + PCI_EXP_LNKCAP, 102 PCI_EXP_LNKCAP_MLW | PCI_EXP_LNKCAP_SLS); 103 pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP, 104 QEMU_PCI_EXP_LNKCAP_MLW(s->width) | 105 QEMU_PCI_EXP_LNKCAP_MLS(s->speed)); 106 107 /* 108 * Link bandwidth notification is required for all root ports and 109 * downstream ports supporting links wider than x1 or multiple link 110 * speeds. 111 */ 112 if (s->width > QEMU_PCI_EXP_LNK_X1 || 113 s->speed > QEMU_PCI_EXP_LNK_2_5GT) { 114 pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP, 115 PCI_EXP_LNKCAP_LBNC); 116 } 117 118 if (s->speed > QEMU_PCI_EXP_LNK_2_5GT) { 119 /* 120 * Hot-plug capable downstream ports and downstream ports supporting 121 * link speeds greater than 5GT/s must hardwire PCI_EXP_LNKCAP_DLLLARC 122 * to 1b. PCI_EXP_LNKCAP_DLLLARC implies PCI_EXP_LNKSTA_DLLLA, which 123 * we also hardwire to 1b here. 2.5GT/s hot-plug slots should also 124 * technically implement this, but it's not done here for compatibility. 125 */ 126 pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP, 127 PCI_EXP_LNKCAP_DLLLARC); 128 /* the PCI_EXP_LNKSTA_DLLLA will be set in the hotplug function */ 129 130 /* 131 * Target Link Speed defaults to the highest link speed supported by 132 * the component. 2.5GT/s devices are permitted to hardwire to zero. 133 */ 134 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_LNKCTL2, 135 PCI_EXP_LNKCTL2_TLS); 136 pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKCTL2, 137 QEMU_PCI_EXP_LNKCAP_MLS(s->speed) & 138 PCI_EXP_LNKCTL2_TLS); 139 } 140 141 /* 142 * 2.5 & 5.0GT/s can be fully described by LNKCAP, but 8.0GT/s is 143 * actually a reference to the highest bit supported in this register. 144 * We assume the device supports all link speeds. 145 */ 146 if (s->speed > QEMU_PCI_EXP_LNK_5GT) { 147 pci_long_test_and_clear_mask(exp_cap + PCI_EXP_LNKCAP2, ~0U); 148 pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP2, 149 PCI_EXP_LNKCAP2_SLS_2_5GB | 150 PCI_EXP_LNKCAP2_SLS_5_0GB | 151 PCI_EXP_LNKCAP2_SLS_8_0GB); 152 if (s->speed > QEMU_PCI_EXP_LNK_8GT) { 153 pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP2, 154 PCI_EXP_LNKCAP2_SLS_16_0GB); 155 } 156 } 157 } 158 159 int pcie_cap_init(PCIDevice *dev, uint8_t offset, 160 uint8_t type, uint8_t port, 161 Error **errp) 162 { 163 /* PCIe cap v2 init */ 164 int pos; 165 uint8_t *exp_cap; 166 167 assert(pci_is_express(dev)); 168 169 pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset, 170 PCI_EXP_VER2_SIZEOF, errp); 171 if (pos < 0) { 172 return pos; 173 } 174 dev->exp.exp_cap = pos; 175 exp_cap = dev->config + pos; 176 177 /* Filling values common with v1 */ 178 pcie_cap_v1_fill(dev, port, type, PCI_EXP_FLAGS_VER2); 179 180 /* Fill link speed and width options */ 181 pcie_cap_fill_slot_lnk(dev); 182 183 /* Filling v2 specific values */ 184 pci_set_long(exp_cap + PCI_EXP_DEVCAP2, 185 PCI_EXP_DEVCAP2_EFF | PCI_EXP_DEVCAP2_EETLPP); 186 187 pci_set_word(dev->wmask + pos + PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_EETLPPB); 188 189 if (dev->cap_present & QEMU_PCIE_EXTCAP_INIT) { 190 /* read-only to behave like a 'NULL' Extended Capability Header */ 191 pci_set_long(dev->wmask + PCI_CONFIG_SPACE_SIZE, 0); 192 } 193 194 return pos; 195 } 196 197 int pcie_cap_v1_init(PCIDevice *dev, uint8_t offset, uint8_t type, 198 uint8_t port) 199 { 200 /* PCIe cap v1 init */ 201 int pos; 202 Error *local_err = NULL; 203 204 assert(pci_is_express(dev)); 205 206 pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset, 207 PCI_EXP_VER1_SIZEOF, &local_err); 208 if (pos < 0) { 209 error_report_err(local_err); 210 return pos; 211 } 212 dev->exp.exp_cap = pos; 213 214 pcie_cap_v1_fill(dev, port, type, PCI_EXP_FLAGS_VER1); 215 216 return pos; 217 } 218 219 static int 220 pcie_endpoint_cap_common_init(PCIDevice *dev, uint8_t offset, uint8_t cap_size) 221 { 222 uint8_t type = PCI_EXP_TYPE_ENDPOINT; 223 Error *local_err = NULL; 224 int ret; 225 226 /* 227 * Windows guests will report Code 10, device cannot start, if 228 * a regular Endpoint type is exposed on a root complex. These 229 * should instead be Root Complex Integrated Endpoints. 230 */ 231 if (pci_bus_is_express(pci_get_bus(dev)) 232 && pci_bus_is_root(pci_get_bus(dev))) { 233 type = PCI_EXP_TYPE_RC_END; 234 } 235 236 if (cap_size == PCI_EXP_VER1_SIZEOF) { 237 return pcie_cap_v1_init(dev, offset, type, 0); 238 } else { 239 ret = pcie_cap_init(dev, offset, type, 0, &local_err); 240 241 if (ret < 0) { 242 error_report_err(local_err); 243 } 244 245 return ret; 246 } 247 } 248 249 int pcie_endpoint_cap_init(PCIDevice *dev, uint8_t offset) 250 { 251 return pcie_endpoint_cap_common_init(dev, offset, PCI_EXP_VER2_SIZEOF); 252 } 253 254 int pcie_endpoint_cap_v1_init(PCIDevice *dev, uint8_t offset) 255 { 256 return pcie_endpoint_cap_common_init(dev, offset, PCI_EXP_VER1_SIZEOF); 257 } 258 259 void pcie_cap_exit(PCIDevice *dev) 260 { 261 pci_del_capability(dev, PCI_CAP_ID_EXP, PCI_EXP_VER2_SIZEOF); 262 } 263 264 void pcie_cap_v1_exit(PCIDevice *dev) 265 { 266 pci_del_capability(dev, PCI_CAP_ID_EXP, PCI_EXP_VER1_SIZEOF); 267 } 268 269 uint8_t pcie_cap_get_type(const PCIDevice *dev) 270 { 271 uint32_t pos = dev->exp.exp_cap; 272 assert(pos > 0); 273 return (pci_get_word(dev->config + pos + PCI_EXP_FLAGS) & 274 PCI_EXP_FLAGS_TYPE) >> PCI_EXP_FLAGS_TYPE_SHIFT; 275 } 276 277 /* MSI/MSI-X */ 278 /* pci express interrupt message number */ 279 /* 7.8.2 PCI Express Capabilities Register: Interrupt Message Number */ 280 void pcie_cap_flags_set_vector(PCIDevice *dev, uint8_t vector) 281 { 282 uint8_t *exp_cap = dev->config + dev->exp.exp_cap; 283 assert(vector < 32); 284 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_FLAGS, PCI_EXP_FLAGS_IRQ); 285 pci_word_test_and_set_mask(exp_cap + PCI_EXP_FLAGS, 286 vector << PCI_EXP_FLAGS_IRQ_SHIFT); 287 } 288 289 uint8_t pcie_cap_flags_get_vector(PCIDevice *dev) 290 { 291 return (pci_get_word(dev->config + dev->exp.exp_cap + PCI_EXP_FLAGS) & 292 PCI_EXP_FLAGS_IRQ) >> PCI_EXP_FLAGS_IRQ_SHIFT; 293 } 294 295 void pcie_cap_deverr_init(PCIDevice *dev) 296 { 297 uint32_t pos = dev->exp.exp_cap; 298 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP, 299 PCI_EXP_DEVCAP_RBER); 300 pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL, 301 PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | 302 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE); 303 pci_long_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_DEVSTA, 304 PCI_EXP_DEVSTA_CED | PCI_EXP_DEVSTA_NFED | 305 PCI_EXP_DEVSTA_FED | PCI_EXP_DEVSTA_URD); 306 } 307 308 void pcie_cap_deverr_reset(PCIDevice *dev) 309 { 310 uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL; 311 pci_long_test_and_clear_mask(devctl, 312 PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | 313 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE); 314 } 315 316 void pcie_cap_lnkctl_init(PCIDevice *dev) 317 { 318 uint32_t pos = dev->exp.exp_cap; 319 pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_LNKCTL, 320 PCI_EXP_LNKCTL_CCC | PCI_EXP_LNKCTL_ES); 321 } 322 323 void pcie_cap_lnkctl_reset(PCIDevice *dev) 324 { 325 uint8_t *lnkctl = dev->config + dev->exp.exp_cap + PCI_EXP_LNKCTL; 326 pci_long_test_and_clear_mask(lnkctl, 327 PCI_EXP_LNKCTL_CCC | PCI_EXP_LNKCTL_ES); 328 } 329 330 static void hotplug_event_update_event_status(PCIDevice *dev) 331 { 332 uint32_t pos = dev->exp.exp_cap; 333 uint8_t *exp_cap = dev->config + pos; 334 uint16_t sltctl = pci_get_word(exp_cap + PCI_EXP_SLTCTL); 335 uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA); 336 337 dev->exp.hpev_notified = (sltctl & PCI_EXP_SLTCTL_HPIE) && 338 (sltsta & sltctl & PCI_EXP_HP_EV_SUPPORTED); 339 } 340 341 static void hotplug_event_notify(PCIDevice *dev) 342 { 343 bool prev = dev->exp.hpev_notified; 344 345 hotplug_event_update_event_status(dev); 346 347 if (prev == dev->exp.hpev_notified) { 348 return; 349 } 350 351 /* Note: the logic above does not take into account whether interrupts 352 * are masked. The result is that interrupt will be sent when it is 353 * subsequently unmasked. This appears to be legal: Section 6.7.3.4: 354 * The Port may optionally send an MSI when there are hot-plug events that 355 * occur while interrupt generation is disabled, and interrupt generation is 356 * subsequently enabled. */ 357 if (msix_enabled(dev)) { 358 msix_notify(dev, pcie_cap_flags_get_vector(dev)); 359 } else if (msi_enabled(dev)) { 360 msi_notify(dev, pcie_cap_flags_get_vector(dev)); 361 } else if (pci_intx(dev) != -1) { 362 pci_set_irq(dev, dev->exp.hpev_notified); 363 } 364 } 365 366 static void hotplug_event_clear(PCIDevice *dev) 367 { 368 hotplug_event_update_event_status(dev); 369 if (!msix_enabled(dev) && !msi_enabled(dev) && pci_intx(dev) != -1 && 370 !dev->exp.hpev_notified) { 371 pci_irq_deassert(dev); 372 } 373 } 374 375 void pcie_cap_slot_enable_power(PCIDevice *dev) 376 { 377 uint8_t *exp_cap = dev->config + dev->exp.exp_cap; 378 uint32_t sltcap = pci_get_long(exp_cap + PCI_EXP_SLTCAP); 379 380 if (sltcap & PCI_EXP_SLTCAP_PCP) { 381 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL, 382 PCI_EXP_SLTCTL_PCC); 383 } 384 } 385 386 static void pcie_set_power_device(PCIBus *bus, PCIDevice *dev, void *opaque) 387 { 388 bool *power = opaque; 389 390 pci_set_power(dev, *power); 391 } 392 393 static void pcie_cap_update_power(PCIDevice *hotplug_dev) 394 { 395 uint8_t *exp_cap = hotplug_dev->config + hotplug_dev->exp.exp_cap; 396 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(hotplug_dev)); 397 uint32_t sltcap = pci_get_long(exp_cap + PCI_EXP_SLTCAP); 398 uint16_t sltctl = pci_get_word(exp_cap + PCI_EXP_SLTCTL); 399 bool power = true; 400 401 if (sltcap & PCI_EXP_SLTCAP_PCP) { 402 power = (sltctl & PCI_EXP_SLTCTL_PCC) == PCI_EXP_SLTCTL_PWR_ON; 403 /* Don't we need to check also (sltctl & PCI_EXP_SLTCTL_PIC) ? */ 404 } 405 406 pci_for_each_device(sec_bus, pci_bus_num(sec_bus), 407 pcie_set_power_device, &power); 408 } 409 410 /* 411 * A PCI Express Hot-Plug Event has occurred, so update slot status register 412 * and notify OS of the event if necessary. 413 * 414 * 6.7.3 PCI Express Hot-Plug Events 415 * 6.7.3.4 Software Notification of Hot-Plug Events 416 */ 417 static void pcie_cap_slot_event(PCIDevice *dev, PCIExpressHotPlugEvent event) 418 { 419 /* Minor optimization: if nothing changed - no event is needed. */ 420 if (pci_word_test_and_set_mask(dev->config + dev->exp.exp_cap + 421 PCI_EXP_SLTSTA, event) == event) { 422 return; 423 } 424 hotplug_event_notify(dev); 425 } 426 427 static void pcie_cap_slot_plug_common(PCIDevice *hotplug_dev, DeviceState *dev, 428 Error **errp) 429 { 430 uint8_t *exp_cap = hotplug_dev->config + hotplug_dev->exp.exp_cap; 431 uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA); 432 433 PCIE_DEV_PRINTF(PCI_DEVICE(dev), "hotplug state: 0x%x\n", sltsta); 434 if (sltsta & PCI_EXP_SLTSTA_EIS) { 435 /* the slot is electromechanically locked. 436 * This error is propagated up to qdev and then to HMP/QMP. 437 */ 438 error_setg_errno(errp, EBUSY, "slot is electromechanically locked"); 439 } 440 } 441 442 void pcie_cap_slot_pre_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, 443 Error **errp) 444 { 445 PCIDevice *hotplug_pdev = PCI_DEVICE(hotplug_dev); 446 uint8_t *exp_cap = hotplug_pdev->config + hotplug_pdev->exp.exp_cap; 447 uint32_t sltcap = pci_get_word(exp_cap + PCI_EXP_SLTCAP); 448 449 /* Check if hot-plug is disabled on the slot */ 450 if (dev->hotplugged && (sltcap & PCI_EXP_SLTCAP_HPC) == 0) { 451 error_setg(errp, "Hot-plug failed: unsupported by the port device '%s'", 452 DEVICE(hotplug_pdev)->id); 453 return; 454 } 455 456 pcie_cap_slot_plug_common(PCI_DEVICE(hotplug_dev), dev, errp); 457 } 458 459 void pcie_cap_slot_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, 460 Error **errp) 461 { 462 PCIDevice *hotplug_pdev = PCI_DEVICE(hotplug_dev); 463 uint8_t *exp_cap = hotplug_pdev->config + hotplug_pdev->exp.exp_cap; 464 PCIDevice *pci_dev = PCI_DEVICE(dev); 465 uint32_t lnkcap = pci_get_long(exp_cap + PCI_EXP_LNKCAP); 466 467 if (pci_is_vf(pci_dev)) { 468 /* Virtual function cannot be physically disconnected */ 469 return; 470 } 471 472 /* Don't send event when device is enabled during qemu machine creation: 473 * it is present on boot, no hotplug event is necessary. We do send an 474 * event when the device is disabled later. */ 475 if (!dev->hotplugged) { 476 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA, 477 PCI_EXP_SLTSTA_PDS); 478 if (pci_dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA || 479 (lnkcap & PCI_EXP_LNKCAP_DLLLARC)) { 480 pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA, 481 PCI_EXP_LNKSTA_DLLLA); 482 } 483 pcie_cap_update_power(hotplug_pdev); 484 return; 485 } 486 487 /* To enable multifunction hot-plug, we just ensure the function 488 * 0 added last. When function 0 is added, we set the sltsta and 489 * inform OS via event notification. 490 */ 491 if (pci_get_function_0(pci_dev)) { 492 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA, 493 PCI_EXP_SLTSTA_PDS); 494 if (pci_dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA || 495 (lnkcap & PCI_EXP_LNKCAP_DLLLARC)) { 496 pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA, 497 PCI_EXP_LNKSTA_DLLLA); 498 } 499 pcie_cap_slot_event(hotplug_pdev, 500 PCI_EXP_HP_EV_PDC | PCI_EXP_HP_EV_ABP); 501 pcie_cap_update_power(hotplug_pdev); 502 } 503 } 504 505 void pcie_cap_slot_unplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, 506 Error **errp) 507 { 508 qdev_unrealize(dev); 509 } 510 511 static void pcie_unplug_device(PCIBus *bus, PCIDevice *dev, void *opaque) 512 { 513 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(DEVICE(dev)); 514 515 if (dev->partially_hotplugged) { 516 dev->qdev.pending_deleted_event = false; 517 return; 518 } 519 hotplug_handler_unplug(hotplug_ctrl, DEVICE(dev), &error_abort); 520 object_unparent(OBJECT(dev)); 521 } 522 523 static void pcie_cap_slot_do_unplug(PCIDevice *dev) 524 { 525 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev)); 526 uint8_t *exp_cap = dev->config + dev->exp.exp_cap; 527 uint32_t lnkcap = pci_get_long(exp_cap + PCI_EXP_LNKCAP); 528 529 pci_for_each_device_under_bus(sec_bus, pcie_unplug_device, NULL); 530 531 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA, 532 PCI_EXP_SLTSTA_PDS); 533 if (dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA || 534 (lnkcap & PCI_EXP_LNKCAP_DLLLARC)) { 535 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_LNKSTA, 536 PCI_EXP_LNKSTA_DLLLA); 537 } 538 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA, 539 PCI_EXP_SLTSTA_PDC); 540 } 541 542 void pcie_cap_slot_unplug_request_cb(HotplugHandler *hotplug_dev, 543 DeviceState *dev, Error **errp) 544 { 545 Error *local_err = NULL; 546 PCIDevice *pci_dev = PCI_DEVICE(dev); 547 PCIBus *bus = pci_get_bus(pci_dev); 548 PCIDevice *hotplug_pdev = PCI_DEVICE(hotplug_dev); 549 uint8_t *exp_cap = hotplug_pdev->config + hotplug_pdev->exp.exp_cap; 550 uint32_t sltcap = pci_get_word(exp_cap + PCI_EXP_SLTCAP); 551 uint16_t sltctl = pci_get_word(exp_cap + PCI_EXP_SLTCTL); 552 553 /* Check if hot-unplug is disabled on the slot */ 554 if ((sltcap & PCI_EXP_SLTCAP_HPC) == 0) { 555 error_setg(errp, "Hot-unplug failed: " 556 "unsupported by the port device '%s'", 557 DEVICE(hotplug_pdev)->id); 558 return; 559 } 560 561 pcie_cap_slot_plug_common(hotplug_pdev, dev, &local_err); 562 if (local_err) { 563 error_propagate(errp, local_err); 564 return; 565 } 566 567 if ((sltctl & PCI_EXP_SLTCTL_PIC) == PCI_EXP_SLTCTL_PWR_IND_BLINK) { 568 error_setg(errp, "Hot-unplug failed: " 569 "guest is busy (power indicator blinking)"); 570 return; 571 } 572 573 dev->pending_deleted_event = true; 574 dev->pending_deleted_expires_ms = 575 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 5000; /* 5 secs */ 576 577 /* In case user cancel the operation of multi-function hot-add, 578 * remove the function that is unexposed to guest individually, 579 * without interaction with guest. 580 */ 581 if (pci_dev->devfn && 582 !bus->devices[0]) { 583 pcie_unplug_device(bus, pci_dev, NULL); 584 585 return; 586 } 587 588 if (pcie_sltctl_powered_off(sltctl)) { 589 /* slot is powered off -> unplug without round-trip to the guest */ 590 pcie_cap_slot_do_unplug(hotplug_pdev); 591 hotplug_event_notify(hotplug_pdev); 592 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA, 593 PCI_EXP_SLTSTA_ABP); 594 return; 595 } 596 597 pcie_cap_slot_push_attention_button(hotplug_pdev); 598 } 599 600 /* pci express slot for pci express root/downstream port 601 PCI express capability slot registers */ 602 void pcie_cap_slot_init(PCIDevice *dev, PCIESlot *s) 603 { 604 uint32_t pos = dev->exp.exp_cap; 605 606 pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_FLAGS, 607 PCI_EXP_FLAGS_SLOT); 608 609 pci_long_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCAP, 610 ~PCI_EXP_SLTCAP_PSN); 611 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP, 612 (s->slot << PCI_EXP_SLTCAP_PSN_SHIFT) | 613 PCI_EXP_SLTCAP_EIP | 614 PCI_EXP_SLTCAP_PIP | 615 PCI_EXP_SLTCAP_AIP | 616 PCI_EXP_SLTCAP_ABP); 617 618 /* 619 * Expose native hot-plug on all bridges if hot-plug is enabled on the slot. 620 * (unless broken 6.1 ABI is enforced for compat reasons) 621 */ 622 if (s->hotplug && 623 (!s->hide_native_hotplug_cap || DEVICE(dev)->hotplugged)) { 624 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP, 625 PCI_EXP_SLTCAP_HPS | 626 PCI_EXP_SLTCAP_HPC); 627 } 628 629 if (dev->cap_present & QEMU_PCIE_SLTCAP_PCP) { 630 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP, 631 PCI_EXP_SLTCAP_PCP); 632 pci_word_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCTL, 633 PCI_EXP_SLTCTL_PCC); 634 pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL, 635 PCI_EXP_SLTCTL_PCC); 636 } 637 638 pci_word_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCTL, 639 PCI_EXP_SLTCTL_PIC | 640 PCI_EXP_SLTCTL_AIC); 641 pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCTL, 642 PCI_EXP_SLTCTL_PWR_IND_OFF | 643 PCI_EXP_SLTCTL_ATTN_IND_OFF); 644 pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL, 645 PCI_EXP_SLTCTL_PIC | 646 PCI_EXP_SLTCTL_AIC | 647 PCI_EXP_SLTCTL_HPIE | 648 PCI_EXP_SLTCTL_CCIE | 649 PCI_EXP_SLTCTL_PDCE | 650 PCI_EXP_SLTCTL_ABPE); 651 /* Although reading PCI_EXP_SLTCTL_EIC returns always 0, 652 * make the bit writable here in order to detect 1b is written. 653 * pcie_cap_slot_write_config() test-and-clear the bit, so 654 * this bit always returns 0 to the guest. 655 */ 656 pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL, 657 PCI_EXP_SLTCTL_EIC); 658 659 pci_word_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_SLTSTA, 660 PCI_EXP_HP_EV_SUPPORTED); 661 662 dev->exp.hpev_notified = false; 663 664 qbus_set_hotplug_handler(BUS(pci_bridge_get_sec_bus(PCI_BRIDGE(dev))), 665 OBJECT(dev)); 666 } 667 668 void pcie_cap_slot_reset(PCIDevice *dev) 669 { 670 uint8_t *exp_cap = dev->config + dev->exp.exp_cap; 671 uint8_t port_type = pcie_cap_get_type(dev); 672 673 assert(port_type == PCI_EXP_TYPE_DOWNSTREAM || 674 port_type == PCI_EXP_TYPE_ROOT_PORT); 675 676 PCIE_DEV_PRINTF(dev, "reset\n"); 677 678 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL, 679 PCI_EXP_SLTCTL_EIC | 680 PCI_EXP_SLTCTL_PIC | 681 PCI_EXP_SLTCTL_AIC | 682 PCI_EXP_SLTCTL_HPIE | 683 PCI_EXP_SLTCTL_CCIE | 684 PCI_EXP_SLTCTL_PDCE | 685 PCI_EXP_SLTCTL_ABPE); 686 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL, 687 PCI_EXP_SLTCTL_PWR_IND_OFF | 688 PCI_EXP_SLTCTL_ATTN_IND_OFF); 689 690 if (dev->cap_present & QEMU_PCIE_SLTCAP_PCP) { 691 /* Downstream ports enforce device number 0. */ 692 bool populated = pci_bridge_get_sec_bus(PCI_BRIDGE(dev))->devices[0]; 693 uint16_t pic; 694 695 if (populated) { 696 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL, 697 PCI_EXP_SLTCTL_PCC); 698 } else { 699 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL, 700 PCI_EXP_SLTCTL_PCC); 701 } 702 703 pic = populated ? 704 PCI_EXP_SLTCTL_PWR_IND_ON : PCI_EXP_SLTCTL_PWR_IND_OFF; 705 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL, pic); 706 } 707 708 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA, 709 PCI_EXP_SLTSTA_EIS |/* on reset, 710 the lock is released */ 711 PCI_EXP_SLTSTA_CC | 712 PCI_EXP_SLTSTA_PDC | 713 PCI_EXP_SLTSTA_ABP); 714 715 pcie_cap_update_power(dev); 716 hotplug_event_update_event_status(dev); 717 } 718 719 void pcie_cap_slot_get(PCIDevice *dev, uint16_t *slt_ctl, uint16_t *slt_sta) 720 { 721 uint32_t pos = dev->exp.exp_cap; 722 uint8_t *exp_cap = dev->config + pos; 723 *slt_ctl = pci_get_word(exp_cap + PCI_EXP_SLTCTL); 724 *slt_sta = pci_get_word(exp_cap + PCI_EXP_SLTSTA); 725 } 726 727 void pcie_cap_slot_write_config(PCIDevice *dev, 728 uint16_t old_slt_ctl, uint16_t old_slt_sta, 729 uint32_t addr, uint32_t val, int len) 730 { 731 uint32_t pos = dev->exp.exp_cap; 732 uint8_t *exp_cap = dev->config + pos; 733 uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA); 734 735 if (ranges_overlap(addr, len, pos + PCI_EXP_SLTSTA, 2)) { 736 /* 737 * Guests tend to clears all bits during init. 738 * If they clear bits that weren't set this is racy and will lose events: 739 * not a big problem for manual button presses, but a problem for us. 740 * As a work-around, detect this and revert status to what it was 741 * before the write. 742 * 743 * Note: in theory this can be detected as a duplicate button press 744 * which cancels the previous press. Does not seem to happen in 745 * practice as guests seem to only have this bug during init. 746 */ 747 #define PCIE_SLOT_EVENTS (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD | \ 748 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC | \ 749 PCI_EXP_SLTSTA_CC) 750 751 if (val & ~old_slt_sta & PCIE_SLOT_EVENTS) { 752 sltsta = (sltsta & ~PCIE_SLOT_EVENTS) | (old_slt_sta & PCIE_SLOT_EVENTS); 753 pci_set_word(exp_cap + PCI_EXP_SLTSTA, sltsta); 754 } 755 hotplug_event_clear(dev); 756 } 757 758 if (!ranges_overlap(addr, len, pos + PCI_EXP_SLTCTL, 2)) { 759 return; 760 } 761 762 if (pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL, 763 PCI_EXP_SLTCTL_EIC)) { 764 sltsta ^= PCI_EXP_SLTSTA_EIS; /* toggle PCI_EXP_SLTSTA_EIS bit */ 765 pci_set_word(exp_cap + PCI_EXP_SLTSTA, sltsta); 766 PCIE_DEV_PRINTF(dev, "PCI_EXP_SLTCTL_EIC: " 767 "sltsta -> 0x%02"PRIx16"\n", 768 sltsta); 769 } 770 771 /* 772 * If the slot is populated, power indicator is off and power 773 * controller is off, it is safe to detach the devices. 774 * 775 * Note: don't detach if condition was already true: 776 * this is a work around for guests that overwrite 777 * control of powered off slots before powering them on. 778 */ 779 if ((sltsta & PCI_EXP_SLTSTA_PDS) && pcie_sltctl_powered_off(val) && 780 !pcie_sltctl_powered_off(old_slt_ctl)) 781 { 782 pcie_cap_slot_do_unplug(dev); 783 } 784 pcie_cap_update_power(dev); 785 786 hotplug_event_notify(dev); 787 788 /* 789 * 6.7.3.2 Command Completed Events 790 * 791 * Software issues a command to a hot-plug capable Downstream Port by 792 * issuing a write transaction that targets any portion of the Port’s Slot 793 * Control register. A single write to the Slot Control register is 794 * considered to be a single command, even if the write affects more than 795 * one field in the Slot Control register. In response to this transaction, 796 * the Port must carry out the requested actions and then set the 797 * associated status field for the command completed event. */ 798 799 /* Real hardware might take a while to complete requested command because 800 * physical movement would be involved like locking the electromechanical 801 * lock. However in our case, command is completed instantaneously above, 802 * so send a command completion event right now. 803 */ 804 pcie_cap_slot_event(dev, PCI_EXP_HP_EV_CCI); 805 } 806 807 int pcie_cap_slot_post_load(void *opaque, int version_id) 808 { 809 PCIDevice *dev = opaque; 810 hotplug_event_update_event_status(dev); 811 pcie_cap_update_power(dev); 812 return 0; 813 } 814 815 void pcie_cap_slot_push_attention_button(PCIDevice *dev) 816 { 817 pcie_cap_slot_event(dev, PCI_EXP_HP_EV_ABP); 818 } 819 820 /* root control/capabilities/status. PME isn't emulated for now */ 821 void pcie_cap_root_init(PCIDevice *dev) 822 { 823 pci_set_word(dev->wmask + dev->exp.exp_cap + PCI_EXP_RTCTL, 824 PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE | 825 PCI_EXP_RTCTL_SEFEE); 826 } 827 828 void pcie_cap_root_reset(PCIDevice *dev) 829 { 830 pci_set_word(dev->config + dev->exp.exp_cap + PCI_EXP_RTCTL, 0); 831 } 832 833 /* function level reset(FLR) */ 834 void pcie_cap_flr_init(PCIDevice *dev) 835 { 836 pci_long_test_and_set_mask(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCAP, 837 PCI_EXP_DEVCAP_FLR); 838 839 /* Although reading BCR_FLR returns always 0, 840 * the bit is made writable here in order to detect the 1b is written 841 * pcie_cap_flr_write_config() test-and-clear the bit, so 842 * this bit always returns 0 to the guest. 843 */ 844 pci_word_test_and_set_mask(dev->wmask + dev->exp.exp_cap + PCI_EXP_DEVCTL, 845 PCI_EXP_DEVCTL_BCR_FLR); 846 } 847 848 void pcie_cap_flr_write_config(PCIDevice *dev, 849 uint32_t addr, uint32_t val, int len) 850 { 851 uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL; 852 if (pci_get_word(devctl) & PCI_EXP_DEVCTL_BCR_FLR) { 853 /* Clear PCI_EXP_DEVCTL_BCR_FLR after invoking the reset handler 854 so the handler can detect FLR by looking at this bit. */ 855 pci_device_reset(dev); 856 pci_word_test_and_clear_mask(devctl, PCI_EXP_DEVCTL_BCR_FLR); 857 } 858 } 859 860 /* Alternative Routing-ID Interpretation (ARI) 861 * forwarding support for root and downstream ports 862 */ 863 void pcie_cap_arifwd_init(PCIDevice *dev) 864 { 865 uint32_t pos = dev->exp.exp_cap; 866 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP2, 867 PCI_EXP_DEVCAP2_ARI); 868 pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL2, 869 PCI_EXP_DEVCTL2_ARI); 870 } 871 872 void pcie_cap_arifwd_reset(PCIDevice *dev) 873 { 874 uint8_t *devctl2 = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2; 875 pci_long_test_and_clear_mask(devctl2, PCI_EXP_DEVCTL2_ARI); 876 } 877 878 bool pcie_cap_is_arifwd_enabled(const PCIDevice *dev) 879 { 880 if (!pci_is_express(dev)) { 881 return false; 882 } 883 if (!dev->exp.exp_cap) { 884 return false; 885 } 886 887 return pci_get_long(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2) & 888 PCI_EXP_DEVCTL2_ARI; 889 } 890 891 /************************************************************************** 892 * pci express extended capability list management functions 893 * uint16_t ext_cap_id (16 bit) 894 * uint8_t cap_ver (4 bit) 895 * uint16_t cap_offset (12 bit) 896 * uint16_t ext_cap_size 897 */ 898 899 /* Passing a cap_id value > 0xffff will return 0 and put end of list in prev */ 900 static uint16_t pcie_find_capability_list(PCIDevice *dev, uint32_t cap_id, 901 uint16_t *prev_p) 902 { 903 uint16_t prev = 0; 904 uint16_t next; 905 uint32_t header = pci_get_long(dev->config + PCI_CONFIG_SPACE_SIZE); 906 907 if (!header) { 908 /* no extended capability */ 909 next = 0; 910 goto out; 911 } 912 for (next = PCI_CONFIG_SPACE_SIZE; next; 913 prev = next, next = PCI_EXT_CAP_NEXT(header)) { 914 915 assert(next >= PCI_CONFIG_SPACE_SIZE); 916 assert(next <= PCIE_CONFIG_SPACE_SIZE - 8); 917 918 header = pci_get_long(dev->config + next); 919 if (PCI_EXT_CAP_ID(header) == cap_id) { 920 break; 921 } 922 } 923 924 out: 925 if (prev_p) { 926 *prev_p = prev; 927 } 928 return next; 929 } 930 931 uint16_t pcie_find_capability(PCIDevice *dev, uint16_t cap_id) 932 { 933 return pcie_find_capability_list(dev, cap_id, NULL); 934 } 935 936 static void pcie_ext_cap_set_next(PCIDevice *dev, uint16_t pos, uint16_t next) 937 { 938 uint32_t header = pci_get_long(dev->config + pos); 939 assert(!(next & (PCI_EXT_CAP_ALIGN - 1))); 940 header = (header & ~PCI_EXT_CAP_NEXT_MASK) | 941 ((next << PCI_EXT_CAP_NEXT_SHIFT) & PCI_EXT_CAP_NEXT_MASK); 942 pci_set_long(dev->config + pos, header); 943 } 944 945 /* 946 * Caller must supply valid (offset, size) such that the range wouldn't 947 * overlap with other capability or other registers. 948 * This function doesn't check it. 949 */ 950 void pcie_add_capability(PCIDevice *dev, 951 uint16_t cap_id, uint8_t cap_ver, 952 uint16_t offset, uint16_t size) 953 { 954 assert(offset >= PCI_CONFIG_SPACE_SIZE); 955 assert(offset < (uint16_t)(offset + size)); 956 assert((uint16_t)(offset + size) <= PCIE_CONFIG_SPACE_SIZE); 957 assert(size >= 8); 958 assert(pci_is_express(dev)); 959 960 if (offset != PCI_CONFIG_SPACE_SIZE) { 961 uint16_t prev; 962 963 /* 964 * 0xffffffff is not a valid cap id (it's a 16 bit field). use 965 * internally to find the last capability in the linked list. 966 */ 967 pcie_find_capability_list(dev, 0xffffffff, &prev); 968 assert(prev >= PCI_CONFIG_SPACE_SIZE); 969 pcie_ext_cap_set_next(dev, prev, offset); 970 } 971 pci_set_long(dev->config + offset, PCI_EXT_CAP(cap_id, cap_ver, 0)); 972 973 /* Make capability read-only by default */ 974 memset(dev->wmask + offset, 0, size); 975 memset(dev->w1cmask + offset, 0, size); 976 /* Check capability by default */ 977 memset(dev->cmask + offset, 0xFF, size); 978 } 979 980 /* 981 * Sync the PCIe Link Status negotiated speed and width of a bridge with the 982 * downstream device. If downstream device is not present, re-write with the 983 * Link Capability fields. If downstream device reports invalid width or 984 * speed, replace with minimum values (LnkSta fields are RsvdZ on VFs but such 985 * values interfere with PCIe native hotplug detecting new devices). Limit 986 * width and speed to bridge capabilities for compatibility. Use config_read 987 * to access the downstream device since it could be an assigned device with 988 * volatile link information. 989 */ 990 void pcie_sync_bridge_lnk(PCIDevice *bridge_dev) 991 { 992 PCIBridge *br = PCI_BRIDGE(bridge_dev); 993 PCIBus *bus = pci_bridge_get_sec_bus(br); 994 PCIDevice *target = bus->devices[0]; 995 uint8_t *exp_cap = bridge_dev->config + bridge_dev->exp.exp_cap; 996 uint16_t lnksta, lnkcap = pci_get_word(exp_cap + PCI_EXP_LNKCAP); 997 998 if (!target || !target->exp.exp_cap) { 999 lnksta = lnkcap; 1000 } else { 1001 lnksta = target->config_read(target, 1002 target->exp.exp_cap + PCI_EXP_LNKSTA, 1003 sizeof(lnksta)); 1004 1005 if ((lnksta & PCI_EXP_LNKSTA_NLW) > (lnkcap & PCI_EXP_LNKCAP_MLW)) { 1006 lnksta &= ~PCI_EXP_LNKSTA_NLW; 1007 lnksta |= lnkcap & PCI_EXP_LNKCAP_MLW; 1008 } else if (!(lnksta & PCI_EXP_LNKSTA_NLW)) { 1009 lnksta |= QEMU_PCI_EXP_LNKSTA_NLW(QEMU_PCI_EXP_LNK_X1); 1010 } 1011 1012 if ((lnksta & PCI_EXP_LNKSTA_CLS) > (lnkcap & PCI_EXP_LNKCAP_SLS)) { 1013 lnksta &= ~PCI_EXP_LNKSTA_CLS; 1014 lnksta |= lnkcap & PCI_EXP_LNKCAP_SLS; 1015 } else if (!(lnksta & PCI_EXP_LNKSTA_CLS)) { 1016 lnksta |= QEMU_PCI_EXP_LNKSTA_CLS(QEMU_PCI_EXP_LNK_2_5GT); 1017 } 1018 } 1019 1020 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_LNKSTA, 1021 PCI_EXP_LNKSTA_CLS | PCI_EXP_LNKSTA_NLW); 1022 pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA, lnksta & 1023 (PCI_EXP_LNKSTA_CLS | PCI_EXP_LNKSTA_NLW)); 1024 } 1025 1026 /************************************************************************** 1027 * pci express extended capability helper functions 1028 */ 1029 1030 /* ARI */ 1031 void pcie_ari_init(PCIDevice *dev, uint16_t offset, uint16_t nextfn) 1032 { 1033 pcie_add_capability(dev, PCI_EXT_CAP_ID_ARI, PCI_ARI_VER, 1034 offset, PCI_ARI_SIZEOF); 1035 pci_set_long(dev->config + offset + PCI_ARI_CAP, (nextfn & 0xff) << 8); 1036 } 1037 1038 void pcie_dev_ser_num_init(PCIDevice *dev, uint16_t offset, uint64_t ser_num) 1039 { 1040 static const int pci_dsn_ver = 1; 1041 static const int pci_dsn_cap = 4; 1042 1043 pcie_add_capability(dev, PCI_EXT_CAP_ID_DSN, pci_dsn_ver, offset, 1044 PCI_EXT_CAP_DSN_SIZEOF); 1045 pci_set_quad(dev->config + offset + pci_dsn_cap, ser_num); 1046 } 1047 1048 void pcie_ats_init(PCIDevice *dev, uint16_t offset, bool aligned) 1049 { 1050 pcie_add_capability(dev, PCI_EXT_CAP_ID_ATS, 0x1, 1051 offset, PCI_EXT_CAP_ATS_SIZEOF); 1052 1053 dev->exp.ats_cap = offset; 1054 1055 /* Invalidate Queue Depth 0 */ 1056 if (aligned) { 1057 pci_set_word(dev->config + offset + PCI_ATS_CAP, 1058 PCI_ATS_CAP_PAGE_ALIGNED); 1059 } 1060 /* STU 0, Disabled by default */ 1061 pci_set_word(dev->config + offset + PCI_ATS_CTRL, 0); 1062 1063 pci_set_word(dev->wmask + dev->exp.ats_cap + PCI_ATS_CTRL, 0x800f); 1064 } 1065 1066 /* ACS (Access Control Services) */ 1067 void pcie_acs_init(PCIDevice *dev, uint16_t offset) 1068 { 1069 bool is_downstream = pci_is_express_downstream_port(dev); 1070 uint16_t cap_bits = 0; 1071 1072 /* For endpoints, only multifunction devs may have an ACS capability: */ 1073 assert(is_downstream || 1074 (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) || 1075 PCI_FUNC(dev->devfn)); 1076 1077 pcie_add_capability(dev, PCI_EXT_CAP_ID_ACS, PCI_ACS_VER, offset, 1078 PCI_ACS_SIZEOF); 1079 dev->exp.acs_cap = offset; 1080 1081 if (is_downstream) { 1082 /* 1083 * Downstream ports must implement SV, TB, RR, CR, UF, and DT (with 1084 * caveats on the latter four that we ignore for simplicity). 1085 * Endpoints may also implement a subset of ACS capabilities, 1086 * but these are optional if the endpoint does not support 1087 * peer-to-peer between functions and thus omitted here. 1088 */ 1089 cap_bits = PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR | 1090 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT; 1091 } 1092 1093 pci_set_word(dev->config + offset + PCI_ACS_CAP, cap_bits); 1094 pci_set_word(dev->wmask + offset + PCI_ACS_CTRL, cap_bits); 1095 } 1096 1097 void pcie_acs_reset(PCIDevice *dev) 1098 { 1099 if (dev->exp.acs_cap) { 1100 pci_set_word(dev->config + dev->exp.acs_cap + PCI_ACS_CTRL, 0); 1101 } 1102 } 1103