1 /* 2 * pcie.c 3 * 4 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp> 5 * VA Linux Systems Japan K.K. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "hw/pci/pci_bridge.h" 24 #include "hw/pci/pcie.h" 25 #include "hw/pci/msix.h" 26 #include "hw/pci/msi.h" 27 #include "hw/pci/pci_bus.h" 28 #include "hw/pci/pcie_regs.h" 29 #include "hw/pci/pcie_port.h" 30 #include "qemu/range.h" 31 32 //#define DEBUG_PCIE 33 #ifdef DEBUG_PCIE 34 # define PCIE_DPRINTF(fmt, ...) \ 35 fprintf(stderr, "%s:%d " fmt, __func__, __LINE__, ## __VA_ARGS__) 36 #else 37 # define PCIE_DPRINTF(fmt, ...) do {} while (0) 38 #endif 39 #define PCIE_DEV_PRINTF(dev, fmt, ...) \ 40 PCIE_DPRINTF("%s:%x "fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__) 41 42 static bool pcie_sltctl_powered_off(uint16_t sltctl) 43 { 44 return (sltctl & PCI_EXP_SLTCTL_PCC) == PCI_EXP_SLTCTL_PWR_OFF 45 && (sltctl & PCI_EXP_SLTCTL_PIC) == PCI_EXP_SLTCTL_PWR_IND_OFF; 46 } 47 48 /*************************************************************************** 49 * pci express capability helper functions 50 */ 51 52 static void 53 pcie_cap_v1_fill(PCIDevice *dev, uint8_t port, uint8_t type, uint8_t version) 54 { 55 uint8_t *exp_cap = dev->config + dev->exp.exp_cap; 56 uint8_t *cmask = dev->cmask + dev->exp.exp_cap; 57 58 /* capability register 59 interrupt message number defaults to 0 */ 60 pci_set_word(exp_cap + PCI_EXP_FLAGS, 61 ((type << PCI_EXP_FLAGS_TYPE_SHIFT) & PCI_EXP_FLAGS_TYPE) | 62 version); 63 64 /* device capability register 65 * table 7-12: 66 * roll based error reporting bit must be set by all 67 * Functions conforming to the ECN, PCI Express Base 68 * Specification, Revision 1.1., or subsequent PCI Express Base 69 * Specification revisions. 70 */ 71 pci_set_long(exp_cap + PCI_EXP_DEVCAP, PCI_EXP_DEVCAP_RBER); 72 73 pci_set_long(exp_cap + PCI_EXP_LNKCAP, 74 (port << PCI_EXP_LNKCAP_PN_SHIFT) | 75 PCI_EXP_LNKCAP_ASPMS_0S | 76 QEMU_PCI_EXP_LNKCAP_MLW(QEMU_PCI_EXP_LNK_X1) | 77 QEMU_PCI_EXP_LNKCAP_MLS(QEMU_PCI_EXP_LNK_2_5GT)); 78 79 pci_set_word(exp_cap + PCI_EXP_LNKSTA, 80 QEMU_PCI_EXP_LNKSTA_NLW(QEMU_PCI_EXP_LNK_X1) | 81 QEMU_PCI_EXP_LNKSTA_CLS(QEMU_PCI_EXP_LNK_2_5GT)); 82 83 /* We changed link status bits over time, and changing them across 84 * migrations is generally fine as hardware changes them too. 85 * Let's not bother checking. 86 */ 87 pci_set_word(cmask + PCI_EXP_LNKSTA, 0); 88 } 89 90 static void pcie_cap_fill_slot_lnk(PCIDevice *dev) 91 { 92 PCIESlot *s = (PCIESlot *)object_dynamic_cast(OBJECT(dev), TYPE_PCIE_SLOT); 93 uint8_t *exp_cap = dev->config + dev->exp.exp_cap; 94 95 /* Skip anything that isn't a PCIESlot */ 96 if (!s) { 97 return; 98 } 99 100 /* Clear and fill LNKCAP from what was configured above */ 101 pci_long_test_and_clear_mask(exp_cap + PCI_EXP_LNKCAP, 102 PCI_EXP_LNKCAP_MLW | PCI_EXP_LNKCAP_SLS); 103 pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP, 104 QEMU_PCI_EXP_LNKCAP_MLW(s->width) | 105 QEMU_PCI_EXP_LNKCAP_MLS(s->speed)); 106 107 /* 108 * Link bandwidth notification is required for all root ports and 109 * downstream ports supporting links wider than x1 or multiple link 110 * speeds. 111 */ 112 if (s->width > QEMU_PCI_EXP_LNK_X1 || 113 s->speed > QEMU_PCI_EXP_LNK_2_5GT) { 114 pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP, 115 PCI_EXP_LNKCAP_LBNC); 116 } 117 118 if (s->speed > QEMU_PCI_EXP_LNK_2_5GT) { 119 /* 120 * Hot-plug capable downstream ports and downstream ports supporting 121 * link speeds greater than 5GT/s must hardwire PCI_EXP_LNKCAP_DLLLARC 122 * to 1b. PCI_EXP_LNKCAP_DLLLARC implies PCI_EXP_LNKSTA_DLLLA, which 123 * we also hardwire to 1b here. 2.5GT/s hot-plug slots should also 124 * technically implement this, but it's not done here for compatibility. 125 */ 126 pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP, 127 PCI_EXP_LNKCAP_DLLLARC); 128 /* the PCI_EXP_LNKSTA_DLLLA will be set in the hotplug function */ 129 130 /* 131 * Target Link Speed defaults to the highest link speed supported by 132 * the component. 2.5GT/s devices are permitted to hardwire to zero. 133 */ 134 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_LNKCTL2, 135 PCI_EXP_LNKCTL2_TLS); 136 pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKCTL2, 137 QEMU_PCI_EXP_LNKCAP_MLS(s->speed) & 138 PCI_EXP_LNKCTL2_TLS); 139 } 140 141 /* 142 * 2.5 & 5.0GT/s can be fully described by LNKCAP, but 8.0GT/s is 143 * actually a reference to the highest bit supported in this register. 144 * We assume the device supports all link speeds. 145 */ 146 if (s->speed > QEMU_PCI_EXP_LNK_5GT) { 147 pci_long_test_and_clear_mask(exp_cap + PCI_EXP_LNKCAP2, ~0U); 148 pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP2, 149 PCI_EXP_LNKCAP2_SLS_2_5GB | 150 PCI_EXP_LNKCAP2_SLS_5_0GB | 151 PCI_EXP_LNKCAP2_SLS_8_0GB); 152 if (s->speed > QEMU_PCI_EXP_LNK_8GT) { 153 pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP2, 154 PCI_EXP_LNKCAP2_SLS_16_0GB); 155 } 156 if (s->speed > QEMU_PCI_EXP_LNK_16GT) { 157 pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP2, 158 PCI_EXP_LNKCAP2_SLS_32_0GB); 159 } 160 if (s->speed > QEMU_PCI_EXP_LNK_32GT) { 161 pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP2, 162 PCI_EXP_LNKCAP2_SLS_64_0GB); 163 } 164 } 165 } 166 167 int pcie_cap_init(PCIDevice *dev, uint8_t offset, 168 uint8_t type, uint8_t port, 169 Error **errp) 170 { 171 /* PCIe cap v2 init */ 172 int pos; 173 uint8_t *exp_cap; 174 175 assert(pci_is_express(dev)); 176 177 pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset, 178 PCI_EXP_VER2_SIZEOF, errp); 179 if (pos < 0) { 180 return pos; 181 } 182 dev->exp.exp_cap = pos; 183 exp_cap = dev->config + pos; 184 185 /* Filling values common with v1 */ 186 pcie_cap_v1_fill(dev, port, type, PCI_EXP_FLAGS_VER2); 187 188 /* Fill link speed and width options */ 189 pcie_cap_fill_slot_lnk(dev); 190 191 /* Filling v2 specific values */ 192 pci_set_long(exp_cap + PCI_EXP_DEVCAP2, 193 PCI_EXP_DEVCAP2_EFF | PCI_EXP_DEVCAP2_EETLPP); 194 195 pci_set_word(dev->wmask + pos + PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_EETLPPB); 196 197 if (dev->cap_present & QEMU_PCIE_EXTCAP_INIT) { 198 /* read-only to behave like a 'NULL' Extended Capability Header */ 199 pci_set_long(dev->wmask + PCI_CONFIG_SPACE_SIZE, 0); 200 } 201 202 return pos; 203 } 204 205 int pcie_cap_v1_init(PCIDevice *dev, uint8_t offset, uint8_t type, 206 uint8_t port) 207 { 208 /* PCIe cap v1 init */ 209 int pos; 210 Error *local_err = NULL; 211 212 assert(pci_is_express(dev)); 213 214 pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset, 215 PCI_EXP_VER1_SIZEOF, &local_err); 216 if (pos < 0) { 217 error_report_err(local_err); 218 return pos; 219 } 220 dev->exp.exp_cap = pos; 221 222 pcie_cap_v1_fill(dev, port, type, PCI_EXP_FLAGS_VER1); 223 224 return pos; 225 } 226 227 static int 228 pcie_endpoint_cap_common_init(PCIDevice *dev, uint8_t offset, uint8_t cap_size) 229 { 230 uint8_t type = PCI_EXP_TYPE_ENDPOINT; 231 Error *local_err = NULL; 232 int ret; 233 234 /* 235 * Windows guests will report Code 10, device cannot start, if 236 * a regular Endpoint type is exposed on a root complex. These 237 * should instead be Root Complex Integrated Endpoints. 238 */ 239 if (pci_bus_is_express(pci_get_bus(dev)) 240 && pci_bus_is_root(pci_get_bus(dev))) { 241 type = PCI_EXP_TYPE_RC_END; 242 } 243 244 if (cap_size == PCI_EXP_VER1_SIZEOF) { 245 return pcie_cap_v1_init(dev, offset, type, 0); 246 } else { 247 ret = pcie_cap_init(dev, offset, type, 0, &local_err); 248 249 if (ret < 0) { 250 error_report_err(local_err); 251 } 252 253 return ret; 254 } 255 } 256 257 int pcie_endpoint_cap_init(PCIDevice *dev, uint8_t offset) 258 { 259 return pcie_endpoint_cap_common_init(dev, offset, PCI_EXP_VER2_SIZEOF); 260 } 261 262 int pcie_endpoint_cap_v1_init(PCIDevice *dev, uint8_t offset) 263 { 264 return pcie_endpoint_cap_common_init(dev, offset, PCI_EXP_VER1_SIZEOF); 265 } 266 267 void pcie_cap_exit(PCIDevice *dev) 268 { 269 pci_del_capability(dev, PCI_CAP_ID_EXP, PCI_EXP_VER2_SIZEOF); 270 } 271 272 void pcie_cap_v1_exit(PCIDevice *dev) 273 { 274 pci_del_capability(dev, PCI_CAP_ID_EXP, PCI_EXP_VER1_SIZEOF); 275 } 276 277 uint8_t pcie_cap_get_type(const PCIDevice *dev) 278 { 279 uint32_t pos = dev->exp.exp_cap; 280 assert(pos > 0); 281 return (pci_get_word(dev->config + pos + PCI_EXP_FLAGS) & 282 PCI_EXP_FLAGS_TYPE) >> PCI_EXP_FLAGS_TYPE_SHIFT; 283 } 284 285 uint8_t pcie_cap_get_version(const PCIDevice *dev) 286 { 287 uint32_t pos = dev->exp.exp_cap; 288 assert(pos > 0); 289 return pci_get_word(dev->config + pos + PCI_EXP_FLAGS) & PCI_EXP_FLAGS_VERS; 290 } 291 292 /* MSI/MSI-X */ 293 /* pci express interrupt message number */ 294 /* 7.8.2 PCI Express Capabilities Register: Interrupt Message Number */ 295 void pcie_cap_flags_set_vector(PCIDevice *dev, uint8_t vector) 296 { 297 uint8_t *exp_cap = dev->config + dev->exp.exp_cap; 298 assert(vector < 32); 299 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_FLAGS, PCI_EXP_FLAGS_IRQ); 300 pci_word_test_and_set_mask(exp_cap + PCI_EXP_FLAGS, 301 vector << PCI_EXP_FLAGS_IRQ_SHIFT); 302 } 303 304 uint8_t pcie_cap_flags_get_vector(PCIDevice *dev) 305 { 306 return (pci_get_word(dev->config + dev->exp.exp_cap + PCI_EXP_FLAGS) & 307 PCI_EXP_FLAGS_IRQ) >> PCI_EXP_FLAGS_IRQ_SHIFT; 308 } 309 310 void pcie_cap_deverr_init(PCIDevice *dev) 311 { 312 uint32_t pos = dev->exp.exp_cap; 313 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP, 314 PCI_EXP_DEVCAP_RBER); 315 pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL, 316 PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | 317 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE); 318 pci_long_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_DEVSTA, 319 PCI_EXP_DEVSTA_CED | PCI_EXP_DEVSTA_NFED | 320 PCI_EXP_DEVSTA_FED | PCI_EXP_DEVSTA_URD); 321 } 322 323 void pcie_cap_deverr_reset(PCIDevice *dev) 324 { 325 uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL; 326 pci_long_test_and_clear_mask(devctl, 327 PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | 328 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE); 329 } 330 331 void pcie_cap_lnkctl_init(PCIDevice *dev) 332 { 333 uint32_t pos = dev->exp.exp_cap; 334 pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_LNKCTL, 335 PCI_EXP_LNKCTL_CCC | PCI_EXP_LNKCTL_ES); 336 } 337 338 void pcie_cap_lnkctl_reset(PCIDevice *dev) 339 { 340 uint8_t *lnkctl = dev->config + dev->exp.exp_cap + PCI_EXP_LNKCTL; 341 pci_long_test_and_clear_mask(lnkctl, 342 PCI_EXP_LNKCTL_CCC | PCI_EXP_LNKCTL_ES); 343 } 344 345 static void hotplug_event_update_event_status(PCIDevice *dev) 346 { 347 uint32_t pos = dev->exp.exp_cap; 348 uint8_t *exp_cap = dev->config + pos; 349 uint16_t sltctl = pci_get_word(exp_cap + PCI_EXP_SLTCTL); 350 uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA); 351 352 dev->exp.hpev_notified = (sltctl & PCI_EXP_SLTCTL_HPIE) && 353 (sltsta & sltctl & PCI_EXP_HP_EV_SUPPORTED); 354 } 355 356 static void hotplug_event_notify(PCIDevice *dev) 357 { 358 bool prev = dev->exp.hpev_notified; 359 360 hotplug_event_update_event_status(dev); 361 362 if (prev == dev->exp.hpev_notified) { 363 return; 364 } 365 366 /* Note: the logic above does not take into account whether interrupts 367 * are masked. The result is that interrupt will be sent when it is 368 * subsequently unmasked. This appears to be legal: Section 6.7.3.4: 369 * The Port may optionally send an MSI when there are hot-plug events that 370 * occur while interrupt generation is disabled, and interrupt generation is 371 * subsequently enabled. */ 372 if (msix_enabled(dev)) { 373 msix_notify(dev, pcie_cap_flags_get_vector(dev)); 374 } else if (msi_enabled(dev)) { 375 msi_notify(dev, pcie_cap_flags_get_vector(dev)); 376 } else if (pci_intx(dev) != -1) { 377 pci_set_irq(dev, dev->exp.hpev_notified); 378 } 379 } 380 381 static void hotplug_event_clear(PCIDevice *dev) 382 { 383 hotplug_event_update_event_status(dev); 384 if (!msix_enabled(dev) && !msi_enabled(dev) && pci_intx(dev) != -1 && 385 !dev->exp.hpev_notified) { 386 pci_irq_deassert(dev); 387 } 388 } 389 390 void pcie_cap_slot_enable_power(PCIDevice *dev) 391 { 392 uint8_t *exp_cap = dev->config + dev->exp.exp_cap; 393 uint32_t sltcap = pci_get_long(exp_cap + PCI_EXP_SLTCAP); 394 395 if (sltcap & PCI_EXP_SLTCAP_PCP) { 396 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL, 397 PCI_EXP_SLTCTL_PCC); 398 } 399 } 400 401 static void pcie_set_power_device(PCIBus *bus, PCIDevice *dev, void *opaque) 402 { 403 bool *power = opaque; 404 405 pci_set_power(dev, *power); 406 } 407 408 static void pcie_cap_update_power(PCIDevice *hotplug_dev) 409 { 410 uint8_t *exp_cap = hotplug_dev->config + hotplug_dev->exp.exp_cap; 411 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(hotplug_dev)); 412 uint32_t sltcap = pci_get_long(exp_cap + PCI_EXP_SLTCAP); 413 uint16_t sltctl = pci_get_word(exp_cap + PCI_EXP_SLTCTL); 414 bool power = true; 415 416 if (sltcap & PCI_EXP_SLTCAP_PCP) { 417 power = (sltctl & PCI_EXP_SLTCTL_PCC) == PCI_EXP_SLTCTL_PWR_ON; 418 /* Don't we need to check also (sltctl & PCI_EXP_SLTCTL_PIC) ? */ 419 } 420 421 pci_for_each_device(sec_bus, pci_bus_num(sec_bus), 422 pcie_set_power_device, &power); 423 } 424 425 /* 426 * A PCI Express Hot-Plug Event has occurred, so update slot status register 427 * and notify OS of the event if necessary. 428 * 429 * 6.7.3 PCI Express Hot-Plug Events 430 * 6.7.3.4 Software Notification of Hot-Plug Events 431 */ 432 static void pcie_cap_slot_event(PCIDevice *dev, PCIExpressHotPlugEvent event) 433 { 434 /* Minor optimization: if nothing changed - no event is needed. */ 435 if (pci_word_test_and_set_mask(dev->config + dev->exp.exp_cap + 436 PCI_EXP_SLTSTA, event) == event) { 437 return; 438 } 439 hotplug_event_notify(dev); 440 } 441 442 static void pcie_cap_slot_plug_common(PCIDevice *hotplug_dev, DeviceState *dev, 443 Error **errp) 444 { 445 uint8_t *exp_cap = hotplug_dev->config + hotplug_dev->exp.exp_cap; 446 uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA); 447 448 PCIE_DEV_PRINTF(PCI_DEVICE(dev), "hotplug state: 0x%x\n", sltsta); 449 if (sltsta & PCI_EXP_SLTSTA_EIS) { 450 /* the slot is electromechanically locked. 451 * This error is propagated up to qdev and then to HMP/QMP. 452 */ 453 error_setg_errno(errp, EBUSY, "slot is electromechanically locked"); 454 } 455 } 456 457 void pcie_cap_slot_pre_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, 458 Error **errp) 459 { 460 PCIDevice *hotplug_pdev = PCI_DEVICE(hotplug_dev); 461 uint8_t *exp_cap = hotplug_pdev->config + hotplug_pdev->exp.exp_cap; 462 uint32_t sltcap = pci_get_word(exp_cap + PCI_EXP_SLTCAP); 463 464 /* Check if hot-plug is disabled on the slot */ 465 if (dev->hotplugged && (sltcap & PCI_EXP_SLTCAP_HPC) == 0) { 466 error_setg(errp, "Hot-plug failed: unsupported by the port device '%s'", 467 DEVICE(hotplug_pdev)->id); 468 return; 469 } 470 471 pcie_cap_slot_plug_common(PCI_DEVICE(hotplug_dev), dev, errp); 472 } 473 474 void pcie_cap_slot_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, 475 Error **errp) 476 { 477 PCIDevice *hotplug_pdev = PCI_DEVICE(hotplug_dev); 478 uint8_t *exp_cap = hotplug_pdev->config + hotplug_pdev->exp.exp_cap; 479 PCIDevice *pci_dev = PCI_DEVICE(dev); 480 uint32_t lnkcap = pci_get_long(exp_cap + PCI_EXP_LNKCAP); 481 482 if (pci_is_vf(pci_dev)) { 483 /* Virtual function cannot be physically disconnected */ 484 return; 485 } 486 487 /* Don't send event when device is enabled during qemu machine creation: 488 * it is present on boot, no hotplug event is necessary. We do send an 489 * event when the device is disabled later. */ 490 if (!dev->hotplugged) { 491 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA, 492 PCI_EXP_SLTSTA_PDS); 493 if (pci_dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA || 494 (lnkcap & PCI_EXP_LNKCAP_DLLLARC)) { 495 pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA, 496 PCI_EXP_LNKSTA_DLLLA); 497 } 498 pcie_cap_update_power(hotplug_pdev); 499 return; 500 } 501 502 /* To enable multifunction hot-plug, we just ensure the function 503 * 0 added last. When function 0 is added, we set the sltsta and 504 * inform OS via event notification. 505 */ 506 if (pci_get_function_0(pci_dev)) { 507 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA, 508 PCI_EXP_SLTSTA_PDS); 509 if (pci_dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA || 510 (lnkcap & PCI_EXP_LNKCAP_DLLLARC)) { 511 pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA, 512 PCI_EXP_LNKSTA_DLLLA); 513 } 514 pcie_cap_slot_event(hotplug_pdev, 515 PCI_EXP_HP_EV_PDC | PCI_EXP_HP_EV_ABP); 516 pcie_cap_update_power(hotplug_pdev); 517 } 518 } 519 520 void pcie_cap_slot_unplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, 521 Error **errp) 522 { 523 qdev_unrealize(dev); 524 } 525 526 static void pcie_unplug_device(PCIBus *bus, PCIDevice *dev, void *opaque) 527 { 528 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(DEVICE(dev)); 529 530 if (dev->partially_hotplugged) { 531 dev->qdev.pending_deleted_event = false; 532 return; 533 } 534 hotplug_handler_unplug(hotplug_ctrl, DEVICE(dev), &error_abort); 535 object_unparent(OBJECT(dev)); 536 } 537 538 static void pcie_cap_slot_do_unplug(PCIDevice *dev) 539 { 540 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev)); 541 uint8_t *exp_cap = dev->config + dev->exp.exp_cap; 542 uint32_t lnkcap = pci_get_long(exp_cap + PCI_EXP_LNKCAP); 543 544 pci_for_each_device_under_bus(sec_bus, pcie_unplug_device, NULL); 545 546 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA, 547 PCI_EXP_SLTSTA_PDS); 548 if (dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA || 549 (lnkcap & PCI_EXP_LNKCAP_DLLLARC)) { 550 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_LNKSTA, 551 PCI_EXP_LNKSTA_DLLLA); 552 } 553 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA, 554 PCI_EXP_SLTSTA_PDC); 555 } 556 557 void pcie_cap_slot_unplug_request_cb(HotplugHandler *hotplug_dev, 558 DeviceState *dev, Error **errp) 559 { 560 Error *local_err = NULL; 561 PCIDevice *pci_dev = PCI_DEVICE(dev); 562 PCIBus *bus = pci_get_bus(pci_dev); 563 PCIDevice *hotplug_pdev = PCI_DEVICE(hotplug_dev); 564 uint8_t *exp_cap = hotplug_pdev->config + hotplug_pdev->exp.exp_cap; 565 uint32_t sltcap = pci_get_word(exp_cap + PCI_EXP_SLTCAP); 566 uint16_t sltctl = pci_get_word(exp_cap + PCI_EXP_SLTCTL); 567 568 /* Check if hot-unplug is disabled on the slot */ 569 if ((sltcap & PCI_EXP_SLTCAP_HPC) == 0) { 570 error_setg(errp, "Hot-unplug failed: " 571 "unsupported by the port device '%s'", 572 DEVICE(hotplug_pdev)->id); 573 return; 574 } 575 576 pcie_cap_slot_plug_common(hotplug_pdev, dev, &local_err); 577 if (local_err) { 578 error_propagate(errp, local_err); 579 return; 580 } 581 582 if ((sltctl & PCI_EXP_SLTCTL_PIC) == PCI_EXP_SLTCTL_PWR_IND_BLINK) { 583 error_setg(errp, "Hot-unplug failed: " 584 "guest is busy (power indicator blinking)"); 585 return; 586 } 587 588 dev->pending_deleted_event = true; 589 dev->pending_deleted_expires_ms = 590 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 5000; /* 5 secs */ 591 592 /* In case user cancel the operation of multi-function hot-add, 593 * remove the function that is unexposed to guest individually, 594 * without interaction with guest. 595 */ 596 if (pci_dev->devfn && 597 !bus->devices[0]) { 598 pcie_unplug_device(bus, pci_dev, NULL); 599 600 return; 601 } 602 603 if (pcie_sltctl_powered_off(sltctl)) { 604 /* slot is powered off -> unplug without round-trip to the guest */ 605 pcie_cap_slot_do_unplug(hotplug_pdev); 606 hotplug_event_notify(hotplug_pdev); 607 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA, 608 PCI_EXP_SLTSTA_ABP); 609 return; 610 } 611 612 pcie_cap_slot_push_attention_button(hotplug_pdev); 613 } 614 615 /* pci express slot for pci express root/downstream port 616 PCI express capability slot registers */ 617 void pcie_cap_slot_init(PCIDevice *dev, PCIESlot *s) 618 { 619 uint32_t pos = dev->exp.exp_cap; 620 621 pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_FLAGS, 622 PCI_EXP_FLAGS_SLOT); 623 624 pci_long_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCAP, 625 ~PCI_EXP_SLTCAP_PSN); 626 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP, 627 (s->slot << PCI_EXP_SLTCAP_PSN_SHIFT) | 628 PCI_EXP_SLTCAP_EIP | 629 PCI_EXP_SLTCAP_PIP | 630 PCI_EXP_SLTCAP_AIP | 631 PCI_EXP_SLTCAP_ABP); 632 633 /* 634 * Expose native hot-plug on all bridges if hot-plug is enabled on the slot. 635 * (unless broken 6.1 ABI is enforced for compat reasons) 636 */ 637 if (s->hotplug && 638 (!s->hide_native_hotplug_cap || DEVICE(dev)->hotplugged)) { 639 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP, 640 PCI_EXP_SLTCAP_HPS | 641 PCI_EXP_SLTCAP_HPC); 642 } 643 644 if (dev->cap_present & QEMU_PCIE_SLTCAP_PCP) { 645 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP, 646 PCI_EXP_SLTCAP_PCP); 647 pci_word_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCTL, 648 PCI_EXP_SLTCTL_PCC); 649 pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL, 650 PCI_EXP_SLTCTL_PCC); 651 } 652 653 pci_word_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCTL, 654 PCI_EXP_SLTCTL_PIC | 655 PCI_EXP_SLTCTL_AIC); 656 pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCTL, 657 PCI_EXP_SLTCTL_PWR_IND_OFF | 658 PCI_EXP_SLTCTL_ATTN_IND_OFF); 659 pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL, 660 PCI_EXP_SLTCTL_PIC | 661 PCI_EXP_SLTCTL_AIC | 662 PCI_EXP_SLTCTL_HPIE | 663 PCI_EXP_SLTCTL_CCIE | 664 PCI_EXP_SLTCTL_PDCE | 665 PCI_EXP_SLTCTL_ABPE); 666 /* Although reading PCI_EXP_SLTCTL_EIC returns always 0, 667 * make the bit writable here in order to detect 1b is written. 668 * pcie_cap_slot_write_config() test-and-clear the bit, so 669 * this bit always returns 0 to the guest. 670 */ 671 pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL, 672 PCI_EXP_SLTCTL_EIC); 673 674 pci_word_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_SLTSTA, 675 PCI_EXP_HP_EV_SUPPORTED); 676 677 /* Avoid migration abortion when this device hot-removed by guest */ 678 pci_word_test_and_clear_mask(dev->cmask + pos + PCI_EXP_SLTSTA, 679 PCI_EXP_SLTSTA_PDS); 680 681 dev->exp.hpev_notified = false; 682 683 qbus_set_hotplug_handler(BUS(pci_bridge_get_sec_bus(PCI_BRIDGE(dev))), 684 OBJECT(dev)); 685 } 686 687 void pcie_cap_slot_reset(PCIDevice *dev) 688 { 689 uint8_t *exp_cap = dev->config + dev->exp.exp_cap; 690 uint8_t port_type = pcie_cap_get_type(dev); 691 692 assert(port_type == PCI_EXP_TYPE_DOWNSTREAM || 693 port_type == PCI_EXP_TYPE_ROOT_PORT); 694 695 PCIE_DEV_PRINTF(dev, "reset\n"); 696 697 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL, 698 PCI_EXP_SLTCTL_EIC | 699 PCI_EXP_SLTCTL_PIC | 700 PCI_EXP_SLTCTL_AIC | 701 PCI_EXP_SLTCTL_HPIE | 702 PCI_EXP_SLTCTL_CCIE | 703 PCI_EXP_SLTCTL_PDCE | 704 PCI_EXP_SLTCTL_ABPE); 705 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL, 706 PCI_EXP_SLTCTL_PWR_IND_OFF | 707 PCI_EXP_SLTCTL_ATTN_IND_OFF); 708 709 if (dev->cap_present & QEMU_PCIE_SLTCAP_PCP) { 710 /* Downstream ports enforce device number 0. */ 711 bool populated = pci_bridge_get_sec_bus(PCI_BRIDGE(dev))->devices[0]; 712 uint16_t pic; 713 714 if (populated) { 715 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL, 716 PCI_EXP_SLTCTL_PCC); 717 } else { 718 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL, 719 PCI_EXP_SLTCTL_PCC); 720 } 721 722 pic = populated ? 723 PCI_EXP_SLTCTL_PWR_IND_ON : PCI_EXP_SLTCTL_PWR_IND_OFF; 724 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL, pic); 725 } 726 727 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA, 728 PCI_EXP_SLTSTA_EIS |/* on reset, 729 the lock is released */ 730 PCI_EXP_SLTSTA_CC | 731 PCI_EXP_SLTSTA_PDC | 732 PCI_EXP_SLTSTA_ABP); 733 734 pcie_cap_update_power(dev); 735 hotplug_event_update_event_status(dev); 736 } 737 738 void pcie_cap_slot_get(PCIDevice *dev, uint16_t *slt_ctl, uint16_t *slt_sta) 739 { 740 uint32_t pos = dev->exp.exp_cap; 741 uint8_t *exp_cap = dev->config + pos; 742 *slt_ctl = pci_get_word(exp_cap + PCI_EXP_SLTCTL); 743 *slt_sta = pci_get_word(exp_cap + PCI_EXP_SLTSTA); 744 } 745 746 void pcie_cap_slot_write_config(PCIDevice *dev, 747 uint16_t old_slt_ctl, uint16_t old_slt_sta, 748 uint32_t addr, uint32_t val, int len) 749 { 750 uint32_t pos = dev->exp.exp_cap; 751 uint8_t *exp_cap = dev->config + pos; 752 uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA); 753 754 if (ranges_overlap(addr, len, pos + PCI_EXP_SLTSTA, 2)) { 755 /* 756 * Guests tend to clears all bits during init. 757 * If they clear bits that weren't set this is racy and will lose events: 758 * not a big problem for manual button presses, but a problem for us. 759 * As a work-around, detect this and revert status to what it was 760 * before the write. 761 * 762 * Note: in theory this can be detected as a duplicate button press 763 * which cancels the previous press. Does not seem to happen in 764 * practice as guests seem to only have this bug during init. 765 */ 766 #define PCIE_SLOT_EVENTS (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD | \ 767 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC | \ 768 PCI_EXP_SLTSTA_CC) 769 770 if (val & ~old_slt_sta & PCIE_SLOT_EVENTS) { 771 sltsta = (sltsta & ~PCIE_SLOT_EVENTS) | (old_slt_sta & PCIE_SLOT_EVENTS); 772 pci_set_word(exp_cap + PCI_EXP_SLTSTA, sltsta); 773 } 774 hotplug_event_clear(dev); 775 } 776 777 if (!ranges_overlap(addr, len, pos + PCI_EXP_SLTCTL, 2)) { 778 return; 779 } 780 781 if (pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL, 782 PCI_EXP_SLTCTL_EIC)) { 783 sltsta ^= PCI_EXP_SLTSTA_EIS; /* toggle PCI_EXP_SLTSTA_EIS bit */ 784 pci_set_word(exp_cap + PCI_EXP_SLTSTA, sltsta); 785 PCIE_DEV_PRINTF(dev, "PCI_EXP_SLTCTL_EIC: " 786 "sltsta -> 0x%02"PRIx16"\n", 787 sltsta); 788 } 789 790 /* 791 * If the slot is populated, power indicator is off and power 792 * controller is off, it is safe to detach the devices. 793 * 794 * Note: don't detach if condition was already true: 795 * this is a work around for guests that overwrite 796 * control of powered off slots before powering them on. 797 */ 798 if ((sltsta & PCI_EXP_SLTSTA_PDS) && pcie_sltctl_powered_off(val) && 799 !pcie_sltctl_powered_off(old_slt_ctl)) 800 { 801 pcie_cap_slot_do_unplug(dev); 802 } 803 pcie_cap_update_power(dev); 804 805 hotplug_event_notify(dev); 806 807 /* 808 * 6.7.3.2 Command Completed Events 809 * 810 * Software issues a command to a hot-plug capable Downstream Port by 811 * issuing a write transaction that targets any portion of the Port’s Slot 812 * Control register. A single write to the Slot Control register is 813 * considered to be a single command, even if the write affects more than 814 * one field in the Slot Control register. In response to this transaction, 815 * the Port must carry out the requested actions and then set the 816 * associated status field for the command completed event. */ 817 818 /* Real hardware might take a while to complete requested command because 819 * physical movement would be involved like locking the electromechanical 820 * lock. However in our case, command is completed instantaneously above, 821 * so send a command completion event right now. 822 */ 823 pcie_cap_slot_event(dev, PCI_EXP_HP_EV_CCI); 824 } 825 826 int pcie_cap_slot_post_load(void *opaque, int version_id) 827 { 828 PCIDevice *dev = opaque; 829 hotplug_event_update_event_status(dev); 830 pcie_cap_update_power(dev); 831 return 0; 832 } 833 834 void pcie_cap_slot_push_attention_button(PCIDevice *dev) 835 { 836 pcie_cap_slot_event(dev, PCI_EXP_HP_EV_ABP); 837 } 838 839 /* root control/capabilities/status. PME isn't emulated for now */ 840 void pcie_cap_root_init(PCIDevice *dev) 841 { 842 pci_set_word(dev->wmask + dev->exp.exp_cap + PCI_EXP_RTCTL, 843 PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE | 844 PCI_EXP_RTCTL_SEFEE); 845 } 846 847 void pcie_cap_root_reset(PCIDevice *dev) 848 { 849 pci_set_word(dev->config + dev->exp.exp_cap + PCI_EXP_RTCTL, 0); 850 } 851 852 /* function level reset(FLR) */ 853 void pcie_cap_flr_init(PCIDevice *dev) 854 { 855 pci_long_test_and_set_mask(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCAP, 856 PCI_EXP_DEVCAP_FLR); 857 858 /* Although reading BCR_FLR returns always 0, 859 * the bit is made writable here in order to detect the 1b is written 860 * pcie_cap_flr_write_config() test-and-clear the bit, so 861 * this bit always returns 0 to the guest. 862 */ 863 pci_word_test_and_set_mask(dev->wmask + dev->exp.exp_cap + PCI_EXP_DEVCTL, 864 PCI_EXP_DEVCTL_BCR_FLR); 865 } 866 867 void pcie_cap_flr_write_config(PCIDevice *dev, 868 uint32_t addr, uint32_t val, int len) 869 { 870 uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL; 871 if (pci_get_word(devctl) & PCI_EXP_DEVCTL_BCR_FLR) { 872 /* Clear PCI_EXP_DEVCTL_BCR_FLR after invoking the reset handler 873 so the handler can detect FLR by looking at this bit. */ 874 pci_device_reset(dev); 875 pci_word_test_and_clear_mask(devctl, PCI_EXP_DEVCTL_BCR_FLR); 876 } 877 } 878 879 /* Alternative Routing-ID Interpretation (ARI) 880 * forwarding support for root and downstream ports 881 */ 882 void pcie_cap_arifwd_init(PCIDevice *dev) 883 { 884 uint32_t pos = dev->exp.exp_cap; 885 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP2, 886 PCI_EXP_DEVCAP2_ARI); 887 pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL2, 888 PCI_EXP_DEVCTL2_ARI); 889 } 890 891 void pcie_cap_arifwd_reset(PCIDevice *dev) 892 { 893 uint8_t *devctl2 = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2; 894 pci_long_test_and_clear_mask(devctl2, PCI_EXP_DEVCTL2_ARI); 895 } 896 897 bool pcie_cap_is_arifwd_enabled(const PCIDevice *dev) 898 { 899 if (!pci_is_express(dev)) { 900 return false; 901 } 902 if (!dev->exp.exp_cap) { 903 return false; 904 } 905 906 return pci_get_long(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2) & 907 PCI_EXP_DEVCTL2_ARI; 908 } 909 910 /************************************************************************** 911 * pci express extended capability list management functions 912 * uint16_t ext_cap_id (16 bit) 913 * uint8_t cap_ver (4 bit) 914 * uint16_t cap_offset (12 bit) 915 * uint16_t ext_cap_size 916 */ 917 918 /* Passing a cap_id value > 0xffff will return 0 and put end of list in prev */ 919 static uint16_t pcie_find_capability_list(PCIDevice *dev, uint32_t cap_id, 920 uint16_t *prev_p) 921 { 922 uint16_t prev = 0; 923 uint16_t next; 924 uint32_t header = pci_get_long(dev->config + PCI_CONFIG_SPACE_SIZE); 925 926 if (!header) { 927 /* no extended capability */ 928 next = 0; 929 goto out; 930 } 931 for (next = PCI_CONFIG_SPACE_SIZE; next; 932 prev = next, next = PCI_EXT_CAP_NEXT(header)) { 933 934 assert(next >= PCI_CONFIG_SPACE_SIZE); 935 assert(next <= PCIE_CONFIG_SPACE_SIZE - 8); 936 937 header = pci_get_long(dev->config + next); 938 if (PCI_EXT_CAP_ID(header) == cap_id) { 939 break; 940 } 941 } 942 943 out: 944 if (prev_p) { 945 *prev_p = prev; 946 } 947 return next; 948 } 949 950 uint16_t pcie_find_capability(PCIDevice *dev, uint16_t cap_id) 951 { 952 return pcie_find_capability_list(dev, cap_id, NULL); 953 } 954 955 static void pcie_ext_cap_set_next(PCIDevice *dev, uint16_t pos, uint16_t next) 956 { 957 uint32_t header = pci_get_long(dev->config + pos); 958 assert(!(next & (PCI_EXT_CAP_ALIGN - 1))); 959 header = (header & ~PCI_EXT_CAP_NEXT_MASK) | 960 ((next << PCI_EXT_CAP_NEXT_SHIFT) & PCI_EXT_CAP_NEXT_MASK); 961 pci_set_long(dev->config + pos, header); 962 } 963 964 /* 965 * Caller must supply valid (offset, size) such that the range wouldn't 966 * overlap with other capability or other registers. 967 * This function doesn't check it. 968 */ 969 void pcie_add_capability(PCIDevice *dev, 970 uint16_t cap_id, uint8_t cap_ver, 971 uint16_t offset, uint16_t size) 972 { 973 assert(offset >= PCI_CONFIG_SPACE_SIZE); 974 assert(offset < (uint16_t)(offset + size)); 975 assert((uint16_t)(offset + size) <= PCIE_CONFIG_SPACE_SIZE); 976 assert(size >= 8); 977 assert(pci_is_express(dev)); 978 979 if (offset != PCI_CONFIG_SPACE_SIZE) { 980 uint16_t prev; 981 982 /* 983 * 0xffffffff is not a valid cap id (it's a 16 bit field). use 984 * internally to find the last capability in the linked list. 985 */ 986 pcie_find_capability_list(dev, 0xffffffff, &prev); 987 assert(prev >= PCI_CONFIG_SPACE_SIZE); 988 pcie_ext_cap_set_next(dev, prev, offset); 989 } 990 pci_set_long(dev->config + offset, PCI_EXT_CAP(cap_id, cap_ver, 0)); 991 992 /* Make capability read-only by default */ 993 memset(dev->wmask + offset, 0, size); 994 memset(dev->w1cmask + offset, 0, size); 995 /* Check capability by default */ 996 memset(dev->cmask + offset, 0xFF, size); 997 } 998 999 /* 1000 * Sync the PCIe Link Status negotiated speed and width of a bridge with the 1001 * downstream device. If downstream device is not present, re-write with the 1002 * Link Capability fields. If downstream device reports invalid width or 1003 * speed, replace with minimum values (LnkSta fields are RsvdZ on VFs but such 1004 * values interfere with PCIe native hotplug detecting new devices). Limit 1005 * width and speed to bridge capabilities for compatibility. Use config_read 1006 * to access the downstream device since it could be an assigned device with 1007 * volatile link information. 1008 */ 1009 void pcie_sync_bridge_lnk(PCIDevice *bridge_dev) 1010 { 1011 PCIBridge *br = PCI_BRIDGE(bridge_dev); 1012 PCIBus *bus = pci_bridge_get_sec_bus(br); 1013 PCIDevice *target = bus->devices[0]; 1014 uint8_t *exp_cap = bridge_dev->config + bridge_dev->exp.exp_cap; 1015 uint16_t lnksta, lnkcap = pci_get_word(exp_cap + PCI_EXP_LNKCAP); 1016 1017 if (!target || !target->exp.exp_cap) { 1018 lnksta = lnkcap; 1019 } else { 1020 lnksta = target->config_read(target, 1021 target->exp.exp_cap + PCI_EXP_LNKSTA, 1022 sizeof(lnksta)); 1023 1024 if ((lnksta & PCI_EXP_LNKSTA_NLW) > (lnkcap & PCI_EXP_LNKCAP_MLW)) { 1025 lnksta &= ~PCI_EXP_LNKSTA_NLW; 1026 lnksta |= lnkcap & PCI_EXP_LNKCAP_MLW; 1027 } else if (!(lnksta & PCI_EXP_LNKSTA_NLW)) { 1028 lnksta |= QEMU_PCI_EXP_LNKSTA_NLW(QEMU_PCI_EXP_LNK_X1); 1029 } 1030 1031 if ((lnksta & PCI_EXP_LNKSTA_CLS) > (lnkcap & PCI_EXP_LNKCAP_SLS)) { 1032 lnksta &= ~PCI_EXP_LNKSTA_CLS; 1033 lnksta |= lnkcap & PCI_EXP_LNKCAP_SLS; 1034 } else if (!(lnksta & PCI_EXP_LNKSTA_CLS)) { 1035 lnksta |= QEMU_PCI_EXP_LNKSTA_CLS(QEMU_PCI_EXP_LNK_2_5GT); 1036 } 1037 } 1038 1039 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_LNKSTA, 1040 PCI_EXP_LNKSTA_CLS | PCI_EXP_LNKSTA_NLW); 1041 pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA, lnksta & 1042 (PCI_EXP_LNKSTA_CLS | PCI_EXP_LNKSTA_NLW)); 1043 } 1044 1045 /************************************************************************** 1046 * pci express extended capability helper functions 1047 */ 1048 1049 /* ARI */ 1050 void pcie_ari_init(PCIDevice *dev, uint16_t offset) 1051 { 1052 uint16_t nextfn = dev->cap_present & QEMU_PCIE_ARI_NEXTFN_1 ? 1 : 0; 1053 1054 pcie_add_capability(dev, PCI_EXT_CAP_ID_ARI, PCI_ARI_VER, 1055 offset, PCI_ARI_SIZEOF); 1056 pci_set_long(dev->config + offset + PCI_ARI_CAP, (nextfn & 0xff) << 8); 1057 } 1058 1059 void pcie_dev_ser_num_init(PCIDevice *dev, uint16_t offset, uint64_t ser_num) 1060 { 1061 static const int pci_dsn_ver = 1; 1062 static const int pci_dsn_cap = 4; 1063 1064 pcie_add_capability(dev, PCI_EXT_CAP_ID_DSN, pci_dsn_ver, offset, 1065 PCI_EXT_CAP_DSN_SIZEOF); 1066 pci_set_quad(dev->config + offset + pci_dsn_cap, ser_num); 1067 } 1068 1069 void pcie_ats_init(PCIDevice *dev, uint16_t offset, bool aligned) 1070 { 1071 pcie_add_capability(dev, PCI_EXT_CAP_ID_ATS, 0x1, 1072 offset, PCI_EXT_CAP_ATS_SIZEOF); 1073 1074 dev->exp.ats_cap = offset; 1075 1076 /* Invalidate Queue Depth 0 */ 1077 if (aligned) { 1078 pci_set_word(dev->config + offset + PCI_ATS_CAP, 1079 PCI_ATS_CAP_PAGE_ALIGNED); 1080 } 1081 /* STU 0, Disabled by default */ 1082 pci_set_word(dev->config + offset + PCI_ATS_CTRL, 0); 1083 1084 pci_set_word(dev->wmask + dev->exp.ats_cap + PCI_ATS_CTRL, 0x800f); 1085 } 1086 1087 /* ACS (Access Control Services) */ 1088 void pcie_acs_init(PCIDevice *dev, uint16_t offset) 1089 { 1090 bool is_downstream = pci_is_express_downstream_port(dev); 1091 uint16_t cap_bits = 0; 1092 1093 /* For endpoints, only multifunction devs may have an ACS capability: */ 1094 assert(is_downstream || 1095 (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) || 1096 PCI_FUNC(dev->devfn)); 1097 1098 pcie_add_capability(dev, PCI_EXT_CAP_ID_ACS, PCI_ACS_VER, offset, 1099 PCI_ACS_SIZEOF); 1100 dev->exp.acs_cap = offset; 1101 1102 if (is_downstream) { 1103 /* 1104 * Downstream ports must implement SV, TB, RR, CR, UF, and DT (with 1105 * caveats on the latter four that we ignore for simplicity). 1106 * Endpoints may also implement a subset of ACS capabilities, 1107 * but these are optional if the endpoint does not support 1108 * peer-to-peer between functions and thus omitted here. 1109 */ 1110 cap_bits = PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR | 1111 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT; 1112 } 1113 1114 pci_set_word(dev->config + offset + PCI_ACS_CAP, cap_bits); 1115 pci_set_word(dev->wmask + offset + PCI_ACS_CTRL, cap_bits); 1116 } 1117 1118 void pcie_acs_reset(PCIDevice *dev) 1119 { 1120 if (dev->exp.acs_cap) { 1121 pci_set_word(dev->config + dev->exp.acs_cap + PCI_ACS_CTRL, 0); 1122 } 1123 } 1124