1 /* 2 * pcie.c 3 * 4 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp> 5 * VA Linux Systems Japan K.K. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "qemu-common.h" 24 #include "hw/pci/pci_bridge.h" 25 #include "hw/pci/pcie.h" 26 #include "hw/pci/msix.h" 27 #include "hw/pci/msi.h" 28 #include "hw/pci/pci_bus.h" 29 #include "hw/pci/pcie_regs.h" 30 #include "qemu/range.h" 31 32 //#define DEBUG_PCIE 33 #ifdef DEBUG_PCIE 34 # define PCIE_DPRINTF(fmt, ...) \ 35 fprintf(stderr, "%s:%d " fmt, __func__, __LINE__, ## __VA_ARGS__) 36 #else 37 # define PCIE_DPRINTF(fmt, ...) do {} while (0) 38 #endif 39 #define PCIE_DEV_PRINTF(dev, fmt, ...) \ 40 PCIE_DPRINTF("%s:%x "fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__) 41 42 43 /*************************************************************************** 44 * pci express capability helper functions 45 */ 46 47 static void 48 pcie_cap_v1_fill(uint8_t *exp_cap, uint8_t port, uint8_t type, uint8_t version) 49 { 50 /* capability register 51 interrupt message number defaults to 0 */ 52 pci_set_word(exp_cap + PCI_EXP_FLAGS, 53 ((type << PCI_EXP_FLAGS_TYPE_SHIFT) & PCI_EXP_FLAGS_TYPE) | 54 version); 55 56 /* device capability register 57 * table 7-12: 58 * roll based error reporting bit must be set by all 59 * Functions conforming to the ECN, PCI Express Base 60 * Specification, Revision 1.1., or subsequent PCI Express Base 61 * Specification revisions. 62 */ 63 pci_set_long(exp_cap + PCI_EXP_DEVCAP, PCI_EXP_DEVCAP_RBER); 64 65 pci_set_long(exp_cap + PCI_EXP_LNKCAP, 66 (port << PCI_EXP_LNKCAP_PN_SHIFT) | 67 PCI_EXP_LNKCAP_ASPMS_0S | 68 PCI_EXP_LNK_MLW_1 | 69 PCI_EXP_LNK_LS_25); 70 71 pci_set_word(exp_cap + PCI_EXP_LNKSTA, 72 PCI_EXP_LNK_MLW_1 | PCI_EXP_LNK_LS_25 |PCI_EXP_LNKSTA_DLLLA); 73 } 74 75 int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, uint8_t port) 76 { 77 /* PCIe cap v2 init */ 78 int pos; 79 uint8_t *exp_cap; 80 81 assert(pci_is_express(dev)); 82 83 pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset, PCI_EXP_VER2_SIZEOF); 84 if (pos < 0) { 85 return pos; 86 } 87 dev->exp.exp_cap = pos; 88 exp_cap = dev->config + pos; 89 90 /* Filling values common with v1 */ 91 pcie_cap_v1_fill(exp_cap, port, type, PCI_EXP_FLAGS_VER2); 92 93 /* Filling v2 specific values */ 94 pci_set_long(exp_cap + PCI_EXP_DEVCAP2, 95 PCI_EXP_DEVCAP2_EFF | PCI_EXP_DEVCAP2_EETLPP); 96 97 pci_set_word(dev->wmask + pos + PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_EETLPPB); 98 return pos; 99 } 100 101 int pcie_cap_v1_init(PCIDevice *dev, uint8_t offset, uint8_t type, 102 uint8_t port) 103 { 104 /* PCIe cap v1 init */ 105 int pos; 106 uint8_t *exp_cap; 107 108 assert(pci_is_express(dev)); 109 110 pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset, PCI_EXP_VER1_SIZEOF); 111 if (pos < 0) { 112 return pos; 113 } 114 dev->exp.exp_cap = pos; 115 exp_cap = dev->config + pos; 116 117 pcie_cap_v1_fill(exp_cap, port, type, PCI_EXP_FLAGS_VER1); 118 119 return pos; 120 } 121 122 static int 123 pcie_endpoint_cap_common_init(PCIDevice *dev, uint8_t offset, uint8_t cap_size) 124 { 125 uint8_t type = PCI_EXP_TYPE_ENDPOINT; 126 127 /* 128 * Windows guests will report Code 10, device cannot start, if 129 * a regular Endpoint type is exposed on a root complex. These 130 * should instead be Root Complex Integrated Endpoints. 131 */ 132 if (pci_bus_is_express(dev->bus) && pci_bus_is_root(dev->bus)) { 133 type = PCI_EXP_TYPE_RC_END; 134 } 135 136 return (cap_size == PCI_EXP_VER1_SIZEOF) 137 ? pcie_cap_v1_init(dev, offset, type, 0) 138 : pcie_cap_init(dev, offset, type, 0); 139 } 140 141 int pcie_endpoint_cap_init(PCIDevice *dev, uint8_t offset) 142 { 143 return pcie_endpoint_cap_common_init(dev, offset, PCI_EXP_VER2_SIZEOF); 144 } 145 146 int pcie_endpoint_cap_v1_init(PCIDevice *dev, uint8_t offset) 147 { 148 return pcie_endpoint_cap_common_init(dev, offset, PCI_EXP_VER1_SIZEOF); 149 } 150 151 void pcie_cap_exit(PCIDevice *dev) 152 { 153 pci_del_capability(dev, PCI_CAP_ID_EXP, PCI_EXP_VER2_SIZEOF); 154 } 155 156 void pcie_cap_v1_exit(PCIDevice *dev) 157 { 158 pci_del_capability(dev, PCI_CAP_ID_EXP, PCI_EXP_VER1_SIZEOF); 159 } 160 161 uint8_t pcie_cap_get_type(const PCIDevice *dev) 162 { 163 uint32_t pos = dev->exp.exp_cap; 164 assert(pos > 0); 165 return (pci_get_word(dev->config + pos + PCI_EXP_FLAGS) & 166 PCI_EXP_FLAGS_TYPE) >> PCI_EXP_FLAGS_TYPE_SHIFT; 167 } 168 169 /* MSI/MSI-X */ 170 /* pci express interrupt message number */ 171 /* 7.8.2 PCI Express Capabilities Register: Interrupt Message Number */ 172 void pcie_cap_flags_set_vector(PCIDevice *dev, uint8_t vector) 173 { 174 uint8_t *exp_cap = dev->config + dev->exp.exp_cap; 175 assert(vector < 32); 176 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_FLAGS, PCI_EXP_FLAGS_IRQ); 177 pci_word_test_and_set_mask(exp_cap + PCI_EXP_FLAGS, 178 vector << PCI_EXP_FLAGS_IRQ_SHIFT); 179 } 180 181 uint8_t pcie_cap_flags_get_vector(PCIDevice *dev) 182 { 183 return (pci_get_word(dev->config + dev->exp.exp_cap + PCI_EXP_FLAGS) & 184 PCI_EXP_FLAGS_IRQ) >> PCI_EXP_FLAGS_IRQ_SHIFT; 185 } 186 187 void pcie_cap_deverr_init(PCIDevice *dev) 188 { 189 uint32_t pos = dev->exp.exp_cap; 190 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP, 191 PCI_EXP_DEVCAP_RBER); 192 pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL, 193 PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | 194 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE); 195 pci_long_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_DEVSTA, 196 PCI_EXP_DEVSTA_CED | PCI_EXP_DEVSTA_NFED | 197 PCI_EXP_DEVSTA_FED | PCI_EXP_DEVSTA_URD); 198 } 199 200 void pcie_cap_deverr_reset(PCIDevice *dev) 201 { 202 uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL; 203 pci_long_test_and_clear_mask(devctl, 204 PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | 205 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE); 206 } 207 208 static void hotplug_event_update_event_status(PCIDevice *dev) 209 { 210 uint32_t pos = dev->exp.exp_cap; 211 uint8_t *exp_cap = dev->config + pos; 212 uint16_t sltctl = pci_get_word(exp_cap + PCI_EXP_SLTCTL); 213 uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA); 214 215 dev->exp.hpev_notified = (sltctl & PCI_EXP_SLTCTL_HPIE) && 216 (sltsta & sltctl & PCI_EXP_HP_EV_SUPPORTED); 217 } 218 219 static void hotplug_event_notify(PCIDevice *dev) 220 { 221 bool prev = dev->exp.hpev_notified; 222 223 hotplug_event_update_event_status(dev); 224 225 if (prev == dev->exp.hpev_notified) { 226 return; 227 } 228 229 /* Note: the logic above does not take into account whether interrupts 230 * are masked. The result is that interrupt will be sent when it is 231 * subsequently unmasked. This appears to be legal: Section 6.7.3.4: 232 * The Port may optionally send an MSI when there are hot-plug events that 233 * occur while interrupt generation is disabled, and interrupt generation is 234 * subsequently enabled. */ 235 if (msix_enabled(dev)) { 236 msix_notify(dev, pcie_cap_flags_get_vector(dev)); 237 } else if (msi_enabled(dev)) { 238 msi_notify(dev, pcie_cap_flags_get_vector(dev)); 239 } else { 240 pci_set_irq(dev, dev->exp.hpev_notified); 241 } 242 } 243 244 static void hotplug_event_clear(PCIDevice *dev) 245 { 246 hotplug_event_update_event_status(dev); 247 if (!msix_enabled(dev) && !msi_enabled(dev) && !dev->exp.hpev_notified) { 248 pci_irq_deassert(dev); 249 } 250 } 251 252 /* 253 * A PCI Express Hot-Plug Event has occurred, so update slot status register 254 * and notify OS of the event if necessary. 255 * 256 * 6.7.3 PCI Express Hot-Plug Events 257 * 6.7.3.4 Software Notification of Hot-Plug Events 258 */ 259 static void pcie_cap_slot_event(PCIDevice *dev, PCIExpressHotPlugEvent event) 260 { 261 /* Minor optimization: if nothing changed - no event is needed. */ 262 if (pci_word_test_and_set_mask(dev->config + dev->exp.exp_cap + 263 PCI_EXP_SLTSTA, event)) { 264 return; 265 } 266 hotplug_event_notify(dev); 267 } 268 269 static void pcie_cap_slot_hotplug_common(PCIDevice *hotplug_dev, 270 DeviceState *dev, 271 uint8_t **exp_cap, Error **errp) 272 { 273 *exp_cap = hotplug_dev->config + hotplug_dev->exp.exp_cap; 274 uint16_t sltsta = pci_get_word(*exp_cap + PCI_EXP_SLTSTA); 275 276 PCIE_DEV_PRINTF(PCI_DEVICE(dev), "hotplug state: 0x%x\n", sltsta); 277 if (sltsta & PCI_EXP_SLTSTA_EIS) { 278 /* the slot is electromechanically locked. 279 * This error is propagated up to qdev and then to HMP/QMP. 280 */ 281 error_setg_errno(errp, EBUSY, "slot is electromechanically locked"); 282 } 283 } 284 285 void pcie_cap_slot_hotplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, 286 Error **errp) 287 { 288 uint8_t *exp_cap; 289 PCIDevice *pci_dev = PCI_DEVICE(dev); 290 291 pcie_cap_slot_hotplug_common(PCI_DEVICE(hotplug_dev), dev, &exp_cap, errp); 292 293 /* Don't send event when device is enabled during qemu machine creation: 294 * it is present on boot, no hotplug event is necessary. We do send an 295 * event when the device is disabled later. */ 296 if (!dev->hotplugged) { 297 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA, 298 PCI_EXP_SLTSTA_PDS); 299 return; 300 } 301 302 /* To enable multifunction hot-plug, we just ensure the function 303 * 0 added last. When function 0 is added, we set the sltsta and 304 * inform OS via event notification. 305 */ 306 if (pci_get_function_0(pci_dev)) { 307 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA, 308 PCI_EXP_SLTSTA_PDS); 309 pcie_cap_slot_event(PCI_DEVICE(hotplug_dev), 310 PCI_EXP_HP_EV_PDC | PCI_EXP_HP_EV_ABP); 311 } 312 } 313 314 static void pcie_unplug_device(PCIBus *bus, PCIDevice *dev, void *opaque) 315 { 316 object_unparent(OBJECT(dev)); 317 } 318 319 void pcie_cap_slot_hot_unplug_request_cb(HotplugHandler *hotplug_dev, 320 DeviceState *dev, Error **errp) 321 { 322 uint8_t *exp_cap; 323 PCIDevice *pci_dev = PCI_DEVICE(dev); 324 PCIBus *bus = pci_dev->bus; 325 326 pcie_cap_slot_hotplug_common(PCI_DEVICE(hotplug_dev), dev, &exp_cap, errp); 327 328 /* In case user cancel the operation of multi-function hot-add, 329 * remove the function that is unexposed to guest individually, 330 * without interaction with guest. 331 */ 332 if (pci_dev->devfn && 333 !bus->devices[0]) { 334 pcie_unplug_device(bus, pci_dev, NULL); 335 336 return; 337 } 338 339 pcie_cap_slot_push_attention_button(PCI_DEVICE(hotplug_dev)); 340 } 341 342 /* pci express slot for pci express root/downstream port 343 PCI express capability slot registers */ 344 void pcie_cap_slot_init(PCIDevice *dev, uint16_t slot) 345 { 346 uint32_t pos = dev->exp.exp_cap; 347 348 pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_FLAGS, 349 PCI_EXP_FLAGS_SLOT); 350 351 pci_long_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCAP, 352 ~PCI_EXP_SLTCAP_PSN); 353 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP, 354 (slot << PCI_EXP_SLTCAP_PSN_SHIFT) | 355 PCI_EXP_SLTCAP_EIP | 356 PCI_EXP_SLTCAP_HPS | 357 PCI_EXP_SLTCAP_HPC | 358 PCI_EXP_SLTCAP_PIP | 359 PCI_EXP_SLTCAP_AIP | 360 PCI_EXP_SLTCAP_ABP); 361 362 if (dev->cap_present & QEMU_PCIE_SLTCAP_PCP) { 363 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP, 364 PCI_EXP_SLTCAP_PCP); 365 pci_word_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCTL, 366 PCI_EXP_SLTCTL_PCC); 367 pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL, 368 PCI_EXP_SLTCTL_PCC); 369 } 370 371 pci_word_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCTL, 372 PCI_EXP_SLTCTL_PIC | 373 PCI_EXP_SLTCTL_AIC); 374 pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCTL, 375 PCI_EXP_SLTCTL_PIC_OFF | 376 PCI_EXP_SLTCTL_AIC_OFF); 377 pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL, 378 PCI_EXP_SLTCTL_PIC | 379 PCI_EXP_SLTCTL_AIC | 380 PCI_EXP_SLTCTL_HPIE | 381 PCI_EXP_SLTCTL_CCIE | 382 PCI_EXP_SLTCTL_PDCE | 383 PCI_EXP_SLTCTL_ABPE); 384 /* Although reading PCI_EXP_SLTCTL_EIC returns always 0, 385 * make the bit writable here in order to detect 1b is written. 386 * pcie_cap_slot_write_config() test-and-clear the bit, so 387 * this bit always returns 0 to the guest. 388 */ 389 pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL, 390 PCI_EXP_SLTCTL_EIC); 391 392 pci_word_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_SLTSTA, 393 PCI_EXP_HP_EV_SUPPORTED); 394 395 dev->exp.hpev_notified = false; 396 397 qbus_set_hotplug_handler(BUS(pci_bridge_get_sec_bus(PCI_BRIDGE(dev))), 398 DEVICE(dev), NULL); 399 } 400 401 void pcie_cap_slot_reset(PCIDevice *dev) 402 { 403 uint8_t *exp_cap = dev->config + dev->exp.exp_cap; 404 uint8_t port_type = pcie_cap_get_type(dev); 405 406 assert(port_type == PCI_EXP_TYPE_DOWNSTREAM || 407 port_type == PCI_EXP_TYPE_ROOT_PORT); 408 409 PCIE_DEV_PRINTF(dev, "reset\n"); 410 411 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL, 412 PCI_EXP_SLTCTL_EIC | 413 PCI_EXP_SLTCTL_PIC | 414 PCI_EXP_SLTCTL_AIC | 415 PCI_EXP_SLTCTL_HPIE | 416 PCI_EXP_SLTCTL_CCIE | 417 PCI_EXP_SLTCTL_PDCE | 418 PCI_EXP_SLTCTL_ABPE); 419 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL, 420 PCI_EXP_SLTCTL_AIC_OFF); 421 422 if (dev->cap_present & QEMU_PCIE_SLTCAP_PCP) { 423 /* Downstream ports enforce device number 0. */ 424 bool populated = pci_bridge_get_sec_bus(PCI_BRIDGE(dev))->devices[0]; 425 uint16_t pic; 426 427 if (populated) { 428 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL, 429 PCI_EXP_SLTCTL_PCC); 430 } else { 431 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL, 432 PCI_EXP_SLTCTL_PCC); 433 } 434 435 pic = populated ? PCI_EXP_SLTCTL_PIC_ON : PCI_EXP_SLTCTL_PIC_OFF; 436 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL, pic); 437 } 438 439 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA, 440 PCI_EXP_SLTSTA_EIS |/* on reset, 441 the lock is released */ 442 PCI_EXP_SLTSTA_CC | 443 PCI_EXP_SLTSTA_PDC | 444 PCI_EXP_SLTSTA_ABP); 445 446 hotplug_event_update_event_status(dev); 447 } 448 449 void pcie_cap_slot_write_config(PCIDevice *dev, 450 uint32_t addr, uint32_t val, int len) 451 { 452 uint32_t pos = dev->exp.exp_cap; 453 uint8_t *exp_cap = dev->config + pos; 454 uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA); 455 456 if (ranges_overlap(addr, len, pos + PCI_EXP_SLTSTA, 2)) { 457 hotplug_event_clear(dev); 458 } 459 460 if (!ranges_overlap(addr, len, pos + PCI_EXP_SLTCTL, 2)) { 461 return; 462 } 463 464 if (pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL, 465 PCI_EXP_SLTCTL_EIC)) { 466 sltsta ^= PCI_EXP_SLTSTA_EIS; /* toggle PCI_EXP_SLTSTA_EIS bit */ 467 pci_set_word(exp_cap + PCI_EXP_SLTSTA, sltsta); 468 PCIE_DEV_PRINTF(dev, "PCI_EXP_SLTCTL_EIC: " 469 "sltsta -> 0x%02"PRIx16"\n", 470 sltsta); 471 } 472 473 /* 474 * If the slot is polulated, power indicator is off and power 475 * controller is off, it is safe to detach the devices. 476 */ 477 if ((sltsta & PCI_EXP_SLTSTA_PDS) && (val & PCI_EXP_SLTCTL_PCC) && 478 ((val & PCI_EXP_SLTCTL_PIC_OFF) == PCI_EXP_SLTCTL_PIC_OFF)) { 479 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev)); 480 pci_for_each_device(sec_bus, pci_bus_num(sec_bus), 481 pcie_unplug_device, NULL); 482 483 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA, 484 PCI_EXP_SLTSTA_PDS); 485 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA, 486 PCI_EXP_SLTSTA_PDC); 487 } 488 489 hotplug_event_notify(dev); 490 491 /* 492 * 6.7.3.2 Command Completed Events 493 * 494 * Software issues a command to a hot-plug capable Downstream Port by 495 * issuing a write transaction that targets any portion of the Port’s Slot 496 * Control register. A single write to the Slot Control register is 497 * considered to be a single command, even if the write affects more than 498 * one field in the Slot Control register. In response to this transaction, 499 * the Port must carry out the requested actions and then set the 500 * associated status field for the command completed event. */ 501 502 /* Real hardware might take a while to complete requested command because 503 * physical movement would be involved like locking the electromechanical 504 * lock. However in our case, command is completed instantaneously above, 505 * so send a command completion event right now. 506 */ 507 pcie_cap_slot_event(dev, PCI_EXP_HP_EV_CCI); 508 } 509 510 int pcie_cap_slot_post_load(void *opaque, int version_id) 511 { 512 PCIDevice *dev = opaque; 513 hotplug_event_update_event_status(dev); 514 return 0; 515 } 516 517 void pcie_cap_slot_push_attention_button(PCIDevice *dev) 518 { 519 pcie_cap_slot_event(dev, PCI_EXP_HP_EV_ABP); 520 } 521 522 /* root control/capabilities/status. PME isn't emulated for now */ 523 void pcie_cap_root_init(PCIDevice *dev) 524 { 525 pci_set_word(dev->wmask + dev->exp.exp_cap + PCI_EXP_RTCTL, 526 PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE | 527 PCI_EXP_RTCTL_SEFEE); 528 } 529 530 void pcie_cap_root_reset(PCIDevice *dev) 531 { 532 pci_set_word(dev->config + dev->exp.exp_cap + PCI_EXP_RTCTL, 0); 533 } 534 535 /* function level reset(FLR) */ 536 void pcie_cap_flr_init(PCIDevice *dev) 537 { 538 pci_long_test_and_set_mask(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCAP, 539 PCI_EXP_DEVCAP_FLR); 540 541 /* Although reading BCR_FLR returns always 0, 542 * the bit is made writable here in order to detect the 1b is written 543 * pcie_cap_flr_write_config() test-and-clear the bit, so 544 * this bit always returns 0 to the guest. 545 */ 546 pci_word_test_and_set_mask(dev->wmask + dev->exp.exp_cap + PCI_EXP_DEVCTL, 547 PCI_EXP_DEVCTL_BCR_FLR); 548 } 549 550 void pcie_cap_flr_write_config(PCIDevice *dev, 551 uint32_t addr, uint32_t val, int len) 552 { 553 uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL; 554 if (pci_get_word(devctl) & PCI_EXP_DEVCTL_BCR_FLR) { 555 /* Clear PCI_EXP_DEVCTL_BCR_FLR after invoking the reset handler 556 so the handler can detect FLR by looking at this bit. */ 557 pci_device_reset(dev); 558 pci_word_test_and_clear_mask(devctl, PCI_EXP_DEVCTL_BCR_FLR); 559 } 560 } 561 562 /* Alternative Routing-ID Interpretation (ARI) 563 * forwarding support for root and downstream ports 564 */ 565 void pcie_cap_arifwd_init(PCIDevice *dev) 566 { 567 uint32_t pos = dev->exp.exp_cap; 568 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP2, 569 PCI_EXP_DEVCAP2_ARI); 570 pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL2, 571 PCI_EXP_DEVCTL2_ARI); 572 } 573 574 void pcie_cap_arifwd_reset(PCIDevice *dev) 575 { 576 uint8_t *devctl2 = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2; 577 pci_long_test_and_clear_mask(devctl2, PCI_EXP_DEVCTL2_ARI); 578 } 579 580 bool pcie_cap_is_arifwd_enabled(const PCIDevice *dev) 581 { 582 if (!pci_is_express(dev)) { 583 return false; 584 } 585 if (!dev->exp.exp_cap) { 586 return false; 587 } 588 589 return pci_get_long(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2) & 590 PCI_EXP_DEVCTL2_ARI; 591 } 592 593 /************************************************************************** 594 * pci express extended capability list management functions 595 * uint16_t ext_cap_id (16 bit) 596 * uint8_t cap_ver (4 bit) 597 * uint16_t cap_offset (12 bit) 598 * uint16_t ext_cap_size 599 */ 600 601 static uint16_t pcie_find_capability_list(PCIDevice *dev, uint16_t cap_id, 602 uint16_t *prev_p) 603 { 604 uint16_t prev = 0; 605 uint16_t next; 606 uint32_t header = pci_get_long(dev->config + PCI_CONFIG_SPACE_SIZE); 607 608 if (!header) { 609 /* no extended capability */ 610 next = 0; 611 goto out; 612 } 613 for (next = PCI_CONFIG_SPACE_SIZE; next; 614 prev = next, next = PCI_EXT_CAP_NEXT(header)) { 615 616 assert(next >= PCI_CONFIG_SPACE_SIZE); 617 assert(next <= PCIE_CONFIG_SPACE_SIZE - 8); 618 619 header = pci_get_long(dev->config + next); 620 if (PCI_EXT_CAP_ID(header) == cap_id) { 621 break; 622 } 623 } 624 625 out: 626 if (prev_p) { 627 *prev_p = prev; 628 } 629 return next; 630 } 631 632 uint16_t pcie_find_capability(PCIDevice *dev, uint16_t cap_id) 633 { 634 return pcie_find_capability_list(dev, cap_id, NULL); 635 } 636 637 static void pcie_ext_cap_set_next(PCIDevice *dev, uint16_t pos, uint16_t next) 638 { 639 uint32_t header = pci_get_long(dev->config + pos); 640 assert(!(next & (PCI_EXT_CAP_ALIGN - 1))); 641 header = (header & ~PCI_EXT_CAP_NEXT_MASK) | 642 ((next << PCI_EXT_CAP_NEXT_SHIFT) & PCI_EXT_CAP_NEXT_MASK); 643 pci_set_long(dev->config + pos, header); 644 } 645 646 /* 647 * caller must supply valid (offset, size) * such that the range shouldn't 648 * overlap with other capability or other registers. 649 * This function doesn't check it. 650 */ 651 void pcie_add_capability(PCIDevice *dev, 652 uint16_t cap_id, uint8_t cap_ver, 653 uint16_t offset, uint16_t size) 654 { 655 uint32_t header; 656 uint16_t next; 657 658 assert(offset >= PCI_CONFIG_SPACE_SIZE); 659 assert(offset < offset + size); 660 assert(offset + size <= PCIE_CONFIG_SPACE_SIZE); 661 assert(size >= 8); 662 assert(pci_is_express(dev)); 663 664 if (offset == PCI_CONFIG_SPACE_SIZE) { 665 header = pci_get_long(dev->config + offset); 666 next = PCI_EXT_CAP_NEXT(header); 667 } else { 668 uint16_t prev; 669 670 /* 0 is reserved cap id. use internally to find the last capability 671 in the linked list */ 672 next = pcie_find_capability_list(dev, 0, &prev); 673 674 assert(prev >= PCI_CONFIG_SPACE_SIZE); 675 assert(next == 0); 676 pcie_ext_cap_set_next(dev, prev, offset); 677 } 678 pci_set_long(dev->config + offset, PCI_EXT_CAP(cap_id, cap_ver, next)); 679 680 /* Make capability read-only by default */ 681 memset(dev->wmask + offset, 0, size); 682 memset(dev->w1cmask + offset, 0, size); 683 /* Check capability by default */ 684 memset(dev->cmask + offset, 0xFF, size); 685 } 686 687 /************************************************************************** 688 * pci express extended capability helper functions 689 */ 690 691 /* ARI */ 692 void pcie_ari_init(PCIDevice *dev, uint16_t offset, uint16_t nextfn) 693 { 694 pcie_add_capability(dev, PCI_EXT_CAP_ID_ARI, PCI_ARI_VER, 695 offset, PCI_ARI_SIZEOF); 696 pci_set_long(dev->config + offset + PCI_ARI_CAP, (nextfn & 0xff) << 8); 697 } 698 699 void pcie_dev_ser_num_init(PCIDevice *dev, uint16_t offset, uint64_t ser_num) 700 { 701 static const int pci_dsn_ver = 1; 702 static const int pci_dsn_cap = 4; 703 704 pcie_add_capability(dev, PCI_EXT_CAP_ID_DSN, pci_dsn_ver, offset, 705 PCI_EXT_CAP_DSN_SIZEOF); 706 pci_set_quad(dev->config + offset + pci_dsn_cap, ser_num); 707 } 708