1 /* 2 * pcie.c 3 * 4 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp> 5 * VA Linux Systems Japan K.K. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu-common.h" 22 #include "hw/pci/pci_bridge.h" 23 #include "hw/pci/pcie.h" 24 #include "hw/pci/msix.h" 25 #include "hw/pci/msi.h" 26 #include "hw/pci/pci_bus.h" 27 #include "hw/pci/pcie_regs.h" 28 #include "qemu/range.h" 29 #include "qapi/qmp/qerror.h" 30 31 //#define DEBUG_PCIE 32 #ifdef DEBUG_PCIE 33 # define PCIE_DPRINTF(fmt, ...) \ 34 fprintf(stderr, "%s:%d " fmt, __func__, __LINE__, ## __VA_ARGS__) 35 #else 36 # define PCIE_DPRINTF(fmt, ...) do {} while (0) 37 #endif 38 #define PCIE_DEV_PRINTF(dev, fmt, ...) \ 39 PCIE_DPRINTF("%s:%x "fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__) 40 41 42 /*************************************************************************** 43 * pci express capability helper functions 44 */ 45 int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, uint8_t port) 46 { 47 int pos; 48 uint8_t *exp_cap; 49 50 assert(pci_is_express(dev)); 51 52 pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset, 53 PCI_EXP_VER2_SIZEOF); 54 if (pos < 0) { 55 return pos; 56 } 57 dev->exp.exp_cap = pos; 58 exp_cap = dev->config + pos; 59 60 /* capability register 61 interrupt message number defaults to 0 */ 62 pci_set_word(exp_cap + PCI_EXP_FLAGS, 63 ((type << PCI_EXP_FLAGS_TYPE_SHIFT) & PCI_EXP_FLAGS_TYPE) | 64 PCI_EXP_FLAGS_VER2); 65 66 /* device capability register 67 * table 7-12: 68 * roll based error reporting bit must be set by all 69 * Functions conforming to the ECN, PCI Express Base 70 * Specification, Revision 1.1., or subsequent PCI Express Base 71 * Specification revisions. 72 */ 73 pci_set_long(exp_cap + PCI_EXP_DEVCAP, PCI_EXP_DEVCAP_RBER); 74 75 pci_set_long(exp_cap + PCI_EXP_LNKCAP, 76 (port << PCI_EXP_LNKCAP_PN_SHIFT) | 77 PCI_EXP_LNKCAP_ASPMS_0S | 78 PCI_EXP_LNK_MLW_1 | 79 PCI_EXP_LNK_LS_25); 80 81 pci_set_word(exp_cap + PCI_EXP_LNKSTA, 82 PCI_EXP_LNK_MLW_1 | PCI_EXP_LNK_LS_25); 83 84 pci_set_long(exp_cap + PCI_EXP_DEVCAP2, 85 PCI_EXP_DEVCAP2_EFF | PCI_EXP_DEVCAP2_EETLPP); 86 87 pci_set_word(dev->wmask + pos, PCI_EXP_DEVCTL2_EETLPPB); 88 return pos; 89 } 90 91 int pcie_endpoint_cap_init(PCIDevice *dev, uint8_t offset) 92 { 93 uint8_t type = PCI_EXP_TYPE_ENDPOINT; 94 95 /* 96 * Windows guests will report Code 10, device cannot start, if 97 * a regular Endpoint type is exposed on a root complex. These 98 * should instead be Root Complex Integrated Endpoints. 99 */ 100 if (pci_bus_is_express(dev->bus) && pci_bus_is_root(dev->bus)) { 101 type = PCI_EXP_TYPE_RC_END; 102 } 103 104 return pcie_cap_init(dev, offset, type, 0); 105 } 106 107 void pcie_cap_exit(PCIDevice *dev) 108 { 109 pci_del_capability(dev, PCI_CAP_ID_EXP, PCI_EXP_VER2_SIZEOF); 110 } 111 112 uint8_t pcie_cap_get_type(const PCIDevice *dev) 113 { 114 uint32_t pos = dev->exp.exp_cap; 115 assert(pos > 0); 116 return (pci_get_word(dev->config + pos + PCI_EXP_FLAGS) & 117 PCI_EXP_FLAGS_TYPE) >> PCI_EXP_FLAGS_TYPE_SHIFT; 118 } 119 120 /* MSI/MSI-X */ 121 /* pci express interrupt message number */ 122 /* 7.8.2 PCI Express Capabilities Register: Interrupt Message Number */ 123 void pcie_cap_flags_set_vector(PCIDevice *dev, uint8_t vector) 124 { 125 uint8_t *exp_cap = dev->config + dev->exp.exp_cap; 126 assert(vector < 32); 127 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_FLAGS, PCI_EXP_FLAGS_IRQ); 128 pci_word_test_and_set_mask(exp_cap + PCI_EXP_FLAGS, 129 vector << PCI_EXP_FLAGS_IRQ_SHIFT); 130 } 131 132 uint8_t pcie_cap_flags_get_vector(PCIDevice *dev) 133 { 134 return (pci_get_word(dev->config + dev->exp.exp_cap + PCI_EXP_FLAGS) & 135 PCI_EXP_FLAGS_IRQ) >> PCI_EXP_FLAGS_IRQ_SHIFT; 136 } 137 138 void pcie_cap_deverr_init(PCIDevice *dev) 139 { 140 uint32_t pos = dev->exp.exp_cap; 141 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP, 142 PCI_EXP_DEVCAP_RBER); 143 pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL, 144 PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | 145 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE); 146 pci_long_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_DEVSTA, 147 PCI_EXP_DEVSTA_CED | PCI_EXP_DEVSTA_NFED | 148 PCI_EXP_DEVSTA_URD | PCI_EXP_DEVSTA_URD); 149 } 150 151 void pcie_cap_deverr_reset(PCIDevice *dev) 152 { 153 uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL; 154 pci_long_test_and_clear_mask(devctl, 155 PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | 156 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE); 157 } 158 159 static void hotplug_event_update_event_status(PCIDevice *dev) 160 { 161 uint32_t pos = dev->exp.exp_cap; 162 uint8_t *exp_cap = dev->config + pos; 163 uint16_t sltctl = pci_get_word(exp_cap + PCI_EXP_SLTCTL); 164 uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA); 165 166 dev->exp.hpev_notified = (sltctl & PCI_EXP_SLTCTL_HPIE) && 167 (sltsta & sltctl & PCI_EXP_HP_EV_SUPPORTED); 168 } 169 170 static void hotplug_event_notify(PCIDevice *dev) 171 { 172 bool prev = dev->exp.hpev_notified; 173 174 hotplug_event_update_event_status(dev); 175 176 if (prev == dev->exp.hpev_notified) { 177 return; 178 } 179 180 /* Note: the logic above does not take into account whether interrupts 181 * are masked. The result is that interrupt will be sent when it is 182 * subsequently unmasked. This appears to be legal: Section 6.7.3.4: 183 * The Port may optionally send an MSI when there are hot-plug events that 184 * occur while interrupt generation is disabled, and interrupt generation is 185 * subsequently enabled. */ 186 if (msix_enabled(dev)) { 187 msix_notify(dev, pcie_cap_flags_get_vector(dev)); 188 } else if (msi_enabled(dev)) { 189 msi_notify(dev, pcie_cap_flags_get_vector(dev)); 190 } else { 191 pci_set_irq(dev, dev->exp.hpev_notified); 192 } 193 } 194 195 static void hotplug_event_clear(PCIDevice *dev) 196 { 197 hotplug_event_update_event_status(dev); 198 if (!msix_enabled(dev) && !msi_enabled(dev) && !dev->exp.hpev_notified) { 199 pci_irq_deassert(dev); 200 } 201 } 202 203 /* 204 * A PCI Express Hot-Plug Event has occurred, so update slot status register 205 * and notify OS of the event if necessary. 206 * 207 * 6.7.3 PCI Express Hot-Plug Events 208 * 6.7.3.4 Software Notification of Hot-Plug Events 209 */ 210 static void pcie_cap_slot_event(PCIDevice *dev, PCIExpressHotPlugEvent event) 211 { 212 /* Minor optimization: if nothing changed - no event is needed. */ 213 if (pci_word_test_and_set_mask(dev->config + dev->exp.exp_cap + 214 PCI_EXP_SLTSTA, event)) { 215 return; 216 } 217 hotplug_event_notify(dev); 218 } 219 220 static void pcie_cap_slot_hotplug_common(PCIDevice *hotplug_dev, 221 DeviceState *dev, 222 uint8_t **exp_cap, Error **errp) 223 { 224 *exp_cap = hotplug_dev->config + hotplug_dev->exp.exp_cap; 225 uint16_t sltsta = pci_get_word(*exp_cap + PCI_EXP_SLTSTA); 226 227 PCIE_DEV_PRINTF(PCI_DEVICE(dev), "hotplug state: 0x%x\n", sltsta); 228 if (sltsta & PCI_EXP_SLTSTA_EIS) { 229 /* the slot is electromechanically locked. 230 * This error is propagated up to qdev and then to HMP/QMP. 231 */ 232 error_setg_errno(errp, -EBUSY, "slot is electromechanically locked"); 233 } 234 } 235 236 void pcie_cap_slot_hotplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, 237 Error **errp) 238 { 239 uint8_t *exp_cap; 240 PCIDevice *pci_dev = PCI_DEVICE(dev); 241 242 pcie_cap_slot_hotplug_common(PCI_DEVICE(hotplug_dev), dev, &exp_cap, errp); 243 244 /* Don't send event when device is enabled during qemu machine creation: 245 * it is present on boot, no hotplug event is necessary. We do send an 246 * event when the device is disabled later. */ 247 if (!dev->hotplugged) { 248 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA, 249 PCI_EXP_SLTSTA_PDS); 250 return; 251 } 252 253 /* TODO: multifunction hot-plug. 254 * Right now, only a device of function = 0 is allowed to be 255 * hot plugged/unplugged. 256 */ 257 assert(PCI_FUNC(pci_dev->devfn) == 0); 258 259 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA, 260 PCI_EXP_SLTSTA_PDS); 261 pcie_cap_slot_event(PCI_DEVICE(hotplug_dev), 262 PCI_EXP_HP_EV_PDC | PCI_EXP_HP_EV_ABP); 263 } 264 265 void pcie_cap_slot_hot_unplug_request_cb(HotplugHandler *hotplug_dev, 266 DeviceState *dev, Error **errp) 267 { 268 uint8_t *exp_cap; 269 270 pcie_cap_slot_hotplug_common(PCI_DEVICE(hotplug_dev), dev, &exp_cap, errp); 271 272 pcie_cap_slot_push_attention_button(PCI_DEVICE(hotplug_dev)); 273 } 274 275 /* pci express slot for pci express root/downstream port 276 PCI express capability slot registers */ 277 void pcie_cap_slot_init(PCIDevice *dev, uint16_t slot) 278 { 279 uint32_t pos = dev->exp.exp_cap; 280 281 pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_FLAGS, 282 PCI_EXP_FLAGS_SLOT); 283 284 pci_long_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCAP, 285 ~PCI_EXP_SLTCAP_PSN); 286 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP, 287 (slot << PCI_EXP_SLTCAP_PSN_SHIFT) | 288 PCI_EXP_SLTCAP_EIP | 289 PCI_EXP_SLTCAP_HPS | 290 PCI_EXP_SLTCAP_HPC | 291 PCI_EXP_SLTCAP_PIP | 292 PCI_EXP_SLTCAP_AIP | 293 PCI_EXP_SLTCAP_ABP); 294 295 if (dev->cap_present & QEMU_PCIE_SLTCAP_PCP) { 296 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP, 297 PCI_EXP_SLTCAP_PCP); 298 pci_word_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCTL, 299 PCI_EXP_SLTCTL_PCC); 300 pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL, 301 PCI_EXP_SLTCTL_PCC); 302 } 303 304 pci_word_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCTL, 305 PCI_EXP_SLTCTL_PIC | 306 PCI_EXP_SLTCTL_AIC); 307 pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCTL, 308 PCI_EXP_SLTCTL_PIC_OFF | 309 PCI_EXP_SLTCTL_AIC_OFF); 310 pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL, 311 PCI_EXP_SLTCTL_PIC | 312 PCI_EXP_SLTCTL_AIC | 313 PCI_EXP_SLTCTL_HPIE | 314 PCI_EXP_SLTCTL_CCIE | 315 PCI_EXP_SLTCTL_PDCE | 316 PCI_EXP_SLTCTL_ABPE); 317 /* Although reading PCI_EXP_SLTCTL_EIC returns always 0, 318 * make the bit writable here in order to detect 1b is written. 319 * pcie_cap_slot_write_config() test-and-clear the bit, so 320 * this bit always returns 0 to the guest. 321 */ 322 pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL, 323 PCI_EXP_SLTCTL_EIC); 324 325 pci_word_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_SLTSTA, 326 PCI_EXP_HP_EV_SUPPORTED); 327 328 dev->exp.hpev_notified = false; 329 330 qbus_set_hotplug_handler(BUS(pci_bridge_get_sec_bus(PCI_BRIDGE(dev))), 331 DEVICE(dev), NULL); 332 } 333 334 void pcie_cap_slot_reset(PCIDevice *dev) 335 { 336 uint8_t *exp_cap = dev->config + dev->exp.exp_cap; 337 uint8_t port_type = pcie_cap_get_type(dev); 338 339 assert(port_type == PCI_EXP_TYPE_DOWNSTREAM || 340 port_type == PCI_EXP_TYPE_ROOT_PORT); 341 342 PCIE_DEV_PRINTF(dev, "reset\n"); 343 344 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL, 345 PCI_EXP_SLTCTL_EIC | 346 PCI_EXP_SLTCTL_PIC | 347 PCI_EXP_SLTCTL_AIC | 348 PCI_EXP_SLTCTL_HPIE | 349 PCI_EXP_SLTCTL_CCIE | 350 PCI_EXP_SLTCTL_PDCE | 351 PCI_EXP_SLTCTL_ABPE); 352 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL, 353 PCI_EXP_SLTCTL_AIC_OFF); 354 355 if (dev->cap_present & QEMU_PCIE_SLTCAP_PCP) { 356 /* Downstream ports enforce device number 0. */ 357 bool populated = pci_bridge_get_sec_bus(PCI_BRIDGE(dev))->devices[0]; 358 uint16_t pic; 359 360 if (populated) { 361 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL, 362 PCI_EXP_SLTCTL_PCC); 363 } else { 364 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL, 365 PCI_EXP_SLTCTL_PCC); 366 } 367 368 pic = populated ? PCI_EXP_SLTCTL_PIC_ON : PCI_EXP_SLTCTL_PIC_OFF; 369 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL, pic); 370 } 371 372 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA, 373 PCI_EXP_SLTSTA_EIS |/* on reset, 374 the lock is released */ 375 PCI_EXP_SLTSTA_CC | 376 PCI_EXP_SLTSTA_PDC | 377 PCI_EXP_SLTSTA_ABP); 378 379 hotplug_event_update_event_status(dev); 380 } 381 382 static void pcie_unplug_device(PCIBus *bus, PCIDevice *dev, void *opaque) 383 { 384 object_unparent(OBJECT(dev)); 385 } 386 387 void pcie_cap_slot_write_config(PCIDevice *dev, 388 uint32_t addr, uint32_t val, int len) 389 { 390 uint32_t pos = dev->exp.exp_cap; 391 uint8_t *exp_cap = dev->config + pos; 392 uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA); 393 394 if (ranges_overlap(addr, len, pos + PCI_EXP_SLTSTA, 2)) { 395 hotplug_event_clear(dev); 396 } 397 398 if (!ranges_overlap(addr, len, pos + PCI_EXP_SLTCTL, 2)) { 399 return; 400 } 401 402 if (pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL, 403 PCI_EXP_SLTCTL_EIC)) { 404 sltsta ^= PCI_EXP_SLTSTA_EIS; /* toggle PCI_EXP_SLTSTA_EIS bit */ 405 pci_set_word(exp_cap + PCI_EXP_SLTSTA, sltsta); 406 PCIE_DEV_PRINTF(dev, "PCI_EXP_SLTCTL_EIC: " 407 "sltsta -> 0x%02"PRIx16"\n", 408 sltsta); 409 } 410 411 /* 412 * If the slot is polulated, power indicator is off and power 413 * controller is off, it is safe to detach the devices. 414 */ 415 if ((sltsta & PCI_EXP_SLTSTA_PDS) && (val & PCI_EXP_SLTCTL_PCC) && 416 ((val & PCI_EXP_SLTCTL_PIC_OFF) == PCI_EXP_SLTCTL_PIC_OFF)) { 417 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev)); 418 pci_for_each_device(sec_bus, pci_bus_num(sec_bus), 419 pcie_unplug_device, NULL); 420 421 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA, 422 PCI_EXP_SLTSTA_PDS); 423 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA, 424 PCI_EXP_SLTSTA_PDC); 425 } 426 427 hotplug_event_notify(dev); 428 429 /* 430 * 6.7.3.2 Command Completed Events 431 * 432 * Software issues a command to a hot-plug capable Downstream Port by 433 * issuing a write transaction that targets any portion of the Port’s Slot 434 * Control register. A single write to the Slot Control register is 435 * considered to be a single command, even if the write affects more than 436 * one field in the Slot Control register. In response to this transaction, 437 * the Port must carry out the requested actions and then set the 438 * associated status field for the command completed event. */ 439 440 /* Real hardware might take a while to complete requested command because 441 * physical movement would be involved like locking the electromechanical 442 * lock. However in our case, command is completed instantaneously above, 443 * so send a command completion event right now. 444 */ 445 pcie_cap_slot_event(dev, PCI_EXP_HP_EV_CCI); 446 } 447 448 int pcie_cap_slot_post_load(void *opaque, int version_id) 449 { 450 PCIDevice *dev = opaque; 451 hotplug_event_update_event_status(dev); 452 return 0; 453 } 454 455 void pcie_cap_slot_push_attention_button(PCIDevice *dev) 456 { 457 pcie_cap_slot_event(dev, PCI_EXP_HP_EV_ABP); 458 } 459 460 /* root control/capabilities/status. PME isn't emulated for now */ 461 void pcie_cap_root_init(PCIDevice *dev) 462 { 463 pci_set_word(dev->wmask + dev->exp.exp_cap + PCI_EXP_RTCTL, 464 PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE | 465 PCI_EXP_RTCTL_SEFEE); 466 } 467 468 void pcie_cap_root_reset(PCIDevice *dev) 469 { 470 pci_set_word(dev->config + dev->exp.exp_cap + PCI_EXP_RTCTL, 0); 471 } 472 473 /* function level reset(FLR) */ 474 void pcie_cap_flr_init(PCIDevice *dev) 475 { 476 pci_long_test_and_set_mask(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCAP, 477 PCI_EXP_DEVCAP_FLR); 478 479 /* Although reading BCR_FLR returns always 0, 480 * the bit is made writable here in order to detect the 1b is written 481 * pcie_cap_flr_write_config() test-and-clear the bit, so 482 * this bit always returns 0 to the guest. 483 */ 484 pci_word_test_and_set_mask(dev->wmask + dev->exp.exp_cap + PCI_EXP_DEVCTL, 485 PCI_EXP_DEVCTL_BCR_FLR); 486 } 487 488 void pcie_cap_flr_write_config(PCIDevice *dev, 489 uint32_t addr, uint32_t val, int len) 490 { 491 uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL; 492 if (pci_get_word(devctl) & PCI_EXP_DEVCTL_BCR_FLR) { 493 /* Clear PCI_EXP_DEVCTL_BCR_FLR after invoking the reset handler 494 so the handler can detect FLR by looking at this bit. */ 495 pci_device_reset(dev); 496 pci_word_test_and_clear_mask(devctl, PCI_EXP_DEVCTL_BCR_FLR); 497 } 498 } 499 500 /* Alternative Routing-ID Interpretation (ARI) 501 * forwarding support for root and downstream ports 502 */ 503 void pcie_cap_arifwd_init(PCIDevice *dev) 504 { 505 uint32_t pos = dev->exp.exp_cap; 506 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP2, 507 PCI_EXP_DEVCAP2_ARI); 508 pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL2, 509 PCI_EXP_DEVCTL2_ARI); 510 } 511 512 void pcie_cap_arifwd_reset(PCIDevice *dev) 513 { 514 uint8_t *devctl2 = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2; 515 pci_long_test_and_clear_mask(devctl2, PCI_EXP_DEVCTL2_ARI); 516 } 517 518 bool pcie_cap_is_arifwd_enabled(const PCIDevice *dev) 519 { 520 if (!pci_is_express(dev)) { 521 return false; 522 } 523 if (!dev->exp.exp_cap) { 524 return false; 525 } 526 527 return pci_get_long(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2) & 528 PCI_EXP_DEVCTL2_ARI; 529 } 530 531 /************************************************************************** 532 * pci express extended capability list management functions 533 * uint16_t ext_cap_id (16 bit) 534 * uint8_t cap_ver (4 bit) 535 * uint16_t cap_offset (12 bit) 536 * uint16_t ext_cap_size 537 */ 538 539 static uint16_t pcie_find_capability_list(PCIDevice *dev, uint16_t cap_id, 540 uint16_t *prev_p) 541 { 542 uint16_t prev = 0; 543 uint16_t next; 544 uint32_t header = pci_get_long(dev->config + PCI_CONFIG_SPACE_SIZE); 545 546 if (!header) { 547 /* no extended capability */ 548 next = 0; 549 goto out; 550 } 551 for (next = PCI_CONFIG_SPACE_SIZE; next; 552 prev = next, next = PCI_EXT_CAP_NEXT(header)) { 553 554 assert(next >= PCI_CONFIG_SPACE_SIZE); 555 assert(next <= PCIE_CONFIG_SPACE_SIZE - 8); 556 557 header = pci_get_long(dev->config + next); 558 if (PCI_EXT_CAP_ID(header) == cap_id) { 559 break; 560 } 561 } 562 563 out: 564 if (prev_p) { 565 *prev_p = prev; 566 } 567 return next; 568 } 569 570 uint16_t pcie_find_capability(PCIDevice *dev, uint16_t cap_id) 571 { 572 return pcie_find_capability_list(dev, cap_id, NULL); 573 } 574 575 static void pcie_ext_cap_set_next(PCIDevice *dev, uint16_t pos, uint16_t next) 576 { 577 uint32_t header = pci_get_long(dev->config + pos); 578 assert(!(next & (PCI_EXT_CAP_ALIGN - 1))); 579 header = (header & ~PCI_EXT_CAP_NEXT_MASK) | 580 ((next << PCI_EXT_CAP_NEXT_SHIFT) & PCI_EXT_CAP_NEXT_MASK); 581 pci_set_long(dev->config + pos, header); 582 } 583 584 /* 585 * caller must supply valid (offset, size) * such that the range shouldn't 586 * overlap with other capability or other registers. 587 * This function doesn't check it. 588 */ 589 void pcie_add_capability(PCIDevice *dev, 590 uint16_t cap_id, uint8_t cap_ver, 591 uint16_t offset, uint16_t size) 592 { 593 uint32_t header; 594 uint16_t next; 595 596 assert(offset >= PCI_CONFIG_SPACE_SIZE); 597 assert(offset < offset + size); 598 assert(offset + size < PCIE_CONFIG_SPACE_SIZE); 599 assert(size >= 8); 600 assert(pci_is_express(dev)); 601 602 if (offset == PCI_CONFIG_SPACE_SIZE) { 603 header = pci_get_long(dev->config + offset); 604 next = PCI_EXT_CAP_NEXT(header); 605 } else { 606 uint16_t prev; 607 608 /* 0 is reserved cap id. use internally to find the last capability 609 in the linked list */ 610 next = pcie_find_capability_list(dev, 0, &prev); 611 612 assert(prev >= PCI_CONFIG_SPACE_SIZE); 613 assert(next == 0); 614 pcie_ext_cap_set_next(dev, prev, offset); 615 } 616 pci_set_long(dev->config + offset, PCI_EXT_CAP(cap_id, cap_ver, next)); 617 618 /* Make capability read-only by default */ 619 memset(dev->wmask + offset, 0, size); 620 memset(dev->w1cmask + offset, 0, size); 621 /* Check capability by default */ 622 memset(dev->cmask + offset, 0xFF, size); 623 } 624 625 /************************************************************************** 626 * pci express extended capability helper functions 627 */ 628 629 /* ARI */ 630 void pcie_ari_init(PCIDevice *dev, uint16_t offset, uint16_t nextfn) 631 { 632 pcie_add_capability(dev, PCI_EXT_CAP_ID_ARI, PCI_ARI_VER, 633 offset, PCI_ARI_SIZEOF); 634 pci_set_long(dev->config + offset + PCI_ARI_CAP, (nextfn & 0xff) << 8); 635 } 636