1 /* 2 * pcie.c 3 * 4 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp> 5 * VA Linux Systems Japan K.K. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "hw/pci/pci_bridge.h" 24 #include "hw/pci/pcie.h" 25 #include "hw/pci/msix.h" 26 #include "hw/pci/msi.h" 27 #include "hw/pci/pci_bus.h" 28 #include "hw/pci/pcie_regs.h" 29 #include "hw/pci/pcie_port.h" 30 #include "qemu/range.h" 31 32 //#define DEBUG_PCIE 33 #ifdef DEBUG_PCIE 34 # define PCIE_DPRINTF(fmt, ...) \ 35 fprintf(stderr, "%s:%d " fmt, __func__, __LINE__, ## __VA_ARGS__) 36 #else 37 # define PCIE_DPRINTF(fmt, ...) do {} while (0) 38 #endif 39 #define PCIE_DEV_PRINTF(dev, fmt, ...) \ 40 PCIE_DPRINTF("%s:%x "fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__) 41 42 43 /*************************************************************************** 44 * pci express capability helper functions 45 */ 46 47 static void 48 pcie_cap_v1_fill(PCIDevice *dev, uint8_t port, uint8_t type, uint8_t version) 49 { 50 uint8_t *exp_cap = dev->config + dev->exp.exp_cap; 51 uint8_t *cmask = dev->cmask + dev->exp.exp_cap; 52 53 /* capability register 54 interrupt message number defaults to 0 */ 55 pci_set_word(exp_cap + PCI_EXP_FLAGS, 56 ((type << PCI_EXP_FLAGS_TYPE_SHIFT) & PCI_EXP_FLAGS_TYPE) | 57 version); 58 59 /* device capability register 60 * table 7-12: 61 * roll based error reporting bit must be set by all 62 * Functions conforming to the ECN, PCI Express Base 63 * Specification, Revision 1.1., or subsequent PCI Express Base 64 * Specification revisions. 65 */ 66 pci_set_long(exp_cap + PCI_EXP_DEVCAP, PCI_EXP_DEVCAP_RBER); 67 68 pci_set_long(exp_cap + PCI_EXP_LNKCAP, 69 (port << PCI_EXP_LNKCAP_PN_SHIFT) | 70 PCI_EXP_LNKCAP_ASPMS_0S | 71 QEMU_PCI_EXP_LNKCAP_MLW(QEMU_PCI_EXP_LNK_X1) | 72 QEMU_PCI_EXP_LNKCAP_MLS(QEMU_PCI_EXP_LNK_2_5GT)); 73 74 pci_set_word(exp_cap + PCI_EXP_LNKSTA, 75 QEMU_PCI_EXP_LNKSTA_NLW(QEMU_PCI_EXP_LNK_X1) | 76 QEMU_PCI_EXP_LNKSTA_CLS(QEMU_PCI_EXP_LNK_2_5GT)); 77 78 if (dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA) { 79 pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA, 80 PCI_EXP_LNKSTA_DLLLA); 81 } 82 83 /* We changed link status bits over time, and changing them across 84 * migrations is generally fine as hardware changes them too. 85 * Let's not bother checking. 86 */ 87 pci_set_word(cmask + PCI_EXP_LNKSTA, 0); 88 } 89 90 static void pcie_cap_fill_slot_lnk(PCIDevice *dev) 91 { 92 PCIESlot *s = (PCIESlot *)object_dynamic_cast(OBJECT(dev), TYPE_PCIE_SLOT); 93 uint8_t *exp_cap = dev->config + dev->exp.exp_cap; 94 95 /* Skip anything that isn't a PCIESlot */ 96 if (!s) { 97 return; 98 } 99 100 /* Clear and fill LNKCAP from what was configured above */ 101 pci_long_test_and_clear_mask(exp_cap + PCI_EXP_LNKCAP, 102 PCI_EXP_LNKCAP_MLW | PCI_EXP_LNKCAP_SLS); 103 pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP, 104 QEMU_PCI_EXP_LNKCAP_MLW(s->width) | 105 QEMU_PCI_EXP_LNKCAP_MLS(s->speed)); 106 107 /* 108 * Link bandwidth notification is required for all root ports and 109 * downstream ports supporting links wider than x1 or multiple link 110 * speeds. 111 */ 112 if (s->width > QEMU_PCI_EXP_LNK_X1 || 113 s->speed > QEMU_PCI_EXP_LNK_2_5GT) { 114 pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP, 115 PCI_EXP_LNKCAP_LBNC); 116 } 117 118 if (s->speed > QEMU_PCI_EXP_LNK_2_5GT) { 119 /* 120 * Hot-plug capable downstream ports and downstream ports supporting 121 * link speeds greater than 5GT/s must hardwire PCI_EXP_LNKCAP_DLLLARC 122 * to 1b. PCI_EXP_LNKCAP_DLLLARC implies PCI_EXP_LNKSTA_DLLLA, which 123 * we also hardwire to 1b here. 2.5GT/s hot-plug slots should also 124 * technically implement this, but it's not done here for compatibility. 125 */ 126 pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP, 127 PCI_EXP_LNKCAP_DLLLARC); 128 pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA, 129 PCI_EXP_LNKSTA_DLLLA); 130 131 /* 132 * Target Link Speed defaults to the highest link speed supported by 133 * the component. 2.5GT/s devices are permitted to hardwire to zero. 134 */ 135 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_LNKCTL2, 136 PCI_EXP_LNKCTL2_TLS); 137 pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKCTL2, 138 QEMU_PCI_EXP_LNKCAP_MLS(s->speed) & 139 PCI_EXP_LNKCTL2_TLS); 140 } 141 142 /* 143 * 2.5 & 5.0GT/s can be fully described by LNKCAP, but 8.0GT/s is 144 * actually a reference to the highest bit supported in this register. 145 * We assume the device supports all link speeds. 146 */ 147 if (s->speed > QEMU_PCI_EXP_LNK_5GT) { 148 pci_long_test_and_clear_mask(exp_cap + PCI_EXP_LNKCAP2, ~0U); 149 pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP2, 150 PCI_EXP_LNKCAP2_SLS_2_5GB | 151 PCI_EXP_LNKCAP2_SLS_5_0GB | 152 PCI_EXP_LNKCAP2_SLS_8_0GB); 153 if (s->speed > QEMU_PCI_EXP_LNK_8GT) { 154 pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP2, 155 PCI_EXP_LNKCAP2_SLS_16_0GB); 156 } 157 } 158 } 159 160 int pcie_cap_init(PCIDevice *dev, uint8_t offset, 161 uint8_t type, uint8_t port, 162 Error **errp) 163 { 164 /* PCIe cap v2 init */ 165 int pos; 166 uint8_t *exp_cap; 167 168 assert(pci_is_express(dev)); 169 170 pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset, 171 PCI_EXP_VER2_SIZEOF, errp); 172 if (pos < 0) { 173 return pos; 174 } 175 dev->exp.exp_cap = pos; 176 exp_cap = dev->config + pos; 177 178 /* Filling values common with v1 */ 179 pcie_cap_v1_fill(dev, port, type, PCI_EXP_FLAGS_VER2); 180 181 /* Fill link speed and width options */ 182 pcie_cap_fill_slot_lnk(dev); 183 184 /* Filling v2 specific values */ 185 pci_set_long(exp_cap + PCI_EXP_DEVCAP2, 186 PCI_EXP_DEVCAP2_EFF | PCI_EXP_DEVCAP2_EETLPP); 187 188 pci_set_word(dev->wmask + pos + PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_EETLPPB); 189 190 if (dev->cap_present & QEMU_PCIE_EXTCAP_INIT) { 191 /* read-only to behave like a 'NULL' Extended Capability Header */ 192 pci_set_long(dev->wmask + PCI_CONFIG_SPACE_SIZE, 0); 193 } 194 195 return pos; 196 } 197 198 int pcie_cap_v1_init(PCIDevice *dev, uint8_t offset, uint8_t type, 199 uint8_t port) 200 { 201 /* PCIe cap v1 init */ 202 int pos; 203 Error *local_err = NULL; 204 205 assert(pci_is_express(dev)); 206 207 pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset, 208 PCI_EXP_VER1_SIZEOF, &local_err); 209 if (pos < 0) { 210 error_report_err(local_err); 211 return pos; 212 } 213 dev->exp.exp_cap = pos; 214 215 pcie_cap_v1_fill(dev, port, type, PCI_EXP_FLAGS_VER1); 216 217 return pos; 218 } 219 220 static int 221 pcie_endpoint_cap_common_init(PCIDevice *dev, uint8_t offset, uint8_t cap_size) 222 { 223 uint8_t type = PCI_EXP_TYPE_ENDPOINT; 224 Error *local_err = NULL; 225 int ret; 226 227 /* 228 * Windows guests will report Code 10, device cannot start, if 229 * a regular Endpoint type is exposed on a root complex. These 230 * should instead be Root Complex Integrated Endpoints. 231 */ 232 if (pci_bus_is_express(pci_get_bus(dev)) 233 && pci_bus_is_root(pci_get_bus(dev))) { 234 type = PCI_EXP_TYPE_RC_END; 235 } 236 237 if (cap_size == PCI_EXP_VER1_SIZEOF) { 238 return pcie_cap_v1_init(dev, offset, type, 0); 239 } else { 240 ret = pcie_cap_init(dev, offset, type, 0, &local_err); 241 242 if (ret < 0) { 243 error_report_err(local_err); 244 } 245 246 return ret; 247 } 248 } 249 250 int pcie_endpoint_cap_init(PCIDevice *dev, uint8_t offset) 251 { 252 return pcie_endpoint_cap_common_init(dev, offset, PCI_EXP_VER2_SIZEOF); 253 } 254 255 int pcie_endpoint_cap_v1_init(PCIDevice *dev, uint8_t offset) 256 { 257 return pcie_endpoint_cap_common_init(dev, offset, PCI_EXP_VER1_SIZEOF); 258 } 259 260 void pcie_cap_exit(PCIDevice *dev) 261 { 262 pci_del_capability(dev, PCI_CAP_ID_EXP, PCI_EXP_VER2_SIZEOF); 263 } 264 265 void pcie_cap_v1_exit(PCIDevice *dev) 266 { 267 pci_del_capability(dev, PCI_CAP_ID_EXP, PCI_EXP_VER1_SIZEOF); 268 } 269 270 uint8_t pcie_cap_get_type(const PCIDevice *dev) 271 { 272 uint32_t pos = dev->exp.exp_cap; 273 assert(pos > 0); 274 return (pci_get_word(dev->config + pos + PCI_EXP_FLAGS) & 275 PCI_EXP_FLAGS_TYPE) >> PCI_EXP_FLAGS_TYPE_SHIFT; 276 } 277 278 /* MSI/MSI-X */ 279 /* pci express interrupt message number */ 280 /* 7.8.2 PCI Express Capabilities Register: Interrupt Message Number */ 281 void pcie_cap_flags_set_vector(PCIDevice *dev, uint8_t vector) 282 { 283 uint8_t *exp_cap = dev->config + dev->exp.exp_cap; 284 assert(vector < 32); 285 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_FLAGS, PCI_EXP_FLAGS_IRQ); 286 pci_word_test_and_set_mask(exp_cap + PCI_EXP_FLAGS, 287 vector << PCI_EXP_FLAGS_IRQ_SHIFT); 288 } 289 290 uint8_t pcie_cap_flags_get_vector(PCIDevice *dev) 291 { 292 return (pci_get_word(dev->config + dev->exp.exp_cap + PCI_EXP_FLAGS) & 293 PCI_EXP_FLAGS_IRQ) >> PCI_EXP_FLAGS_IRQ_SHIFT; 294 } 295 296 void pcie_cap_deverr_init(PCIDevice *dev) 297 { 298 uint32_t pos = dev->exp.exp_cap; 299 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP, 300 PCI_EXP_DEVCAP_RBER); 301 pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL, 302 PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | 303 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE); 304 pci_long_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_DEVSTA, 305 PCI_EXP_DEVSTA_CED | PCI_EXP_DEVSTA_NFED | 306 PCI_EXP_DEVSTA_FED | PCI_EXP_DEVSTA_URD); 307 } 308 309 void pcie_cap_deverr_reset(PCIDevice *dev) 310 { 311 uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL; 312 pci_long_test_and_clear_mask(devctl, 313 PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | 314 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE); 315 } 316 317 void pcie_cap_lnkctl_init(PCIDevice *dev) 318 { 319 uint32_t pos = dev->exp.exp_cap; 320 pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_LNKCTL, 321 PCI_EXP_LNKCTL_CCC | PCI_EXP_LNKCTL_ES); 322 } 323 324 void pcie_cap_lnkctl_reset(PCIDevice *dev) 325 { 326 uint8_t *lnkctl = dev->config + dev->exp.exp_cap + PCI_EXP_LNKCTL; 327 pci_long_test_and_clear_mask(lnkctl, 328 PCI_EXP_LNKCTL_CCC | PCI_EXP_LNKCTL_ES); 329 } 330 331 static void hotplug_event_update_event_status(PCIDevice *dev) 332 { 333 uint32_t pos = dev->exp.exp_cap; 334 uint8_t *exp_cap = dev->config + pos; 335 uint16_t sltctl = pci_get_word(exp_cap + PCI_EXP_SLTCTL); 336 uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA); 337 338 dev->exp.hpev_notified = (sltctl & PCI_EXP_SLTCTL_HPIE) && 339 (sltsta & sltctl & PCI_EXP_HP_EV_SUPPORTED); 340 } 341 342 static void hotplug_event_notify(PCIDevice *dev) 343 { 344 bool prev = dev->exp.hpev_notified; 345 346 hotplug_event_update_event_status(dev); 347 348 if (prev == dev->exp.hpev_notified) { 349 return; 350 } 351 352 /* Note: the logic above does not take into account whether interrupts 353 * are masked. The result is that interrupt will be sent when it is 354 * subsequently unmasked. This appears to be legal: Section 6.7.3.4: 355 * The Port may optionally send an MSI when there are hot-plug events that 356 * occur while interrupt generation is disabled, and interrupt generation is 357 * subsequently enabled. */ 358 if (msix_enabled(dev)) { 359 msix_notify(dev, pcie_cap_flags_get_vector(dev)); 360 } else if (msi_enabled(dev)) { 361 msi_notify(dev, pcie_cap_flags_get_vector(dev)); 362 } else { 363 pci_set_irq(dev, dev->exp.hpev_notified); 364 } 365 } 366 367 static void hotplug_event_clear(PCIDevice *dev) 368 { 369 hotplug_event_update_event_status(dev); 370 if (!msix_enabled(dev) && !msi_enabled(dev) && !dev->exp.hpev_notified) { 371 pci_irq_deassert(dev); 372 } 373 } 374 375 /* 376 * A PCI Express Hot-Plug Event has occurred, so update slot status register 377 * and notify OS of the event if necessary. 378 * 379 * 6.7.3 PCI Express Hot-Plug Events 380 * 6.7.3.4 Software Notification of Hot-Plug Events 381 */ 382 static void pcie_cap_slot_event(PCIDevice *dev, PCIExpressHotPlugEvent event) 383 { 384 /* Minor optimization: if nothing changed - no event is needed. */ 385 if (pci_word_test_and_set_mask(dev->config + dev->exp.exp_cap + 386 PCI_EXP_SLTSTA, event) == event) { 387 return; 388 } 389 hotplug_event_notify(dev); 390 } 391 392 static void pcie_cap_slot_plug_common(PCIDevice *hotplug_dev, DeviceState *dev, 393 Error **errp) 394 { 395 uint8_t *exp_cap = hotplug_dev->config + hotplug_dev->exp.exp_cap; 396 uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA); 397 398 PCIE_DEV_PRINTF(PCI_DEVICE(dev), "hotplug state: 0x%x\n", sltsta); 399 if (sltsta & PCI_EXP_SLTSTA_EIS) { 400 /* the slot is electromechanically locked. 401 * This error is propagated up to qdev and then to HMP/QMP. 402 */ 403 error_setg_errno(errp, EBUSY, "slot is electromechanically locked"); 404 } 405 } 406 407 void pcie_cap_slot_pre_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, 408 Error **errp) 409 { 410 PCIDevice *hotplug_pdev = PCI_DEVICE(hotplug_dev); 411 uint8_t *exp_cap = hotplug_pdev->config + hotplug_pdev->exp.exp_cap; 412 uint32_t sltcap = pci_get_word(exp_cap + PCI_EXP_SLTCAP); 413 414 /* Check if hot-plug is disabled on the slot */ 415 if (dev->hotplugged && (sltcap & PCI_EXP_SLTCAP_HPC) == 0) { 416 error_setg(errp, "Hot-plug failed: unsupported by the port device '%s'", 417 DEVICE(hotplug_pdev)->id); 418 return; 419 } 420 421 pcie_cap_slot_plug_common(PCI_DEVICE(hotplug_dev), dev, errp); 422 } 423 424 void pcie_cap_slot_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, 425 Error **errp) 426 { 427 PCIDevice *hotplug_pdev = PCI_DEVICE(hotplug_dev); 428 uint8_t *exp_cap = hotplug_pdev->config + hotplug_pdev->exp.exp_cap; 429 PCIDevice *pci_dev = PCI_DEVICE(dev); 430 431 /* Don't send event when device is enabled during qemu machine creation: 432 * it is present on boot, no hotplug event is necessary. We do send an 433 * event when the device is disabled later. */ 434 if (!dev->hotplugged) { 435 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA, 436 PCI_EXP_SLTSTA_PDS); 437 if (pci_dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA) { 438 pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA, 439 PCI_EXP_LNKSTA_DLLLA); 440 } 441 return; 442 } 443 444 /* To enable multifunction hot-plug, we just ensure the function 445 * 0 added last. When function 0 is added, we set the sltsta and 446 * inform OS via event notification. 447 */ 448 if (pci_get_function_0(pci_dev)) { 449 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA, 450 PCI_EXP_SLTSTA_PDS); 451 if (pci_dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA) { 452 pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA, 453 PCI_EXP_LNKSTA_DLLLA); 454 } 455 pcie_cap_slot_event(hotplug_pdev, 456 PCI_EXP_HP_EV_PDC | PCI_EXP_HP_EV_ABP); 457 } 458 } 459 460 void pcie_cap_slot_unplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, 461 Error **errp) 462 { 463 qdev_unrealize(dev); 464 } 465 466 static void pcie_unplug_device(PCIBus *bus, PCIDevice *dev, void *opaque) 467 { 468 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(DEVICE(dev)); 469 470 if (dev->partially_hotplugged) { 471 dev->qdev.pending_deleted_event = false; 472 return; 473 } 474 hotplug_handler_unplug(hotplug_ctrl, DEVICE(dev), &error_abort); 475 object_unparent(OBJECT(dev)); 476 } 477 478 void pcie_cap_slot_unplug_request_cb(HotplugHandler *hotplug_dev, 479 DeviceState *dev, Error **errp) 480 { 481 Error *local_err = NULL; 482 PCIDevice *pci_dev = PCI_DEVICE(dev); 483 PCIBus *bus = pci_get_bus(pci_dev); 484 PCIDevice *hotplug_pdev = PCI_DEVICE(hotplug_dev); 485 uint8_t *exp_cap = hotplug_pdev->config + hotplug_pdev->exp.exp_cap; 486 uint32_t sltcap = pci_get_word(exp_cap + PCI_EXP_SLTCAP); 487 488 /* Check if hot-unplug is disabled on the slot */ 489 if ((sltcap & PCI_EXP_SLTCAP_HPC) == 0) { 490 error_setg(errp, "Hot-unplug failed: " 491 "unsupported by the port device '%s'", 492 DEVICE(hotplug_pdev)->id); 493 return; 494 } 495 496 pcie_cap_slot_plug_common(hotplug_pdev, dev, &local_err); 497 if (local_err) { 498 error_propagate(errp, local_err); 499 return; 500 } 501 502 dev->pending_deleted_event = true; 503 504 /* In case user cancel the operation of multi-function hot-add, 505 * remove the function that is unexposed to guest individually, 506 * without interaction with guest. 507 */ 508 if (pci_dev->devfn && 509 !bus->devices[0]) { 510 pcie_unplug_device(bus, pci_dev, NULL); 511 512 return; 513 } 514 515 pcie_cap_slot_push_attention_button(hotplug_pdev); 516 } 517 518 /* pci express slot for pci express root/downstream port 519 PCI express capability slot registers */ 520 void pcie_cap_slot_init(PCIDevice *dev, PCIESlot *s) 521 { 522 uint32_t pos = dev->exp.exp_cap; 523 524 pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_FLAGS, 525 PCI_EXP_FLAGS_SLOT); 526 527 pci_long_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCAP, 528 ~PCI_EXP_SLTCAP_PSN); 529 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP, 530 (s->slot << PCI_EXP_SLTCAP_PSN_SHIFT) | 531 PCI_EXP_SLTCAP_EIP | 532 PCI_EXP_SLTCAP_PIP | 533 PCI_EXP_SLTCAP_AIP | 534 PCI_EXP_SLTCAP_ABP); 535 if (s->hotplug) { 536 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP, 537 PCI_EXP_SLTCAP_HPS | 538 PCI_EXP_SLTCAP_HPC); 539 } 540 541 if (dev->cap_present & QEMU_PCIE_SLTCAP_PCP) { 542 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP, 543 PCI_EXP_SLTCAP_PCP); 544 pci_word_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCTL, 545 PCI_EXP_SLTCTL_PCC); 546 pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL, 547 PCI_EXP_SLTCTL_PCC); 548 } 549 550 pci_word_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCTL, 551 PCI_EXP_SLTCTL_PIC | 552 PCI_EXP_SLTCTL_AIC); 553 pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCTL, 554 PCI_EXP_SLTCTL_PIC_OFF | 555 PCI_EXP_SLTCTL_AIC_OFF); 556 pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL, 557 PCI_EXP_SLTCTL_PIC | 558 PCI_EXP_SLTCTL_AIC | 559 PCI_EXP_SLTCTL_HPIE | 560 PCI_EXP_SLTCTL_CCIE | 561 PCI_EXP_SLTCTL_PDCE | 562 PCI_EXP_SLTCTL_ABPE); 563 /* Although reading PCI_EXP_SLTCTL_EIC returns always 0, 564 * make the bit writable here in order to detect 1b is written. 565 * pcie_cap_slot_write_config() test-and-clear the bit, so 566 * this bit always returns 0 to the guest. 567 */ 568 pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL, 569 PCI_EXP_SLTCTL_EIC); 570 571 pci_word_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_SLTSTA, 572 PCI_EXP_HP_EV_SUPPORTED); 573 574 dev->exp.hpev_notified = false; 575 576 qbus_set_hotplug_handler(BUS(pci_bridge_get_sec_bus(PCI_BRIDGE(dev))), 577 OBJECT(dev)); 578 } 579 580 void pcie_cap_slot_reset(PCIDevice *dev) 581 { 582 uint8_t *exp_cap = dev->config + dev->exp.exp_cap; 583 uint8_t port_type = pcie_cap_get_type(dev); 584 585 assert(port_type == PCI_EXP_TYPE_DOWNSTREAM || 586 port_type == PCI_EXP_TYPE_ROOT_PORT); 587 588 PCIE_DEV_PRINTF(dev, "reset\n"); 589 590 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL, 591 PCI_EXP_SLTCTL_EIC | 592 PCI_EXP_SLTCTL_PIC | 593 PCI_EXP_SLTCTL_AIC | 594 PCI_EXP_SLTCTL_HPIE | 595 PCI_EXP_SLTCTL_CCIE | 596 PCI_EXP_SLTCTL_PDCE | 597 PCI_EXP_SLTCTL_ABPE); 598 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL, 599 PCI_EXP_SLTCTL_AIC_OFF); 600 601 if (dev->cap_present & QEMU_PCIE_SLTCAP_PCP) { 602 /* Downstream ports enforce device number 0. */ 603 bool populated = pci_bridge_get_sec_bus(PCI_BRIDGE(dev))->devices[0]; 604 uint16_t pic; 605 606 if (populated) { 607 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL, 608 PCI_EXP_SLTCTL_PCC); 609 } else { 610 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL, 611 PCI_EXP_SLTCTL_PCC); 612 } 613 614 pic = populated ? PCI_EXP_SLTCTL_PIC_ON : PCI_EXP_SLTCTL_PIC_OFF; 615 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL, pic); 616 } 617 618 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA, 619 PCI_EXP_SLTSTA_EIS |/* on reset, 620 the lock is released */ 621 PCI_EXP_SLTSTA_CC | 622 PCI_EXP_SLTSTA_PDC | 623 PCI_EXP_SLTSTA_ABP); 624 625 hotplug_event_update_event_status(dev); 626 } 627 628 void pcie_cap_slot_get(PCIDevice *dev, uint16_t *slt_ctl, uint16_t *slt_sta) 629 { 630 uint32_t pos = dev->exp.exp_cap; 631 uint8_t *exp_cap = dev->config + pos; 632 *slt_ctl = pci_get_word(exp_cap + PCI_EXP_SLTCTL); 633 *slt_sta = pci_get_word(exp_cap + PCI_EXP_SLTSTA); 634 } 635 636 void pcie_cap_slot_write_config(PCIDevice *dev, 637 uint16_t old_slt_ctl, uint16_t old_slt_sta, 638 uint32_t addr, uint32_t val, int len) 639 { 640 uint32_t pos = dev->exp.exp_cap; 641 uint8_t *exp_cap = dev->config + pos; 642 uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA); 643 644 if (ranges_overlap(addr, len, pos + PCI_EXP_SLTSTA, 2)) { 645 /* 646 * Guests tend to clears all bits during init. 647 * If they clear bits that weren't set this is racy and will lose events: 648 * not a big problem for manual button presses, but a problem for us. 649 * As a work-around, detect this and revert status to what it was 650 * before the write. 651 * 652 * Note: in theory this can be detected as a duplicate button press 653 * which cancels the previous press. Does not seem to happen in 654 * practice as guests seem to only have this bug during init. 655 */ 656 #define PCIE_SLOT_EVENTS (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD | \ 657 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC | \ 658 PCI_EXP_SLTSTA_CC) 659 660 if (val & ~old_slt_sta & PCIE_SLOT_EVENTS) { 661 sltsta = (sltsta & ~PCIE_SLOT_EVENTS) | (old_slt_sta & PCIE_SLOT_EVENTS); 662 pci_set_word(exp_cap + PCI_EXP_SLTSTA, sltsta); 663 } 664 hotplug_event_clear(dev); 665 } 666 667 if (!ranges_overlap(addr, len, pos + PCI_EXP_SLTCTL, 2)) { 668 return; 669 } 670 671 if (pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL, 672 PCI_EXP_SLTCTL_EIC)) { 673 sltsta ^= PCI_EXP_SLTSTA_EIS; /* toggle PCI_EXP_SLTSTA_EIS bit */ 674 pci_set_word(exp_cap + PCI_EXP_SLTSTA, sltsta); 675 PCIE_DEV_PRINTF(dev, "PCI_EXP_SLTCTL_EIC: " 676 "sltsta -> 0x%02"PRIx16"\n", 677 sltsta); 678 } 679 680 /* 681 * If the slot is populated, power indicator is off and power 682 * controller is off, it is safe to detach the devices. 683 * 684 * Note: don't detach if condition was already true: 685 * this is a work around for guests that overwrite 686 * control of powered off slots before powering them on. 687 */ 688 if ((sltsta & PCI_EXP_SLTSTA_PDS) && (val & PCI_EXP_SLTCTL_PCC) && 689 (val & PCI_EXP_SLTCTL_PIC_OFF) == PCI_EXP_SLTCTL_PIC_OFF && 690 (!(old_slt_ctl & PCI_EXP_SLTCTL_PCC) || 691 (old_slt_ctl & PCI_EXP_SLTCTL_PIC_OFF) != PCI_EXP_SLTCTL_PIC_OFF)) { 692 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev)); 693 pci_for_each_device(sec_bus, pci_bus_num(sec_bus), 694 pcie_unplug_device, NULL); 695 696 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA, 697 PCI_EXP_SLTSTA_PDS); 698 if (dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA) { 699 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_LNKSTA, 700 PCI_EXP_LNKSTA_DLLLA); 701 } 702 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA, 703 PCI_EXP_SLTSTA_PDC); 704 } 705 706 hotplug_event_notify(dev); 707 708 /* 709 * 6.7.3.2 Command Completed Events 710 * 711 * Software issues a command to a hot-plug capable Downstream Port by 712 * issuing a write transaction that targets any portion of the Port’s Slot 713 * Control register. A single write to the Slot Control register is 714 * considered to be a single command, even if the write affects more than 715 * one field in the Slot Control register. In response to this transaction, 716 * the Port must carry out the requested actions and then set the 717 * associated status field for the command completed event. */ 718 719 /* Real hardware might take a while to complete requested command because 720 * physical movement would be involved like locking the electromechanical 721 * lock. However in our case, command is completed instantaneously above, 722 * so send a command completion event right now. 723 */ 724 pcie_cap_slot_event(dev, PCI_EXP_HP_EV_CCI); 725 } 726 727 int pcie_cap_slot_post_load(void *opaque, int version_id) 728 { 729 PCIDevice *dev = opaque; 730 hotplug_event_update_event_status(dev); 731 return 0; 732 } 733 734 void pcie_cap_slot_push_attention_button(PCIDevice *dev) 735 { 736 pcie_cap_slot_event(dev, PCI_EXP_HP_EV_ABP); 737 } 738 739 /* root control/capabilities/status. PME isn't emulated for now */ 740 void pcie_cap_root_init(PCIDevice *dev) 741 { 742 pci_set_word(dev->wmask + dev->exp.exp_cap + PCI_EXP_RTCTL, 743 PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE | 744 PCI_EXP_RTCTL_SEFEE); 745 } 746 747 void pcie_cap_root_reset(PCIDevice *dev) 748 { 749 pci_set_word(dev->config + dev->exp.exp_cap + PCI_EXP_RTCTL, 0); 750 } 751 752 /* function level reset(FLR) */ 753 void pcie_cap_flr_init(PCIDevice *dev) 754 { 755 pci_long_test_and_set_mask(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCAP, 756 PCI_EXP_DEVCAP_FLR); 757 758 /* Although reading BCR_FLR returns always 0, 759 * the bit is made writable here in order to detect the 1b is written 760 * pcie_cap_flr_write_config() test-and-clear the bit, so 761 * this bit always returns 0 to the guest. 762 */ 763 pci_word_test_and_set_mask(dev->wmask + dev->exp.exp_cap + PCI_EXP_DEVCTL, 764 PCI_EXP_DEVCTL_BCR_FLR); 765 } 766 767 void pcie_cap_flr_write_config(PCIDevice *dev, 768 uint32_t addr, uint32_t val, int len) 769 { 770 uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL; 771 if (pci_get_word(devctl) & PCI_EXP_DEVCTL_BCR_FLR) { 772 /* Clear PCI_EXP_DEVCTL_BCR_FLR after invoking the reset handler 773 so the handler can detect FLR by looking at this bit. */ 774 pci_device_reset(dev); 775 pci_word_test_and_clear_mask(devctl, PCI_EXP_DEVCTL_BCR_FLR); 776 } 777 } 778 779 /* Alternative Routing-ID Interpretation (ARI) 780 * forwarding support for root and downstream ports 781 */ 782 void pcie_cap_arifwd_init(PCIDevice *dev) 783 { 784 uint32_t pos = dev->exp.exp_cap; 785 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP2, 786 PCI_EXP_DEVCAP2_ARI); 787 pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL2, 788 PCI_EXP_DEVCTL2_ARI); 789 } 790 791 void pcie_cap_arifwd_reset(PCIDevice *dev) 792 { 793 uint8_t *devctl2 = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2; 794 pci_long_test_and_clear_mask(devctl2, PCI_EXP_DEVCTL2_ARI); 795 } 796 797 bool pcie_cap_is_arifwd_enabled(const PCIDevice *dev) 798 { 799 if (!pci_is_express(dev)) { 800 return false; 801 } 802 if (!dev->exp.exp_cap) { 803 return false; 804 } 805 806 return pci_get_long(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2) & 807 PCI_EXP_DEVCTL2_ARI; 808 } 809 810 /************************************************************************** 811 * pci express extended capability list management functions 812 * uint16_t ext_cap_id (16 bit) 813 * uint8_t cap_ver (4 bit) 814 * uint16_t cap_offset (12 bit) 815 * uint16_t ext_cap_size 816 */ 817 818 /* Passing a cap_id value > 0xffff will return 0 and put end of list in prev */ 819 static uint16_t pcie_find_capability_list(PCIDevice *dev, uint32_t cap_id, 820 uint16_t *prev_p) 821 { 822 uint16_t prev = 0; 823 uint16_t next; 824 uint32_t header = pci_get_long(dev->config + PCI_CONFIG_SPACE_SIZE); 825 826 if (!header) { 827 /* no extended capability */ 828 next = 0; 829 goto out; 830 } 831 for (next = PCI_CONFIG_SPACE_SIZE; next; 832 prev = next, next = PCI_EXT_CAP_NEXT(header)) { 833 834 assert(next >= PCI_CONFIG_SPACE_SIZE); 835 assert(next <= PCIE_CONFIG_SPACE_SIZE - 8); 836 837 header = pci_get_long(dev->config + next); 838 if (PCI_EXT_CAP_ID(header) == cap_id) { 839 break; 840 } 841 } 842 843 out: 844 if (prev_p) { 845 *prev_p = prev; 846 } 847 return next; 848 } 849 850 uint16_t pcie_find_capability(PCIDevice *dev, uint16_t cap_id) 851 { 852 return pcie_find_capability_list(dev, cap_id, NULL); 853 } 854 855 static void pcie_ext_cap_set_next(PCIDevice *dev, uint16_t pos, uint16_t next) 856 { 857 uint32_t header = pci_get_long(dev->config + pos); 858 assert(!(next & (PCI_EXT_CAP_ALIGN - 1))); 859 header = (header & ~PCI_EXT_CAP_NEXT_MASK) | 860 ((next << PCI_EXT_CAP_NEXT_SHIFT) & PCI_EXT_CAP_NEXT_MASK); 861 pci_set_long(dev->config + pos, header); 862 } 863 864 /* 865 * Caller must supply valid (offset, size) such that the range wouldn't 866 * overlap with other capability or other registers. 867 * This function doesn't check it. 868 */ 869 void pcie_add_capability(PCIDevice *dev, 870 uint16_t cap_id, uint8_t cap_ver, 871 uint16_t offset, uint16_t size) 872 { 873 assert(offset >= PCI_CONFIG_SPACE_SIZE); 874 assert(offset < offset + size); 875 assert(offset + size <= PCIE_CONFIG_SPACE_SIZE); 876 assert(size >= 8); 877 assert(pci_is_express(dev)); 878 879 if (offset != PCI_CONFIG_SPACE_SIZE) { 880 uint16_t prev; 881 882 /* 883 * 0xffffffff is not a valid cap id (it's a 16 bit field). use 884 * internally to find the last capability in the linked list. 885 */ 886 pcie_find_capability_list(dev, 0xffffffff, &prev); 887 assert(prev >= PCI_CONFIG_SPACE_SIZE); 888 pcie_ext_cap_set_next(dev, prev, offset); 889 } 890 pci_set_long(dev->config + offset, PCI_EXT_CAP(cap_id, cap_ver, 0)); 891 892 /* Make capability read-only by default */ 893 memset(dev->wmask + offset, 0, size); 894 memset(dev->w1cmask + offset, 0, size); 895 /* Check capability by default */ 896 memset(dev->cmask + offset, 0xFF, size); 897 } 898 899 /* 900 * Sync the PCIe Link Status negotiated speed and width of a bridge with the 901 * downstream device. If downstream device is not present, re-write with the 902 * Link Capability fields. If downstream device reports invalid width or 903 * speed, replace with minimum values (LnkSta fields are RsvdZ on VFs but such 904 * values interfere with PCIe native hotplug detecting new devices). Limit 905 * width and speed to bridge capabilities for compatibility. Use config_read 906 * to access the downstream device since it could be an assigned device with 907 * volatile link information. 908 */ 909 void pcie_sync_bridge_lnk(PCIDevice *bridge_dev) 910 { 911 PCIBridge *br = PCI_BRIDGE(bridge_dev); 912 PCIBus *bus = pci_bridge_get_sec_bus(br); 913 PCIDevice *target = bus->devices[0]; 914 uint8_t *exp_cap = bridge_dev->config + bridge_dev->exp.exp_cap; 915 uint16_t lnksta, lnkcap = pci_get_word(exp_cap + PCI_EXP_LNKCAP); 916 917 if (!target || !target->exp.exp_cap) { 918 lnksta = lnkcap; 919 } else { 920 lnksta = target->config_read(target, 921 target->exp.exp_cap + PCI_EXP_LNKSTA, 922 sizeof(lnksta)); 923 924 if ((lnksta & PCI_EXP_LNKSTA_NLW) > (lnkcap & PCI_EXP_LNKCAP_MLW)) { 925 lnksta &= ~PCI_EXP_LNKSTA_NLW; 926 lnksta |= lnkcap & PCI_EXP_LNKCAP_MLW; 927 } else if (!(lnksta & PCI_EXP_LNKSTA_NLW)) { 928 lnksta |= QEMU_PCI_EXP_LNKSTA_NLW(QEMU_PCI_EXP_LNK_X1); 929 } 930 931 if ((lnksta & PCI_EXP_LNKSTA_CLS) > (lnkcap & PCI_EXP_LNKCAP_SLS)) { 932 lnksta &= ~PCI_EXP_LNKSTA_CLS; 933 lnksta |= lnkcap & PCI_EXP_LNKCAP_SLS; 934 } else if (!(lnksta & PCI_EXP_LNKSTA_CLS)) { 935 lnksta |= QEMU_PCI_EXP_LNKSTA_CLS(QEMU_PCI_EXP_LNK_2_5GT); 936 } 937 } 938 939 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_LNKSTA, 940 PCI_EXP_LNKSTA_CLS | PCI_EXP_LNKSTA_NLW); 941 pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA, lnksta & 942 (PCI_EXP_LNKSTA_CLS | PCI_EXP_LNKSTA_NLW)); 943 } 944 945 /************************************************************************** 946 * pci express extended capability helper functions 947 */ 948 949 /* ARI */ 950 void pcie_ari_init(PCIDevice *dev, uint16_t offset, uint16_t nextfn) 951 { 952 pcie_add_capability(dev, PCI_EXT_CAP_ID_ARI, PCI_ARI_VER, 953 offset, PCI_ARI_SIZEOF); 954 pci_set_long(dev->config + offset + PCI_ARI_CAP, (nextfn & 0xff) << 8); 955 } 956 957 void pcie_dev_ser_num_init(PCIDevice *dev, uint16_t offset, uint64_t ser_num) 958 { 959 static const int pci_dsn_ver = 1; 960 static const int pci_dsn_cap = 4; 961 962 pcie_add_capability(dev, PCI_EXT_CAP_ID_DSN, pci_dsn_ver, offset, 963 PCI_EXT_CAP_DSN_SIZEOF); 964 pci_set_quad(dev->config + offset + pci_dsn_cap, ser_num); 965 } 966 967 void pcie_ats_init(PCIDevice *dev, uint16_t offset) 968 { 969 pcie_add_capability(dev, PCI_EXT_CAP_ID_ATS, 0x1, 970 offset, PCI_EXT_CAP_ATS_SIZEOF); 971 972 dev->exp.ats_cap = offset; 973 974 /* Invalidate Queue Depth 0, Page Aligned Request 0 */ 975 pci_set_word(dev->config + offset + PCI_ATS_CAP, 0); 976 /* STU 0, Disabled by default */ 977 pci_set_word(dev->config + offset + PCI_ATS_CTRL, 0); 978 979 pci_set_word(dev->wmask + dev->exp.ats_cap + PCI_ATS_CTRL, 0x800f); 980 } 981 982 /* ACS (Access Control Services) */ 983 void pcie_acs_init(PCIDevice *dev, uint16_t offset) 984 { 985 bool is_downstream = pci_is_express_downstream_port(dev); 986 uint16_t cap_bits = 0; 987 988 /* For endpoints, only multifunction devs may have an ACS capability: */ 989 assert(is_downstream || 990 (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) || 991 PCI_FUNC(dev->devfn)); 992 993 pcie_add_capability(dev, PCI_EXT_CAP_ID_ACS, PCI_ACS_VER, offset, 994 PCI_ACS_SIZEOF); 995 dev->exp.acs_cap = offset; 996 997 if (is_downstream) { 998 /* 999 * Downstream ports must implement SV, TB, RR, CR, UF, and DT (with 1000 * caveats on the latter four that we ignore for simplicity). 1001 * Endpoints may also implement a subset of ACS capabilities, 1002 * but these are optional if the endpoint does not support 1003 * peer-to-peer between functions and thus omitted here. 1004 */ 1005 cap_bits = PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR | 1006 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT; 1007 } 1008 1009 pci_set_word(dev->config + offset + PCI_ACS_CAP, cap_bits); 1010 pci_set_word(dev->wmask + offset + PCI_ACS_CTRL, cap_bits); 1011 } 1012 1013 void pcie_acs_reset(PCIDevice *dev) 1014 { 1015 if (dev->exp.acs_cap) { 1016 pci_set_word(dev->config + dev->exp.acs_cap + PCI_ACS_CTRL, 0); 1017 } 1018 } 1019