1 /* 2 * pci_host.c 3 * 4 * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp> 5 * VA Linux Systems Japan K.K. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "hw/pci/pci.h" 23 #include "hw/pci/pci_bridge.h" 24 #include "hw/pci/pci_host.h" 25 #include "hw/pci/pci_bus.h" 26 #include "trace.h" 27 28 /* debug PCI */ 29 //#define DEBUG_PCI 30 31 #ifdef DEBUG_PCI 32 #define PCI_DPRINTF(fmt, ...) \ 33 do { printf("pci_host_data: " fmt , ## __VA_ARGS__); } while (0) 34 #else 35 #define PCI_DPRINTF(fmt, ...) 36 #endif 37 38 /* 39 * PCI address 40 * bit 16 - 24: bus number 41 * bit 8 - 15: devfun number 42 * bit 0 - 7: offset in configuration space of a given pci device 43 */ 44 45 /* the helper function to get a PCIDevice* for a given pci address */ 46 static inline PCIDevice *pci_dev_find_by_addr(PCIBus *bus, uint32_t addr) 47 { 48 uint8_t bus_num = addr >> 16; 49 uint8_t devfn = addr >> 8; 50 51 return pci_find_device(bus, bus_num, devfn); 52 } 53 54 static void pci_adjust_config_limit(PCIBus *bus, uint32_t *limit) 55 { 56 if (*limit > PCI_CONFIG_SPACE_SIZE) { 57 if (!pci_bus_allows_extended_config_space(bus)) { 58 *limit = PCI_CONFIG_SPACE_SIZE; 59 return; 60 } 61 62 if (!pci_bus_is_root(bus)) { 63 PCIDevice *bridge = pci_bridge_get_device(bus); 64 pci_adjust_config_limit(pci_get_bus(bridge), limit); 65 } 66 } 67 } 68 69 void pci_host_config_write_common(PCIDevice *pci_dev, uint32_t addr, 70 uint32_t limit, uint32_t val, uint32_t len) 71 { 72 pci_adjust_config_limit(pci_get_bus(pci_dev), &limit); 73 if (limit <= addr) { 74 return; 75 } 76 77 assert(len <= 4); 78 /* non-zero functions are only exposed when function 0 is present, 79 * allowing direct removal of unexposed functions. 80 */ 81 if (pci_dev->qdev.hotplugged && !pci_get_function_0(pci_dev)) { 82 return; 83 } 84 85 trace_pci_cfg_write(pci_dev->name, PCI_SLOT(pci_dev->devfn), 86 PCI_FUNC(pci_dev->devfn), addr, val); 87 pci_dev->config_write(pci_dev, addr, val, MIN(len, limit - addr)); 88 } 89 90 uint32_t pci_host_config_read_common(PCIDevice *pci_dev, uint32_t addr, 91 uint32_t limit, uint32_t len) 92 { 93 uint32_t ret; 94 95 pci_adjust_config_limit(pci_get_bus(pci_dev), &limit); 96 if (limit <= addr) { 97 return ~0x0; 98 } 99 100 assert(len <= 4); 101 /* non-zero functions are only exposed when function 0 is present, 102 * allowing direct removal of unexposed functions. 103 */ 104 if (pci_dev->qdev.hotplugged && !pci_get_function_0(pci_dev)) { 105 return ~0x0; 106 } 107 108 ret = pci_dev->config_read(pci_dev, addr, MIN(len, limit - addr)); 109 trace_pci_cfg_read(pci_dev->name, PCI_SLOT(pci_dev->devfn), 110 PCI_FUNC(pci_dev->devfn), addr, ret); 111 112 return ret; 113 } 114 115 void pci_data_write(PCIBus *s, uint32_t addr, uint32_t val, int len) 116 { 117 PCIDevice *pci_dev = pci_dev_find_by_addr(s, addr); 118 uint32_t config_addr = addr & (PCI_CONFIG_SPACE_SIZE - 1); 119 120 if (!pci_dev) { 121 return; 122 } 123 124 PCI_DPRINTF("%s: %s: addr=%02" PRIx32 " val=%08" PRIx32 " len=%d\n", 125 __func__, pci_dev->name, config_addr, val, len); 126 pci_host_config_write_common(pci_dev, config_addr, PCI_CONFIG_SPACE_SIZE, 127 val, len); 128 } 129 130 uint32_t pci_data_read(PCIBus *s, uint32_t addr, int len) 131 { 132 PCIDevice *pci_dev = pci_dev_find_by_addr(s, addr); 133 uint32_t config_addr = addr & (PCI_CONFIG_SPACE_SIZE - 1); 134 uint32_t val; 135 136 if (!pci_dev) { 137 return ~0x0; 138 } 139 140 val = pci_host_config_read_common(pci_dev, config_addr, 141 PCI_CONFIG_SPACE_SIZE, len); 142 PCI_DPRINTF("%s: %s: addr=%02"PRIx32" val=%08"PRIx32" len=%d\n", 143 __func__, pci_dev->name, config_addr, val, len); 144 145 return val; 146 } 147 148 static void pci_host_config_write(void *opaque, hwaddr addr, 149 uint64_t val, unsigned len) 150 { 151 PCIHostState *s = opaque; 152 153 PCI_DPRINTF("%s addr " TARGET_FMT_plx " len %d val %"PRIx64"\n", 154 __func__, addr, len, val); 155 if (addr != 0 || len != 4) { 156 return; 157 } 158 s->config_reg = val; 159 } 160 161 static uint64_t pci_host_config_read(void *opaque, hwaddr addr, 162 unsigned len) 163 { 164 PCIHostState *s = opaque; 165 uint32_t val = s->config_reg; 166 167 PCI_DPRINTF("%s addr " TARGET_FMT_plx " len %d val %"PRIx32"\n", 168 __func__, addr, len, val); 169 return val; 170 } 171 172 static void pci_host_data_write(void *opaque, hwaddr addr, 173 uint64_t val, unsigned len) 174 { 175 PCIHostState *s = opaque; 176 PCI_DPRINTF("write addr " TARGET_FMT_plx " len %d val %x\n", 177 addr, len, (unsigned)val); 178 if (s->config_reg & (1u << 31)) 179 pci_data_write(s->bus, s->config_reg | (addr & 3), val, len); 180 } 181 182 static uint64_t pci_host_data_read(void *opaque, 183 hwaddr addr, unsigned len) 184 { 185 PCIHostState *s = opaque; 186 uint32_t val; 187 if (!(s->config_reg & (1U << 31))) { 188 return 0xffffffff; 189 } 190 val = pci_data_read(s->bus, s->config_reg | (addr & 3), len); 191 PCI_DPRINTF("read addr " TARGET_FMT_plx " len %d val %x\n", 192 addr, len, val); 193 return val; 194 } 195 196 const MemoryRegionOps pci_host_conf_le_ops = { 197 .read = pci_host_config_read, 198 .write = pci_host_config_write, 199 .endianness = DEVICE_LITTLE_ENDIAN, 200 }; 201 202 const MemoryRegionOps pci_host_conf_be_ops = { 203 .read = pci_host_config_read, 204 .write = pci_host_config_write, 205 .endianness = DEVICE_BIG_ENDIAN, 206 }; 207 208 const MemoryRegionOps pci_host_data_le_ops = { 209 .read = pci_host_data_read, 210 .write = pci_host_data_write, 211 .endianness = DEVICE_LITTLE_ENDIAN, 212 }; 213 214 const MemoryRegionOps pci_host_data_be_ops = { 215 .read = pci_host_data_read, 216 .write = pci_host_data_write, 217 .endianness = DEVICE_BIG_ENDIAN, 218 }; 219 220 static const TypeInfo pci_host_type_info = { 221 .name = TYPE_PCI_HOST_BRIDGE, 222 .parent = TYPE_SYS_BUS_DEVICE, 223 .abstract = true, 224 .class_size = sizeof(PCIHostBridgeClass), 225 .instance_size = sizeof(PCIHostState), 226 }; 227 228 static void pci_host_register_types(void) 229 { 230 type_register_static(&pci_host_type_info); 231 } 232 233 type_init(pci_host_register_types) 234