1 /* 2 * pci_host.c 3 * 4 * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp> 5 * VA Linux Systems Japan K.K. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "hw/pci/pci.h" 22 #include "hw/pci/pci_host.h" 23 #include "trace.h" 24 25 /* debug PCI */ 26 //#define DEBUG_PCI 27 28 #ifdef DEBUG_PCI 29 #define PCI_DPRINTF(fmt, ...) \ 30 do { printf("pci_host_data: " fmt , ## __VA_ARGS__); } while (0) 31 #else 32 #define PCI_DPRINTF(fmt, ...) 33 #endif 34 35 /* 36 * PCI address 37 * bit 16 - 24: bus number 38 * bit 8 - 15: devfun number 39 * bit 0 - 7: offset in configuration space of a given pci device 40 */ 41 42 /* the helper function to get a PCIDevice* for a given pci address */ 43 static inline PCIDevice *pci_dev_find_by_addr(PCIBus *bus, uint32_t addr) 44 { 45 uint8_t bus_num = addr >> 16; 46 uint8_t devfn = addr >> 8; 47 48 return pci_find_device(bus, bus_num, devfn); 49 } 50 51 void pci_host_config_write_common(PCIDevice *pci_dev, uint32_t addr, 52 uint32_t limit, uint32_t val, uint32_t len) 53 { 54 assert(len <= 4); 55 trace_pci_cfg_write(pci_dev->name, PCI_SLOT(pci_dev->devfn), 56 PCI_FUNC(pci_dev->devfn), addr, val); 57 pci_dev->config_write(pci_dev, addr, val, MIN(len, limit - addr)); 58 } 59 60 uint32_t pci_host_config_read_common(PCIDevice *pci_dev, uint32_t addr, 61 uint32_t limit, uint32_t len) 62 { 63 uint32_t ret; 64 65 assert(len <= 4); 66 ret = pci_dev->config_read(pci_dev, addr, MIN(len, limit - addr)); 67 trace_pci_cfg_read(pci_dev->name, PCI_SLOT(pci_dev->devfn), 68 PCI_FUNC(pci_dev->devfn), addr, ret); 69 70 return ret; 71 } 72 73 void pci_data_write(PCIBus *s, uint32_t addr, uint32_t val, int len) 74 { 75 PCIDevice *pci_dev = pci_dev_find_by_addr(s, addr); 76 uint32_t config_addr = addr & (PCI_CONFIG_SPACE_SIZE - 1); 77 78 if (!pci_dev) { 79 return; 80 } 81 82 PCI_DPRINTF("%s: %s: addr=%02" PRIx32 " val=%08" PRIx32 " len=%d\n", 83 __func__, pci_dev->name, config_addr, val, len); 84 pci_host_config_write_common(pci_dev, config_addr, PCI_CONFIG_SPACE_SIZE, 85 val, len); 86 } 87 88 uint32_t pci_data_read(PCIBus *s, uint32_t addr, int len) 89 { 90 PCIDevice *pci_dev = pci_dev_find_by_addr(s, addr); 91 uint32_t config_addr = addr & (PCI_CONFIG_SPACE_SIZE - 1); 92 uint32_t val; 93 94 if (!pci_dev) { 95 return ~0x0; 96 } 97 98 val = pci_host_config_read_common(pci_dev, config_addr, 99 PCI_CONFIG_SPACE_SIZE, len); 100 PCI_DPRINTF("%s: %s: addr=%02"PRIx32" val=%08"PRIx32" len=%d\n", 101 __func__, pci_dev->name, config_addr, val, len); 102 103 return val; 104 } 105 106 static void pci_host_config_write(void *opaque, hwaddr addr, 107 uint64_t val, unsigned len) 108 { 109 PCIHostState *s = opaque; 110 111 PCI_DPRINTF("%s addr " TARGET_FMT_plx " len %d val %"PRIx64"\n", 112 __func__, addr, len, val); 113 if (addr != 0 || len != 4) { 114 return; 115 } 116 s->config_reg = val; 117 } 118 119 static uint64_t pci_host_config_read(void *opaque, hwaddr addr, 120 unsigned len) 121 { 122 PCIHostState *s = opaque; 123 uint32_t val = s->config_reg; 124 125 PCI_DPRINTF("%s addr " TARGET_FMT_plx " len %d val %"PRIx32"\n", 126 __func__, addr, len, val); 127 return val; 128 } 129 130 static void pci_host_data_write(void *opaque, hwaddr addr, 131 uint64_t val, unsigned len) 132 { 133 PCIHostState *s = opaque; 134 PCI_DPRINTF("write addr " TARGET_FMT_plx " len %d val %x\n", 135 addr, len, (unsigned)val); 136 if (s->config_reg & (1u << 31)) 137 pci_data_write(s->bus, s->config_reg | (addr & 3), val, len); 138 } 139 140 static uint64_t pci_host_data_read(void *opaque, 141 hwaddr addr, unsigned len) 142 { 143 PCIHostState *s = opaque; 144 uint32_t val; 145 if (!(s->config_reg & (1 << 31))) 146 return 0xffffffff; 147 val = pci_data_read(s->bus, s->config_reg | (addr & 3), len); 148 PCI_DPRINTF("read addr " TARGET_FMT_plx " len %d val %x\n", 149 addr, len, val); 150 return val; 151 } 152 153 const MemoryRegionOps pci_host_conf_le_ops = { 154 .read = pci_host_config_read, 155 .write = pci_host_config_write, 156 .endianness = DEVICE_LITTLE_ENDIAN, 157 }; 158 159 const MemoryRegionOps pci_host_conf_be_ops = { 160 .read = pci_host_config_read, 161 .write = pci_host_config_write, 162 .endianness = DEVICE_BIG_ENDIAN, 163 }; 164 165 const MemoryRegionOps pci_host_data_le_ops = { 166 .read = pci_host_data_read, 167 .write = pci_host_data_write, 168 .endianness = DEVICE_LITTLE_ENDIAN, 169 }; 170 171 const MemoryRegionOps pci_host_data_be_ops = { 172 .read = pci_host_data_read, 173 .write = pci_host_data_write, 174 .endianness = DEVICE_BIG_ENDIAN, 175 }; 176 177 static const TypeInfo pci_host_type_info = { 178 .name = TYPE_PCI_HOST_BRIDGE, 179 .parent = TYPE_SYS_BUS_DEVICE, 180 .abstract = true, 181 .class_size = sizeof(PCIHostBridgeClass), 182 .instance_size = sizeof(PCIHostState), 183 }; 184 185 static void pci_host_register_types(void) 186 { 187 type_register_static(&pci_host_type_info); 188 } 189 190 type_init(pci_host_register_types) 191