1 /* 2 * QEMU PCI bus manager 3 * 4 * Copyright (c) 2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to dea 8 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM 22 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 /* 27 * split out from pci.c 28 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp> 29 * VA Linux Systems Japan K.K. 30 */ 31 32 #include "qemu/osdep.h" 33 #include "hw/pci/pci_bridge.h" 34 #include "hw/pci/pci_bus.h" 35 #include "qemu/module.h" 36 #include "qemu/range.h" 37 #include "qapi/error.h" 38 39 /* PCI bridge subsystem vendor ID helper functions */ 40 #define PCI_SSVID_SIZEOF 8 41 #define PCI_SSVID_SVID 4 42 #define PCI_SSVID_SSID 6 43 44 int pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset, 45 uint16_t svid, uint16_t ssid, 46 Error **errp) 47 { 48 int pos; 49 50 pos = pci_add_capability(dev, PCI_CAP_ID_SSVID, offset, 51 PCI_SSVID_SIZEOF, errp); 52 if (pos < 0) { 53 return pos; 54 } 55 56 pci_set_word(dev->config + pos + PCI_SSVID_SVID, svid); 57 pci_set_word(dev->config + pos + PCI_SSVID_SSID, ssid); 58 return pos; 59 } 60 61 /* Accessor function to get parent bridge device from pci bus. */ 62 PCIDevice *pci_bridge_get_device(PCIBus *bus) 63 { 64 return bus->parent_dev; 65 } 66 67 /* Accessor function to get secondary bus from pci-to-pci bridge device */ 68 PCIBus *pci_bridge_get_sec_bus(PCIBridge *br) 69 { 70 return &br->sec_bus; 71 } 72 73 static uint32_t pci_config_get_io_base(const PCIDevice *d, 74 uint32_t base, uint32_t base_upper16) 75 { 76 uint32_t val; 77 78 val = ((uint32_t)d->config[base] & PCI_IO_RANGE_MASK) << 8; 79 if (d->config[base] & PCI_IO_RANGE_TYPE_32) { 80 val |= (uint32_t)pci_get_word(d->config + base_upper16) << 16; 81 } 82 return val; 83 } 84 85 static pcibus_t pci_config_get_memory_base(const PCIDevice *d, uint32_t base) 86 { 87 return ((pcibus_t)pci_get_word(d->config + base) & PCI_MEMORY_RANGE_MASK) 88 << 16; 89 } 90 91 static pcibus_t pci_config_get_pref_base(const PCIDevice *d, 92 uint32_t base, uint32_t upper) 93 { 94 pcibus_t tmp; 95 pcibus_t val; 96 97 tmp = (pcibus_t)pci_get_word(d->config + base); 98 val = (tmp & PCI_PREF_RANGE_MASK) << 16; 99 if (tmp & PCI_PREF_RANGE_TYPE_64) { 100 val |= (pcibus_t)pci_get_long(d->config + upper) << 32; 101 } 102 return val; 103 } 104 105 /* accessor function to get bridge filtering base address */ 106 pcibus_t pci_bridge_get_base(const PCIDevice *bridge, uint8_t type) 107 { 108 pcibus_t base; 109 if (type & PCI_BASE_ADDRESS_SPACE_IO) { 110 base = pci_config_get_io_base(bridge, 111 PCI_IO_BASE, PCI_IO_BASE_UPPER16); 112 } else { 113 if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) { 114 base = pci_config_get_pref_base( 115 bridge, PCI_PREF_MEMORY_BASE, PCI_PREF_BASE_UPPER32); 116 } else { 117 base = pci_config_get_memory_base(bridge, PCI_MEMORY_BASE); 118 } 119 } 120 121 return base; 122 } 123 124 /* accessor function to get bridge filtering limit */ 125 pcibus_t pci_bridge_get_limit(const PCIDevice *bridge, uint8_t type) 126 { 127 pcibus_t limit; 128 if (type & PCI_BASE_ADDRESS_SPACE_IO) { 129 limit = pci_config_get_io_base(bridge, 130 PCI_IO_LIMIT, PCI_IO_LIMIT_UPPER16); 131 limit |= 0xfff; /* PCI bridge spec 3.2.5.6. */ 132 } else { 133 if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) { 134 limit = pci_config_get_pref_base( 135 bridge, PCI_PREF_MEMORY_LIMIT, PCI_PREF_LIMIT_UPPER32); 136 } else { 137 limit = pci_config_get_memory_base(bridge, PCI_MEMORY_LIMIT); 138 } 139 limit |= 0xfffff; /* PCI bridge spec 3.2.5.{1, 8}. */ 140 } 141 return limit; 142 } 143 144 static void pci_bridge_init_alias(PCIBridge *bridge, MemoryRegion *alias, 145 uint8_t type, const char *name, 146 MemoryRegion *space, 147 MemoryRegion *parent_space, 148 bool enabled) 149 { 150 PCIDevice *bridge_dev = PCI_DEVICE(bridge); 151 pcibus_t base = pci_bridge_get_base(bridge_dev, type); 152 pcibus_t limit = pci_bridge_get_limit(bridge_dev, type); 153 /* TODO: this doesn't handle base = 0 limit = 2^64 - 1 correctly. 154 * Apparently no way to do this with existing memory APIs. */ 155 pcibus_t size = enabled && limit >= base ? limit + 1 - base : 0; 156 157 memory_region_init_alias(alias, OBJECT(bridge), name, space, base, size); 158 memory_region_add_subregion_overlap(parent_space, base, alias, 1); 159 } 160 161 static void pci_bridge_init_vga_aliases(PCIBridge *br, PCIBus *parent, 162 MemoryRegion *alias_vga) 163 { 164 PCIDevice *pd = PCI_DEVICE(br); 165 uint16_t brctl = pci_get_word(pd->config + PCI_BRIDGE_CONTROL); 166 167 memory_region_init_alias(&alias_vga[QEMU_PCI_VGA_IO_LO], OBJECT(br), 168 "pci_bridge_vga_io_lo", &br->address_space_io, 169 QEMU_PCI_VGA_IO_LO_BASE, QEMU_PCI_VGA_IO_LO_SIZE); 170 memory_region_init_alias(&alias_vga[QEMU_PCI_VGA_IO_HI], OBJECT(br), 171 "pci_bridge_vga_io_hi", &br->address_space_io, 172 QEMU_PCI_VGA_IO_HI_BASE, QEMU_PCI_VGA_IO_HI_SIZE); 173 memory_region_init_alias(&alias_vga[QEMU_PCI_VGA_MEM], OBJECT(br), 174 "pci_bridge_vga_mem", &br->address_space_mem, 175 QEMU_PCI_VGA_MEM_BASE, QEMU_PCI_VGA_MEM_SIZE); 176 177 if (brctl & PCI_BRIDGE_CTL_VGA) { 178 pci_register_vga(pd, &alias_vga[QEMU_PCI_VGA_MEM], 179 &alias_vga[QEMU_PCI_VGA_IO_LO], 180 &alias_vga[QEMU_PCI_VGA_IO_HI]); 181 } 182 } 183 184 static PCIBridgeWindows *pci_bridge_region_init(PCIBridge *br) 185 { 186 PCIDevice *pd = PCI_DEVICE(br); 187 PCIBus *parent = pci_get_bus(pd); 188 PCIBridgeWindows *w = g_new(PCIBridgeWindows, 1); 189 uint16_t cmd = pci_get_word(pd->config + PCI_COMMAND); 190 191 pci_bridge_init_alias(br, &w->alias_pref_mem, 192 PCI_BASE_ADDRESS_MEM_PREFETCH, 193 "pci_bridge_pref_mem", 194 &br->address_space_mem, 195 parent->address_space_mem, 196 cmd & PCI_COMMAND_MEMORY); 197 pci_bridge_init_alias(br, &w->alias_mem, 198 PCI_BASE_ADDRESS_SPACE_MEMORY, 199 "pci_bridge_mem", 200 &br->address_space_mem, 201 parent->address_space_mem, 202 cmd & PCI_COMMAND_MEMORY); 203 pci_bridge_init_alias(br, &w->alias_io, 204 PCI_BASE_ADDRESS_SPACE_IO, 205 "pci_bridge_io", 206 &br->address_space_io, 207 parent->address_space_io, 208 cmd & PCI_COMMAND_IO); 209 210 pci_bridge_init_vga_aliases(br, parent, w->alias_vga); 211 212 return w; 213 } 214 215 static void pci_bridge_region_del(PCIBridge *br, PCIBridgeWindows *w) 216 { 217 PCIDevice *pd = PCI_DEVICE(br); 218 PCIBus *parent = pci_get_bus(pd); 219 220 memory_region_del_subregion(parent->address_space_io, &w->alias_io); 221 memory_region_del_subregion(parent->address_space_mem, &w->alias_mem); 222 memory_region_del_subregion(parent->address_space_mem, &w->alias_pref_mem); 223 pci_unregister_vga(pd); 224 } 225 226 static void pci_bridge_region_cleanup(PCIBridge *br, PCIBridgeWindows *w) 227 { 228 object_unparent(OBJECT(&w->alias_io)); 229 object_unparent(OBJECT(&w->alias_mem)); 230 object_unparent(OBJECT(&w->alias_pref_mem)); 231 object_unparent(OBJECT(&w->alias_vga[QEMU_PCI_VGA_IO_LO])); 232 object_unparent(OBJECT(&w->alias_vga[QEMU_PCI_VGA_IO_HI])); 233 object_unparent(OBJECT(&w->alias_vga[QEMU_PCI_VGA_MEM])); 234 g_free(w); 235 } 236 237 void pci_bridge_update_mappings(PCIBridge *br) 238 { 239 PCIBridgeWindows *w = br->windows; 240 241 /* Make updates atomic to: handle the case of one VCPU updating the bridge 242 * while another accesses an unaffected region. */ 243 memory_region_transaction_begin(); 244 pci_bridge_region_del(br, br->windows); 245 pci_bridge_region_cleanup(br, w); 246 br->windows = pci_bridge_region_init(br); 247 memory_region_transaction_commit(); 248 } 249 250 /* default write_config function for PCI-to-PCI bridge */ 251 void pci_bridge_write_config(PCIDevice *d, 252 uint32_t address, uint32_t val, int len) 253 { 254 PCIBridge *s = PCI_BRIDGE(d); 255 uint16_t oldctl = pci_get_word(d->config + PCI_BRIDGE_CONTROL); 256 uint16_t newctl; 257 258 pci_default_write_config(d, address, val, len); 259 260 if (ranges_overlap(address, len, PCI_COMMAND, 2) || 261 262 /* io base/limit */ 263 ranges_overlap(address, len, PCI_IO_BASE, 2) || 264 265 /* memory base/limit, prefetchable base/limit and 266 io base/limit upper 16 */ 267 ranges_overlap(address, len, PCI_MEMORY_BASE, 20) || 268 269 /* vga enable */ 270 ranges_overlap(address, len, PCI_BRIDGE_CONTROL, 2)) { 271 pci_bridge_update_mappings(s); 272 } 273 274 newctl = pci_get_word(d->config + PCI_BRIDGE_CONTROL); 275 if (~oldctl & newctl & PCI_BRIDGE_CTL_BUS_RESET) { 276 /* Trigger hot reset on 0->1 transition. */ 277 qbus_reset_all(BUS(&s->sec_bus)); 278 } 279 } 280 281 void pci_bridge_disable_base_limit(PCIDevice *dev) 282 { 283 uint8_t *conf = dev->config; 284 285 pci_byte_test_and_set_mask(conf + PCI_IO_BASE, 286 PCI_IO_RANGE_MASK & 0xff); 287 pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT, 288 PCI_IO_RANGE_MASK & 0xff); 289 pci_word_test_and_set_mask(conf + PCI_MEMORY_BASE, 290 PCI_MEMORY_RANGE_MASK & 0xffff); 291 pci_word_test_and_clear_mask(conf + PCI_MEMORY_LIMIT, 292 PCI_MEMORY_RANGE_MASK & 0xffff); 293 pci_word_test_and_set_mask(conf + PCI_PREF_MEMORY_BASE, 294 PCI_PREF_RANGE_MASK & 0xffff); 295 pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_LIMIT, 296 PCI_PREF_RANGE_MASK & 0xffff); 297 pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0); 298 pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0); 299 } 300 301 /* reset bridge specific configuration registers */ 302 void pci_bridge_reset(DeviceState *qdev) 303 { 304 PCIDevice *dev = PCI_DEVICE(qdev); 305 uint8_t *conf = dev->config; 306 307 conf[PCI_PRIMARY_BUS] = 0; 308 conf[PCI_SECONDARY_BUS] = 0; 309 conf[PCI_SUBORDINATE_BUS] = 0; 310 conf[PCI_SEC_LATENCY_TIMER] = 0; 311 312 /* 313 * the default values for base/limit registers aren't specified 314 * in the PCI-to-PCI-bridge spec. So we don't thouch them here. 315 * Each implementation can override it. 316 * typical implementation does 317 * zero base/limit registers or 318 * disable forwarding: pci_bridge_disable_base_limit() 319 * If disable forwarding is wanted, call pci_bridge_disable_base_limit() 320 * after this function. 321 */ 322 pci_byte_test_and_clear_mask(conf + PCI_IO_BASE, 323 PCI_IO_RANGE_MASK & 0xff); 324 pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT, 325 PCI_IO_RANGE_MASK & 0xff); 326 pci_word_test_and_clear_mask(conf + PCI_MEMORY_BASE, 327 PCI_MEMORY_RANGE_MASK & 0xffff); 328 pci_word_test_and_clear_mask(conf + PCI_MEMORY_LIMIT, 329 PCI_MEMORY_RANGE_MASK & 0xffff); 330 pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_BASE, 331 PCI_PREF_RANGE_MASK & 0xffff); 332 pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_LIMIT, 333 PCI_PREF_RANGE_MASK & 0xffff); 334 pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0); 335 pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0); 336 337 pci_set_word(conf + PCI_BRIDGE_CONTROL, 0); 338 } 339 340 /* default qdev initialization function for PCI-to-PCI bridge */ 341 void pci_bridge_initfn(PCIDevice *dev, const char *typename) 342 { 343 PCIBus *parent = pci_get_bus(dev); 344 PCIBridge *br = PCI_BRIDGE(dev); 345 PCIBus *sec_bus = &br->sec_bus; 346 347 pci_word_test_and_set_mask(dev->config + PCI_STATUS, 348 PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK); 349 350 /* 351 * TODO: We implement VGA Enable in the Bridge Control Register 352 * therefore per the PCI to PCI bridge spec we must also implement 353 * VGA Palette Snooping. When done, set this bit writable: 354 * 355 * pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, 356 * PCI_COMMAND_VGA_PALETTE); 357 */ 358 359 pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_PCI); 360 dev->config[PCI_HEADER_TYPE] = 361 (dev->config[PCI_HEADER_TYPE] & PCI_HEADER_TYPE_MULTI_FUNCTION) | 362 PCI_HEADER_TYPE_BRIDGE; 363 pci_set_word(dev->config + PCI_SEC_STATUS, 364 PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK); 365 366 /* 367 * If we don't specify the name, the bus will be addressed as <id>.0, where 368 * id is the device id. 369 * Since PCI Bridge devices have a single bus each, we don't need the index: 370 * let users address the bus using the device name. 371 */ 372 if (!br->bus_name && dev->qdev.id && *dev->qdev.id) { 373 br->bus_name = dev->qdev.id; 374 } 375 376 qbus_create_inplace(sec_bus, sizeof(br->sec_bus), typename, DEVICE(dev), 377 br->bus_name); 378 sec_bus->parent_dev = dev; 379 sec_bus->map_irq = br->map_irq ? br->map_irq : pci_swizzle_map_irq_fn; 380 sec_bus->address_space_mem = &br->address_space_mem; 381 memory_region_init(&br->address_space_mem, OBJECT(br), "pci_bridge_pci", UINT64_MAX); 382 sec_bus->address_space_io = &br->address_space_io; 383 memory_region_init(&br->address_space_io, OBJECT(br), "pci_bridge_io", 384 UINT32_MAX); 385 br->windows = pci_bridge_region_init(br); 386 QLIST_INIT(&sec_bus->child); 387 QLIST_INSERT_HEAD(&parent->child, sec_bus, sibling); 388 } 389 390 /* default qdev clean up function for PCI-to-PCI bridge */ 391 void pci_bridge_exitfn(PCIDevice *pci_dev) 392 { 393 PCIBridge *s = PCI_BRIDGE(pci_dev); 394 assert(QLIST_EMPTY(&s->sec_bus.child)); 395 QLIST_REMOVE(&s->sec_bus, sibling); 396 pci_bridge_region_del(s, s->windows); 397 pci_bridge_region_cleanup(s, s->windows); 398 /* object_unparent() is called automatically during device deletion */ 399 } 400 401 /* 402 * before qdev initialization(qdev_init()), this function sets bus_name and 403 * map_irq callback which are necessary for pci_bridge_initfn() to 404 * initialize bus. 405 */ 406 void pci_bridge_map_irq(PCIBridge *br, const char* bus_name, 407 pci_map_irq_fn map_irq) 408 { 409 br->map_irq = map_irq; 410 br->bus_name = bus_name; 411 } 412 413 414 int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset, 415 PCIResReserve res_reserve, Error **errp) 416 { 417 if (res_reserve.mem_pref_32 != (uint64_t)-1 && 418 res_reserve.mem_pref_64 != (uint64_t)-1) { 419 error_setg(errp, 420 "PCI resource reserve cap: PREF32 and PREF64 conflict"); 421 return -EINVAL; 422 } 423 424 if (res_reserve.mem_non_pref != (uint64_t)-1 && 425 res_reserve.mem_non_pref >= (1ULL << 32)) { 426 error_setg(errp, 427 "PCI resource reserve cap: mem-reserve must be less than 4G"); 428 return -EINVAL; 429 } 430 431 if (res_reserve.mem_pref_32 != (uint64_t)-1 && 432 res_reserve.mem_pref_32 >= (1ULL << 32)) { 433 error_setg(errp, 434 "PCI resource reserve cap: pref32-reserve must be less than 4G"); 435 return -EINVAL; 436 } 437 438 if (res_reserve.bus == (uint32_t)-1 && 439 res_reserve.io == (uint64_t)-1 && 440 res_reserve.mem_non_pref == (uint64_t)-1 && 441 res_reserve.mem_pref_32 == (uint64_t)-1 && 442 res_reserve.mem_pref_64 == (uint64_t)-1) { 443 return 0; 444 } 445 446 size_t cap_len = sizeof(PCIBridgeQemuCap); 447 PCIBridgeQemuCap cap = { 448 .len = cap_len, 449 .type = REDHAT_PCI_CAP_RESOURCE_RESERVE, 450 .bus_res = res_reserve.bus, 451 .io = res_reserve.io, 452 .mem = res_reserve.mem_non_pref, 453 .mem_pref_32 = res_reserve.mem_pref_32, 454 .mem_pref_64 = res_reserve.mem_pref_64 455 }; 456 457 int offset = pci_add_capability(dev, PCI_CAP_ID_VNDR, 458 cap_offset, cap_len, errp); 459 if (offset < 0) { 460 return offset; 461 } 462 463 memcpy(dev->config + offset + PCI_CAP_FLAGS, 464 (char *)&cap + PCI_CAP_FLAGS, 465 cap_len - PCI_CAP_FLAGS); 466 return 0; 467 } 468 469 static const TypeInfo pci_bridge_type_info = { 470 .name = TYPE_PCI_BRIDGE, 471 .parent = TYPE_PCI_DEVICE, 472 .instance_size = sizeof(PCIBridge), 473 .abstract = true, 474 }; 475 476 static void pci_bridge_register_types(void) 477 { 478 type_register_static(&pci_bridge_type_info); 479 } 480 481 type_init(pci_bridge_register_types) 482