1 /* 2 * QEMU PCI bus manager 3 * 4 * Copyright (c) 2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to dea 8 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM 22 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 /* 27 * split out from pci.c 28 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp> 29 * VA Linux Systems Japan K.K. 30 */ 31 32 #include "qemu/osdep.h" 33 #include "qemu/units.h" 34 #include "hw/pci/pci_bridge.h" 35 #include "hw/pci/pci_bus.h" 36 #include "qemu/module.h" 37 #include "qemu/range.h" 38 #include "qapi/error.h" 39 #include "hw/acpi/acpi_aml_interface.h" 40 #include "hw/acpi/pci.h" 41 #include "hw/qdev-properties.h" 42 43 /* PCI bridge subsystem vendor ID helper functions */ 44 #define PCI_SSVID_SIZEOF 8 45 #define PCI_SSVID_SVID 4 46 #define PCI_SSVID_SSID 6 47 48 int pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset, 49 uint16_t svid, uint16_t ssid, 50 Error **errp) 51 { 52 int pos; 53 54 pos = pci_add_capability(dev, PCI_CAP_ID_SSVID, offset, 55 PCI_SSVID_SIZEOF, errp); 56 if (pos < 0) { 57 return pos; 58 } 59 60 pci_set_word(dev->config + pos + PCI_SSVID_SVID, svid); 61 pci_set_word(dev->config + pos + PCI_SSVID_SSID, ssid); 62 return pos; 63 } 64 65 /* Accessor function to get parent bridge device from pci bus. */ 66 PCIDevice *pci_bridge_get_device(PCIBus *bus) 67 { 68 return bus->parent_dev; 69 } 70 71 /* Accessor function to get secondary bus from pci-to-pci bridge device */ 72 PCIBus *pci_bridge_get_sec_bus(PCIBridge *br) 73 { 74 return &br->sec_bus; 75 } 76 77 static uint32_t pci_config_get_io_base(const PCIDevice *d, 78 uint32_t base, uint32_t base_upper16) 79 { 80 uint32_t val; 81 82 val = ((uint32_t)d->config[base] & PCI_IO_RANGE_MASK) << 8; 83 if (d->config[base] & PCI_IO_RANGE_TYPE_32) { 84 val |= (uint32_t)pci_get_word(d->config + base_upper16) << 16; 85 } 86 return val; 87 } 88 89 static pcibus_t pci_config_get_memory_base(const PCIDevice *d, uint32_t base) 90 { 91 return ((pcibus_t)pci_get_word(d->config + base) & PCI_MEMORY_RANGE_MASK) 92 << 16; 93 } 94 95 static pcibus_t pci_config_get_pref_base(const PCIDevice *d, 96 uint32_t base, uint32_t upper) 97 { 98 pcibus_t tmp; 99 pcibus_t val; 100 101 tmp = (pcibus_t)pci_get_word(d->config + base); 102 val = (tmp & PCI_PREF_RANGE_MASK) << 16; 103 if (tmp & PCI_PREF_RANGE_TYPE_64) { 104 val |= (pcibus_t)pci_get_long(d->config + upper) << 32; 105 } 106 return val; 107 } 108 109 /* accessor function to get bridge filtering base address */ 110 pcibus_t pci_bridge_get_base(const PCIDevice *bridge, uint8_t type) 111 { 112 pcibus_t base; 113 if (type & PCI_BASE_ADDRESS_SPACE_IO) { 114 base = pci_config_get_io_base(bridge, 115 PCI_IO_BASE, PCI_IO_BASE_UPPER16); 116 } else { 117 if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) { 118 base = pci_config_get_pref_base( 119 bridge, PCI_PREF_MEMORY_BASE, PCI_PREF_BASE_UPPER32); 120 } else { 121 base = pci_config_get_memory_base(bridge, PCI_MEMORY_BASE); 122 } 123 } 124 125 return base; 126 } 127 128 /* accessor function to get bridge filtering limit */ 129 pcibus_t pci_bridge_get_limit(const PCIDevice *bridge, uint8_t type) 130 { 131 pcibus_t limit; 132 if (type & PCI_BASE_ADDRESS_SPACE_IO) { 133 limit = pci_config_get_io_base(bridge, 134 PCI_IO_LIMIT, PCI_IO_LIMIT_UPPER16); 135 limit |= 0xfff; /* PCI bridge spec 3.2.5.6. */ 136 } else { 137 if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) { 138 limit = pci_config_get_pref_base( 139 bridge, PCI_PREF_MEMORY_LIMIT, PCI_PREF_LIMIT_UPPER32); 140 } else { 141 limit = pci_config_get_memory_base(bridge, PCI_MEMORY_LIMIT); 142 } 143 limit |= 0xfffff; /* PCI bridge spec 3.2.5.{1, 8}. */ 144 } 145 return limit; 146 } 147 148 static void pci_bridge_init_alias(PCIBridge *bridge, MemoryRegion *alias, 149 uint8_t type, const char *name, 150 MemoryRegion *space, 151 MemoryRegion *parent_space, 152 bool enabled) 153 { 154 PCIDevice *bridge_dev = PCI_DEVICE(bridge); 155 pcibus_t base = pci_bridge_get_base(bridge_dev, type); 156 pcibus_t limit = pci_bridge_get_limit(bridge_dev, type); 157 /* TODO: this doesn't handle base = 0 limit = 2^64 - 1 correctly. 158 * Apparently no way to do this with existing memory APIs. */ 159 pcibus_t size = enabled && limit >= base ? limit + 1 - base : 0; 160 161 memory_region_init_alias(alias, OBJECT(bridge), name, space, base, size); 162 memory_region_add_subregion_overlap(parent_space, base, alias, 1); 163 } 164 165 static void pci_bridge_init_vga_aliases(PCIBridge *br, PCIBus *parent, 166 MemoryRegion *alias_vga) 167 { 168 PCIDevice *pd = PCI_DEVICE(br); 169 uint16_t brctl = pci_get_word(pd->config + PCI_BRIDGE_CONTROL); 170 171 memory_region_init_alias(&alias_vga[QEMU_PCI_VGA_IO_LO], OBJECT(br), 172 "pci_bridge_vga_io_lo", &br->address_space_io, 173 QEMU_PCI_VGA_IO_LO_BASE, QEMU_PCI_VGA_IO_LO_SIZE); 174 memory_region_init_alias(&alias_vga[QEMU_PCI_VGA_IO_HI], OBJECT(br), 175 "pci_bridge_vga_io_hi", &br->address_space_io, 176 QEMU_PCI_VGA_IO_HI_BASE, QEMU_PCI_VGA_IO_HI_SIZE); 177 memory_region_init_alias(&alias_vga[QEMU_PCI_VGA_MEM], OBJECT(br), 178 "pci_bridge_vga_mem", &br->address_space_mem, 179 QEMU_PCI_VGA_MEM_BASE, QEMU_PCI_VGA_MEM_SIZE); 180 181 if (brctl & PCI_BRIDGE_CTL_VGA) { 182 pci_register_vga(pd, &alias_vga[QEMU_PCI_VGA_MEM], 183 &alias_vga[QEMU_PCI_VGA_IO_LO], 184 &alias_vga[QEMU_PCI_VGA_IO_HI]); 185 } 186 } 187 188 static void pci_bridge_region_init(PCIBridge *br) 189 { 190 PCIDevice *pd = PCI_DEVICE(br); 191 PCIBus *parent = pci_get_bus(pd); 192 PCIBridgeWindows *w = &br->windows; 193 uint16_t cmd = pci_get_word(pd->config + PCI_COMMAND); 194 195 pci_bridge_init_alias(br, &w->alias_pref_mem, 196 PCI_BASE_ADDRESS_MEM_PREFETCH, 197 "pci_bridge_pref_mem", 198 &br->address_space_mem, 199 parent->address_space_mem, 200 cmd & PCI_COMMAND_MEMORY); 201 pci_bridge_init_alias(br, &w->alias_mem, 202 PCI_BASE_ADDRESS_SPACE_MEMORY, 203 "pci_bridge_mem", 204 &br->address_space_mem, 205 parent->address_space_mem, 206 cmd & PCI_COMMAND_MEMORY); 207 pci_bridge_init_alias(br, &w->alias_io, 208 PCI_BASE_ADDRESS_SPACE_IO, 209 "pci_bridge_io", 210 &br->address_space_io, 211 parent->address_space_io, 212 cmd & PCI_COMMAND_IO); 213 214 pci_bridge_init_vga_aliases(br, parent, w->alias_vga); 215 } 216 217 static void pci_bridge_region_del(PCIBridge *br, PCIBridgeWindows *w) 218 { 219 PCIDevice *pd = PCI_DEVICE(br); 220 PCIBus *parent = pci_get_bus(pd); 221 222 memory_region_del_subregion(parent->address_space_io, &w->alias_io); 223 memory_region_del_subregion(parent->address_space_mem, &w->alias_mem); 224 memory_region_del_subregion(parent->address_space_mem, &w->alias_pref_mem); 225 pci_unregister_vga(pd); 226 } 227 228 static void pci_bridge_region_cleanup(PCIBridge *br, PCIBridgeWindows *w) 229 { 230 object_unparent(OBJECT(&w->alias_io)); 231 object_unparent(OBJECT(&w->alias_mem)); 232 object_unparent(OBJECT(&w->alias_pref_mem)); 233 object_unparent(OBJECT(&w->alias_vga[QEMU_PCI_VGA_IO_LO])); 234 object_unparent(OBJECT(&w->alias_vga[QEMU_PCI_VGA_IO_HI])); 235 object_unparent(OBJECT(&w->alias_vga[QEMU_PCI_VGA_MEM])); 236 } 237 238 void pci_bridge_update_mappings(PCIBridge *br) 239 { 240 PCIBridgeWindows *w = &br->windows; 241 242 /* Make updates atomic to: handle the case of one VCPU updating the bridge 243 * while another accesses an unaffected region. */ 244 memory_region_transaction_begin(); 245 pci_bridge_region_del(br, w); 246 pci_bridge_region_cleanup(br, w); 247 pci_bridge_region_init(br); 248 memory_region_transaction_commit(); 249 } 250 251 /* default write_config function for PCI-to-PCI bridge */ 252 void pci_bridge_write_config(PCIDevice *d, 253 uint32_t address, uint32_t val, int len) 254 { 255 PCIBridge *s = PCI_BRIDGE(d); 256 uint16_t oldctl = pci_get_word(d->config + PCI_BRIDGE_CONTROL); 257 uint16_t newctl; 258 259 pci_default_write_config(d, address, val, len); 260 261 if (ranges_overlap(address, len, PCI_COMMAND, 2) || 262 263 /* io base/limit */ 264 ranges_overlap(address, len, PCI_IO_BASE, 2) || 265 266 /* memory base/limit, prefetchable base/limit and 267 io base/limit upper 16 */ 268 ranges_overlap(address, len, PCI_MEMORY_BASE, 20) || 269 270 /* vga enable */ 271 ranges_overlap(address, len, PCI_BRIDGE_CONTROL, 2)) { 272 pci_bridge_update_mappings(s); 273 } 274 275 newctl = pci_get_word(d->config + PCI_BRIDGE_CONTROL); 276 if (~oldctl & newctl & PCI_BRIDGE_CTL_BUS_RESET) { 277 /* Trigger hot reset on 0->1 transition. */ 278 bus_cold_reset(BUS(&s->sec_bus)); 279 } 280 } 281 282 void pci_bridge_disable_base_limit(PCIDevice *dev) 283 { 284 uint8_t *conf = dev->config; 285 286 pci_byte_test_and_set_mask(conf + PCI_IO_BASE, 287 PCI_IO_RANGE_MASK & 0xff); 288 pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT, 289 PCI_IO_RANGE_MASK & 0xff); 290 pci_word_test_and_set_mask(conf + PCI_MEMORY_BASE, 291 PCI_MEMORY_RANGE_MASK & 0xffff); 292 pci_word_test_and_clear_mask(conf + PCI_MEMORY_LIMIT, 293 PCI_MEMORY_RANGE_MASK & 0xffff); 294 pci_word_test_and_set_mask(conf + PCI_PREF_MEMORY_BASE, 295 PCI_PREF_RANGE_MASK & 0xffff); 296 pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_LIMIT, 297 PCI_PREF_RANGE_MASK & 0xffff); 298 pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0); 299 pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0); 300 } 301 302 /* reset bridge specific configuration registers */ 303 void pci_bridge_reset(DeviceState *qdev) 304 { 305 PCIDevice *dev = PCI_DEVICE(qdev); 306 uint8_t *conf = dev->config; 307 308 conf[PCI_PRIMARY_BUS] = 0; 309 conf[PCI_SECONDARY_BUS] = 0; 310 conf[PCI_SUBORDINATE_BUS] = 0; 311 conf[PCI_SEC_LATENCY_TIMER] = 0; 312 313 /* 314 * the default values for base/limit registers aren't specified 315 * in the PCI-to-PCI-bridge spec. So we don't touch them here. 316 * Each implementation can override it. 317 * typical implementation does 318 * zero base/limit registers or 319 * disable forwarding: pci_bridge_disable_base_limit() 320 * If disable forwarding is wanted, call pci_bridge_disable_base_limit() 321 * after this function. 322 */ 323 pci_byte_test_and_clear_mask(conf + PCI_IO_BASE, 324 PCI_IO_RANGE_MASK & 0xff); 325 pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT, 326 PCI_IO_RANGE_MASK & 0xff); 327 pci_word_test_and_clear_mask(conf + PCI_MEMORY_BASE, 328 PCI_MEMORY_RANGE_MASK & 0xffff); 329 pci_word_test_and_clear_mask(conf + PCI_MEMORY_LIMIT, 330 PCI_MEMORY_RANGE_MASK & 0xffff); 331 pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_BASE, 332 PCI_PREF_RANGE_MASK & 0xffff); 333 pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_LIMIT, 334 PCI_PREF_RANGE_MASK & 0xffff); 335 pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0); 336 pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0); 337 338 pci_set_word(conf + PCI_BRIDGE_CONTROL, 0); 339 } 340 341 /* default qdev initialization function for PCI-to-PCI bridge */ 342 void pci_bridge_initfn(PCIDevice *dev, const char *typename) 343 { 344 PCIBus *parent = pci_get_bus(dev); 345 PCIBridge *br = PCI_BRIDGE(dev); 346 PCIBus *sec_bus = &br->sec_bus; 347 348 pci_word_test_and_set_mask(dev->config + PCI_STATUS, 349 PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK); 350 351 /* 352 * TODO: We implement VGA Enable in the Bridge Control Register 353 * therefore per the PCI to PCI bridge spec we must also implement 354 * VGA Palette Snooping. When done, set this bit writable: 355 * 356 * pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, 357 * PCI_COMMAND_VGA_PALETTE); 358 */ 359 360 pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_PCI); 361 dev->config[PCI_HEADER_TYPE] = 362 (dev->config[PCI_HEADER_TYPE] & PCI_HEADER_TYPE_MULTI_FUNCTION) | 363 PCI_HEADER_TYPE_BRIDGE; 364 pci_set_word(dev->config + PCI_SEC_STATUS, 365 PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK); 366 367 /* 368 * If we don't specify the name, the bus will be addressed as <id>.0, where 369 * id is the device id. 370 * Since PCI Bridge devices have a single bus each, we don't need the index: 371 * let users address the bus using the device name. 372 */ 373 if (!br->bus_name && dev->qdev.id && *dev->qdev.id) { 374 br->bus_name = dev->qdev.id; 375 } 376 377 qbus_init(sec_bus, sizeof(br->sec_bus), typename, DEVICE(dev), 378 br->bus_name); 379 sec_bus->parent_dev = dev; 380 sec_bus->map_irq = br->map_irq ? br->map_irq : pci_swizzle_map_irq_fn; 381 sec_bus->address_space_mem = &br->address_space_mem; 382 memory_region_init(&br->address_space_mem, OBJECT(br), "pci_bridge_pci", UINT64_MAX); 383 sec_bus->address_space_io = &br->address_space_io; 384 memory_region_init(&br->address_space_io, OBJECT(br), "pci_bridge_io", 385 4 * GiB); 386 pci_bridge_region_init(br); 387 QLIST_INIT(&sec_bus->child); 388 QLIST_INSERT_HEAD(&parent->child, sec_bus, sibling); 389 390 /* For express secondary buses, secondary latency timer is RO 0 */ 391 if (pci_bus_is_express(sec_bus) && !br->pcie_writeable_slt_bug) { 392 dev->wmask[PCI_SEC_LATENCY_TIMER] = 0; 393 } 394 } 395 396 /* default qdev clean up function for PCI-to-PCI bridge */ 397 void pci_bridge_exitfn(PCIDevice *pci_dev) 398 { 399 PCIBridge *s = PCI_BRIDGE(pci_dev); 400 assert(QLIST_EMPTY(&s->sec_bus.child)); 401 QLIST_REMOVE(&s->sec_bus, sibling); 402 pci_bridge_region_del(s, &s->windows); 403 pci_bridge_region_cleanup(s, &s->windows); 404 /* object_unparent() is called automatically during device deletion */ 405 } 406 407 /* 408 * before qdev initialization(qdev_init()), this function sets bus_name and 409 * map_irq callback which are necessary for pci_bridge_initfn() to 410 * initialize bus. 411 */ 412 void pci_bridge_map_irq(PCIBridge *br, const char* bus_name, 413 pci_map_irq_fn map_irq) 414 { 415 br->map_irq = map_irq; 416 br->bus_name = bus_name; 417 } 418 419 420 int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset, 421 PCIResReserve res_reserve, Error **errp) 422 { 423 if (res_reserve.mem_pref_32 != (uint64_t)-1 && 424 res_reserve.mem_pref_64 != (uint64_t)-1) { 425 error_setg(errp, 426 "PCI resource reserve cap: PREF32 and PREF64 conflict"); 427 return -EINVAL; 428 } 429 430 if (res_reserve.mem_non_pref != (uint64_t)-1 && 431 res_reserve.mem_non_pref >= 4 * GiB) { 432 error_setg(errp, 433 "PCI resource reserve cap: mem-reserve must be less than 4G"); 434 return -EINVAL; 435 } 436 437 if (res_reserve.mem_pref_32 != (uint64_t)-1 && 438 res_reserve.mem_pref_32 >= 4 * GiB) { 439 error_setg(errp, 440 "PCI resource reserve cap: pref32-reserve must be less than 4G"); 441 return -EINVAL; 442 } 443 444 if (res_reserve.bus == (uint32_t)-1 && 445 res_reserve.io == (uint64_t)-1 && 446 res_reserve.mem_non_pref == (uint64_t)-1 && 447 res_reserve.mem_pref_32 == (uint64_t)-1 && 448 res_reserve.mem_pref_64 == (uint64_t)-1) { 449 return 0; 450 } 451 452 size_t cap_len = sizeof(PCIBridgeQemuCap); 453 PCIBridgeQemuCap cap = { 454 .len = cap_len, 455 .type = REDHAT_PCI_CAP_RESOURCE_RESERVE, 456 .bus_res = cpu_to_le32(res_reserve.bus), 457 .io = cpu_to_le64(res_reserve.io), 458 .mem = cpu_to_le32(res_reserve.mem_non_pref), 459 .mem_pref_32 = cpu_to_le32(res_reserve.mem_pref_32), 460 .mem_pref_64 = cpu_to_le64(res_reserve.mem_pref_64) 461 }; 462 463 int offset = pci_add_capability(dev, PCI_CAP_ID_VNDR, 464 cap_offset, cap_len, errp); 465 if (offset < 0) { 466 return offset; 467 } 468 469 memcpy(dev->config + offset + PCI_CAP_FLAGS, 470 (char *)&cap + PCI_CAP_FLAGS, 471 cap_len - PCI_CAP_FLAGS); 472 return 0; 473 } 474 475 static Property pci_bridge_properties[] = { 476 DEFINE_PROP_BOOL("x-pci-express-writeable-slt-bug", PCIBridge, 477 pcie_writeable_slt_bug, false), 478 DEFINE_PROP_END_OF_LIST(), 479 }; 480 481 static void pci_bridge_class_init(ObjectClass *klass, void *data) 482 { 483 AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass); 484 DeviceClass *k = DEVICE_CLASS(klass); 485 486 device_class_set_props(k, pci_bridge_properties); 487 adevc->build_dev_aml = build_pci_bridge_aml; 488 } 489 490 static const TypeInfo pci_bridge_type_info = { 491 .name = TYPE_PCI_BRIDGE, 492 .parent = TYPE_PCI_DEVICE, 493 .instance_size = sizeof(PCIBridge), 494 .class_init = pci_bridge_class_init, 495 .abstract = true, 496 .interfaces = (InterfaceInfo[]) { 497 { TYPE_ACPI_DEV_AML_IF }, 498 { }, 499 }, 500 }; 501 502 static void pci_bridge_register_types(void) 503 { 504 type_register_static(&pci_bridge_type_info); 505 } 506 507 type_init(pci_bridge_register_types) 508