1 /* 2 * QEMU PCI bus manager 3 * 4 * Copyright (c) 2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to dea 8 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM 22 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 /* 27 * split out from pci.c 28 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp> 29 * VA Linux Systems Japan K.K. 30 */ 31 32 #include "hw/pci/pci_bridge.h" 33 #include "hw/pci/pci_bus.h" 34 #include "qemu/range.h" 35 36 /* PCI bridge subsystem vendor ID helper functions */ 37 #define PCI_SSVID_SIZEOF 8 38 #define PCI_SSVID_SVID 4 39 #define PCI_SSVID_SSID 6 40 41 int pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset, 42 uint16_t svid, uint16_t ssid) 43 { 44 int pos; 45 pos = pci_add_capability(dev, PCI_CAP_ID_SSVID, offset, PCI_SSVID_SIZEOF); 46 if (pos < 0) { 47 return pos; 48 } 49 50 pci_set_word(dev->config + pos + PCI_SSVID_SVID, svid); 51 pci_set_word(dev->config + pos + PCI_SSVID_SSID, ssid); 52 return pos; 53 } 54 55 /* Accessor function to get parent bridge device from pci bus. */ 56 PCIDevice *pci_bridge_get_device(PCIBus *bus) 57 { 58 return bus->parent_dev; 59 } 60 61 /* Accessor function to get secondary bus from pci-to-pci bridge device */ 62 PCIBus *pci_bridge_get_sec_bus(PCIBridge *br) 63 { 64 return &br->sec_bus; 65 } 66 67 static uint32_t pci_config_get_io_base(const PCIDevice *d, 68 uint32_t base, uint32_t base_upper16) 69 { 70 uint32_t val; 71 72 val = ((uint32_t)d->config[base] & PCI_IO_RANGE_MASK) << 8; 73 if (d->config[base] & PCI_IO_RANGE_TYPE_32) { 74 val |= (uint32_t)pci_get_word(d->config + base_upper16) << 16; 75 } 76 return val; 77 } 78 79 static pcibus_t pci_config_get_memory_base(const PCIDevice *d, uint32_t base) 80 { 81 return ((pcibus_t)pci_get_word(d->config + base) & PCI_MEMORY_RANGE_MASK) 82 << 16; 83 } 84 85 static pcibus_t pci_config_get_pref_base(const PCIDevice *d, 86 uint32_t base, uint32_t upper) 87 { 88 pcibus_t tmp; 89 pcibus_t val; 90 91 tmp = (pcibus_t)pci_get_word(d->config + base); 92 val = (tmp & PCI_PREF_RANGE_MASK) << 16; 93 if (tmp & PCI_PREF_RANGE_TYPE_64) { 94 val |= (pcibus_t)pci_get_long(d->config + upper) << 32; 95 } 96 return val; 97 } 98 99 /* accessor function to get bridge filtering base address */ 100 pcibus_t pci_bridge_get_base(const PCIDevice *bridge, uint8_t type) 101 { 102 pcibus_t base; 103 if (type & PCI_BASE_ADDRESS_SPACE_IO) { 104 base = pci_config_get_io_base(bridge, 105 PCI_IO_BASE, PCI_IO_BASE_UPPER16); 106 } else { 107 if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) { 108 base = pci_config_get_pref_base( 109 bridge, PCI_PREF_MEMORY_BASE, PCI_PREF_BASE_UPPER32); 110 } else { 111 base = pci_config_get_memory_base(bridge, PCI_MEMORY_BASE); 112 } 113 } 114 115 return base; 116 } 117 118 /* accessor funciton to get bridge filtering limit */ 119 pcibus_t pci_bridge_get_limit(const PCIDevice *bridge, uint8_t type) 120 { 121 pcibus_t limit; 122 if (type & PCI_BASE_ADDRESS_SPACE_IO) { 123 limit = pci_config_get_io_base(bridge, 124 PCI_IO_LIMIT, PCI_IO_LIMIT_UPPER16); 125 limit |= 0xfff; /* PCI bridge spec 3.2.5.6. */ 126 } else { 127 if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) { 128 limit = pci_config_get_pref_base( 129 bridge, PCI_PREF_MEMORY_LIMIT, PCI_PREF_LIMIT_UPPER32); 130 } else { 131 limit = pci_config_get_memory_base(bridge, PCI_MEMORY_LIMIT); 132 } 133 limit |= 0xfffff; /* PCI bridge spec 3.2.5.{1, 8}. */ 134 } 135 return limit; 136 } 137 138 static void pci_bridge_init_alias(PCIBridge *bridge, MemoryRegion *alias, 139 uint8_t type, const char *name, 140 MemoryRegion *space, 141 MemoryRegion *parent_space, 142 bool enabled) 143 { 144 pcibus_t base = pci_bridge_get_base(&bridge->dev, type); 145 pcibus_t limit = pci_bridge_get_limit(&bridge->dev, type); 146 /* TODO: this doesn't handle base = 0 limit = 2^64 - 1 correctly. 147 * Apparently no way to do this with existing memory APIs. */ 148 pcibus_t size = enabled && limit >= base ? limit + 1 - base : 0; 149 150 memory_region_init_alias(alias, name, space, base, size); 151 memory_region_add_subregion_overlap(parent_space, base, alias, 1); 152 } 153 154 static PCIBridgeWindows *pci_bridge_region_init(PCIBridge *br) 155 { 156 PCIBus *parent = br->dev.bus; 157 PCIBridgeWindows *w = g_new(PCIBridgeWindows, 1); 158 uint16_t cmd = pci_get_word(br->dev.config + PCI_COMMAND); 159 160 pci_bridge_init_alias(br, &w->alias_pref_mem, 161 PCI_BASE_ADDRESS_MEM_PREFETCH, 162 "pci_bridge_pref_mem", 163 &br->address_space_mem, 164 parent->address_space_mem, 165 cmd & PCI_COMMAND_MEMORY); 166 pci_bridge_init_alias(br, &w->alias_mem, 167 PCI_BASE_ADDRESS_SPACE_MEMORY, 168 "pci_bridge_mem", 169 &br->address_space_mem, 170 parent->address_space_mem, 171 cmd & PCI_COMMAND_MEMORY); 172 pci_bridge_init_alias(br, &w->alias_io, 173 PCI_BASE_ADDRESS_SPACE_IO, 174 "pci_bridge_io", 175 &br->address_space_io, 176 parent->address_space_io, 177 cmd & PCI_COMMAND_IO); 178 /* TODO: optinal VGA and VGA palette snooping support. */ 179 180 return w; 181 } 182 183 static void pci_bridge_region_del(PCIBridge *br, PCIBridgeWindows *w) 184 { 185 PCIBus *parent = br->dev.bus; 186 187 memory_region_del_subregion(parent->address_space_io, &w->alias_io); 188 memory_region_del_subregion(parent->address_space_mem, &w->alias_mem); 189 memory_region_del_subregion(parent->address_space_mem, &w->alias_pref_mem); 190 } 191 192 static void pci_bridge_region_cleanup(PCIBridge *br, PCIBridgeWindows *w) 193 { 194 memory_region_destroy(&w->alias_io); 195 memory_region_destroy(&w->alias_mem); 196 memory_region_destroy(&w->alias_pref_mem); 197 g_free(w); 198 } 199 200 static void pci_bridge_update_mappings(PCIBridge *br) 201 { 202 PCIBridgeWindows *w = br->windows; 203 204 /* Make updates atomic to: handle the case of one VCPU updating the bridge 205 * while another accesses an unaffected region. */ 206 memory_region_transaction_begin(); 207 pci_bridge_region_del(br, br->windows); 208 br->windows = pci_bridge_region_init(br); 209 memory_region_transaction_commit(); 210 pci_bridge_region_cleanup(br, w); 211 } 212 213 /* default write_config function for PCI-to-PCI bridge */ 214 void pci_bridge_write_config(PCIDevice *d, 215 uint32_t address, uint32_t val, int len) 216 { 217 PCIBridge *s = container_of(d, PCIBridge, dev); 218 uint16_t oldctl = pci_get_word(d->config + PCI_BRIDGE_CONTROL); 219 uint16_t newctl; 220 221 pci_default_write_config(d, address, val, len); 222 223 if (ranges_overlap(address, len, PCI_COMMAND, 2) || 224 225 /* io base/limit */ 226 ranges_overlap(address, len, PCI_IO_BASE, 2) || 227 228 /* memory base/limit, prefetchable base/limit and 229 io base/limit upper 16 */ 230 ranges_overlap(address, len, PCI_MEMORY_BASE, 20)) { 231 pci_bridge_update_mappings(s); 232 } 233 234 newctl = pci_get_word(d->config + PCI_BRIDGE_CONTROL); 235 if (~oldctl & newctl & PCI_BRIDGE_CTL_BUS_RESET) { 236 /* Trigger hot reset on 0->1 transition. */ 237 pci_bus_reset(&s->sec_bus); 238 } 239 } 240 241 void pci_bridge_disable_base_limit(PCIDevice *dev) 242 { 243 uint8_t *conf = dev->config; 244 245 pci_byte_test_and_set_mask(conf + PCI_IO_BASE, 246 PCI_IO_RANGE_MASK & 0xff); 247 pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT, 248 PCI_IO_RANGE_MASK & 0xff); 249 pci_word_test_and_set_mask(conf + PCI_MEMORY_BASE, 250 PCI_MEMORY_RANGE_MASK & 0xffff); 251 pci_word_test_and_clear_mask(conf + PCI_MEMORY_LIMIT, 252 PCI_MEMORY_RANGE_MASK & 0xffff); 253 pci_word_test_and_set_mask(conf + PCI_PREF_MEMORY_BASE, 254 PCI_PREF_RANGE_MASK & 0xffff); 255 pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_LIMIT, 256 PCI_PREF_RANGE_MASK & 0xffff); 257 pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0); 258 pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0); 259 } 260 261 /* reset bridge specific configuration registers */ 262 void pci_bridge_reset(DeviceState *qdev) 263 { 264 PCIDevice *dev = PCI_DEVICE(qdev); 265 uint8_t *conf = dev->config; 266 267 conf[PCI_PRIMARY_BUS] = 0; 268 conf[PCI_SECONDARY_BUS] = 0; 269 conf[PCI_SUBORDINATE_BUS] = 0; 270 conf[PCI_SEC_LATENCY_TIMER] = 0; 271 272 /* 273 * the default values for base/limit registers aren't specified 274 * in the PCI-to-PCI-bridge spec. So we don't thouch them here. 275 * Each implementation can override it. 276 * typical implementation does 277 * zero base/limit registers or 278 * disable forwarding: pci_bridge_disable_base_limit() 279 * If disable forwarding is wanted, call pci_bridge_disable_base_limit() 280 * after this function. 281 */ 282 pci_byte_test_and_clear_mask(conf + PCI_IO_BASE, 283 PCI_IO_RANGE_MASK & 0xff); 284 pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT, 285 PCI_IO_RANGE_MASK & 0xff); 286 pci_word_test_and_clear_mask(conf + PCI_MEMORY_BASE, 287 PCI_MEMORY_RANGE_MASK & 0xffff); 288 pci_word_test_and_clear_mask(conf + PCI_MEMORY_LIMIT, 289 PCI_MEMORY_RANGE_MASK & 0xffff); 290 pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_BASE, 291 PCI_PREF_RANGE_MASK & 0xffff); 292 pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_LIMIT, 293 PCI_PREF_RANGE_MASK & 0xffff); 294 pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0); 295 pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0); 296 297 pci_set_word(conf + PCI_BRIDGE_CONTROL, 0); 298 } 299 300 /* default qdev initialization function for PCI-to-PCI bridge */ 301 int pci_bridge_initfn(PCIDevice *dev) 302 { 303 PCIBus *parent = dev->bus; 304 PCIBridge *br = DO_UPCAST(PCIBridge, dev, dev); 305 PCIBus *sec_bus = &br->sec_bus; 306 307 pci_word_test_and_set_mask(dev->config + PCI_STATUS, 308 PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK); 309 pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_PCI); 310 dev->config[PCI_HEADER_TYPE] = 311 (dev->config[PCI_HEADER_TYPE] & PCI_HEADER_TYPE_MULTI_FUNCTION) | 312 PCI_HEADER_TYPE_BRIDGE; 313 pci_set_word(dev->config + PCI_SEC_STATUS, 314 PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK); 315 316 /* 317 * If we don't specify the name, the bus will be addressed as <id>.0, where 318 * id is the device id. 319 * Since PCI Bridge devices have a single bus each, we don't need the index: 320 * let users address the bus using the device name. 321 */ 322 if (!br->bus_name && dev->qdev.id && *dev->qdev.id) { 323 br->bus_name = dev->qdev.id; 324 } 325 326 qbus_create_inplace(&sec_bus->qbus, TYPE_PCI_BUS, &dev->qdev, 327 br->bus_name); 328 sec_bus->parent_dev = dev; 329 sec_bus->map_irq = br->map_irq; 330 sec_bus->address_space_mem = &br->address_space_mem; 331 memory_region_init(&br->address_space_mem, "pci_bridge_pci", INT64_MAX); 332 sec_bus->address_space_io = &br->address_space_io; 333 memory_region_init(&br->address_space_io, "pci_bridge_io", 65536); 334 br->windows = pci_bridge_region_init(br); 335 QLIST_INIT(&sec_bus->child); 336 QLIST_INSERT_HEAD(&parent->child, sec_bus, sibling); 337 return 0; 338 } 339 340 /* default qdev clean up function for PCI-to-PCI bridge */ 341 void pci_bridge_exitfn(PCIDevice *pci_dev) 342 { 343 PCIBridge *s = DO_UPCAST(PCIBridge, dev, pci_dev); 344 assert(QLIST_EMPTY(&s->sec_bus.child)); 345 QLIST_REMOVE(&s->sec_bus, sibling); 346 pci_bridge_region_del(s, s->windows); 347 pci_bridge_region_cleanup(s, s->windows); 348 memory_region_destroy(&s->address_space_mem); 349 memory_region_destroy(&s->address_space_io); 350 /* qbus_free() is called automatically by qdev_free() */ 351 } 352 353 /* 354 * before qdev initialization(qdev_init()), this function sets bus_name and 355 * map_irq callback which are necessry for pci_bridge_initfn() to 356 * initialize bus. 357 */ 358 void pci_bridge_map_irq(PCIBridge *br, const char* bus_name, 359 pci_map_irq_fn map_irq) 360 { 361 br->map_irq = map_irq; 362 br->bus_name = bus_name; 363 } 364