1 /* 2 * QEMU PCI bus manager 3 * 4 * Copyright (c) 2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to dea 8 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM 22 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 /* 27 * split out from pci.c 28 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp> 29 * VA Linux Systems Japan K.K. 30 */ 31 32 #include "qemu/osdep.h" 33 #include "hw/pci/pci_bridge.h" 34 #include "hw/pci/pci_bus.h" 35 #include "qemu/range.h" 36 37 /* PCI bridge subsystem vendor ID helper functions */ 38 #define PCI_SSVID_SIZEOF 8 39 #define PCI_SSVID_SVID 4 40 #define PCI_SSVID_SSID 6 41 42 int pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset, 43 uint16_t svid, uint16_t ssid) 44 { 45 int pos; 46 pos = pci_add_capability(dev, PCI_CAP_ID_SSVID, offset, PCI_SSVID_SIZEOF); 47 if (pos < 0) { 48 return pos; 49 } 50 51 pci_set_word(dev->config + pos + PCI_SSVID_SVID, svid); 52 pci_set_word(dev->config + pos + PCI_SSVID_SSID, ssid); 53 return pos; 54 } 55 56 /* Accessor function to get parent bridge device from pci bus. */ 57 PCIDevice *pci_bridge_get_device(PCIBus *bus) 58 { 59 return bus->parent_dev; 60 } 61 62 /* Accessor function to get secondary bus from pci-to-pci bridge device */ 63 PCIBus *pci_bridge_get_sec_bus(PCIBridge *br) 64 { 65 return &br->sec_bus; 66 } 67 68 static uint32_t pci_config_get_io_base(const PCIDevice *d, 69 uint32_t base, uint32_t base_upper16) 70 { 71 uint32_t val; 72 73 val = ((uint32_t)d->config[base] & PCI_IO_RANGE_MASK) << 8; 74 if (d->config[base] & PCI_IO_RANGE_TYPE_32) { 75 val |= (uint32_t)pci_get_word(d->config + base_upper16) << 16; 76 } 77 return val; 78 } 79 80 static pcibus_t pci_config_get_memory_base(const PCIDevice *d, uint32_t base) 81 { 82 return ((pcibus_t)pci_get_word(d->config + base) & PCI_MEMORY_RANGE_MASK) 83 << 16; 84 } 85 86 static pcibus_t pci_config_get_pref_base(const PCIDevice *d, 87 uint32_t base, uint32_t upper) 88 { 89 pcibus_t tmp; 90 pcibus_t val; 91 92 tmp = (pcibus_t)pci_get_word(d->config + base); 93 val = (tmp & PCI_PREF_RANGE_MASK) << 16; 94 if (tmp & PCI_PREF_RANGE_TYPE_64) { 95 val |= (pcibus_t)pci_get_long(d->config + upper) << 32; 96 } 97 return val; 98 } 99 100 /* accessor function to get bridge filtering base address */ 101 pcibus_t pci_bridge_get_base(const PCIDevice *bridge, uint8_t type) 102 { 103 pcibus_t base; 104 if (type & PCI_BASE_ADDRESS_SPACE_IO) { 105 base = pci_config_get_io_base(bridge, 106 PCI_IO_BASE, PCI_IO_BASE_UPPER16); 107 } else { 108 if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) { 109 base = pci_config_get_pref_base( 110 bridge, PCI_PREF_MEMORY_BASE, PCI_PREF_BASE_UPPER32); 111 } else { 112 base = pci_config_get_memory_base(bridge, PCI_MEMORY_BASE); 113 } 114 } 115 116 return base; 117 } 118 119 /* accessor function to get bridge filtering limit */ 120 pcibus_t pci_bridge_get_limit(const PCIDevice *bridge, uint8_t type) 121 { 122 pcibus_t limit; 123 if (type & PCI_BASE_ADDRESS_SPACE_IO) { 124 limit = pci_config_get_io_base(bridge, 125 PCI_IO_LIMIT, PCI_IO_LIMIT_UPPER16); 126 limit |= 0xfff; /* PCI bridge spec 3.2.5.6. */ 127 } else { 128 if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) { 129 limit = pci_config_get_pref_base( 130 bridge, PCI_PREF_MEMORY_LIMIT, PCI_PREF_LIMIT_UPPER32); 131 } else { 132 limit = pci_config_get_memory_base(bridge, PCI_MEMORY_LIMIT); 133 } 134 limit |= 0xfffff; /* PCI bridge spec 3.2.5.{1, 8}. */ 135 } 136 return limit; 137 } 138 139 static void pci_bridge_init_alias(PCIBridge *bridge, MemoryRegion *alias, 140 uint8_t type, const char *name, 141 MemoryRegion *space, 142 MemoryRegion *parent_space, 143 bool enabled) 144 { 145 PCIDevice *bridge_dev = PCI_DEVICE(bridge); 146 pcibus_t base = pci_bridge_get_base(bridge_dev, type); 147 pcibus_t limit = pci_bridge_get_limit(bridge_dev, type); 148 /* TODO: this doesn't handle base = 0 limit = 2^64 - 1 correctly. 149 * Apparently no way to do this with existing memory APIs. */ 150 pcibus_t size = enabled && limit >= base ? limit + 1 - base : 0; 151 152 memory_region_init_alias(alias, OBJECT(bridge), name, space, base, size); 153 memory_region_add_subregion_overlap(parent_space, base, alias, 1); 154 } 155 156 static void pci_bridge_init_vga_aliases(PCIBridge *br, PCIBus *parent, 157 MemoryRegion *alias_vga) 158 { 159 PCIDevice *pd = PCI_DEVICE(br); 160 uint16_t brctl = pci_get_word(pd->config + PCI_BRIDGE_CONTROL); 161 162 memory_region_init_alias(&alias_vga[QEMU_PCI_VGA_IO_LO], OBJECT(br), 163 "pci_bridge_vga_io_lo", &br->address_space_io, 164 QEMU_PCI_VGA_IO_LO_BASE, QEMU_PCI_VGA_IO_LO_SIZE); 165 memory_region_init_alias(&alias_vga[QEMU_PCI_VGA_IO_HI], OBJECT(br), 166 "pci_bridge_vga_io_hi", &br->address_space_io, 167 QEMU_PCI_VGA_IO_HI_BASE, QEMU_PCI_VGA_IO_HI_SIZE); 168 memory_region_init_alias(&alias_vga[QEMU_PCI_VGA_MEM], OBJECT(br), 169 "pci_bridge_vga_mem", &br->address_space_mem, 170 QEMU_PCI_VGA_MEM_BASE, QEMU_PCI_VGA_MEM_SIZE); 171 172 if (brctl & PCI_BRIDGE_CTL_VGA) { 173 pci_register_vga(pd, &alias_vga[QEMU_PCI_VGA_MEM], 174 &alias_vga[QEMU_PCI_VGA_IO_LO], 175 &alias_vga[QEMU_PCI_VGA_IO_HI]); 176 } 177 } 178 179 static PCIBridgeWindows *pci_bridge_region_init(PCIBridge *br) 180 { 181 PCIDevice *pd = PCI_DEVICE(br); 182 PCIBus *parent = pd->bus; 183 PCIBridgeWindows *w = g_new(PCIBridgeWindows, 1); 184 uint16_t cmd = pci_get_word(pd->config + PCI_COMMAND); 185 186 pci_bridge_init_alias(br, &w->alias_pref_mem, 187 PCI_BASE_ADDRESS_MEM_PREFETCH, 188 "pci_bridge_pref_mem", 189 &br->address_space_mem, 190 parent->address_space_mem, 191 cmd & PCI_COMMAND_MEMORY); 192 pci_bridge_init_alias(br, &w->alias_mem, 193 PCI_BASE_ADDRESS_SPACE_MEMORY, 194 "pci_bridge_mem", 195 &br->address_space_mem, 196 parent->address_space_mem, 197 cmd & PCI_COMMAND_MEMORY); 198 pci_bridge_init_alias(br, &w->alias_io, 199 PCI_BASE_ADDRESS_SPACE_IO, 200 "pci_bridge_io", 201 &br->address_space_io, 202 parent->address_space_io, 203 cmd & PCI_COMMAND_IO); 204 205 pci_bridge_init_vga_aliases(br, parent, w->alias_vga); 206 207 return w; 208 } 209 210 static void pci_bridge_region_del(PCIBridge *br, PCIBridgeWindows *w) 211 { 212 PCIDevice *pd = PCI_DEVICE(br); 213 PCIBus *parent = pd->bus; 214 215 memory_region_del_subregion(parent->address_space_io, &w->alias_io); 216 memory_region_del_subregion(parent->address_space_mem, &w->alias_mem); 217 memory_region_del_subregion(parent->address_space_mem, &w->alias_pref_mem); 218 pci_unregister_vga(pd); 219 } 220 221 static void pci_bridge_region_cleanup(PCIBridge *br, PCIBridgeWindows *w) 222 { 223 object_unparent(OBJECT(&w->alias_io)); 224 object_unparent(OBJECT(&w->alias_mem)); 225 object_unparent(OBJECT(&w->alias_pref_mem)); 226 object_unparent(OBJECT(&w->alias_vga[QEMU_PCI_VGA_IO_LO])); 227 object_unparent(OBJECT(&w->alias_vga[QEMU_PCI_VGA_IO_HI])); 228 object_unparent(OBJECT(&w->alias_vga[QEMU_PCI_VGA_MEM])); 229 g_free(w); 230 } 231 232 void pci_bridge_update_mappings(PCIBridge *br) 233 { 234 PCIBridgeWindows *w = br->windows; 235 236 /* Make updates atomic to: handle the case of one VCPU updating the bridge 237 * while another accesses an unaffected region. */ 238 memory_region_transaction_begin(); 239 pci_bridge_region_del(br, br->windows); 240 br->windows = pci_bridge_region_init(br); 241 memory_region_transaction_commit(); 242 pci_bridge_region_cleanup(br, w); 243 } 244 245 /* default write_config function for PCI-to-PCI bridge */ 246 void pci_bridge_write_config(PCIDevice *d, 247 uint32_t address, uint32_t val, int len) 248 { 249 PCIBridge *s = PCI_BRIDGE(d); 250 uint16_t oldctl = pci_get_word(d->config + PCI_BRIDGE_CONTROL); 251 uint16_t newctl; 252 253 pci_default_write_config(d, address, val, len); 254 255 if (ranges_overlap(address, len, PCI_COMMAND, 2) || 256 257 /* io base/limit */ 258 ranges_overlap(address, len, PCI_IO_BASE, 2) || 259 260 /* memory base/limit, prefetchable base/limit and 261 io base/limit upper 16 */ 262 ranges_overlap(address, len, PCI_MEMORY_BASE, 20) || 263 264 /* vga enable */ 265 ranges_overlap(address, len, PCI_BRIDGE_CONTROL, 2)) { 266 pci_bridge_update_mappings(s); 267 } 268 269 newctl = pci_get_word(d->config + PCI_BRIDGE_CONTROL); 270 if (~oldctl & newctl & PCI_BRIDGE_CTL_BUS_RESET) { 271 /* Trigger hot reset on 0->1 transition. */ 272 qbus_reset_all(&s->sec_bus.qbus); 273 } 274 } 275 276 void pci_bridge_disable_base_limit(PCIDevice *dev) 277 { 278 uint8_t *conf = dev->config; 279 280 pci_byte_test_and_set_mask(conf + PCI_IO_BASE, 281 PCI_IO_RANGE_MASK & 0xff); 282 pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT, 283 PCI_IO_RANGE_MASK & 0xff); 284 pci_word_test_and_set_mask(conf + PCI_MEMORY_BASE, 285 PCI_MEMORY_RANGE_MASK & 0xffff); 286 pci_word_test_and_clear_mask(conf + PCI_MEMORY_LIMIT, 287 PCI_MEMORY_RANGE_MASK & 0xffff); 288 pci_word_test_and_set_mask(conf + PCI_PREF_MEMORY_BASE, 289 PCI_PREF_RANGE_MASK & 0xffff); 290 pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_LIMIT, 291 PCI_PREF_RANGE_MASK & 0xffff); 292 pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0); 293 pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0); 294 } 295 296 /* reset bridge specific configuration registers */ 297 void pci_bridge_reset(DeviceState *qdev) 298 { 299 PCIDevice *dev = PCI_DEVICE(qdev); 300 uint8_t *conf = dev->config; 301 302 conf[PCI_PRIMARY_BUS] = 0; 303 conf[PCI_SECONDARY_BUS] = 0; 304 conf[PCI_SUBORDINATE_BUS] = 0; 305 conf[PCI_SEC_LATENCY_TIMER] = 0; 306 307 /* 308 * the default values for base/limit registers aren't specified 309 * in the PCI-to-PCI-bridge spec. So we don't thouch them here. 310 * Each implementation can override it. 311 * typical implementation does 312 * zero base/limit registers or 313 * disable forwarding: pci_bridge_disable_base_limit() 314 * If disable forwarding is wanted, call pci_bridge_disable_base_limit() 315 * after this function. 316 */ 317 pci_byte_test_and_clear_mask(conf + PCI_IO_BASE, 318 PCI_IO_RANGE_MASK & 0xff); 319 pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT, 320 PCI_IO_RANGE_MASK & 0xff); 321 pci_word_test_and_clear_mask(conf + PCI_MEMORY_BASE, 322 PCI_MEMORY_RANGE_MASK & 0xffff); 323 pci_word_test_and_clear_mask(conf + PCI_MEMORY_LIMIT, 324 PCI_MEMORY_RANGE_MASK & 0xffff); 325 pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_BASE, 326 PCI_PREF_RANGE_MASK & 0xffff); 327 pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_LIMIT, 328 PCI_PREF_RANGE_MASK & 0xffff); 329 pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0); 330 pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0); 331 332 pci_set_word(conf + PCI_BRIDGE_CONTROL, 0); 333 } 334 335 /* default qdev initialization function for PCI-to-PCI bridge */ 336 void pci_bridge_initfn(PCIDevice *dev, const char *typename) 337 { 338 PCIBus *parent = dev->bus; 339 PCIBridge *br = PCI_BRIDGE(dev); 340 PCIBus *sec_bus = &br->sec_bus; 341 342 pci_word_test_and_set_mask(dev->config + PCI_STATUS, 343 PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK); 344 345 /* 346 * TODO: We implement VGA Enable in the Bridge Control Register 347 * therefore per the PCI to PCI bridge spec we must also implement 348 * VGA Palette Snooping. When done, set this bit writable: 349 * 350 * pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, 351 * PCI_COMMAND_VGA_PALETTE); 352 */ 353 354 pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_PCI); 355 dev->config[PCI_HEADER_TYPE] = 356 (dev->config[PCI_HEADER_TYPE] & PCI_HEADER_TYPE_MULTI_FUNCTION) | 357 PCI_HEADER_TYPE_BRIDGE; 358 pci_set_word(dev->config + PCI_SEC_STATUS, 359 PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK); 360 361 /* 362 * If we don't specify the name, the bus will be addressed as <id>.0, where 363 * id is the device id. 364 * Since PCI Bridge devices have a single bus each, we don't need the index: 365 * let users address the bus using the device name. 366 */ 367 if (!br->bus_name && dev->qdev.id && *dev->qdev.id) { 368 br->bus_name = dev->qdev.id; 369 } 370 371 qbus_create_inplace(sec_bus, sizeof(br->sec_bus), typename, DEVICE(dev), 372 br->bus_name); 373 sec_bus->parent_dev = dev; 374 sec_bus->map_irq = br->map_irq ? br->map_irq : pci_swizzle_map_irq_fn; 375 sec_bus->address_space_mem = &br->address_space_mem; 376 memory_region_init(&br->address_space_mem, OBJECT(br), "pci_bridge_pci", UINT64_MAX); 377 sec_bus->address_space_io = &br->address_space_io; 378 memory_region_init(&br->address_space_io, OBJECT(br), "pci_bridge_io", 65536); 379 br->windows = pci_bridge_region_init(br); 380 QLIST_INIT(&sec_bus->child); 381 QLIST_INSERT_HEAD(&parent->child, sec_bus, sibling); 382 } 383 384 /* default qdev clean up function for PCI-to-PCI bridge */ 385 void pci_bridge_exitfn(PCIDevice *pci_dev) 386 { 387 PCIBridge *s = PCI_BRIDGE(pci_dev); 388 assert(QLIST_EMPTY(&s->sec_bus.child)); 389 QLIST_REMOVE(&s->sec_bus, sibling); 390 pci_bridge_region_del(s, s->windows); 391 pci_bridge_region_cleanup(s, s->windows); 392 /* object_unparent() is called automatically during device deletion */ 393 } 394 395 /* 396 * before qdev initialization(qdev_init()), this function sets bus_name and 397 * map_irq callback which are necessry for pci_bridge_initfn() to 398 * initialize bus. 399 */ 400 void pci_bridge_map_irq(PCIBridge *br, const char* bus_name, 401 pci_map_irq_fn map_irq) 402 { 403 br->map_irq = map_irq; 404 br->bus_name = bus_name; 405 } 406 407 static const TypeInfo pci_bridge_type_info = { 408 .name = TYPE_PCI_BRIDGE, 409 .parent = TYPE_PCI_DEVICE, 410 .instance_size = sizeof(PCIBridge), 411 .abstract = true, 412 }; 413 414 static void pci_bridge_register_types(void) 415 { 416 type_register_static(&pci_bridge_type_info); 417 } 418 419 type_init(pci_bridge_register_types) 420