1 /* 2 * QEMU PCI bus manager 3 * 4 * Copyright (c) 2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu-common.h" 27 #include "qemu/datadir.h" 28 #include "qemu/units.h" 29 #include "hw/irq.h" 30 #include "hw/pci/pci.h" 31 #include "hw/pci/pci_bridge.h" 32 #include "hw/pci/pci_bus.h" 33 #include "hw/pci/pci_host.h" 34 #include "hw/qdev-properties.h" 35 #include "hw/qdev-properties-system.h" 36 #include "migration/qemu-file-types.h" 37 #include "migration/vmstate.h" 38 #include "monitor/monitor.h" 39 #include "net/net.h" 40 #include "sysemu/numa.h" 41 #include "sysemu/sysemu.h" 42 #include "hw/loader.h" 43 #include "qemu/error-report.h" 44 #include "qemu/range.h" 45 #include "trace.h" 46 #include "hw/pci/msi.h" 47 #include "hw/pci/msix.h" 48 #include "hw/hotplug.h" 49 #include "hw/boards.h" 50 #include "qapi/error.h" 51 #include "qapi/qapi-commands-pci.h" 52 #include "qemu/cutils.h" 53 54 //#define DEBUG_PCI 55 #ifdef DEBUG_PCI 56 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) 57 #else 58 # define PCI_DPRINTF(format, ...) do { } while (0) 59 #endif 60 61 bool pci_available = true; 62 63 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent); 64 static char *pcibus_get_dev_path(DeviceState *dev); 65 static char *pcibus_get_fw_dev_path(DeviceState *dev); 66 static void pcibus_reset(BusState *qbus); 67 68 static Property pci_props[] = { 69 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1), 70 DEFINE_PROP_STRING("romfile", PCIDevice, romfile), 71 DEFINE_PROP_UINT32("romsize", PCIDevice, romsize, -1), 72 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1), 73 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present, 74 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false), 75 DEFINE_PROP_BIT("x-pcie-lnksta-dllla", PCIDevice, cap_present, 76 QEMU_PCIE_LNKSTA_DLLLA_BITNR, true), 77 DEFINE_PROP_BIT("x-pcie-extcap-init", PCIDevice, cap_present, 78 QEMU_PCIE_EXTCAP_INIT_BITNR, true), 79 DEFINE_PROP_STRING("failover_pair_id", PCIDevice, 80 failover_pair_id), 81 DEFINE_PROP_UINT32("acpi-index", PCIDevice, acpi_index, 0), 82 DEFINE_PROP_END_OF_LIST() 83 }; 84 85 static const VMStateDescription vmstate_pcibus = { 86 .name = "PCIBUS", 87 .version_id = 1, 88 .minimum_version_id = 1, 89 .fields = (VMStateField[]) { 90 VMSTATE_INT32_EQUAL(nirq, PCIBus, NULL), 91 VMSTATE_VARRAY_INT32(irq_count, PCIBus, 92 nirq, 0, vmstate_info_int32, 93 int32_t), 94 VMSTATE_END_OF_LIST() 95 } 96 }; 97 98 static void pci_init_bus_master(PCIDevice *pci_dev) 99 { 100 AddressSpace *dma_as = pci_device_iommu_address_space(pci_dev); 101 102 memory_region_init_alias(&pci_dev->bus_master_enable_region, 103 OBJECT(pci_dev), "bus master", 104 dma_as->root, 0, memory_region_size(dma_as->root)); 105 memory_region_set_enabled(&pci_dev->bus_master_enable_region, false); 106 memory_region_add_subregion(&pci_dev->bus_master_container_region, 0, 107 &pci_dev->bus_master_enable_region); 108 } 109 110 static void pcibus_machine_done(Notifier *notifier, void *data) 111 { 112 PCIBus *bus = container_of(notifier, PCIBus, machine_done); 113 int i; 114 115 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 116 if (bus->devices[i]) { 117 pci_init_bus_master(bus->devices[i]); 118 } 119 } 120 } 121 122 static void pci_bus_realize(BusState *qbus, Error **errp) 123 { 124 PCIBus *bus = PCI_BUS(qbus); 125 126 bus->machine_done.notify = pcibus_machine_done; 127 qemu_add_machine_init_done_notifier(&bus->machine_done); 128 129 vmstate_register(NULL, VMSTATE_INSTANCE_ID_ANY, &vmstate_pcibus, bus); 130 } 131 132 static void pcie_bus_realize(BusState *qbus, Error **errp) 133 { 134 PCIBus *bus = PCI_BUS(qbus); 135 Error *local_err = NULL; 136 137 pci_bus_realize(qbus, &local_err); 138 if (local_err) { 139 error_propagate(errp, local_err); 140 return; 141 } 142 143 /* 144 * A PCI-E bus can support extended config space if it's the root 145 * bus, or if the bus/bridge above it does as well 146 */ 147 if (pci_bus_is_root(bus)) { 148 bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE; 149 } else { 150 PCIBus *parent_bus = pci_get_bus(bus->parent_dev); 151 152 if (pci_bus_allows_extended_config_space(parent_bus)) { 153 bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE; 154 } 155 } 156 } 157 158 static void pci_bus_unrealize(BusState *qbus) 159 { 160 PCIBus *bus = PCI_BUS(qbus); 161 162 qemu_remove_machine_init_done_notifier(&bus->machine_done); 163 164 vmstate_unregister(NULL, &vmstate_pcibus, bus); 165 } 166 167 static int pcibus_num(PCIBus *bus) 168 { 169 if (pci_bus_is_root(bus)) { 170 return 0; /* pci host bridge */ 171 } 172 return bus->parent_dev->config[PCI_SECONDARY_BUS]; 173 } 174 175 static uint16_t pcibus_numa_node(PCIBus *bus) 176 { 177 return NUMA_NODE_UNASSIGNED; 178 } 179 180 static void pci_bus_class_init(ObjectClass *klass, void *data) 181 { 182 BusClass *k = BUS_CLASS(klass); 183 PCIBusClass *pbc = PCI_BUS_CLASS(klass); 184 185 k->print_dev = pcibus_dev_print; 186 k->get_dev_path = pcibus_get_dev_path; 187 k->get_fw_dev_path = pcibus_get_fw_dev_path; 188 k->realize = pci_bus_realize; 189 k->unrealize = pci_bus_unrealize; 190 k->reset = pcibus_reset; 191 192 pbc->bus_num = pcibus_num; 193 pbc->numa_node = pcibus_numa_node; 194 } 195 196 static const TypeInfo pci_bus_info = { 197 .name = TYPE_PCI_BUS, 198 .parent = TYPE_BUS, 199 .instance_size = sizeof(PCIBus), 200 .class_size = sizeof(PCIBusClass), 201 .class_init = pci_bus_class_init, 202 }; 203 204 static const TypeInfo pcie_interface_info = { 205 .name = INTERFACE_PCIE_DEVICE, 206 .parent = TYPE_INTERFACE, 207 }; 208 209 static const TypeInfo conventional_pci_interface_info = { 210 .name = INTERFACE_CONVENTIONAL_PCI_DEVICE, 211 .parent = TYPE_INTERFACE, 212 }; 213 214 static void pcie_bus_class_init(ObjectClass *klass, void *data) 215 { 216 BusClass *k = BUS_CLASS(klass); 217 218 k->realize = pcie_bus_realize; 219 } 220 221 static const TypeInfo pcie_bus_info = { 222 .name = TYPE_PCIE_BUS, 223 .parent = TYPE_PCI_BUS, 224 .class_init = pcie_bus_class_init, 225 }; 226 227 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num); 228 static void pci_update_mappings(PCIDevice *d); 229 static void pci_irq_handler(void *opaque, int irq_num, int level); 230 static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, Error **); 231 static void pci_del_option_rom(PCIDevice *pdev); 232 233 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET; 234 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU; 235 236 static QLIST_HEAD(, PCIHostState) pci_host_bridges; 237 238 int pci_bar(PCIDevice *d, int reg) 239 { 240 uint8_t type; 241 242 if (reg != PCI_ROM_SLOT) 243 return PCI_BASE_ADDRESS_0 + reg * 4; 244 245 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 246 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS; 247 } 248 249 static inline int pci_irq_state(PCIDevice *d, int irq_num) 250 { 251 return (d->irq_state >> irq_num) & 0x1; 252 } 253 254 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level) 255 { 256 d->irq_state &= ~(0x1 << irq_num); 257 d->irq_state |= level << irq_num; 258 } 259 260 static void pci_bus_change_irq_level(PCIBus *bus, int irq_num, int change) 261 { 262 assert(irq_num >= 0); 263 assert(irq_num < bus->nirq); 264 bus->irq_count[irq_num] += change; 265 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0); 266 } 267 268 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change) 269 { 270 PCIBus *bus; 271 for (;;) { 272 bus = pci_get_bus(pci_dev); 273 irq_num = bus->map_irq(pci_dev, irq_num); 274 if (bus->set_irq) 275 break; 276 pci_dev = bus->parent_dev; 277 } 278 pci_bus_change_irq_level(bus, irq_num, change); 279 } 280 281 int pci_bus_get_irq_level(PCIBus *bus, int irq_num) 282 { 283 assert(irq_num >= 0); 284 assert(irq_num < bus->nirq); 285 return !!bus->irq_count[irq_num]; 286 } 287 288 /* Update interrupt status bit in config space on interrupt 289 * state change. */ 290 static void pci_update_irq_status(PCIDevice *dev) 291 { 292 if (dev->irq_state) { 293 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT; 294 } else { 295 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; 296 } 297 } 298 299 void pci_device_deassert_intx(PCIDevice *dev) 300 { 301 int i; 302 for (i = 0; i < PCI_NUM_PINS; ++i) { 303 pci_irq_handler(dev, i, 0); 304 } 305 } 306 307 static void pci_do_device_reset(PCIDevice *dev) 308 { 309 int r; 310 311 pci_device_deassert_intx(dev); 312 assert(dev->irq_state == 0); 313 314 /* Clear all writable bits */ 315 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND, 316 pci_get_word(dev->wmask + PCI_COMMAND) | 317 pci_get_word(dev->w1cmask + PCI_COMMAND)); 318 pci_word_test_and_clear_mask(dev->config + PCI_STATUS, 319 pci_get_word(dev->wmask + PCI_STATUS) | 320 pci_get_word(dev->w1cmask + PCI_STATUS)); 321 /* Some devices make bits of PCI_INTERRUPT_LINE read only */ 322 pci_byte_test_and_clear_mask(dev->config + PCI_INTERRUPT_LINE, 323 pci_get_word(dev->wmask + PCI_INTERRUPT_LINE) | 324 pci_get_word(dev->w1cmask + PCI_INTERRUPT_LINE)); 325 dev->config[PCI_CACHE_LINE_SIZE] = 0x0; 326 for (r = 0; r < PCI_NUM_REGIONS; ++r) { 327 PCIIORegion *region = &dev->io_regions[r]; 328 if (!region->size) { 329 continue; 330 } 331 332 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) && 333 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 334 pci_set_quad(dev->config + pci_bar(dev, r), region->type); 335 } else { 336 pci_set_long(dev->config + pci_bar(dev, r), region->type); 337 } 338 } 339 pci_update_mappings(dev); 340 341 msi_reset(dev); 342 msix_reset(dev); 343 } 344 345 /* 346 * This function is called on #RST and FLR. 347 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set 348 */ 349 void pci_device_reset(PCIDevice *dev) 350 { 351 qdev_reset_all(&dev->qdev); 352 pci_do_device_reset(dev); 353 } 354 355 /* 356 * Trigger pci bus reset under a given bus. 357 * Called via qbus_reset_all on RST# assert, after the devices 358 * have been reset qdev_reset_all-ed already. 359 */ 360 static void pcibus_reset(BusState *qbus) 361 { 362 PCIBus *bus = DO_UPCAST(PCIBus, qbus, qbus); 363 int i; 364 365 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 366 if (bus->devices[i]) { 367 pci_do_device_reset(bus->devices[i]); 368 } 369 } 370 371 for (i = 0; i < bus->nirq; i++) { 372 assert(bus->irq_count[i] == 0); 373 } 374 } 375 376 static void pci_host_bus_register(DeviceState *host) 377 { 378 PCIHostState *host_bridge = PCI_HOST_BRIDGE(host); 379 380 QLIST_INSERT_HEAD(&pci_host_bridges, host_bridge, next); 381 } 382 383 static void pci_host_bus_unregister(DeviceState *host) 384 { 385 PCIHostState *host_bridge = PCI_HOST_BRIDGE(host); 386 387 QLIST_REMOVE(host_bridge, next); 388 } 389 390 PCIBus *pci_device_root_bus(const PCIDevice *d) 391 { 392 PCIBus *bus = pci_get_bus(d); 393 394 while (!pci_bus_is_root(bus)) { 395 d = bus->parent_dev; 396 assert(d != NULL); 397 398 bus = pci_get_bus(d); 399 } 400 401 return bus; 402 } 403 404 const char *pci_root_bus_path(PCIDevice *dev) 405 { 406 PCIBus *rootbus = pci_device_root_bus(dev); 407 PCIHostState *host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent); 408 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_GET_CLASS(host_bridge); 409 410 assert(host_bridge->bus == rootbus); 411 412 if (hc->root_bus_path) { 413 return (*hc->root_bus_path)(host_bridge, rootbus); 414 } 415 416 return rootbus->qbus.name; 417 } 418 419 static void pci_root_bus_init(PCIBus *bus, DeviceState *parent, 420 MemoryRegion *address_space_mem, 421 MemoryRegion *address_space_io, 422 uint8_t devfn_min) 423 { 424 assert(PCI_FUNC(devfn_min) == 0); 425 bus->devfn_min = devfn_min; 426 bus->slot_reserved_mask = 0x0; 427 bus->address_space_mem = address_space_mem; 428 bus->address_space_io = address_space_io; 429 bus->flags |= PCI_BUS_IS_ROOT; 430 431 /* host bridge */ 432 QLIST_INIT(&bus->child); 433 434 pci_host_bus_register(parent); 435 } 436 437 static void pci_bus_uninit(PCIBus *bus) 438 { 439 pci_host_bus_unregister(BUS(bus)->parent); 440 } 441 442 bool pci_bus_is_express(PCIBus *bus) 443 { 444 return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS); 445 } 446 447 void pci_root_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent, 448 const char *name, 449 MemoryRegion *address_space_mem, 450 MemoryRegion *address_space_io, 451 uint8_t devfn_min, const char *typename) 452 { 453 qbus_create_inplace(bus, bus_size, typename, parent, name); 454 pci_root_bus_init(bus, parent, address_space_mem, address_space_io, 455 devfn_min); 456 } 457 458 PCIBus *pci_root_bus_new(DeviceState *parent, const char *name, 459 MemoryRegion *address_space_mem, 460 MemoryRegion *address_space_io, 461 uint8_t devfn_min, const char *typename) 462 { 463 PCIBus *bus; 464 465 bus = PCI_BUS(qbus_create(typename, parent, name)); 466 pci_root_bus_init(bus, parent, address_space_mem, address_space_io, 467 devfn_min); 468 return bus; 469 } 470 471 void pci_root_bus_cleanup(PCIBus *bus) 472 { 473 pci_bus_uninit(bus); 474 /* the caller of the unplug hotplug handler will delete this device */ 475 qbus_unrealize(BUS(bus)); 476 } 477 478 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 479 void *irq_opaque, int nirq) 480 { 481 bus->set_irq = set_irq; 482 bus->map_irq = map_irq; 483 bus->irq_opaque = irq_opaque; 484 bus->nirq = nirq; 485 bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0])); 486 } 487 488 void pci_bus_irqs_cleanup(PCIBus *bus) 489 { 490 bus->set_irq = NULL; 491 bus->map_irq = NULL; 492 bus->irq_opaque = NULL; 493 bus->nirq = 0; 494 g_free(bus->irq_count); 495 } 496 497 PCIBus *pci_register_root_bus(DeviceState *parent, const char *name, 498 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 499 void *irq_opaque, 500 MemoryRegion *address_space_mem, 501 MemoryRegion *address_space_io, 502 uint8_t devfn_min, int nirq, 503 const char *typename) 504 { 505 PCIBus *bus; 506 507 bus = pci_root_bus_new(parent, name, address_space_mem, 508 address_space_io, devfn_min, typename); 509 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq); 510 return bus; 511 } 512 513 void pci_unregister_root_bus(PCIBus *bus) 514 { 515 pci_bus_irqs_cleanup(bus); 516 pci_root_bus_cleanup(bus); 517 } 518 519 int pci_bus_num(PCIBus *s) 520 { 521 return PCI_BUS_GET_CLASS(s)->bus_num(s); 522 } 523 524 int pci_bus_numa_node(PCIBus *bus) 525 { 526 return PCI_BUS_GET_CLASS(bus)->numa_node(bus); 527 } 528 529 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size, 530 const VMStateField *field) 531 { 532 PCIDevice *s = container_of(pv, PCIDevice, config); 533 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(s); 534 uint8_t *config; 535 int i; 536 537 assert(size == pci_config_size(s)); 538 config = g_malloc(size); 539 540 qemu_get_buffer(f, config, size); 541 for (i = 0; i < size; ++i) { 542 if ((config[i] ^ s->config[i]) & 543 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) { 544 error_report("%s: Bad config data: i=0x%x read: %x device: %x " 545 "cmask: %x wmask: %x w1cmask:%x", __func__, 546 i, config[i], s->config[i], 547 s->cmask[i], s->wmask[i], s->w1cmask[i]); 548 g_free(config); 549 return -EINVAL; 550 } 551 } 552 memcpy(s->config, config, size); 553 554 pci_update_mappings(s); 555 if (pc->is_bridge) { 556 PCIBridge *b = PCI_BRIDGE(s); 557 pci_bridge_update_mappings(b); 558 } 559 560 memory_region_set_enabled(&s->bus_master_enable_region, 561 pci_get_word(s->config + PCI_COMMAND) 562 & PCI_COMMAND_MASTER); 563 564 g_free(config); 565 return 0; 566 } 567 568 /* just put buffer */ 569 static int put_pci_config_device(QEMUFile *f, void *pv, size_t size, 570 const VMStateField *field, JSONWriter *vmdesc) 571 { 572 const uint8_t **v = pv; 573 assert(size == pci_config_size(container_of(pv, PCIDevice, config))); 574 qemu_put_buffer(f, *v, size); 575 576 return 0; 577 } 578 579 static VMStateInfo vmstate_info_pci_config = { 580 .name = "pci config", 581 .get = get_pci_config_device, 582 .put = put_pci_config_device, 583 }; 584 585 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size, 586 const VMStateField *field) 587 { 588 PCIDevice *s = container_of(pv, PCIDevice, irq_state); 589 uint32_t irq_state[PCI_NUM_PINS]; 590 int i; 591 for (i = 0; i < PCI_NUM_PINS; ++i) { 592 irq_state[i] = qemu_get_be32(f); 593 if (irq_state[i] != 0x1 && irq_state[i] != 0) { 594 fprintf(stderr, "irq state %d: must be 0 or 1.\n", 595 irq_state[i]); 596 return -EINVAL; 597 } 598 } 599 600 for (i = 0; i < PCI_NUM_PINS; ++i) { 601 pci_set_irq_state(s, i, irq_state[i]); 602 } 603 604 return 0; 605 } 606 607 static int put_pci_irq_state(QEMUFile *f, void *pv, size_t size, 608 const VMStateField *field, JSONWriter *vmdesc) 609 { 610 int i; 611 PCIDevice *s = container_of(pv, PCIDevice, irq_state); 612 613 for (i = 0; i < PCI_NUM_PINS; ++i) { 614 qemu_put_be32(f, pci_irq_state(s, i)); 615 } 616 617 return 0; 618 } 619 620 static VMStateInfo vmstate_info_pci_irq_state = { 621 .name = "pci irq state", 622 .get = get_pci_irq_state, 623 .put = put_pci_irq_state, 624 }; 625 626 static bool migrate_is_pcie(void *opaque, int version_id) 627 { 628 return pci_is_express((PCIDevice *)opaque); 629 } 630 631 static bool migrate_is_not_pcie(void *opaque, int version_id) 632 { 633 return !pci_is_express((PCIDevice *)opaque); 634 } 635 636 const VMStateDescription vmstate_pci_device = { 637 .name = "PCIDevice", 638 .version_id = 2, 639 .minimum_version_id = 1, 640 .fields = (VMStateField[]) { 641 VMSTATE_INT32_POSITIVE_LE(version_id, PCIDevice), 642 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice, 643 migrate_is_not_pcie, 644 0, vmstate_info_pci_config, 645 PCI_CONFIG_SPACE_SIZE), 646 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice, 647 migrate_is_pcie, 648 0, vmstate_info_pci_config, 649 PCIE_CONFIG_SPACE_SIZE), 650 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2, 651 vmstate_info_pci_irq_state, 652 PCI_NUM_PINS * sizeof(int32_t)), 653 VMSTATE_END_OF_LIST() 654 } 655 }; 656 657 658 void pci_device_save(PCIDevice *s, QEMUFile *f) 659 { 660 /* Clear interrupt status bit: it is implicit 661 * in irq_state which we are saving. 662 * This makes us compatible with old devices 663 * which never set or clear this bit. */ 664 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; 665 vmstate_save_state(f, &vmstate_pci_device, s, NULL); 666 /* Restore the interrupt status bit. */ 667 pci_update_irq_status(s); 668 } 669 670 int pci_device_load(PCIDevice *s, QEMUFile *f) 671 { 672 int ret; 673 ret = vmstate_load_state(f, &vmstate_pci_device, s, s->version_id); 674 /* Restore the interrupt status bit. */ 675 pci_update_irq_status(s); 676 return ret; 677 } 678 679 static void pci_set_default_subsystem_id(PCIDevice *pci_dev) 680 { 681 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, 682 pci_default_sub_vendor_id); 683 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 684 pci_default_sub_device_id); 685 } 686 687 /* 688 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL 689 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error 690 */ 691 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, 692 unsigned int *slotp, unsigned int *funcp) 693 { 694 const char *p; 695 char *e; 696 unsigned long val; 697 unsigned long dom = 0, bus = 0; 698 unsigned int slot = 0; 699 unsigned int func = 0; 700 701 p = addr; 702 val = strtoul(p, &e, 16); 703 if (e == p) 704 return -1; 705 if (*e == ':') { 706 bus = val; 707 p = e + 1; 708 val = strtoul(p, &e, 16); 709 if (e == p) 710 return -1; 711 if (*e == ':') { 712 dom = bus; 713 bus = val; 714 p = e + 1; 715 val = strtoul(p, &e, 16); 716 if (e == p) 717 return -1; 718 } 719 } 720 721 slot = val; 722 723 if (funcp != NULL) { 724 if (*e != '.') 725 return -1; 726 727 p = e + 1; 728 val = strtoul(p, &e, 16); 729 if (e == p) 730 return -1; 731 732 func = val; 733 } 734 735 /* if funcp == NULL func is 0 */ 736 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7) 737 return -1; 738 739 if (*e) 740 return -1; 741 742 *domp = dom; 743 *busp = bus; 744 *slotp = slot; 745 if (funcp != NULL) 746 *funcp = func; 747 return 0; 748 } 749 750 static void pci_init_cmask(PCIDevice *dev) 751 { 752 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff); 753 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff); 754 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST; 755 dev->cmask[PCI_REVISION_ID] = 0xff; 756 dev->cmask[PCI_CLASS_PROG] = 0xff; 757 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff); 758 dev->cmask[PCI_HEADER_TYPE] = 0xff; 759 dev->cmask[PCI_CAPABILITY_LIST] = 0xff; 760 } 761 762 static void pci_init_wmask(PCIDevice *dev) 763 { 764 int config_size = pci_config_size(dev); 765 766 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff; 767 dev->wmask[PCI_INTERRUPT_LINE] = 0xff; 768 pci_set_word(dev->wmask + PCI_COMMAND, 769 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | 770 PCI_COMMAND_INTX_DISABLE); 771 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR); 772 773 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff, 774 config_size - PCI_CONFIG_HEADER_SIZE); 775 } 776 777 static void pci_init_w1cmask(PCIDevice *dev) 778 { 779 /* 780 * Note: It's okay to set w1cmask even for readonly bits as 781 * long as their value is hardwired to 0. 782 */ 783 pci_set_word(dev->w1cmask + PCI_STATUS, 784 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT | 785 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT | 786 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY); 787 } 788 789 static void pci_init_mask_bridge(PCIDevice *d) 790 { 791 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and 792 PCI_SEC_LETENCY_TIMER */ 793 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4); 794 795 /* base and limit */ 796 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff; 797 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff; 798 pci_set_word(d->wmask + PCI_MEMORY_BASE, 799 PCI_MEMORY_RANGE_MASK & 0xffff); 800 pci_set_word(d->wmask + PCI_MEMORY_LIMIT, 801 PCI_MEMORY_RANGE_MASK & 0xffff); 802 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE, 803 PCI_PREF_RANGE_MASK & 0xffff); 804 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT, 805 PCI_PREF_RANGE_MASK & 0xffff); 806 807 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */ 808 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8); 809 810 /* Supported memory and i/o types */ 811 d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16; 812 d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16; 813 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE, 814 PCI_PREF_RANGE_TYPE_64); 815 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT, 816 PCI_PREF_RANGE_TYPE_64); 817 818 /* 819 * TODO: Bridges default to 10-bit VGA decoding but we currently only 820 * implement 16-bit decoding (no alias support). 821 */ 822 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 823 PCI_BRIDGE_CTL_PARITY | 824 PCI_BRIDGE_CTL_SERR | 825 PCI_BRIDGE_CTL_ISA | 826 PCI_BRIDGE_CTL_VGA | 827 PCI_BRIDGE_CTL_VGA_16BIT | 828 PCI_BRIDGE_CTL_MASTER_ABORT | 829 PCI_BRIDGE_CTL_BUS_RESET | 830 PCI_BRIDGE_CTL_FAST_BACK | 831 PCI_BRIDGE_CTL_DISCARD | 832 PCI_BRIDGE_CTL_SEC_DISCARD | 833 PCI_BRIDGE_CTL_DISCARD_SERR); 834 /* Below does not do anything as we never set this bit, put here for 835 * completeness. */ 836 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL, 837 PCI_BRIDGE_CTL_DISCARD_STATUS); 838 d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK; 839 d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK; 840 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE, 841 PCI_PREF_RANGE_TYPE_MASK); 842 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT, 843 PCI_PREF_RANGE_TYPE_MASK); 844 } 845 846 static void pci_init_multifunction(PCIBus *bus, PCIDevice *dev, Error **errp) 847 { 848 uint8_t slot = PCI_SLOT(dev->devfn); 849 uint8_t func; 850 851 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 852 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION; 853 } 854 855 /* 856 * multifunction bit is interpreted in two ways as follows. 857 * - all functions must set the bit to 1. 858 * Example: Intel X53 859 * - function 0 must set the bit, but the rest function (> 0) 860 * is allowed to leave the bit to 0. 861 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10, 862 * 863 * So OS (at least Linux) checks the bit of only function 0, 864 * and doesn't see the bit of function > 0. 865 * 866 * The below check allows both interpretation. 867 */ 868 if (PCI_FUNC(dev->devfn)) { 869 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)]; 870 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) { 871 /* function 0 should set multifunction bit */ 872 error_setg(errp, "PCI: single function device can't be populated " 873 "in function %x.%x", slot, PCI_FUNC(dev->devfn)); 874 return; 875 } 876 return; 877 } 878 879 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 880 return; 881 } 882 /* function 0 indicates single function, so function > 0 must be NULL */ 883 for (func = 1; func < PCI_FUNC_MAX; ++func) { 884 if (bus->devices[PCI_DEVFN(slot, func)]) { 885 error_setg(errp, "PCI: %x.0 indicates single function, " 886 "but %x.%x is already populated.", 887 slot, slot, func); 888 return; 889 } 890 } 891 } 892 893 static void pci_config_alloc(PCIDevice *pci_dev) 894 { 895 int config_size = pci_config_size(pci_dev); 896 897 pci_dev->config = g_malloc0(config_size); 898 pci_dev->cmask = g_malloc0(config_size); 899 pci_dev->wmask = g_malloc0(config_size); 900 pci_dev->w1cmask = g_malloc0(config_size); 901 pci_dev->used = g_malloc0(config_size); 902 } 903 904 static void pci_config_free(PCIDevice *pci_dev) 905 { 906 g_free(pci_dev->config); 907 g_free(pci_dev->cmask); 908 g_free(pci_dev->wmask); 909 g_free(pci_dev->w1cmask); 910 g_free(pci_dev->used); 911 } 912 913 static void do_pci_unregister_device(PCIDevice *pci_dev) 914 { 915 pci_get_bus(pci_dev)->devices[pci_dev->devfn] = NULL; 916 pci_config_free(pci_dev); 917 918 if (memory_region_is_mapped(&pci_dev->bus_master_enable_region)) { 919 memory_region_del_subregion(&pci_dev->bus_master_container_region, 920 &pci_dev->bus_master_enable_region); 921 } 922 address_space_destroy(&pci_dev->bus_master_as); 923 } 924 925 /* Extract PCIReqIDCache into BDF format */ 926 static uint16_t pci_req_id_cache_extract(PCIReqIDCache *cache) 927 { 928 uint8_t bus_n; 929 uint16_t result; 930 931 switch (cache->type) { 932 case PCI_REQ_ID_BDF: 933 result = pci_get_bdf(cache->dev); 934 break; 935 case PCI_REQ_ID_SECONDARY_BUS: 936 bus_n = pci_dev_bus_num(cache->dev); 937 result = PCI_BUILD_BDF(bus_n, 0); 938 break; 939 default: 940 error_report("Invalid PCI requester ID cache type: %d", 941 cache->type); 942 exit(1); 943 break; 944 } 945 946 return result; 947 } 948 949 /* Parse bridges up to the root complex and return requester ID 950 * cache for specific device. For full PCIe topology, the cache 951 * result would be exactly the same as getting BDF of the device. 952 * However, several tricks are required when system mixed up with 953 * legacy PCI devices and PCIe-to-PCI bridges. 954 * 955 * Here we cache the proxy device (and type) not requester ID since 956 * bus number might change from time to time. 957 */ 958 static PCIReqIDCache pci_req_id_cache_get(PCIDevice *dev) 959 { 960 PCIDevice *parent; 961 PCIReqIDCache cache = { 962 .dev = dev, 963 .type = PCI_REQ_ID_BDF, 964 }; 965 966 while (!pci_bus_is_root(pci_get_bus(dev))) { 967 /* We are under PCI/PCIe bridges */ 968 parent = pci_get_bus(dev)->parent_dev; 969 if (pci_is_express(parent)) { 970 if (pcie_cap_get_type(parent) == PCI_EXP_TYPE_PCI_BRIDGE) { 971 /* When we pass through PCIe-to-PCI/PCIX bridges, we 972 * override the requester ID using secondary bus 973 * number of parent bridge with zeroed devfn 974 * (pcie-to-pci bridge spec chap 2.3). */ 975 cache.type = PCI_REQ_ID_SECONDARY_BUS; 976 cache.dev = dev; 977 } 978 } else { 979 /* Legacy PCI, override requester ID with the bridge's 980 * BDF upstream. When the root complex connects to 981 * legacy PCI devices (including buses), it can only 982 * obtain requester ID info from directly attached 983 * devices. If devices are attached under bridges, only 984 * the requester ID of the bridge that is directly 985 * attached to the root complex can be recognized. */ 986 cache.type = PCI_REQ_ID_BDF; 987 cache.dev = parent; 988 } 989 dev = parent; 990 } 991 992 return cache; 993 } 994 995 uint16_t pci_requester_id(PCIDevice *dev) 996 { 997 return pci_req_id_cache_extract(&dev->requester_id_cache); 998 } 999 1000 static bool pci_bus_devfn_available(PCIBus *bus, int devfn) 1001 { 1002 return !(bus->devices[devfn]); 1003 } 1004 1005 static bool pci_bus_devfn_reserved(PCIBus *bus, int devfn) 1006 { 1007 return bus->slot_reserved_mask & (1UL << PCI_SLOT(devfn)); 1008 } 1009 1010 /* -1 for devfn means auto assign */ 1011 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, 1012 const char *name, int devfn, 1013 Error **errp) 1014 { 1015 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 1016 PCIConfigReadFunc *config_read = pc->config_read; 1017 PCIConfigWriteFunc *config_write = pc->config_write; 1018 Error *local_err = NULL; 1019 DeviceState *dev = DEVICE(pci_dev); 1020 PCIBus *bus = pci_get_bus(pci_dev); 1021 1022 /* Only pci bridges can be attached to extra PCI root buses */ 1023 if (pci_bus_is_root(bus) && bus->parent_dev && !pc->is_bridge) { 1024 error_setg(errp, 1025 "PCI: Only PCI/PCIe bridges can be plugged into %s", 1026 bus->parent_dev->name); 1027 return NULL; 1028 } 1029 1030 if (devfn < 0) { 1031 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices); 1032 devfn += PCI_FUNC_MAX) { 1033 if (pci_bus_devfn_available(bus, devfn) && 1034 !pci_bus_devfn_reserved(bus, devfn)) { 1035 goto found; 1036 } 1037 } 1038 error_setg(errp, "PCI: no slot/function available for %s, all in use " 1039 "or reserved", name); 1040 return NULL; 1041 found: ; 1042 } else if (pci_bus_devfn_reserved(bus, devfn)) { 1043 error_setg(errp, "PCI: slot %d function %d not available for %s," 1044 " reserved", 1045 PCI_SLOT(devfn), PCI_FUNC(devfn), name); 1046 return NULL; 1047 } else if (!pci_bus_devfn_available(bus, devfn)) { 1048 error_setg(errp, "PCI: slot %d function %d not available for %s," 1049 " in use by %s", 1050 PCI_SLOT(devfn), PCI_FUNC(devfn), name, 1051 bus->devices[devfn]->name); 1052 return NULL; 1053 } else if (dev->hotplugged && 1054 pci_get_function_0(pci_dev)) { 1055 error_setg(errp, "PCI: slot %d function 0 already occupied by %s," 1056 " new func %s cannot be exposed to guest.", 1057 PCI_SLOT(pci_get_function_0(pci_dev)->devfn), 1058 pci_get_function_0(pci_dev)->name, 1059 name); 1060 1061 return NULL; 1062 } 1063 1064 pci_dev->devfn = devfn; 1065 pci_dev->requester_id_cache = pci_req_id_cache_get(pci_dev); 1066 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name); 1067 1068 memory_region_init(&pci_dev->bus_master_container_region, OBJECT(pci_dev), 1069 "bus master container", UINT64_MAX); 1070 address_space_init(&pci_dev->bus_master_as, 1071 &pci_dev->bus_master_container_region, pci_dev->name); 1072 1073 if (phase_check(PHASE_MACHINE_READY)) { 1074 pci_init_bus_master(pci_dev); 1075 } 1076 pci_dev->irq_state = 0; 1077 pci_config_alloc(pci_dev); 1078 1079 pci_config_set_vendor_id(pci_dev->config, pc->vendor_id); 1080 pci_config_set_device_id(pci_dev->config, pc->device_id); 1081 pci_config_set_revision(pci_dev->config, pc->revision); 1082 pci_config_set_class(pci_dev->config, pc->class_id); 1083 1084 if (!pc->is_bridge) { 1085 if (pc->subsystem_vendor_id || pc->subsystem_id) { 1086 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, 1087 pc->subsystem_vendor_id); 1088 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 1089 pc->subsystem_id); 1090 } else { 1091 pci_set_default_subsystem_id(pci_dev); 1092 } 1093 } else { 1094 /* subsystem_vendor_id/subsystem_id are only for header type 0 */ 1095 assert(!pc->subsystem_vendor_id); 1096 assert(!pc->subsystem_id); 1097 } 1098 pci_init_cmask(pci_dev); 1099 pci_init_wmask(pci_dev); 1100 pci_init_w1cmask(pci_dev); 1101 if (pc->is_bridge) { 1102 pci_init_mask_bridge(pci_dev); 1103 } 1104 pci_init_multifunction(bus, pci_dev, &local_err); 1105 if (local_err) { 1106 error_propagate(errp, local_err); 1107 do_pci_unregister_device(pci_dev); 1108 return NULL; 1109 } 1110 1111 if (!config_read) 1112 config_read = pci_default_read_config; 1113 if (!config_write) 1114 config_write = pci_default_write_config; 1115 pci_dev->config_read = config_read; 1116 pci_dev->config_write = config_write; 1117 bus->devices[devfn] = pci_dev; 1118 pci_dev->version_id = 2; /* Current pci device vmstate version */ 1119 return pci_dev; 1120 } 1121 1122 static void pci_unregister_io_regions(PCIDevice *pci_dev) 1123 { 1124 PCIIORegion *r; 1125 int i; 1126 1127 for(i = 0; i < PCI_NUM_REGIONS; i++) { 1128 r = &pci_dev->io_regions[i]; 1129 if (!r->size || r->addr == PCI_BAR_UNMAPPED) 1130 continue; 1131 memory_region_del_subregion(r->address_space, r->memory); 1132 } 1133 1134 pci_unregister_vga(pci_dev); 1135 } 1136 1137 static void pci_qdev_unrealize(DeviceState *dev) 1138 { 1139 PCIDevice *pci_dev = PCI_DEVICE(dev); 1140 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 1141 1142 pci_unregister_io_regions(pci_dev); 1143 pci_del_option_rom(pci_dev); 1144 1145 if (pc->exit) { 1146 pc->exit(pci_dev); 1147 } 1148 1149 pci_device_deassert_intx(pci_dev); 1150 do_pci_unregister_device(pci_dev); 1151 } 1152 1153 void pci_register_bar(PCIDevice *pci_dev, int region_num, 1154 uint8_t type, MemoryRegion *memory) 1155 { 1156 PCIIORegion *r; 1157 uint32_t addr; /* offset in pci config space */ 1158 uint64_t wmask; 1159 pcibus_t size = memory_region_size(memory); 1160 uint8_t hdr_type; 1161 1162 assert(region_num >= 0); 1163 assert(region_num < PCI_NUM_REGIONS); 1164 assert(is_power_of_2(size)); 1165 1166 /* A PCI bridge device (with Type 1 header) may only have at most 2 BARs */ 1167 hdr_type = 1168 pci_dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 1169 assert(hdr_type != PCI_HEADER_TYPE_BRIDGE || region_num < 2); 1170 1171 r = &pci_dev->io_regions[region_num]; 1172 r->addr = PCI_BAR_UNMAPPED; 1173 r->size = size; 1174 r->type = type; 1175 r->memory = memory; 1176 r->address_space = type & PCI_BASE_ADDRESS_SPACE_IO 1177 ? pci_get_bus(pci_dev)->address_space_io 1178 : pci_get_bus(pci_dev)->address_space_mem; 1179 1180 wmask = ~(size - 1); 1181 if (region_num == PCI_ROM_SLOT) { 1182 /* ROM enable bit is writable */ 1183 wmask |= PCI_ROM_ADDRESS_ENABLE; 1184 } 1185 1186 addr = pci_bar(pci_dev, region_num); 1187 pci_set_long(pci_dev->config + addr, type); 1188 1189 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) && 1190 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 1191 pci_set_quad(pci_dev->wmask + addr, wmask); 1192 pci_set_quad(pci_dev->cmask + addr, ~0ULL); 1193 } else { 1194 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff); 1195 pci_set_long(pci_dev->cmask + addr, 0xffffffff); 1196 } 1197 } 1198 1199 static void pci_update_vga(PCIDevice *pci_dev) 1200 { 1201 uint16_t cmd; 1202 1203 if (!pci_dev->has_vga) { 1204 return; 1205 } 1206 1207 cmd = pci_get_word(pci_dev->config + PCI_COMMAND); 1208 1209 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_MEM], 1210 cmd & PCI_COMMAND_MEMORY); 1211 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO], 1212 cmd & PCI_COMMAND_IO); 1213 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI], 1214 cmd & PCI_COMMAND_IO); 1215 } 1216 1217 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, 1218 MemoryRegion *io_lo, MemoryRegion *io_hi) 1219 { 1220 PCIBus *bus = pci_get_bus(pci_dev); 1221 1222 assert(!pci_dev->has_vga); 1223 1224 assert(memory_region_size(mem) == QEMU_PCI_VGA_MEM_SIZE); 1225 pci_dev->vga_regions[QEMU_PCI_VGA_MEM] = mem; 1226 memory_region_add_subregion_overlap(bus->address_space_mem, 1227 QEMU_PCI_VGA_MEM_BASE, mem, 1); 1228 1229 assert(memory_region_size(io_lo) == QEMU_PCI_VGA_IO_LO_SIZE); 1230 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO] = io_lo; 1231 memory_region_add_subregion_overlap(bus->address_space_io, 1232 QEMU_PCI_VGA_IO_LO_BASE, io_lo, 1); 1233 1234 assert(memory_region_size(io_hi) == QEMU_PCI_VGA_IO_HI_SIZE); 1235 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI] = io_hi; 1236 memory_region_add_subregion_overlap(bus->address_space_io, 1237 QEMU_PCI_VGA_IO_HI_BASE, io_hi, 1); 1238 pci_dev->has_vga = true; 1239 1240 pci_update_vga(pci_dev); 1241 } 1242 1243 void pci_unregister_vga(PCIDevice *pci_dev) 1244 { 1245 PCIBus *bus = pci_get_bus(pci_dev); 1246 1247 if (!pci_dev->has_vga) { 1248 return; 1249 } 1250 1251 memory_region_del_subregion(bus->address_space_mem, 1252 pci_dev->vga_regions[QEMU_PCI_VGA_MEM]); 1253 memory_region_del_subregion(bus->address_space_io, 1254 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO]); 1255 memory_region_del_subregion(bus->address_space_io, 1256 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI]); 1257 pci_dev->has_vga = false; 1258 } 1259 1260 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num) 1261 { 1262 return pci_dev->io_regions[region_num].addr; 1263 } 1264 1265 static pcibus_t pci_bar_address(PCIDevice *d, 1266 int reg, uint8_t type, pcibus_t size) 1267 { 1268 pcibus_t new_addr, last_addr; 1269 int bar = pci_bar(d, reg); 1270 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND); 1271 Object *machine = qdev_get_machine(); 1272 ObjectClass *oc = object_get_class(machine); 1273 MachineClass *mc = MACHINE_CLASS(oc); 1274 bool allow_0_address = mc->pci_allow_0_address; 1275 1276 if (type & PCI_BASE_ADDRESS_SPACE_IO) { 1277 if (!(cmd & PCI_COMMAND_IO)) { 1278 return PCI_BAR_UNMAPPED; 1279 } 1280 new_addr = pci_get_long(d->config + bar) & ~(size - 1); 1281 last_addr = new_addr + size - 1; 1282 /* Check if 32 bit BAR wraps around explicitly. 1283 * TODO: make priorities correct and remove this work around. 1284 */ 1285 if (last_addr <= new_addr || last_addr >= UINT32_MAX || 1286 (!allow_0_address && new_addr == 0)) { 1287 return PCI_BAR_UNMAPPED; 1288 } 1289 return new_addr; 1290 } 1291 1292 if (!(cmd & PCI_COMMAND_MEMORY)) { 1293 return PCI_BAR_UNMAPPED; 1294 } 1295 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 1296 new_addr = pci_get_quad(d->config + bar); 1297 } else { 1298 new_addr = pci_get_long(d->config + bar); 1299 } 1300 /* the ROM slot has a specific enable bit */ 1301 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) { 1302 return PCI_BAR_UNMAPPED; 1303 } 1304 new_addr &= ~(size - 1); 1305 last_addr = new_addr + size - 1; 1306 /* NOTE: we do not support wrapping */ 1307 /* XXX: as we cannot support really dynamic 1308 mappings, we handle specific values as invalid 1309 mappings. */ 1310 if (last_addr <= new_addr || last_addr == PCI_BAR_UNMAPPED || 1311 (!allow_0_address && new_addr == 0)) { 1312 return PCI_BAR_UNMAPPED; 1313 } 1314 1315 /* Now pcibus_t is 64bit. 1316 * Check if 32 bit BAR wraps around explicitly. 1317 * Without this, PC ide doesn't work well. 1318 * TODO: remove this work around. 1319 */ 1320 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) { 1321 return PCI_BAR_UNMAPPED; 1322 } 1323 1324 /* 1325 * OS is allowed to set BAR beyond its addressable 1326 * bits. For example, 32 bit OS can set 64bit bar 1327 * to >4G. Check it. TODO: we might need to support 1328 * it in the future for e.g. PAE. 1329 */ 1330 if (last_addr >= HWADDR_MAX) { 1331 return PCI_BAR_UNMAPPED; 1332 } 1333 1334 return new_addr; 1335 } 1336 1337 static void pci_update_mappings(PCIDevice *d) 1338 { 1339 PCIIORegion *r; 1340 int i; 1341 pcibus_t new_addr; 1342 1343 for(i = 0; i < PCI_NUM_REGIONS; i++) { 1344 r = &d->io_regions[i]; 1345 1346 /* this region isn't registered */ 1347 if (!r->size) 1348 continue; 1349 1350 new_addr = pci_bar_address(d, i, r->type, r->size); 1351 1352 /* This bar isn't changed */ 1353 if (new_addr == r->addr) 1354 continue; 1355 1356 /* now do the real mapping */ 1357 if (r->addr != PCI_BAR_UNMAPPED) { 1358 trace_pci_update_mappings_del(d, pci_dev_bus_num(d), 1359 PCI_SLOT(d->devfn), 1360 PCI_FUNC(d->devfn), 1361 i, r->addr, r->size); 1362 memory_region_del_subregion(r->address_space, r->memory); 1363 } 1364 r->addr = new_addr; 1365 if (r->addr != PCI_BAR_UNMAPPED) { 1366 trace_pci_update_mappings_add(d, pci_dev_bus_num(d), 1367 PCI_SLOT(d->devfn), 1368 PCI_FUNC(d->devfn), 1369 i, r->addr, r->size); 1370 memory_region_add_subregion_overlap(r->address_space, 1371 r->addr, r->memory, 1); 1372 } 1373 } 1374 1375 pci_update_vga(d); 1376 } 1377 1378 static inline int pci_irq_disabled(PCIDevice *d) 1379 { 1380 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE; 1381 } 1382 1383 /* Called after interrupt disabled field update in config space, 1384 * assert/deassert interrupts if necessary. 1385 * Gets original interrupt disable bit value (before update). */ 1386 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled) 1387 { 1388 int i, disabled = pci_irq_disabled(d); 1389 if (disabled == was_irq_disabled) 1390 return; 1391 for (i = 0; i < PCI_NUM_PINS; ++i) { 1392 int state = pci_irq_state(d, i); 1393 pci_change_irq_level(d, i, disabled ? -state : state); 1394 } 1395 } 1396 1397 uint32_t pci_default_read_config(PCIDevice *d, 1398 uint32_t address, int len) 1399 { 1400 uint32_t val = 0; 1401 1402 assert(address + len <= pci_config_size(d)); 1403 1404 if (pci_is_express_downstream_port(d) && 1405 ranges_overlap(address, len, d->exp.exp_cap + PCI_EXP_LNKSTA, 2)) { 1406 pcie_sync_bridge_lnk(d); 1407 } 1408 memcpy(&val, d->config + address, len); 1409 return le32_to_cpu(val); 1410 } 1411 1412 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val_in, int l) 1413 { 1414 int i, was_irq_disabled = pci_irq_disabled(d); 1415 uint32_t val = val_in; 1416 1417 assert(addr + l <= pci_config_size(d)); 1418 1419 for (i = 0; i < l; val >>= 8, ++i) { 1420 uint8_t wmask = d->wmask[addr + i]; 1421 uint8_t w1cmask = d->w1cmask[addr + i]; 1422 assert(!(wmask & w1cmask)); 1423 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask); 1424 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */ 1425 } 1426 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) || 1427 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) || 1428 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) || 1429 range_covers_byte(addr, l, PCI_COMMAND)) 1430 pci_update_mappings(d); 1431 1432 if (range_covers_byte(addr, l, PCI_COMMAND)) { 1433 pci_update_irq_disabled(d, was_irq_disabled); 1434 memory_region_set_enabled(&d->bus_master_enable_region, 1435 pci_get_word(d->config + PCI_COMMAND) 1436 & PCI_COMMAND_MASTER); 1437 } 1438 1439 msi_write_config(d, addr, val_in, l); 1440 msix_write_config(d, addr, val_in, l); 1441 } 1442 1443 /***********************************************************/ 1444 /* generic PCI irq support */ 1445 1446 /* 0 <= irq_num <= 3. level must be 0 or 1 */ 1447 static void pci_irq_handler(void *opaque, int irq_num, int level) 1448 { 1449 PCIDevice *pci_dev = opaque; 1450 int change; 1451 1452 assert(0 <= irq_num && irq_num < PCI_NUM_PINS); 1453 assert(level == 0 || level == 1); 1454 change = level - pci_irq_state(pci_dev, irq_num); 1455 if (!change) 1456 return; 1457 1458 pci_set_irq_state(pci_dev, irq_num, level); 1459 pci_update_irq_status(pci_dev); 1460 if (pci_irq_disabled(pci_dev)) 1461 return; 1462 pci_change_irq_level(pci_dev, irq_num, change); 1463 } 1464 1465 static inline int pci_intx(PCIDevice *pci_dev) 1466 { 1467 return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1; 1468 } 1469 1470 qemu_irq pci_allocate_irq(PCIDevice *pci_dev) 1471 { 1472 int intx = pci_intx(pci_dev); 1473 assert(0 <= intx && intx < PCI_NUM_PINS); 1474 1475 return qemu_allocate_irq(pci_irq_handler, pci_dev, intx); 1476 } 1477 1478 void pci_set_irq(PCIDevice *pci_dev, int level) 1479 { 1480 int intx = pci_intx(pci_dev); 1481 pci_irq_handler(pci_dev, intx, level); 1482 } 1483 1484 /* Special hooks used by device assignment */ 1485 void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq) 1486 { 1487 assert(pci_bus_is_root(bus)); 1488 bus->route_intx_to_irq = route_intx_to_irq; 1489 } 1490 1491 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin) 1492 { 1493 PCIBus *bus; 1494 1495 do { 1496 bus = pci_get_bus(dev); 1497 pin = bus->map_irq(dev, pin); 1498 dev = bus->parent_dev; 1499 } while (dev); 1500 1501 if (!bus->route_intx_to_irq) { 1502 error_report("PCI: Bug - unimplemented PCI INTx routing (%s)", 1503 object_get_typename(OBJECT(bus->qbus.parent))); 1504 return (PCIINTxRoute) { PCI_INTX_DISABLED, -1 }; 1505 } 1506 1507 return bus->route_intx_to_irq(bus->irq_opaque, pin); 1508 } 1509 1510 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new) 1511 { 1512 return old->mode != new->mode || old->irq != new->irq; 1513 } 1514 1515 void pci_bus_fire_intx_routing_notifier(PCIBus *bus) 1516 { 1517 PCIDevice *dev; 1518 PCIBus *sec; 1519 int i; 1520 1521 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 1522 dev = bus->devices[i]; 1523 if (dev && dev->intx_routing_notifier) { 1524 dev->intx_routing_notifier(dev); 1525 } 1526 } 1527 1528 QLIST_FOREACH(sec, &bus->child, sibling) { 1529 pci_bus_fire_intx_routing_notifier(sec); 1530 } 1531 } 1532 1533 void pci_device_set_intx_routing_notifier(PCIDevice *dev, 1534 PCIINTxRoutingNotifier notifier) 1535 { 1536 dev->intx_routing_notifier = notifier; 1537 } 1538 1539 /* 1540 * PCI-to-PCI bridge specification 1541 * 9.1: Interrupt routing. Table 9-1 1542 * 1543 * the PCI Express Base Specification, Revision 2.1 1544 * 2.2.8.1: INTx interrutp signaling - Rules 1545 * the Implementation Note 1546 * Table 2-20 1547 */ 1548 /* 1549 * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD 1550 * 0-origin unlike PCI interrupt pin register. 1551 */ 1552 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin) 1553 { 1554 return pci_swizzle(PCI_SLOT(pci_dev->devfn), pin); 1555 } 1556 1557 /***********************************************************/ 1558 /* monitor info on PCI */ 1559 1560 typedef struct { 1561 uint16_t class; 1562 const char *desc; 1563 const char *fw_name; 1564 uint16_t fw_ign_bits; 1565 } pci_class_desc; 1566 1567 static const pci_class_desc pci_class_descriptions[] = 1568 { 1569 { 0x0001, "VGA controller", "display"}, 1570 { 0x0100, "SCSI controller", "scsi"}, 1571 { 0x0101, "IDE controller", "ide"}, 1572 { 0x0102, "Floppy controller", "fdc"}, 1573 { 0x0103, "IPI controller", "ipi"}, 1574 { 0x0104, "RAID controller", "raid"}, 1575 { 0x0106, "SATA controller"}, 1576 { 0x0107, "SAS controller"}, 1577 { 0x0180, "Storage controller"}, 1578 { 0x0200, "Ethernet controller", "ethernet"}, 1579 { 0x0201, "Token Ring controller", "token-ring"}, 1580 { 0x0202, "FDDI controller", "fddi"}, 1581 { 0x0203, "ATM controller", "atm"}, 1582 { 0x0280, "Network controller"}, 1583 { 0x0300, "VGA controller", "display", 0x00ff}, 1584 { 0x0301, "XGA controller"}, 1585 { 0x0302, "3D controller"}, 1586 { 0x0380, "Display controller"}, 1587 { 0x0400, "Video controller", "video"}, 1588 { 0x0401, "Audio controller", "sound"}, 1589 { 0x0402, "Phone"}, 1590 { 0x0403, "Audio controller", "sound"}, 1591 { 0x0480, "Multimedia controller"}, 1592 { 0x0500, "RAM controller", "memory"}, 1593 { 0x0501, "Flash controller", "flash"}, 1594 { 0x0580, "Memory controller"}, 1595 { 0x0600, "Host bridge", "host"}, 1596 { 0x0601, "ISA bridge", "isa"}, 1597 { 0x0602, "EISA bridge", "eisa"}, 1598 { 0x0603, "MC bridge", "mca"}, 1599 { 0x0604, "PCI bridge", "pci-bridge"}, 1600 { 0x0605, "PCMCIA bridge", "pcmcia"}, 1601 { 0x0606, "NUBUS bridge", "nubus"}, 1602 { 0x0607, "CARDBUS bridge", "cardbus"}, 1603 { 0x0608, "RACEWAY bridge"}, 1604 { 0x0680, "Bridge"}, 1605 { 0x0700, "Serial port", "serial"}, 1606 { 0x0701, "Parallel port", "parallel"}, 1607 { 0x0800, "Interrupt controller", "interrupt-controller"}, 1608 { 0x0801, "DMA controller", "dma-controller"}, 1609 { 0x0802, "Timer", "timer"}, 1610 { 0x0803, "RTC", "rtc"}, 1611 { 0x0900, "Keyboard", "keyboard"}, 1612 { 0x0901, "Pen", "pen"}, 1613 { 0x0902, "Mouse", "mouse"}, 1614 { 0x0A00, "Dock station", "dock", 0x00ff}, 1615 { 0x0B00, "i386 cpu", "cpu", 0x00ff}, 1616 { 0x0c00, "Fireware contorller", "fireware"}, 1617 { 0x0c01, "Access bus controller", "access-bus"}, 1618 { 0x0c02, "SSA controller", "ssa"}, 1619 { 0x0c03, "USB controller", "usb"}, 1620 { 0x0c04, "Fibre channel controller", "fibre-channel"}, 1621 { 0x0c05, "SMBus"}, 1622 { 0, NULL} 1623 }; 1624 1625 static void pci_for_each_device_under_bus_reverse(PCIBus *bus, 1626 void (*fn)(PCIBus *b, 1627 PCIDevice *d, 1628 void *opaque), 1629 void *opaque) 1630 { 1631 PCIDevice *d; 1632 int devfn; 1633 1634 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1635 d = bus->devices[ARRAY_SIZE(bus->devices) - 1 - devfn]; 1636 if (d) { 1637 fn(bus, d, opaque); 1638 } 1639 } 1640 } 1641 1642 void pci_for_each_device_reverse(PCIBus *bus, int bus_num, 1643 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque), 1644 void *opaque) 1645 { 1646 bus = pci_find_bus_nr(bus, bus_num); 1647 1648 if (bus) { 1649 pci_for_each_device_under_bus_reverse(bus, fn, opaque); 1650 } 1651 } 1652 1653 static void pci_for_each_device_under_bus(PCIBus *bus, 1654 void (*fn)(PCIBus *b, PCIDevice *d, 1655 void *opaque), 1656 void *opaque) 1657 { 1658 PCIDevice *d; 1659 int devfn; 1660 1661 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1662 d = bus->devices[devfn]; 1663 if (d) { 1664 fn(bus, d, opaque); 1665 } 1666 } 1667 } 1668 1669 void pci_for_each_device(PCIBus *bus, int bus_num, 1670 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque), 1671 void *opaque) 1672 { 1673 bus = pci_find_bus_nr(bus, bus_num); 1674 1675 if (bus) { 1676 pci_for_each_device_under_bus(bus, fn, opaque); 1677 } 1678 } 1679 1680 static const pci_class_desc *get_class_desc(int class) 1681 { 1682 const pci_class_desc *desc; 1683 1684 desc = pci_class_descriptions; 1685 while (desc->desc && class != desc->class) { 1686 desc++; 1687 } 1688 1689 return desc; 1690 } 1691 1692 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num); 1693 1694 static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev) 1695 { 1696 PciMemoryRegionList *head = NULL, **tail = &head; 1697 int i; 1698 1699 for (i = 0; i < PCI_NUM_REGIONS; i++) { 1700 const PCIIORegion *r = &dev->io_regions[i]; 1701 PciMemoryRegion *region; 1702 1703 if (!r->size) { 1704 continue; 1705 } 1706 1707 region = g_malloc0(sizeof(*region)); 1708 1709 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { 1710 region->type = g_strdup("io"); 1711 } else { 1712 region->type = g_strdup("memory"); 1713 region->has_prefetch = true; 1714 region->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH); 1715 region->has_mem_type_64 = true; 1716 region->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64); 1717 } 1718 1719 region->bar = i; 1720 region->address = r->addr; 1721 region->size = r->size; 1722 1723 QAPI_LIST_APPEND(tail, region); 1724 } 1725 1726 return head; 1727 } 1728 1729 static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus, 1730 int bus_num) 1731 { 1732 PciBridgeInfo *info; 1733 PciMemoryRange *range; 1734 1735 info = g_new0(PciBridgeInfo, 1); 1736 1737 info->bus = g_new0(PciBusInfo, 1); 1738 info->bus->number = dev->config[PCI_PRIMARY_BUS]; 1739 info->bus->secondary = dev->config[PCI_SECONDARY_BUS]; 1740 info->bus->subordinate = dev->config[PCI_SUBORDINATE_BUS]; 1741 1742 range = info->bus->io_range = g_new0(PciMemoryRange, 1); 1743 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO); 1744 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO); 1745 1746 range = info->bus->memory_range = g_new0(PciMemoryRange, 1); 1747 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 1748 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 1749 1750 range = info->bus->prefetchable_range = g_new0(PciMemoryRange, 1); 1751 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 1752 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 1753 1754 if (dev->config[PCI_SECONDARY_BUS] != 0) { 1755 PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]); 1756 if (child_bus) { 1757 info->has_devices = true; 1758 info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]); 1759 } 1760 } 1761 1762 return info; 1763 } 1764 1765 static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus, 1766 int bus_num) 1767 { 1768 const pci_class_desc *desc; 1769 PciDeviceInfo *info; 1770 uint8_t type; 1771 int class; 1772 1773 info = g_new0(PciDeviceInfo, 1); 1774 info->bus = bus_num; 1775 info->slot = PCI_SLOT(dev->devfn); 1776 info->function = PCI_FUNC(dev->devfn); 1777 1778 info->class_info = g_new0(PciDeviceClass, 1); 1779 class = pci_get_word(dev->config + PCI_CLASS_DEVICE); 1780 info->class_info->q_class = class; 1781 desc = get_class_desc(class); 1782 if (desc->desc) { 1783 info->class_info->has_desc = true; 1784 info->class_info->desc = g_strdup(desc->desc); 1785 } 1786 1787 info->id = g_new0(PciDeviceId, 1); 1788 info->id->vendor = pci_get_word(dev->config + PCI_VENDOR_ID); 1789 info->id->device = pci_get_word(dev->config + PCI_DEVICE_ID); 1790 info->regions = qmp_query_pci_regions(dev); 1791 info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : ""); 1792 1793 info->irq_pin = dev->config[PCI_INTERRUPT_PIN]; 1794 if (dev->config[PCI_INTERRUPT_PIN] != 0) { 1795 info->has_irq = true; 1796 info->irq = dev->config[PCI_INTERRUPT_LINE]; 1797 } 1798 1799 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 1800 if (type == PCI_HEADER_TYPE_BRIDGE) { 1801 info->has_pci_bridge = true; 1802 info->pci_bridge = qmp_query_pci_bridge(dev, bus, bus_num); 1803 } else if (type == PCI_HEADER_TYPE_NORMAL) { 1804 info->id->has_subsystem = info->id->has_subsystem_vendor = true; 1805 info->id->subsystem = pci_get_word(dev->config + PCI_SUBSYSTEM_ID); 1806 info->id->subsystem_vendor = 1807 pci_get_word(dev->config + PCI_SUBSYSTEM_VENDOR_ID); 1808 } else if (type == PCI_HEADER_TYPE_CARDBUS) { 1809 info->id->has_subsystem = info->id->has_subsystem_vendor = true; 1810 info->id->subsystem = pci_get_word(dev->config + PCI_CB_SUBSYSTEM_ID); 1811 info->id->subsystem_vendor = 1812 pci_get_word(dev->config + PCI_CB_SUBSYSTEM_VENDOR_ID); 1813 } 1814 1815 return info; 1816 } 1817 1818 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num) 1819 { 1820 PciDeviceInfoList *head = NULL, **tail = &head; 1821 PCIDevice *dev; 1822 int devfn; 1823 1824 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1825 dev = bus->devices[devfn]; 1826 if (dev) { 1827 QAPI_LIST_APPEND(tail, qmp_query_pci_device(dev, bus, bus_num)); 1828 } 1829 } 1830 1831 return head; 1832 } 1833 1834 static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num) 1835 { 1836 PciInfo *info = NULL; 1837 1838 bus = pci_find_bus_nr(bus, bus_num); 1839 if (bus) { 1840 info = g_malloc0(sizeof(*info)); 1841 info->bus = bus_num; 1842 info->devices = qmp_query_pci_devices(bus, bus_num); 1843 } 1844 1845 return info; 1846 } 1847 1848 PciInfoList *qmp_query_pci(Error **errp) 1849 { 1850 PciInfoList *head = NULL, **tail = &head; 1851 PCIHostState *host_bridge; 1852 1853 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { 1854 QAPI_LIST_APPEND(tail, 1855 qmp_query_pci_bus(host_bridge->bus, 1856 pci_bus_num(host_bridge->bus))); 1857 } 1858 1859 return head; 1860 } 1861 1862 /* Initialize a PCI NIC. */ 1863 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus, 1864 const char *default_model, 1865 const char *default_devaddr) 1866 { 1867 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr; 1868 GSList *list; 1869 GPtrArray *pci_nic_models; 1870 PCIBus *bus; 1871 PCIDevice *pci_dev; 1872 DeviceState *dev; 1873 int devfn; 1874 int i; 1875 int dom, busnr; 1876 unsigned slot; 1877 1878 if (nd->model && !strcmp(nd->model, "virtio")) { 1879 g_free(nd->model); 1880 nd->model = g_strdup("virtio-net-pci"); 1881 } 1882 1883 list = object_class_get_list_sorted(TYPE_PCI_DEVICE, false); 1884 pci_nic_models = g_ptr_array_new(); 1885 while (list) { 1886 DeviceClass *dc = OBJECT_CLASS_CHECK(DeviceClass, list->data, 1887 TYPE_DEVICE); 1888 GSList *next; 1889 if (test_bit(DEVICE_CATEGORY_NETWORK, dc->categories) && 1890 dc->user_creatable) { 1891 const char *name = object_class_get_name(list->data); 1892 /* 1893 * A network device might also be something else than a NIC, see 1894 * e.g. the "rocker" device. Thus we have to look for the "netdev" 1895 * property, too. Unfortunately, some devices like virtio-net only 1896 * create this property during instance_init, so we have to create 1897 * a temporary instance here to be able to check it. 1898 */ 1899 Object *obj = object_new_with_class(OBJECT_CLASS(dc)); 1900 if (object_property_find(obj, "netdev")) { 1901 g_ptr_array_add(pci_nic_models, (gpointer)name); 1902 } 1903 object_unref(obj); 1904 } 1905 next = list->next; 1906 g_slist_free_1(list); 1907 list = next; 1908 } 1909 g_ptr_array_add(pci_nic_models, NULL); 1910 1911 if (qemu_show_nic_models(nd->model, (const char **)pci_nic_models->pdata)) { 1912 exit(0); 1913 } 1914 1915 i = qemu_find_nic_model(nd, (const char **)pci_nic_models->pdata, 1916 default_model); 1917 if (i < 0) { 1918 exit(1); 1919 } 1920 1921 if (!rootbus) { 1922 error_report("No primary PCI bus"); 1923 exit(1); 1924 } 1925 1926 assert(!rootbus->parent_dev); 1927 1928 if (!devaddr) { 1929 devfn = -1; 1930 busnr = 0; 1931 } else { 1932 if (pci_parse_devaddr(devaddr, &dom, &busnr, &slot, NULL) < 0) { 1933 error_report("Invalid PCI device address %s for device %s", 1934 devaddr, nd->model); 1935 exit(1); 1936 } 1937 1938 if (dom != 0) { 1939 error_report("No support for non-zero PCI domains"); 1940 exit(1); 1941 } 1942 1943 devfn = PCI_DEVFN(slot, 0); 1944 } 1945 1946 bus = pci_find_bus_nr(rootbus, busnr); 1947 if (!bus) { 1948 error_report("Invalid PCI device address %s for device %s", 1949 devaddr, nd->model); 1950 exit(1); 1951 } 1952 1953 pci_dev = pci_new(devfn, nd->model); 1954 dev = &pci_dev->qdev; 1955 qdev_set_nic_properties(dev, nd); 1956 pci_realize_and_unref(pci_dev, bus, &error_fatal); 1957 g_ptr_array_free(pci_nic_models, true); 1958 return pci_dev; 1959 } 1960 1961 PCIDevice *pci_vga_init(PCIBus *bus) 1962 { 1963 switch (vga_interface_type) { 1964 case VGA_CIRRUS: 1965 return pci_create_simple(bus, -1, "cirrus-vga"); 1966 case VGA_QXL: 1967 return pci_create_simple(bus, -1, "qxl-vga"); 1968 case VGA_STD: 1969 return pci_create_simple(bus, -1, "VGA"); 1970 case VGA_VMWARE: 1971 return pci_create_simple(bus, -1, "vmware-svga"); 1972 case VGA_VIRTIO: 1973 return pci_create_simple(bus, -1, "virtio-vga"); 1974 case VGA_NONE: 1975 default: /* Other non-PCI types. Checking for unsupported types is already 1976 done in vl.c. */ 1977 return NULL; 1978 } 1979 } 1980 1981 /* Whether a given bus number is in range of the secondary 1982 * bus of the given bridge device. */ 1983 static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num) 1984 { 1985 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) & 1986 PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ && 1987 dev->config[PCI_SECONDARY_BUS] <= bus_num && 1988 bus_num <= dev->config[PCI_SUBORDINATE_BUS]; 1989 } 1990 1991 /* Whether a given bus number is in a range of a root bus */ 1992 static bool pci_root_bus_in_range(PCIBus *bus, int bus_num) 1993 { 1994 int i; 1995 1996 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 1997 PCIDevice *dev = bus->devices[i]; 1998 1999 if (dev && PCI_DEVICE_GET_CLASS(dev)->is_bridge) { 2000 if (pci_secondary_bus_in_range(dev, bus_num)) { 2001 return true; 2002 } 2003 } 2004 } 2005 2006 return false; 2007 } 2008 2009 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num) 2010 { 2011 PCIBus *sec; 2012 2013 if (!bus) { 2014 return NULL; 2015 } 2016 2017 if (pci_bus_num(bus) == bus_num) { 2018 return bus; 2019 } 2020 2021 /* Consider all bus numbers in range for the host pci bridge. */ 2022 if (!pci_bus_is_root(bus) && 2023 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) { 2024 return NULL; 2025 } 2026 2027 /* try child bus */ 2028 for (; bus; bus = sec) { 2029 QLIST_FOREACH(sec, &bus->child, sibling) { 2030 if (pci_bus_num(sec) == bus_num) { 2031 return sec; 2032 } 2033 /* PXB buses assumed to be children of bus 0 */ 2034 if (pci_bus_is_root(sec)) { 2035 if (pci_root_bus_in_range(sec, bus_num)) { 2036 break; 2037 } 2038 } else { 2039 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) { 2040 break; 2041 } 2042 } 2043 } 2044 } 2045 2046 return NULL; 2047 } 2048 2049 void pci_for_each_bus_depth_first(PCIBus *bus, 2050 void *(*begin)(PCIBus *bus, void *parent_state), 2051 void (*end)(PCIBus *bus, void *state), 2052 void *parent_state) 2053 { 2054 PCIBus *sec; 2055 void *state; 2056 2057 if (!bus) { 2058 return; 2059 } 2060 2061 if (begin) { 2062 state = begin(bus, parent_state); 2063 } else { 2064 state = parent_state; 2065 } 2066 2067 QLIST_FOREACH(sec, &bus->child, sibling) { 2068 pci_for_each_bus_depth_first(sec, begin, end, state); 2069 } 2070 2071 if (end) { 2072 end(bus, state); 2073 } 2074 } 2075 2076 2077 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn) 2078 { 2079 bus = pci_find_bus_nr(bus, bus_num); 2080 2081 if (!bus) 2082 return NULL; 2083 2084 return bus->devices[devfn]; 2085 } 2086 2087 static void pci_qdev_realize(DeviceState *qdev, Error **errp) 2088 { 2089 PCIDevice *pci_dev = (PCIDevice *)qdev; 2090 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 2091 ObjectClass *klass = OBJECT_CLASS(pc); 2092 Error *local_err = NULL; 2093 bool is_default_rom; 2094 uint16_t class_id; 2095 2096 if (pci_dev->romsize != -1 && !is_power_of_2(pci_dev->romsize)) { 2097 error_setg(errp, "ROM size %u is not a power of two", pci_dev->romsize); 2098 return; 2099 } 2100 2101 /* initialize cap_present for pci_is_express() and pci_config_size(), 2102 * Note that hybrid PCIs are not set automatically and need to manage 2103 * QEMU_PCI_CAP_EXPRESS manually */ 2104 if (object_class_dynamic_cast(klass, INTERFACE_PCIE_DEVICE) && 2105 !object_class_dynamic_cast(klass, INTERFACE_CONVENTIONAL_PCI_DEVICE)) { 2106 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; 2107 } 2108 2109 pci_dev = do_pci_register_device(pci_dev, 2110 object_get_typename(OBJECT(qdev)), 2111 pci_dev->devfn, errp); 2112 if (pci_dev == NULL) 2113 return; 2114 2115 if (pc->realize) { 2116 pc->realize(pci_dev, &local_err); 2117 if (local_err) { 2118 error_propagate(errp, local_err); 2119 do_pci_unregister_device(pci_dev); 2120 return; 2121 } 2122 } 2123 2124 if (pci_dev->failover_pair_id) { 2125 if (!pci_bus_is_express(pci_get_bus(pci_dev))) { 2126 error_setg(errp, "failover primary device must be on " 2127 "PCIExpress bus"); 2128 pci_qdev_unrealize(DEVICE(pci_dev)); 2129 return; 2130 } 2131 class_id = pci_get_word(pci_dev->config + PCI_CLASS_DEVICE); 2132 if (class_id != PCI_CLASS_NETWORK_ETHERNET) { 2133 error_setg(errp, "failover primary device is not an " 2134 "Ethernet device"); 2135 pci_qdev_unrealize(DEVICE(pci_dev)); 2136 return; 2137 } 2138 if ((pci_dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) 2139 || (PCI_FUNC(pci_dev->devfn) != 0)) { 2140 error_setg(errp, "failover: primary device must be in its own " 2141 "PCI slot"); 2142 pci_qdev_unrealize(DEVICE(pci_dev)); 2143 return; 2144 } 2145 qdev->allow_unplug_during_migration = true; 2146 } 2147 2148 /* rom loading */ 2149 is_default_rom = false; 2150 if (pci_dev->romfile == NULL && pc->romfile != NULL) { 2151 pci_dev->romfile = g_strdup(pc->romfile); 2152 is_default_rom = true; 2153 } 2154 2155 pci_add_option_rom(pci_dev, is_default_rom, &local_err); 2156 if (local_err) { 2157 error_propagate(errp, local_err); 2158 pci_qdev_unrealize(DEVICE(pci_dev)); 2159 return; 2160 } 2161 } 2162 2163 PCIDevice *pci_new_multifunction(int devfn, bool multifunction, 2164 const char *name) 2165 { 2166 DeviceState *dev; 2167 2168 dev = qdev_new(name); 2169 qdev_prop_set_int32(dev, "addr", devfn); 2170 qdev_prop_set_bit(dev, "multifunction", multifunction); 2171 return PCI_DEVICE(dev); 2172 } 2173 2174 PCIDevice *pci_new(int devfn, const char *name) 2175 { 2176 return pci_new_multifunction(devfn, false, name); 2177 } 2178 2179 bool pci_realize_and_unref(PCIDevice *dev, PCIBus *bus, Error **errp) 2180 { 2181 return qdev_realize_and_unref(&dev->qdev, &bus->qbus, errp); 2182 } 2183 2184 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, 2185 bool multifunction, 2186 const char *name) 2187 { 2188 PCIDevice *dev = pci_new_multifunction(devfn, multifunction, name); 2189 pci_realize_and_unref(dev, bus, &error_fatal); 2190 return dev; 2191 } 2192 2193 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name) 2194 { 2195 return pci_create_simple_multifunction(bus, devfn, false, name); 2196 } 2197 2198 static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size) 2199 { 2200 int offset = PCI_CONFIG_HEADER_SIZE; 2201 int i; 2202 for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) { 2203 if (pdev->used[i]) 2204 offset = i + 1; 2205 else if (i - offset + 1 == size) 2206 return offset; 2207 } 2208 return 0; 2209 } 2210 2211 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id, 2212 uint8_t *prev_p) 2213 { 2214 uint8_t next, prev; 2215 2216 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST)) 2217 return 0; 2218 2219 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); 2220 prev = next + PCI_CAP_LIST_NEXT) 2221 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id) 2222 break; 2223 2224 if (prev_p) 2225 *prev_p = prev; 2226 return next; 2227 } 2228 2229 static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset) 2230 { 2231 uint8_t next, prev, found = 0; 2232 2233 if (!(pdev->used[offset])) { 2234 return 0; 2235 } 2236 2237 assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST); 2238 2239 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); 2240 prev = next + PCI_CAP_LIST_NEXT) { 2241 if (next <= offset && next > found) { 2242 found = next; 2243 } 2244 } 2245 return found; 2246 } 2247 2248 /* Patch the PCI vendor and device ids in a PCI rom image if necessary. 2249 This is needed for an option rom which is used for more than one device. */ 2250 static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, uint32_t size) 2251 { 2252 uint16_t vendor_id; 2253 uint16_t device_id; 2254 uint16_t rom_vendor_id; 2255 uint16_t rom_device_id; 2256 uint16_t rom_magic; 2257 uint16_t pcir_offset; 2258 uint8_t checksum; 2259 2260 /* Words in rom data are little endian (like in PCI configuration), 2261 so they can be read / written with pci_get_word / pci_set_word. */ 2262 2263 /* Only a valid rom will be patched. */ 2264 rom_magic = pci_get_word(ptr); 2265 if (rom_magic != 0xaa55) { 2266 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic); 2267 return; 2268 } 2269 pcir_offset = pci_get_word(ptr + 0x18); 2270 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) { 2271 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset); 2272 return; 2273 } 2274 2275 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID); 2276 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID); 2277 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4); 2278 rom_device_id = pci_get_word(ptr + pcir_offset + 6); 2279 2280 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile, 2281 vendor_id, device_id, rom_vendor_id, rom_device_id); 2282 2283 checksum = ptr[6]; 2284 2285 if (vendor_id != rom_vendor_id) { 2286 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */ 2287 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8); 2288 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8); 2289 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); 2290 ptr[6] = checksum; 2291 pci_set_word(ptr + pcir_offset + 4, vendor_id); 2292 } 2293 2294 if (device_id != rom_device_id) { 2295 /* Patch device id and checksum (at offset 6 for etherboot roms). */ 2296 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8); 2297 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8); 2298 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); 2299 ptr[6] = checksum; 2300 pci_set_word(ptr + pcir_offset + 6, device_id); 2301 } 2302 } 2303 2304 /* Add an option rom for the device */ 2305 static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, 2306 Error **errp) 2307 { 2308 int64_t size; 2309 char *path; 2310 void *ptr; 2311 char name[32]; 2312 const VMStateDescription *vmsd; 2313 2314 if (!pdev->romfile) 2315 return; 2316 if (strlen(pdev->romfile) == 0) 2317 return; 2318 2319 if (!pdev->rom_bar) { 2320 /* 2321 * Load rom via fw_cfg instead of creating a rom bar, 2322 * for 0.11 compatibility. 2323 */ 2324 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE); 2325 2326 /* 2327 * Hot-plugged devices can't use the option ROM 2328 * if the rom bar is disabled. 2329 */ 2330 if (DEVICE(pdev)->hotplugged) { 2331 error_setg(errp, "Hot-plugged device without ROM bar" 2332 " can't have an option ROM"); 2333 return; 2334 } 2335 2336 if (class == 0x0300) { 2337 rom_add_vga(pdev->romfile); 2338 } else { 2339 rom_add_option(pdev->romfile, -1); 2340 } 2341 return; 2342 } 2343 2344 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile); 2345 if (path == NULL) { 2346 path = g_strdup(pdev->romfile); 2347 } 2348 2349 size = get_image_size(path); 2350 if (size < 0) { 2351 error_setg(errp, "failed to find romfile \"%s\"", pdev->romfile); 2352 g_free(path); 2353 return; 2354 } else if (size == 0) { 2355 error_setg(errp, "romfile \"%s\" is empty", pdev->romfile); 2356 g_free(path); 2357 return; 2358 } else if (size > 2 * GiB) { 2359 error_setg(errp, "romfile \"%s\" too large (size cannot exceed 2 GiB)", 2360 pdev->romfile); 2361 g_free(path); 2362 return; 2363 } 2364 if (pdev->romsize != -1) { 2365 if (size > pdev->romsize) { 2366 error_setg(errp, "romfile \"%s\" (%u bytes) is too large for ROM size %u", 2367 pdev->romfile, (uint32_t)size, pdev->romsize); 2368 g_free(path); 2369 return; 2370 } 2371 } else { 2372 pdev->romsize = pow2ceil(size); 2373 } 2374 2375 vmsd = qdev_get_vmsd(DEVICE(pdev)); 2376 2377 if (vmsd) { 2378 snprintf(name, sizeof(name), "%s.rom", vmsd->name); 2379 } else { 2380 snprintf(name, sizeof(name), "%s.rom", object_get_typename(OBJECT(pdev))); 2381 } 2382 pdev->has_rom = true; 2383 memory_region_init_rom(&pdev->rom, OBJECT(pdev), name, pdev->romsize, &error_fatal); 2384 ptr = memory_region_get_ram_ptr(&pdev->rom); 2385 if (load_image_size(path, ptr, size) < 0) { 2386 error_setg(errp, "failed to load romfile \"%s\"", pdev->romfile); 2387 g_free(path); 2388 return; 2389 } 2390 g_free(path); 2391 2392 if (is_default_rom) { 2393 /* Only the default rom images will be patched (if needed). */ 2394 pci_patch_ids(pdev, ptr, size); 2395 } 2396 2397 pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom); 2398 } 2399 2400 static void pci_del_option_rom(PCIDevice *pdev) 2401 { 2402 if (!pdev->has_rom) 2403 return; 2404 2405 vmstate_unregister_ram(&pdev->rom, &pdev->qdev); 2406 pdev->has_rom = false; 2407 } 2408 2409 /* 2410 * On success, pci_add_capability() returns a positive value 2411 * that the offset of the pci capability. 2412 * On failure, it sets an error and returns a negative error 2413 * code. 2414 */ 2415 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, 2416 uint8_t offset, uint8_t size, 2417 Error **errp) 2418 { 2419 uint8_t *config; 2420 int i, overlapping_cap; 2421 2422 if (!offset) { 2423 offset = pci_find_space(pdev, size); 2424 /* out of PCI config space is programming error */ 2425 assert(offset); 2426 } else { 2427 /* Verify that capabilities don't overlap. Note: device assignment 2428 * depends on this check to verify that the device is not broken. 2429 * Should never trigger for emulated devices, but it's helpful 2430 * for debugging these. */ 2431 for (i = offset; i < offset + size; i++) { 2432 overlapping_cap = pci_find_capability_at_offset(pdev, i); 2433 if (overlapping_cap) { 2434 error_setg(errp, "%s:%02x:%02x.%x " 2435 "Attempt to add PCI capability %x at offset " 2436 "%x overlaps existing capability %x at offset %x", 2437 pci_root_bus_path(pdev), pci_dev_bus_num(pdev), 2438 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), 2439 cap_id, offset, overlapping_cap, i); 2440 return -EINVAL; 2441 } 2442 } 2443 } 2444 2445 config = pdev->config + offset; 2446 config[PCI_CAP_LIST_ID] = cap_id; 2447 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST]; 2448 pdev->config[PCI_CAPABILITY_LIST] = offset; 2449 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST; 2450 memset(pdev->used + offset, 0xFF, QEMU_ALIGN_UP(size, 4)); 2451 /* Make capability read-only by default */ 2452 memset(pdev->wmask + offset, 0, size); 2453 /* Check capability by default */ 2454 memset(pdev->cmask + offset, 0xFF, size); 2455 return offset; 2456 } 2457 2458 /* Unlink capability from the pci config space. */ 2459 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size) 2460 { 2461 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev); 2462 if (!offset) 2463 return; 2464 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT]; 2465 /* Make capability writable again */ 2466 memset(pdev->wmask + offset, 0xff, size); 2467 memset(pdev->w1cmask + offset, 0, size); 2468 /* Clear cmask as device-specific registers can't be checked */ 2469 memset(pdev->cmask + offset, 0, size); 2470 memset(pdev->used + offset, 0, QEMU_ALIGN_UP(size, 4)); 2471 2472 if (!pdev->config[PCI_CAPABILITY_LIST]) 2473 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST; 2474 } 2475 2476 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id) 2477 { 2478 return pci_find_capability_list(pdev, cap_id, NULL); 2479 } 2480 2481 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent) 2482 { 2483 PCIDevice *d = (PCIDevice *)dev; 2484 const pci_class_desc *desc; 2485 char ctxt[64]; 2486 PCIIORegion *r; 2487 int i, class; 2488 2489 class = pci_get_word(d->config + PCI_CLASS_DEVICE); 2490 desc = pci_class_descriptions; 2491 while (desc->desc && class != desc->class) 2492 desc++; 2493 if (desc->desc) { 2494 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc); 2495 } else { 2496 snprintf(ctxt, sizeof(ctxt), "Class %04x", class); 2497 } 2498 2499 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, " 2500 "pci id %04x:%04x (sub %04x:%04x)\n", 2501 indent, "", ctxt, pci_dev_bus_num(d), 2502 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn), 2503 pci_get_word(d->config + PCI_VENDOR_ID), 2504 pci_get_word(d->config + PCI_DEVICE_ID), 2505 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID), 2506 pci_get_word(d->config + PCI_SUBSYSTEM_ID)); 2507 for (i = 0; i < PCI_NUM_REGIONS; i++) { 2508 r = &d->io_regions[i]; 2509 if (!r->size) 2510 continue; 2511 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS 2512 " [0x%"FMT_PCIBUS"]\n", 2513 indent, "", 2514 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem", 2515 r->addr, r->addr + r->size - 1); 2516 } 2517 } 2518 2519 static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len) 2520 { 2521 PCIDevice *d = (PCIDevice *)dev; 2522 const char *name = NULL; 2523 const pci_class_desc *desc = pci_class_descriptions; 2524 int class = pci_get_word(d->config + PCI_CLASS_DEVICE); 2525 2526 while (desc->desc && 2527 (class & ~desc->fw_ign_bits) != 2528 (desc->class & ~desc->fw_ign_bits)) { 2529 desc++; 2530 } 2531 2532 if (desc->desc) { 2533 name = desc->fw_name; 2534 } 2535 2536 if (name) { 2537 pstrcpy(buf, len, name); 2538 } else { 2539 snprintf(buf, len, "pci%04x,%04x", 2540 pci_get_word(d->config + PCI_VENDOR_ID), 2541 pci_get_word(d->config + PCI_DEVICE_ID)); 2542 } 2543 2544 return buf; 2545 } 2546 2547 static char *pcibus_get_fw_dev_path(DeviceState *dev) 2548 { 2549 PCIDevice *d = (PCIDevice *)dev; 2550 char path[50], name[33]; 2551 int off; 2552 2553 off = snprintf(path, sizeof(path), "%s@%x", 2554 pci_dev_fw_name(dev, name, sizeof name), 2555 PCI_SLOT(d->devfn)); 2556 if (PCI_FUNC(d->devfn)) 2557 snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn)); 2558 return g_strdup(path); 2559 } 2560 2561 static char *pcibus_get_dev_path(DeviceState *dev) 2562 { 2563 PCIDevice *d = container_of(dev, PCIDevice, qdev); 2564 PCIDevice *t; 2565 int slot_depth; 2566 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function. 2567 * 00 is added here to make this format compatible with 2568 * domain:Bus:Slot.Func for systems without nested PCI bridges. 2569 * Slot.Function list specifies the slot and function numbers for all 2570 * devices on the path from root to the specific device. */ 2571 const char *root_bus_path; 2572 int root_bus_len; 2573 char slot[] = ":SS.F"; 2574 int slot_len = sizeof slot - 1 /* For '\0' */; 2575 int path_len; 2576 char *path, *p; 2577 int s; 2578 2579 root_bus_path = pci_root_bus_path(d); 2580 root_bus_len = strlen(root_bus_path); 2581 2582 /* Calculate # of slots on path between device and root. */; 2583 slot_depth = 0; 2584 for (t = d; t; t = pci_get_bus(t)->parent_dev) { 2585 ++slot_depth; 2586 } 2587 2588 path_len = root_bus_len + slot_len * slot_depth; 2589 2590 /* Allocate memory, fill in the terminating null byte. */ 2591 path = g_malloc(path_len + 1 /* For '\0' */); 2592 path[path_len] = '\0'; 2593 2594 memcpy(path, root_bus_path, root_bus_len); 2595 2596 /* Fill in slot numbers. We walk up from device to root, so need to print 2597 * them in the reverse order, last to first. */ 2598 p = path + path_len; 2599 for (t = d; t; t = pci_get_bus(t)->parent_dev) { 2600 p -= slot_len; 2601 s = snprintf(slot, sizeof slot, ":%02x.%x", 2602 PCI_SLOT(t->devfn), PCI_FUNC(t->devfn)); 2603 assert(s == slot_len); 2604 memcpy(p, slot, slot_len); 2605 } 2606 2607 return path; 2608 } 2609 2610 static int pci_qdev_find_recursive(PCIBus *bus, 2611 const char *id, PCIDevice **pdev) 2612 { 2613 DeviceState *qdev = qdev_find_recursive(&bus->qbus, id); 2614 if (!qdev) { 2615 return -ENODEV; 2616 } 2617 2618 /* roughly check if given qdev is pci device */ 2619 if (object_dynamic_cast(OBJECT(qdev), TYPE_PCI_DEVICE)) { 2620 *pdev = PCI_DEVICE(qdev); 2621 return 0; 2622 } 2623 return -EINVAL; 2624 } 2625 2626 int pci_qdev_find_device(const char *id, PCIDevice **pdev) 2627 { 2628 PCIHostState *host_bridge; 2629 int rc = -ENODEV; 2630 2631 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { 2632 int tmp = pci_qdev_find_recursive(host_bridge->bus, id, pdev); 2633 if (!tmp) { 2634 rc = 0; 2635 break; 2636 } 2637 if (tmp != -ENODEV) { 2638 rc = tmp; 2639 } 2640 } 2641 2642 return rc; 2643 } 2644 2645 MemoryRegion *pci_address_space(PCIDevice *dev) 2646 { 2647 return pci_get_bus(dev)->address_space_mem; 2648 } 2649 2650 MemoryRegion *pci_address_space_io(PCIDevice *dev) 2651 { 2652 return pci_get_bus(dev)->address_space_io; 2653 } 2654 2655 static void pci_device_class_init(ObjectClass *klass, void *data) 2656 { 2657 DeviceClass *k = DEVICE_CLASS(klass); 2658 2659 k->realize = pci_qdev_realize; 2660 k->unrealize = pci_qdev_unrealize; 2661 k->bus_type = TYPE_PCI_BUS; 2662 device_class_set_props(k, pci_props); 2663 } 2664 2665 static void pci_device_class_base_init(ObjectClass *klass, void *data) 2666 { 2667 if (!object_class_is_abstract(klass)) { 2668 ObjectClass *conventional = 2669 object_class_dynamic_cast(klass, INTERFACE_CONVENTIONAL_PCI_DEVICE); 2670 ObjectClass *pcie = 2671 object_class_dynamic_cast(klass, INTERFACE_PCIE_DEVICE); 2672 assert(conventional || pcie); 2673 } 2674 } 2675 2676 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev) 2677 { 2678 PCIBus *bus = pci_get_bus(dev); 2679 PCIBus *iommu_bus = bus; 2680 uint8_t devfn = dev->devfn; 2681 2682 while (iommu_bus && !iommu_bus->iommu_fn && iommu_bus->parent_dev) { 2683 PCIBus *parent_bus = pci_get_bus(iommu_bus->parent_dev); 2684 2685 /* 2686 * The requester ID of the provided device may be aliased, as seen from 2687 * the IOMMU, due to topology limitations. The IOMMU relies on a 2688 * requester ID to provide a unique AddressSpace for devices, but 2689 * conventional PCI buses pre-date such concepts. Instead, the PCIe- 2690 * to-PCI bridge creates and accepts transactions on behalf of down- 2691 * stream devices. When doing so, all downstream devices are masked 2692 * (aliased) behind a single requester ID. The requester ID used 2693 * depends on the format of the bridge devices. Proper PCIe-to-PCI 2694 * bridges, with a PCIe capability indicating such, follow the 2695 * guidelines of chapter 2.3 of the PCIe-to-PCI/X bridge specification, 2696 * where the bridge uses the seconary bus as the bridge portion of the 2697 * requester ID and devfn of 00.0. For other bridges, typically those 2698 * found on the root complex such as the dmi-to-pci-bridge, we follow 2699 * the convention of typical bare-metal hardware, which uses the 2700 * requester ID of the bridge itself. There are device specific 2701 * exceptions to these rules, but these are the defaults that the 2702 * Linux kernel uses when determining DMA aliases itself and believed 2703 * to be true for the bare metal equivalents of the devices emulated 2704 * in QEMU. 2705 */ 2706 if (!pci_bus_is_express(iommu_bus)) { 2707 PCIDevice *parent = iommu_bus->parent_dev; 2708 2709 if (pci_is_express(parent) && 2710 pcie_cap_get_type(parent) == PCI_EXP_TYPE_PCI_BRIDGE) { 2711 devfn = PCI_DEVFN(0, 0); 2712 bus = iommu_bus; 2713 } else { 2714 devfn = parent->devfn; 2715 bus = parent_bus; 2716 } 2717 } 2718 2719 iommu_bus = parent_bus; 2720 } 2721 if (iommu_bus && iommu_bus->iommu_fn) { 2722 return iommu_bus->iommu_fn(bus, iommu_bus->iommu_opaque, devfn); 2723 } 2724 return &address_space_memory; 2725 } 2726 2727 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque) 2728 { 2729 bus->iommu_fn = fn; 2730 bus->iommu_opaque = opaque; 2731 } 2732 2733 static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque) 2734 { 2735 Range *range = opaque; 2736 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 2737 uint16_t cmd = pci_get_word(dev->config + PCI_COMMAND); 2738 int i; 2739 2740 if (!(cmd & PCI_COMMAND_MEMORY)) { 2741 return; 2742 } 2743 2744 if (pc->is_bridge) { 2745 pcibus_t base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 2746 pcibus_t limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 2747 2748 base = MAX(base, 0x1ULL << 32); 2749 2750 if (limit >= base) { 2751 Range pref_range; 2752 range_set_bounds(&pref_range, base, limit); 2753 range_extend(range, &pref_range); 2754 } 2755 } 2756 for (i = 0; i < PCI_NUM_REGIONS; ++i) { 2757 PCIIORegion *r = &dev->io_regions[i]; 2758 pcibus_t lob, upb; 2759 Range region_range; 2760 2761 if (!r->size || 2762 (r->type & PCI_BASE_ADDRESS_SPACE_IO) || 2763 !(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64)) { 2764 continue; 2765 } 2766 2767 lob = pci_bar_address(dev, i, r->type, r->size); 2768 upb = lob + r->size - 1; 2769 if (lob == PCI_BAR_UNMAPPED) { 2770 continue; 2771 } 2772 2773 lob = MAX(lob, 0x1ULL << 32); 2774 2775 if (upb >= lob) { 2776 range_set_bounds(®ion_range, lob, upb); 2777 range_extend(range, ®ion_range); 2778 } 2779 } 2780 } 2781 2782 void pci_bus_get_w64_range(PCIBus *bus, Range *range) 2783 { 2784 range_make_empty(range); 2785 pci_for_each_device_under_bus(bus, pci_dev_get_w64, range); 2786 } 2787 2788 static bool pcie_has_upstream_port(PCIDevice *dev) 2789 { 2790 PCIDevice *parent_dev = pci_bridge_get_device(pci_get_bus(dev)); 2791 2792 /* Device associated with an upstream port. 2793 * As there are several types of these, it's easier to check the 2794 * parent device: upstream ports are always connected to 2795 * root or downstream ports. 2796 */ 2797 return parent_dev && 2798 pci_is_express(parent_dev) && 2799 parent_dev->exp.exp_cap && 2800 (pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_ROOT_PORT || 2801 pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_DOWNSTREAM); 2802 } 2803 2804 PCIDevice *pci_get_function_0(PCIDevice *pci_dev) 2805 { 2806 PCIBus *bus = pci_get_bus(pci_dev); 2807 2808 if(pcie_has_upstream_port(pci_dev)) { 2809 /* With an upstream PCIe port, we only support 1 device at slot 0 */ 2810 return bus->devices[0]; 2811 } else { 2812 /* Other bus types might support multiple devices at slots 0-31 */ 2813 return bus->devices[PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 0)]; 2814 } 2815 } 2816 2817 MSIMessage pci_get_msi_message(PCIDevice *dev, int vector) 2818 { 2819 MSIMessage msg; 2820 if (msix_enabled(dev)) { 2821 msg = msix_get_message(dev, vector); 2822 } else if (msi_enabled(dev)) { 2823 msg = msi_get_message(dev, vector); 2824 } else { 2825 /* Should never happen */ 2826 error_report("%s: unknown interrupt type", __func__); 2827 abort(); 2828 } 2829 return msg; 2830 } 2831 2832 static const TypeInfo pci_device_type_info = { 2833 .name = TYPE_PCI_DEVICE, 2834 .parent = TYPE_DEVICE, 2835 .instance_size = sizeof(PCIDevice), 2836 .abstract = true, 2837 .class_size = sizeof(PCIDeviceClass), 2838 .class_init = pci_device_class_init, 2839 .class_base_init = pci_device_class_base_init, 2840 }; 2841 2842 static void pci_register_types(void) 2843 { 2844 type_register_static(&pci_bus_info); 2845 type_register_static(&pcie_bus_info); 2846 type_register_static(&conventional_pci_interface_info); 2847 type_register_static(&pcie_interface_info); 2848 type_register_static(&pci_device_type_info); 2849 } 2850 2851 type_init(pci_register_types) 2852