1 /* 2 * QEMU PCI bus manager 3 * 4 * Copyright (c) 2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/datadir.h" 27 #include "qemu/units.h" 28 #include "hw/irq.h" 29 #include "hw/pci/pci.h" 30 #include "hw/pci/pci_bridge.h" 31 #include "hw/pci/pci_bus.h" 32 #include "hw/pci/pci_host.h" 33 #include "hw/qdev-properties.h" 34 #include "hw/qdev-properties-system.h" 35 #include "migration/qemu-file-types.h" 36 #include "migration/vmstate.h" 37 #include "net/net.h" 38 #include "sysemu/numa.h" 39 #include "sysemu/runstate.h" 40 #include "sysemu/sysemu.h" 41 #include "hw/loader.h" 42 #include "qemu/error-report.h" 43 #include "qemu/range.h" 44 #include "trace.h" 45 #include "hw/pci/msi.h" 46 #include "hw/pci/msix.h" 47 #include "hw/hotplug.h" 48 #include "hw/boards.h" 49 #include "qapi/error.h" 50 #include "qemu/cutils.h" 51 #include "pci-internal.h" 52 53 #include "hw/xen/xen.h" 54 #include "hw/i386/kvm/xen_evtchn.h" 55 56 //#define DEBUG_PCI 57 #ifdef DEBUG_PCI 58 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) 59 #else 60 # define PCI_DPRINTF(format, ...) do { } while (0) 61 #endif 62 63 bool pci_available = true; 64 65 static char *pcibus_get_dev_path(DeviceState *dev); 66 static char *pcibus_get_fw_dev_path(DeviceState *dev); 67 static void pcibus_reset(BusState *qbus); 68 static bool pcie_has_upstream_port(PCIDevice *dev); 69 70 static Property pci_props[] = { 71 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1), 72 DEFINE_PROP_STRING("romfile", PCIDevice, romfile), 73 DEFINE_PROP_UINT32("romsize", PCIDevice, romsize, -1), 74 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1), 75 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present, 76 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false), 77 DEFINE_PROP_BIT("x-pcie-lnksta-dllla", PCIDevice, cap_present, 78 QEMU_PCIE_LNKSTA_DLLLA_BITNR, true), 79 DEFINE_PROP_BIT("x-pcie-extcap-init", PCIDevice, cap_present, 80 QEMU_PCIE_EXTCAP_INIT_BITNR, true), 81 DEFINE_PROP_STRING("failover_pair_id", PCIDevice, 82 failover_pair_id), 83 DEFINE_PROP_UINT32("acpi-index", PCIDevice, acpi_index, 0), 84 DEFINE_PROP_BIT("x-pcie-err-unc-mask", PCIDevice, cap_present, 85 QEMU_PCIE_ERR_UNC_MASK_BITNR, true), 86 DEFINE_PROP_BIT("x-pcie-ari-nextfn-1", PCIDevice, cap_present, 87 QEMU_PCIE_ARI_NEXTFN_1_BITNR, false), 88 DEFINE_PROP_END_OF_LIST() 89 }; 90 91 static const VMStateDescription vmstate_pcibus = { 92 .name = "PCIBUS", 93 .version_id = 1, 94 .minimum_version_id = 1, 95 .fields = (VMStateField[]) { 96 VMSTATE_INT32_EQUAL(nirq, PCIBus, NULL), 97 VMSTATE_VARRAY_INT32(irq_count, PCIBus, 98 nirq, 0, vmstate_info_int32, 99 int32_t), 100 VMSTATE_END_OF_LIST() 101 } 102 }; 103 104 static gint g_cmp_uint32(gconstpointer a, gconstpointer b, gpointer user_data) 105 { 106 return a - b; 107 } 108 109 static GSequence *pci_acpi_index_list(void) 110 { 111 static GSequence *used_acpi_index_list; 112 113 if (!used_acpi_index_list) { 114 used_acpi_index_list = g_sequence_new(NULL); 115 } 116 return used_acpi_index_list; 117 } 118 119 static void pci_init_bus_master(PCIDevice *pci_dev) 120 { 121 AddressSpace *dma_as = pci_device_iommu_address_space(pci_dev); 122 123 memory_region_init_alias(&pci_dev->bus_master_enable_region, 124 OBJECT(pci_dev), "bus master", 125 dma_as->root, 0, memory_region_size(dma_as->root)); 126 memory_region_set_enabled(&pci_dev->bus_master_enable_region, false); 127 memory_region_add_subregion(&pci_dev->bus_master_container_region, 0, 128 &pci_dev->bus_master_enable_region); 129 } 130 131 static void pcibus_machine_done(Notifier *notifier, void *data) 132 { 133 PCIBus *bus = container_of(notifier, PCIBus, machine_done); 134 int i; 135 136 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 137 if (bus->devices[i]) { 138 pci_init_bus_master(bus->devices[i]); 139 } 140 } 141 } 142 143 static void pci_bus_realize(BusState *qbus, Error **errp) 144 { 145 PCIBus *bus = PCI_BUS(qbus); 146 147 bus->machine_done.notify = pcibus_machine_done; 148 qemu_add_machine_init_done_notifier(&bus->machine_done); 149 150 vmstate_register_any(NULL, &vmstate_pcibus, bus); 151 } 152 153 static void pcie_bus_realize(BusState *qbus, Error **errp) 154 { 155 PCIBus *bus = PCI_BUS(qbus); 156 Error *local_err = NULL; 157 158 pci_bus_realize(qbus, &local_err); 159 if (local_err) { 160 error_propagate(errp, local_err); 161 return; 162 } 163 164 /* 165 * A PCI-E bus can support extended config space if it's the root 166 * bus, or if the bus/bridge above it does as well 167 */ 168 if (pci_bus_is_root(bus)) { 169 bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE; 170 } else { 171 PCIBus *parent_bus = pci_get_bus(bus->parent_dev); 172 173 if (pci_bus_allows_extended_config_space(parent_bus)) { 174 bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE; 175 } 176 } 177 } 178 179 static void pci_bus_unrealize(BusState *qbus) 180 { 181 PCIBus *bus = PCI_BUS(qbus); 182 183 qemu_remove_machine_init_done_notifier(&bus->machine_done); 184 185 vmstate_unregister(NULL, &vmstate_pcibus, bus); 186 } 187 188 static int pcibus_num(PCIBus *bus) 189 { 190 if (pci_bus_is_root(bus)) { 191 return 0; /* pci host bridge */ 192 } 193 return bus->parent_dev->config[PCI_SECONDARY_BUS]; 194 } 195 196 static uint16_t pcibus_numa_node(PCIBus *bus) 197 { 198 return NUMA_NODE_UNASSIGNED; 199 } 200 201 static void pci_bus_class_init(ObjectClass *klass, void *data) 202 { 203 BusClass *k = BUS_CLASS(klass); 204 PCIBusClass *pbc = PCI_BUS_CLASS(klass); 205 206 k->print_dev = pcibus_dev_print; 207 k->get_dev_path = pcibus_get_dev_path; 208 k->get_fw_dev_path = pcibus_get_fw_dev_path; 209 k->realize = pci_bus_realize; 210 k->unrealize = pci_bus_unrealize; 211 k->reset = pcibus_reset; 212 213 pbc->bus_num = pcibus_num; 214 pbc->numa_node = pcibus_numa_node; 215 } 216 217 static const TypeInfo pci_bus_info = { 218 .name = TYPE_PCI_BUS, 219 .parent = TYPE_BUS, 220 .instance_size = sizeof(PCIBus), 221 .class_size = sizeof(PCIBusClass), 222 .class_init = pci_bus_class_init, 223 }; 224 225 static const TypeInfo cxl_interface_info = { 226 .name = INTERFACE_CXL_DEVICE, 227 .parent = TYPE_INTERFACE, 228 }; 229 230 static const TypeInfo pcie_interface_info = { 231 .name = INTERFACE_PCIE_DEVICE, 232 .parent = TYPE_INTERFACE, 233 }; 234 235 static const TypeInfo conventional_pci_interface_info = { 236 .name = INTERFACE_CONVENTIONAL_PCI_DEVICE, 237 .parent = TYPE_INTERFACE, 238 }; 239 240 static void pcie_bus_class_init(ObjectClass *klass, void *data) 241 { 242 BusClass *k = BUS_CLASS(klass); 243 244 k->realize = pcie_bus_realize; 245 } 246 247 static const TypeInfo pcie_bus_info = { 248 .name = TYPE_PCIE_BUS, 249 .parent = TYPE_PCI_BUS, 250 .class_init = pcie_bus_class_init, 251 }; 252 253 static const TypeInfo cxl_bus_info = { 254 .name = TYPE_CXL_BUS, 255 .parent = TYPE_PCIE_BUS, 256 .class_init = pcie_bus_class_init, 257 }; 258 259 static void pci_update_mappings(PCIDevice *d); 260 static void pci_irq_handler(void *opaque, int irq_num, int level); 261 static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, Error **); 262 static void pci_del_option_rom(PCIDevice *pdev); 263 264 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET; 265 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU; 266 267 PCIHostStateList pci_host_bridges; 268 269 int pci_bar(PCIDevice *d, int reg) 270 { 271 uint8_t type; 272 273 /* PCIe virtual functions do not have their own BARs */ 274 assert(!pci_is_vf(d)); 275 276 if (reg != PCI_ROM_SLOT) 277 return PCI_BASE_ADDRESS_0 + reg * 4; 278 279 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 280 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS; 281 } 282 283 static inline int pci_irq_state(PCIDevice *d, int irq_num) 284 { 285 return (d->irq_state >> irq_num) & 0x1; 286 } 287 288 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level) 289 { 290 d->irq_state &= ~(0x1 << irq_num); 291 d->irq_state |= level << irq_num; 292 } 293 294 static void pci_bus_change_irq_level(PCIBus *bus, int irq_num, int change) 295 { 296 assert(irq_num >= 0); 297 assert(irq_num < bus->nirq); 298 bus->irq_count[irq_num] += change; 299 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0); 300 } 301 302 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change) 303 { 304 PCIBus *bus; 305 for (;;) { 306 int dev_irq = irq_num; 307 bus = pci_get_bus(pci_dev); 308 assert(bus->map_irq); 309 irq_num = bus->map_irq(pci_dev, irq_num); 310 trace_pci_route_irq(dev_irq, DEVICE(pci_dev)->canonical_path, irq_num, 311 pci_bus_is_root(bus) ? "root-complex" 312 : DEVICE(bus->parent_dev)->canonical_path); 313 if (bus->set_irq) 314 break; 315 pci_dev = bus->parent_dev; 316 } 317 pci_bus_change_irq_level(bus, irq_num, change); 318 } 319 320 int pci_bus_get_irq_level(PCIBus *bus, int irq_num) 321 { 322 assert(irq_num >= 0); 323 assert(irq_num < bus->nirq); 324 return !!bus->irq_count[irq_num]; 325 } 326 327 /* Update interrupt status bit in config space on interrupt 328 * state change. */ 329 static void pci_update_irq_status(PCIDevice *dev) 330 { 331 if (dev->irq_state) { 332 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT; 333 } else { 334 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; 335 } 336 } 337 338 void pci_device_deassert_intx(PCIDevice *dev) 339 { 340 int i; 341 for (i = 0; i < PCI_NUM_PINS; ++i) { 342 pci_irq_handler(dev, i, 0); 343 } 344 } 345 346 static void pci_msi_trigger(PCIDevice *dev, MSIMessage msg) 347 { 348 MemTxAttrs attrs = {}; 349 350 /* 351 * Xen uses the high bits of the address to contain some of the bits 352 * of the PIRQ#. Therefore we can't just send the write cycle and 353 * trust that it's caught by the APIC at 0xfee00000 because the 354 * target of the write might be e.g. 0x0x1000fee46000 for PIRQ#4166. 355 * So we intercept the delivery here instead of in kvm_send_msi(). 356 */ 357 if (xen_mode == XEN_EMULATE && 358 xen_evtchn_deliver_pirq_msi(msg.address, msg.data)) { 359 return; 360 } 361 attrs.requester_id = pci_requester_id(dev); 362 address_space_stl_le(&dev->bus_master_as, msg.address, msg.data, 363 attrs, NULL); 364 } 365 366 static void pci_reset_regions(PCIDevice *dev) 367 { 368 int r; 369 if (pci_is_vf(dev)) { 370 return; 371 } 372 373 for (r = 0; r < PCI_NUM_REGIONS; ++r) { 374 PCIIORegion *region = &dev->io_regions[r]; 375 if (!region->size) { 376 continue; 377 } 378 379 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) && 380 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 381 pci_set_quad(dev->config + pci_bar(dev, r), region->type); 382 } else { 383 pci_set_long(dev->config + pci_bar(dev, r), region->type); 384 } 385 } 386 } 387 388 static void pci_do_device_reset(PCIDevice *dev) 389 { 390 pci_device_deassert_intx(dev); 391 assert(dev->irq_state == 0); 392 393 /* Clear all writable bits */ 394 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND, 395 pci_get_word(dev->wmask + PCI_COMMAND) | 396 pci_get_word(dev->w1cmask + PCI_COMMAND)); 397 pci_word_test_and_clear_mask(dev->config + PCI_STATUS, 398 pci_get_word(dev->wmask + PCI_STATUS) | 399 pci_get_word(dev->w1cmask + PCI_STATUS)); 400 /* Some devices make bits of PCI_INTERRUPT_LINE read only */ 401 pci_byte_test_and_clear_mask(dev->config + PCI_INTERRUPT_LINE, 402 pci_get_word(dev->wmask + PCI_INTERRUPT_LINE) | 403 pci_get_word(dev->w1cmask + PCI_INTERRUPT_LINE)); 404 dev->config[PCI_CACHE_LINE_SIZE] = 0x0; 405 pci_reset_regions(dev); 406 pci_update_mappings(dev); 407 408 msi_reset(dev); 409 msix_reset(dev); 410 } 411 412 /* 413 * This function is called on #RST and FLR. 414 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set 415 */ 416 void pci_device_reset(PCIDevice *dev) 417 { 418 device_cold_reset(&dev->qdev); 419 pci_do_device_reset(dev); 420 } 421 422 /* 423 * Trigger pci bus reset under a given bus. 424 * Called via bus_cold_reset on RST# assert, after the devices 425 * have been reset device_cold_reset-ed already. 426 */ 427 static void pcibus_reset(BusState *qbus) 428 { 429 PCIBus *bus = DO_UPCAST(PCIBus, qbus, qbus); 430 int i; 431 432 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 433 if (bus->devices[i]) { 434 pci_do_device_reset(bus->devices[i]); 435 } 436 } 437 438 for (i = 0; i < bus->nirq; i++) { 439 assert(bus->irq_count[i] == 0); 440 } 441 } 442 443 static void pci_host_bus_register(DeviceState *host) 444 { 445 PCIHostState *host_bridge = PCI_HOST_BRIDGE(host); 446 447 QLIST_INSERT_HEAD(&pci_host_bridges, host_bridge, next); 448 } 449 450 static void pci_host_bus_unregister(DeviceState *host) 451 { 452 PCIHostState *host_bridge = PCI_HOST_BRIDGE(host); 453 454 QLIST_REMOVE(host_bridge, next); 455 } 456 457 PCIBus *pci_device_root_bus(const PCIDevice *d) 458 { 459 PCIBus *bus = pci_get_bus(d); 460 461 while (!pci_bus_is_root(bus)) { 462 d = bus->parent_dev; 463 assert(d != NULL); 464 465 bus = pci_get_bus(d); 466 } 467 468 return bus; 469 } 470 471 const char *pci_root_bus_path(PCIDevice *dev) 472 { 473 PCIBus *rootbus = pci_device_root_bus(dev); 474 PCIHostState *host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent); 475 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_GET_CLASS(host_bridge); 476 477 assert(host_bridge->bus == rootbus); 478 479 if (hc->root_bus_path) { 480 return (*hc->root_bus_path)(host_bridge, rootbus); 481 } 482 483 return rootbus->qbus.name; 484 } 485 486 bool pci_bus_bypass_iommu(PCIBus *bus) 487 { 488 PCIBus *rootbus = bus; 489 PCIHostState *host_bridge; 490 491 if (!pci_bus_is_root(bus)) { 492 rootbus = pci_device_root_bus(bus->parent_dev); 493 } 494 495 host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent); 496 497 assert(host_bridge->bus == rootbus); 498 499 return host_bridge->bypass_iommu; 500 } 501 502 static void pci_root_bus_internal_init(PCIBus *bus, DeviceState *parent, 503 MemoryRegion *mem, MemoryRegion *io, 504 uint8_t devfn_min) 505 { 506 assert(PCI_FUNC(devfn_min) == 0); 507 bus->devfn_min = devfn_min; 508 bus->slot_reserved_mask = 0x0; 509 bus->address_space_mem = mem; 510 bus->address_space_io = io; 511 bus->flags |= PCI_BUS_IS_ROOT; 512 513 /* host bridge */ 514 QLIST_INIT(&bus->child); 515 516 pci_host_bus_register(parent); 517 } 518 519 static void pci_bus_uninit(PCIBus *bus) 520 { 521 pci_host_bus_unregister(BUS(bus)->parent); 522 } 523 524 bool pci_bus_is_express(const PCIBus *bus) 525 { 526 return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS); 527 } 528 529 void pci_root_bus_init(PCIBus *bus, size_t bus_size, DeviceState *parent, 530 const char *name, 531 MemoryRegion *mem, MemoryRegion *io, 532 uint8_t devfn_min, const char *typename) 533 { 534 qbus_init(bus, bus_size, typename, parent, name); 535 pci_root_bus_internal_init(bus, parent, mem, io, devfn_min); 536 } 537 538 PCIBus *pci_root_bus_new(DeviceState *parent, const char *name, 539 MemoryRegion *mem, MemoryRegion *io, 540 uint8_t devfn_min, const char *typename) 541 { 542 PCIBus *bus; 543 544 bus = PCI_BUS(qbus_new(typename, parent, name)); 545 pci_root_bus_internal_init(bus, parent, mem, io, devfn_min); 546 return bus; 547 } 548 549 void pci_root_bus_cleanup(PCIBus *bus) 550 { 551 pci_bus_uninit(bus); 552 /* the caller of the unplug hotplug handler will delete this device */ 553 qbus_unrealize(BUS(bus)); 554 } 555 556 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, 557 void *irq_opaque, int nirq) 558 { 559 bus->set_irq = set_irq; 560 bus->irq_opaque = irq_opaque; 561 bus->nirq = nirq; 562 g_free(bus->irq_count); 563 bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0])); 564 } 565 566 void pci_bus_map_irqs(PCIBus *bus, pci_map_irq_fn map_irq) 567 { 568 bus->map_irq = map_irq; 569 } 570 571 void pci_bus_irqs_cleanup(PCIBus *bus) 572 { 573 bus->set_irq = NULL; 574 bus->map_irq = NULL; 575 bus->irq_opaque = NULL; 576 bus->nirq = 0; 577 g_free(bus->irq_count); 578 bus->irq_count = NULL; 579 } 580 581 PCIBus *pci_register_root_bus(DeviceState *parent, const char *name, 582 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 583 void *irq_opaque, 584 MemoryRegion *mem, MemoryRegion *io, 585 uint8_t devfn_min, int nirq, 586 const char *typename) 587 { 588 PCIBus *bus; 589 590 bus = pci_root_bus_new(parent, name, mem, io, devfn_min, typename); 591 pci_bus_irqs(bus, set_irq, irq_opaque, nirq); 592 pci_bus_map_irqs(bus, map_irq); 593 return bus; 594 } 595 596 void pci_unregister_root_bus(PCIBus *bus) 597 { 598 pci_bus_irqs_cleanup(bus); 599 pci_root_bus_cleanup(bus); 600 } 601 602 int pci_bus_num(PCIBus *s) 603 { 604 return PCI_BUS_GET_CLASS(s)->bus_num(s); 605 } 606 607 /* Returns the min and max bus numbers of a PCI bus hierarchy */ 608 void pci_bus_range(PCIBus *bus, int *min_bus, int *max_bus) 609 { 610 int i; 611 *min_bus = *max_bus = pci_bus_num(bus); 612 613 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 614 PCIDevice *dev = bus->devices[i]; 615 616 if (dev && IS_PCI_BRIDGE(dev)) { 617 *min_bus = MIN(*min_bus, dev->config[PCI_SECONDARY_BUS]); 618 *max_bus = MAX(*max_bus, dev->config[PCI_SUBORDINATE_BUS]); 619 } 620 } 621 } 622 623 int pci_bus_numa_node(PCIBus *bus) 624 { 625 return PCI_BUS_GET_CLASS(bus)->numa_node(bus); 626 } 627 628 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size, 629 const VMStateField *field) 630 { 631 PCIDevice *s = container_of(pv, PCIDevice, config); 632 uint8_t *config; 633 int i; 634 635 assert(size == pci_config_size(s)); 636 config = g_malloc(size); 637 638 qemu_get_buffer(f, config, size); 639 for (i = 0; i < size; ++i) { 640 if ((config[i] ^ s->config[i]) & 641 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) { 642 error_report("%s: Bad config data: i=0x%x read: %x device: %x " 643 "cmask: %x wmask: %x w1cmask:%x", __func__, 644 i, config[i], s->config[i], 645 s->cmask[i], s->wmask[i], s->w1cmask[i]); 646 g_free(config); 647 return -EINVAL; 648 } 649 } 650 memcpy(s->config, config, size); 651 652 pci_update_mappings(s); 653 if (IS_PCI_BRIDGE(s)) { 654 pci_bridge_update_mappings(PCI_BRIDGE(s)); 655 } 656 657 memory_region_set_enabled(&s->bus_master_enable_region, 658 pci_get_word(s->config + PCI_COMMAND) 659 & PCI_COMMAND_MASTER); 660 661 g_free(config); 662 return 0; 663 } 664 665 /* just put buffer */ 666 static int put_pci_config_device(QEMUFile *f, void *pv, size_t size, 667 const VMStateField *field, JSONWriter *vmdesc) 668 { 669 const uint8_t **v = pv; 670 assert(size == pci_config_size(container_of(pv, PCIDevice, config))); 671 qemu_put_buffer(f, *v, size); 672 673 return 0; 674 } 675 676 static VMStateInfo vmstate_info_pci_config = { 677 .name = "pci config", 678 .get = get_pci_config_device, 679 .put = put_pci_config_device, 680 }; 681 682 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size, 683 const VMStateField *field) 684 { 685 PCIDevice *s = container_of(pv, PCIDevice, irq_state); 686 uint32_t irq_state[PCI_NUM_PINS]; 687 int i; 688 for (i = 0; i < PCI_NUM_PINS; ++i) { 689 irq_state[i] = qemu_get_be32(f); 690 if (irq_state[i] != 0x1 && irq_state[i] != 0) { 691 fprintf(stderr, "irq state %d: must be 0 or 1.\n", 692 irq_state[i]); 693 return -EINVAL; 694 } 695 } 696 697 for (i = 0; i < PCI_NUM_PINS; ++i) { 698 pci_set_irq_state(s, i, irq_state[i]); 699 } 700 701 return 0; 702 } 703 704 static int put_pci_irq_state(QEMUFile *f, void *pv, size_t size, 705 const VMStateField *field, JSONWriter *vmdesc) 706 { 707 int i; 708 PCIDevice *s = container_of(pv, PCIDevice, irq_state); 709 710 for (i = 0; i < PCI_NUM_PINS; ++i) { 711 qemu_put_be32(f, pci_irq_state(s, i)); 712 } 713 714 return 0; 715 } 716 717 static VMStateInfo vmstate_info_pci_irq_state = { 718 .name = "pci irq state", 719 .get = get_pci_irq_state, 720 .put = put_pci_irq_state, 721 }; 722 723 static bool migrate_is_pcie(void *opaque, int version_id) 724 { 725 return pci_is_express((PCIDevice *)opaque); 726 } 727 728 static bool migrate_is_not_pcie(void *opaque, int version_id) 729 { 730 return !pci_is_express((PCIDevice *)opaque); 731 } 732 733 const VMStateDescription vmstate_pci_device = { 734 .name = "PCIDevice", 735 .version_id = 2, 736 .minimum_version_id = 1, 737 .fields = (VMStateField[]) { 738 VMSTATE_INT32_POSITIVE_LE(version_id, PCIDevice), 739 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice, 740 migrate_is_not_pcie, 741 0, vmstate_info_pci_config, 742 PCI_CONFIG_SPACE_SIZE), 743 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice, 744 migrate_is_pcie, 745 0, vmstate_info_pci_config, 746 PCIE_CONFIG_SPACE_SIZE), 747 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2, 748 vmstate_info_pci_irq_state, 749 PCI_NUM_PINS * sizeof(int32_t)), 750 VMSTATE_END_OF_LIST() 751 } 752 }; 753 754 755 void pci_device_save(PCIDevice *s, QEMUFile *f) 756 { 757 /* Clear interrupt status bit: it is implicit 758 * in irq_state which we are saving. 759 * This makes us compatible with old devices 760 * which never set or clear this bit. */ 761 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; 762 vmstate_save_state(f, &vmstate_pci_device, s, NULL); 763 /* Restore the interrupt status bit. */ 764 pci_update_irq_status(s); 765 } 766 767 int pci_device_load(PCIDevice *s, QEMUFile *f) 768 { 769 int ret; 770 ret = vmstate_load_state(f, &vmstate_pci_device, s, s->version_id); 771 /* Restore the interrupt status bit. */ 772 pci_update_irq_status(s); 773 return ret; 774 } 775 776 static void pci_set_default_subsystem_id(PCIDevice *pci_dev) 777 { 778 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, 779 pci_default_sub_vendor_id); 780 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 781 pci_default_sub_device_id); 782 } 783 784 /* 785 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL 786 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error 787 */ 788 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, 789 unsigned int *slotp, unsigned int *funcp) 790 { 791 const char *p; 792 char *e; 793 unsigned long val; 794 unsigned long dom = 0, bus = 0; 795 unsigned int slot = 0; 796 unsigned int func = 0; 797 798 p = addr; 799 val = strtoul(p, &e, 16); 800 if (e == p) 801 return -1; 802 if (*e == ':') { 803 bus = val; 804 p = e + 1; 805 val = strtoul(p, &e, 16); 806 if (e == p) 807 return -1; 808 if (*e == ':') { 809 dom = bus; 810 bus = val; 811 p = e + 1; 812 val = strtoul(p, &e, 16); 813 if (e == p) 814 return -1; 815 } 816 } 817 818 slot = val; 819 820 if (funcp != NULL) { 821 if (*e != '.') 822 return -1; 823 824 p = e + 1; 825 val = strtoul(p, &e, 16); 826 if (e == p) 827 return -1; 828 829 func = val; 830 } 831 832 /* if funcp == NULL func is 0 */ 833 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7) 834 return -1; 835 836 if (*e) 837 return -1; 838 839 *domp = dom; 840 *busp = bus; 841 *slotp = slot; 842 if (funcp != NULL) 843 *funcp = func; 844 return 0; 845 } 846 847 static void pci_init_cmask(PCIDevice *dev) 848 { 849 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff); 850 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff); 851 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST; 852 dev->cmask[PCI_REVISION_ID] = 0xff; 853 dev->cmask[PCI_CLASS_PROG] = 0xff; 854 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff); 855 dev->cmask[PCI_HEADER_TYPE] = 0xff; 856 dev->cmask[PCI_CAPABILITY_LIST] = 0xff; 857 } 858 859 static void pci_init_wmask(PCIDevice *dev) 860 { 861 int config_size = pci_config_size(dev); 862 863 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff; 864 dev->wmask[PCI_INTERRUPT_LINE] = 0xff; 865 pci_set_word(dev->wmask + PCI_COMMAND, 866 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | 867 PCI_COMMAND_INTX_DISABLE); 868 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR); 869 870 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff, 871 config_size - PCI_CONFIG_HEADER_SIZE); 872 } 873 874 static void pci_init_w1cmask(PCIDevice *dev) 875 { 876 /* 877 * Note: It's okay to set w1cmask even for readonly bits as 878 * long as their value is hardwired to 0. 879 */ 880 pci_set_word(dev->w1cmask + PCI_STATUS, 881 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT | 882 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT | 883 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY); 884 } 885 886 static void pci_init_mask_bridge(PCIDevice *d) 887 { 888 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and 889 PCI_SEC_LATENCY_TIMER */ 890 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4); 891 892 /* base and limit */ 893 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff; 894 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff; 895 pci_set_word(d->wmask + PCI_MEMORY_BASE, 896 PCI_MEMORY_RANGE_MASK & 0xffff); 897 pci_set_word(d->wmask + PCI_MEMORY_LIMIT, 898 PCI_MEMORY_RANGE_MASK & 0xffff); 899 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE, 900 PCI_PREF_RANGE_MASK & 0xffff); 901 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT, 902 PCI_PREF_RANGE_MASK & 0xffff); 903 904 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */ 905 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8); 906 907 /* Supported memory and i/o types */ 908 d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16; 909 d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16; 910 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE, 911 PCI_PREF_RANGE_TYPE_64); 912 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT, 913 PCI_PREF_RANGE_TYPE_64); 914 915 /* 916 * TODO: Bridges default to 10-bit VGA decoding but we currently only 917 * implement 16-bit decoding (no alias support). 918 */ 919 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 920 PCI_BRIDGE_CTL_PARITY | 921 PCI_BRIDGE_CTL_SERR | 922 PCI_BRIDGE_CTL_ISA | 923 PCI_BRIDGE_CTL_VGA | 924 PCI_BRIDGE_CTL_VGA_16BIT | 925 PCI_BRIDGE_CTL_MASTER_ABORT | 926 PCI_BRIDGE_CTL_BUS_RESET | 927 PCI_BRIDGE_CTL_FAST_BACK | 928 PCI_BRIDGE_CTL_DISCARD | 929 PCI_BRIDGE_CTL_SEC_DISCARD | 930 PCI_BRIDGE_CTL_DISCARD_SERR); 931 /* Below does not do anything as we never set this bit, put here for 932 * completeness. */ 933 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL, 934 PCI_BRIDGE_CTL_DISCARD_STATUS); 935 d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK; 936 d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK; 937 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE, 938 PCI_PREF_RANGE_TYPE_MASK); 939 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT, 940 PCI_PREF_RANGE_TYPE_MASK); 941 } 942 943 static void pci_init_multifunction(PCIBus *bus, PCIDevice *dev, Error **errp) 944 { 945 uint8_t slot = PCI_SLOT(dev->devfn); 946 uint8_t func; 947 948 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 949 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION; 950 } 951 952 /* 953 * With SR/IOV and ARI, a device at function 0 need not be a multifunction 954 * device, as it may just be a VF that ended up with function 0 in 955 * the legacy PCI interpretation. Avoid failing in such cases: 956 */ 957 if (pci_is_vf(dev) && 958 dev->exp.sriov_vf.pf->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 959 return; 960 } 961 962 /* 963 * multifunction bit is interpreted in two ways as follows. 964 * - all functions must set the bit to 1. 965 * Example: Intel X53 966 * - function 0 must set the bit, but the rest function (> 0) 967 * is allowed to leave the bit to 0. 968 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10, 969 * 970 * So OS (at least Linux) checks the bit of only function 0, 971 * and doesn't see the bit of function > 0. 972 * 973 * The below check allows both interpretation. 974 */ 975 if (PCI_FUNC(dev->devfn)) { 976 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)]; 977 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) { 978 /* function 0 should set multifunction bit */ 979 error_setg(errp, "PCI: single function device can't be populated " 980 "in function %x.%x", slot, PCI_FUNC(dev->devfn)); 981 return; 982 } 983 return; 984 } 985 986 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 987 return; 988 } 989 /* function 0 indicates single function, so function > 0 must be NULL */ 990 for (func = 1; func < PCI_FUNC_MAX; ++func) { 991 if (bus->devices[PCI_DEVFN(slot, func)]) { 992 error_setg(errp, "PCI: %x.0 indicates single function, " 993 "but %x.%x is already populated.", 994 slot, slot, func); 995 return; 996 } 997 } 998 } 999 1000 static void pci_config_alloc(PCIDevice *pci_dev) 1001 { 1002 int config_size = pci_config_size(pci_dev); 1003 1004 pci_dev->config = g_malloc0(config_size); 1005 pci_dev->cmask = g_malloc0(config_size); 1006 pci_dev->wmask = g_malloc0(config_size); 1007 pci_dev->w1cmask = g_malloc0(config_size); 1008 pci_dev->used = g_malloc0(config_size); 1009 } 1010 1011 static void pci_config_free(PCIDevice *pci_dev) 1012 { 1013 g_free(pci_dev->config); 1014 g_free(pci_dev->cmask); 1015 g_free(pci_dev->wmask); 1016 g_free(pci_dev->w1cmask); 1017 g_free(pci_dev->used); 1018 } 1019 1020 static void do_pci_unregister_device(PCIDevice *pci_dev) 1021 { 1022 pci_get_bus(pci_dev)->devices[pci_dev->devfn] = NULL; 1023 pci_config_free(pci_dev); 1024 1025 if (xen_mode == XEN_EMULATE) { 1026 xen_evtchn_remove_pci_device(pci_dev); 1027 } 1028 if (memory_region_is_mapped(&pci_dev->bus_master_enable_region)) { 1029 memory_region_del_subregion(&pci_dev->bus_master_container_region, 1030 &pci_dev->bus_master_enable_region); 1031 } 1032 address_space_destroy(&pci_dev->bus_master_as); 1033 } 1034 1035 /* Extract PCIReqIDCache into BDF format */ 1036 static uint16_t pci_req_id_cache_extract(PCIReqIDCache *cache) 1037 { 1038 uint8_t bus_n; 1039 uint16_t result; 1040 1041 switch (cache->type) { 1042 case PCI_REQ_ID_BDF: 1043 result = pci_get_bdf(cache->dev); 1044 break; 1045 case PCI_REQ_ID_SECONDARY_BUS: 1046 bus_n = pci_dev_bus_num(cache->dev); 1047 result = PCI_BUILD_BDF(bus_n, 0); 1048 break; 1049 default: 1050 error_report("Invalid PCI requester ID cache type: %d", 1051 cache->type); 1052 exit(1); 1053 break; 1054 } 1055 1056 return result; 1057 } 1058 1059 /* Parse bridges up to the root complex and return requester ID 1060 * cache for specific device. For full PCIe topology, the cache 1061 * result would be exactly the same as getting BDF of the device. 1062 * However, several tricks are required when system mixed up with 1063 * legacy PCI devices and PCIe-to-PCI bridges. 1064 * 1065 * Here we cache the proxy device (and type) not requester ID since 1066 * bus number might change from time to time. 1067 */ 1068 static PCIReqIDCache pci_req_id_cache_get(PCIDevice *dev) 1069 { 1070 PCIDevice *parent; 1071 PCIReqIDCache cache = { 1072 .dev = dev, 1073 .type = PCI_REQ_ID_BDF, 1074 }; 1075 1076 while (!pci_bus_is_root(pci_get_bus(dev))) { 1077 /* We are under PCI/PCIe bridges */ 1078 parent = pci_get_bus(dev)->parent_dev; 1079 if (pci_is_express(parent)) { 1080 if (pcie_cap_get_type(parent) == PCI_EXP_TYPE_PCI_BRIDGE) { 1081 /* When we pass through PCIe-to-PCI/PCIX bridges, we 1082 * override the requester ID using secondary bus 1083 * number of parent bridge with zeroed devfn 1084 * (pcie-to-pci bridge spec chap 2.3). */ 1085 cache.type = PCI_REQ_ID_SECONDARY_BUS; 1086 cache.dev = dev; 1087 } 1088 } else { 1089 /* Legacy PCI, override requester ID with the bridge's 1090 * BDF upstream. When the root complex connects to 1091 * legacy PCI devices (including buses), it can only 1092 * obtain requester ID info from directly attached 1093 * devices. If devices are attached under bridges, only 1094 * the requester ID of the bridge that is directly 1095 * attached to the root complex can be recognized. */ 1096 cache.type = PCI_REQ_ID_BDF; 1097 cache.dev = parent; 1098 } 1099 dev = parent; 1100 } 1101 1102 return cache; 1103 } 1104 1105 uint16_t pci_requester_id(PCIDevice *dev) 1106 { 1107 return pci_req_id_cache_extract(&dev->requester_id_cache); 1108 } 1109 1110 static bool pci_bus_devfn_available(PCIBus *bus, int devfn) 1111 { 1112 return !(bus->devices[devfn]); 1113 } 1114 1115 static bool pci_bus_devfn_reserved(PCIBus *bus, int devfn) 1116 { 1117 return bus->slot_reserved_mask & (1UL << PCI_SLOT(devfn)); 1118 } 1119 1120 uint32_t pci_bus_get_slot_reserved_mask(PCIBus *bus) 1121 { 1122 return bus->slot_reserved_mask; 1123 } 1124 1125 void pci_bus_set_slot_reserved_mask(PCIBus *bus, uint32_t mask) 1126 { 1127 bus->slot_reserved_mask |= mask; 1128 } 1129 1130 void pci_bus_clear_slot_reserved_mask(PCIBus *bus, uint32_t mask) 1131 { 1132 bus->slot_reserved_mask &= ~mask; 1133 } 1134 1135 /* -1 for devfn means auto assign */ 1136 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, 1137 const char *name, int devfn, 1138 Error **errp) 1139 { 1140 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 1141 PCIConfigReadFunc *config_read = pc->config_read; 1142 PCIConfigWriteFunc *config_write = pc->config_write; 1143 Error *local_err = NULL; 1144 DeviceState *dev = DEVICE(pci_dev); 1145 PCIBus *bus = pci_get_bus(pci_dev); 1146 bool is_bridge = IS_PCI_BRIDGE(pci_dev); 1147 1148 /* Only pci bridges can be attached to extra PCI root buses */ 1149 if (pci_bus_is_root(bus) && bus->parent_dev && !is_bridge) { 1150 error_setg(errp, 1151 "PCI: Only PCI/PCIe bridges can be plugged into %s", 1152 bus->parent_dev->name); 1153 return NULL; 1154 } 1155 1156 if (devfn < 0) { 1157 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices); 1158 devfn += PCI_FUNC_MAX) { 1159 if (pci_bus_devfn_available(bus, devfn) && 1160 !pci_bus_devfn_reserved(bus, devfn)) { 1161 goto found; 1162 } 1163 } 1164 error_setg(errp, "PCI: no slot/function available for %s, all in use " 1165 "or reserved", name); 1166 return NULL; 1167 found: ; 1168 } else if (pci_bus_devfn_reserved(bus, devfn)) { 1169 error_setg(errp, "PCI: slot %d function %d not available for %s," 1170 " reserved", 1171 PCI_SLOT(devfn), PCI_FUNC(devfn), name); 1172 return NULL; 1173 } else if (!pci_bus_devfn_available(bus, devfn)) { 1174 error_setg(errp, "PCI: slot %d function %d not available for %s," 1175 " in use by %s,id=%s", 1176 PCI_SLOT(devfn), PCI_FUNC(devfn), name, 1177 bus->devices[devfn]->name, bus->devices[devfn]->qdev.id); 1178 return NULL; 1179 } /* 1180 * Populating function 0 triggers a scan from the guest that 1181 * exposes other non-zero functions. Hence we need to ensure that 1182 * function 0 wasn't added yet. 1183 */ 1184 else if (dev->hotplugged && 1185 !pci_is_vf(pci_dev) && 1186 pci_get_function_0(pci_dev)) { 1187 error_setg(errp, "PCI: slot %d function 0 already occupied by %s," 1188 " new func %s cannot be exposed to guest.", 1189 PCI_SLOT(pci_get_function_0(pci_dev)->devfn), 1190 pci_get_function_0(pci_dev)->name, 1191 name); 1192 1193 return NULL; 1194 } 1195 1196 pci_dev->devfn = devfn; 1197 pci_dev->requester_id_cache = pci_req_id_cache_get(pci_dev); 1198 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name); 1199 1200 memory_region_init(&pci_dev->bus_master_container_region, OBJECT(pci_dev), 1201 "bus master container", UINT64_MAX); 1202 address_space_init(&pci_dev->bus_master_as, 1203 &pci_dev->bus_master_container_region, pci_dev->name); 1204 1205 if (phase_check(PHASE_MACHINE_READY)) { 1206 pci_init_bus_master(pci_dev); 1207 } 1208 pci_dev->irq_state = 0; 1209 pci_config_alloc(pci_dev); 1210 1211 pci_config_set_vendor_id(pci_dev->config, pc->vendor_id); 1212 pci_config_set_device_id(pci_dev->config, pc->device_id); 1213 pci_config_set_revision(pci_dev->config, pc->revision); 1214 pci_config_set_class(pci_dev->config, pc->class_id); 1215 1216 if (!is_bridge) { 1217 if (pc->subsystem_vendor_id || pc->subsystem_id) { 1218 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, 1219 pc->subsystem_vendor_id); 1220 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 1221 pc->subsystem_id); 1222 } else { 1223 pci_set_default_subsystem_id(pci_dev); 1224 } 1225 } else { 1226 /* subsystem_vendor_id/subsystem_id are only for header type 0 */ 1227 assert(!pc->subsystem_vendor_id); 1228 assert(!pc->subsystem_id); 1229 } 1230 pci_init_cmask(pci_dev); 1231 pci_init_wmask(pci_dev); 1232 pci_init_w1cmask(pci_dev); 1233 if (is_bridge) { 1234 pci_init_mask_bridge(pci_dev); 1235 } 1236 pci_init_multifunction(bus, pci_dev, &local_err); 1237 if (local_err) { 1238 error_propagate(errp, local_err); 1239 do_pci_unregister_device(pci_dev); 1240 return NULL; 1241 } 1242 1243 if (!config_read) 1244 config_read = pci_default_read_config; 1245 if (!config_write) 1246 config_write = pci_default_write_config; 1247 pci_dev->config_read = config_read; 1248 pci_dev->config_write = config_write; 1249 bus->devices[devfn] = pci_dev; 1250 pci_dev->version_id = 2; /* Current pci device vmstate version */ 1251 return pci_dev; 1252 } 1253 1254 static void pci_unregister_io_regions(PCIDevice *pci_dev) 1255 { 1256 PCIIORegion *r; 1257 int i; 1258 1259 for(i = 0; i < PCI_NUM_REGIONS; i++) { 1260 r = &pci_dev->io_regions[i]; 1261 if (!r->size || r->addr == PCI_BAR_UNMAPPED) 1262 continue; 1263 memory_region_del_subregion(r->address_space, r->memory); 1264 } 1265 1266 pci_unregister_vga(pci_dev); 1267 } 1268 1269 static void pci_qdev_unrealize(DeviceState *dev) 1270 { 1271 PCIDevice *pci_dev = PCI_DEVICE(dev); 1272 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 1273 1274 pci_unregister_io_regions(pci_dev); 1275 pci_del_option_rom(pci_dev); 1276 1277 if (pc->exit) { 1278 pc->exit(pci_dev); 1279 } 1280 1281 pci_device_deassert_intx(pci_dev); 1282 do_pci_unregister_device(pci_dev); 1283 1284 pci_dev->msi_trigger = NULL; 1285 1286 /* 1287 * clean up acpi-index so it could reused by another device 1288 */ 1289 if (pci_dev->acpi_index) { 1290 GSequence *used_indexes = pci_acpi_index_list(); 1291 1292 g_sequence_remove(g_sequence_lookup(used_indexes, 1293 GINT_TO_POINTER(pci_dev->acpi_index), 1294 g_cmp_uint32, NULL)); 1295 } 1296 } 1297 1298 void pci_register_bar(PCIDevice *pci_dev, int region_num, 1299 uint8_t type, MemoryRegion *memory) 1300 { 1301 PCIIORegion *r; 1302 uint32_t addr; /* offset in pci config space */ 1303 uint64_t wmask; 1304 pcibus_t size = memory_region_size(memory); 1305 uint8_t hdr_type; 1306 1307 assert(!pci_is_vf(pci_dev)); /* VFs must use pcie_sriov_vf_register_bar */ 1308 assert(region_num >= 0); 1309 assert(region_num < PCI_NUM_REGIONS); 1310 assert(is_power_of_2(size)); 1311 1312 /* A PCI bridge device (with Type 1 header) may only have at most 2 BARs */ 1313 hdr_type = 1314 pci_dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 1315 assert(hdr_type != PCI_HEADER_TYPE_BRIDGE || region_num < 2); 1316 1317 r = &pci_dev->io_regions[region_num]; 1318 r->addr = PCI_BAR_UNMAPPED; 1319 r->size = size; 1320 r->type = type; 1321 r->memory = memory; 1322 r->address_space = type & PCI_BASE_ADDRESS_SPACE_IO 1323 ? pci_get_bus(pci_dev)->address_space_io 1324 : pci_get_bus(pci_dev)->address_space_mem; 1325 1326 wmask = ~(size - 1); 1327 if (region_num == PCI_ROM_SLOT) { 1328 /* ROM enable bit is writable */ 1329 wmask |= PCI_ROM_ADDRESS_ENABLE; 1330 } 1331 1332 addr = pci_bar(pci_dev, region_num); 1333 pci_set_long(pci_dev->config + addr, type); 1334 1335 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) && 1336 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 1337 pci_set_quad(pci_dev->wmask + addr, wmask); 1338 pci_set_quad(pci_dev->cmask + addr, ~0ULL); 1339 } else { 1340 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff); 1341 pci_set_long(pci_dev->cmask + addr, 0xffffffff); 1342 } 1343 } 1344 1345 static void pci_update_vga(PCIDevice *pci_dev) 1346 { 1347 uint16_t cmd; 1348 1349 if (!pci_dev->has_vga) { 1350 return; 1351 } 1352 1353 cmd = pci_get_word(pci_dev->config + PCI_COMMAND); 1354 1355 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_MEM], 1356 cmd & PCI_COMMAND_MEMORY); 1357 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO], 1358 cmd & PCI_COMMAND_IO); 1359 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI], 1360 cmd & PCI_COMMAND_IO); 1361 } 1362 1363 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, 1364 MemoryRegion *io_lo, MemoryRegion *io_hi) 1365 { 1366 PCIBus *bus = pci_get_bus(pci_dev); 1367 1368 assert(!pci_dev->has_vga); 1369 1370 assert(memory_region_size(mem) == QEMU_PCI_VGA_MEM_SIZE); 1371 pci_dev->vga_regions[QEMU_PCI_VGA_MEM] = mem; 1372 memory_region_add_subregion_overlap(bus->address_space_mem, 1373 QEMU_PCI_VGA_MEM_BASE, mem, 1); 1374 1375 assert(memory_region_size(io_lo) == QEMU_PCI_VGA_IO_LO_SIZE); 1376 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO] = io_lo; 1377 memory_region_add_subregion_overlap(bus->address_space_io, 1378 QEMU_PCI_VGA_IO_LO_BASE, io_lo, 1); 1379 1380 assert(memory_region_size(io_hi) == QEMU_PCI_VGA_IO_HI_SIZE); 1381 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI] = io_hi; 1382 memory_region_add_subregion_overlap(bus->address_space_io, 1383 QEMU_PCI_VGA_IO_HI_BASE, io_hi, 1); 1384 pci_dev->has_vga = true; 1385 1386 pci_update_vga(pci_dev); 1387 } 1388 1389 void pci_unregister_vga(PCIDevice *pci_dev) 1390 { 1391 PCIBus *bus = pci_get_bus(pci_dev); 1392 1393 if (!pci_dev->has_vga) { 1394 return; 1395 } 1396 1397 memory_region_del_subregion(bus->address_space_mem, 1398 pci_dev->vga_regions[QEMU_PCI_VGA_MEM]); 1399 memory_region_del_subregion(bus->address_space_io, 1400 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO]); 1401 memory_region_del_subregion(bus->address_space_io, 1402 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI]); 1403 pci_dev->has_vga = false; 1404 } 1405 1406 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num) 1407 { 1408 return pci_dev->io_regions[region_num].addr; 1409 } 1410 1411 static pcibus_t pci_config_get_bar_addr(PCIDevice *d, int reg, 1412 uint8_t type, pcibus_t size) 1413 { 1414 pcibus_t new_addr; 1415 if (!pci_is_vf(d)) { 1416 int bar = pci_bar(d, reg); 1417 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 1418 new_addr = pci_get_quad(d->config + bar); 1419 } else { 1420 new_addr = pci_get_long(d->config + bar); 1421 } 1422 } else { 1423 PCIDevice *pf = d->exp.sriov_vf.pf; 1424 uint16_t sriov_cap = pf->exp.sriov_cap; 1425 int bar = sriov_cap + PCI_SRIOV_BAR + reg * 4; 1426 uint16_t vf_offset = 1427 pci_get_word(pf->config + sriov_cap + PCI_SRIOV_VF_OFFSET); 1428 uint16_t vf_stride = 1429 pci_get_word(pf->config + sriov_cap + PCI_SRIOV_VF_STRIDE); 1430 uint32_t vf_num = (d->devfn - (pf->devfn + vf_offset)) / vf_stride; 1431 1432 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 1433 new_addr = pci_get_quad(pf->config + bar); 1434 } else { 1435 new_addr = pci_get_long(pf->config + bar); 1436 } 1437 new_addr += vf_num * size; 1438 } 1439 /* The ROM slot has a specific enable bit, keep it intact */ 1440 if (reg != PCI_ROM_SLOT) { 1441 new_addr &= ~(size - 1); 1442 } 1443 return new_addr; 1444 } 1445 1446 pcibus_t pci_bar_address(PCIDevice *d, 1447 int reg, uint8_t type, pcibus_t size) 1448 { 1449 pcibus_t new_addr, last_addr; 1450 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND); 1451 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); 1452 bool allow_0_address = mc->pci_allow_0_address; 1453 1454 if (type & PCI_BASE_ADDRESS_SPACE_IO) { 1455 if (!(cmd & PCI_COMMAND_IO)) { 1456 return PCI_BAR_UNMAPPED; 1457 } 1458 new_addr = pci_config_get_bar_addr(d, reg, type, size); 1459 last_addr = new_addr + size - 1; 1460 /* Check if 32 bit BAR wraps around explicitly. 1461 * TODO: make priorities correct and remove this work around. 1462 */ 1463 if (last_addr <= new_addr || last_addr >= UINT32_MAX || 1464 (!allow_0_address && new_addr == 0)) { 1465 return PCI_BAR_UNMAPPED; 1466 } 1467 return new_addr; 1468 } 1469 1470 if (!(cmd & PCI_COMMAND_MEMORY)) { 1471 return PCI_BAR_UNMAPPED; 1472 } 1473 new_addr = pci_config_get_bar_addr(d, reg, type, size); 1474 /* the ROM slot has a specific enable bit */ 1475 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) { 1476 return PCI_BAR_UNMAPPED; 1477 } 1478 new_addr &= ~(size - 1); 1479 last_addr = new_addr + size - 1; 1480 /* NOTE: we do not support wrapping */ 1481 /* XXX: as we cannot support really dynamic 1482 mappings, we handle specific values as invalid 1483 mappings. */ 1484 if (last_addr <= new_addr || last_addr == PCI_BAR_UNMAPPED || 1485 (!allow_0_address && new_addr == 0)) { 1486 return PCI_BAR_UNMAPPED; 1487 } 1488 1489 /* Now pcibus_t is 64bit. 1490 * Check if 32 bit BAR wraps around explicitly. 1491 * Without this, PC ide doesn't work well. 1492 * TODO: remove this work around. 1493 */ 1494 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) { 1495 return PCI_BAR_UNMAPPED; 1496 } 1497 1498 /* 1499 * OS is allowed to set BAR beyond its addressable 1500 * bits. For example, 32 bit OS can set 64bit bar 1501 * to >4G. Check it. TODO: we might need to support 1502 * it in the future for e.g. PAE. 1503 */ 1504 if (last_addr >= HWADDR_MAX) { 1505 return PCI_BAR_UNMAPPED; 1506 } 1507 1508 return new_addr; 1509 } 1510 1511 static void pci_update_mappings(PCIDevice *d) 1512 { 1513 PCIIORegion *r; 1514 int i; 1515 pcibus_t new_addr; 1516 1517 for(i = 0; i < PCI_NUM_REGIONS; i++) { 1518 r = &d->io_regions[i]; 1519 1520 /* this region isn't registered */ 1521 if (!r->size) 1522 continue; 1523 1524 new_addr = pci_bar_address(d, i, r->type, r->size); 1525 if (!d->has_power) { 1526 new_addr = PCI_BAR_UNMAPPED; 1527 } 1528 1529 /* This bar isn't changed */ 1530 if (new_addr == r->addr) 1531 continue; 1532 1533 /* now do the real mapping */ 1534 if (r->addr != PCI_BAR_UNMAPPED) { 1535 trace_pci_update_mappings_del(d->name, pci_dev_bus_num(d), 1536 PCI_SLOT(d->devfn), 1537 PCI_FUNC(d->devfn), 1538 i, r->addr, r->size); 1539 memory_region_del_subregion(r->address_space, r->memory); 1540 } 1541 r->addr = new_addr; 1542 if (r->addr != PCI_BAR_UNMAPPED) { 1543 trace_pci_update_mappings_add(d->name, pci_dev_bus_num(d), 1544 PCI_SLOT(d->devfn), 1545 PCI_FUNC(d->devfn), 1546 i, r->addr, r->size); 1547 memory_region_add_subregion_overlap(r->address_space, 1548 r->addr, r->memory, 1); 1549 } 1550 } 1551 1552 pci_update_vga(d); 1553 } 1554 1555 static inline int pci_irq_disabled(PCIDevice *d) 1556 { 1557 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE; 1558 } 1559 1560 /* Called after interrupt disabled field update in config space, 1561 * assert/deassert interrupts if necessary. 1562 * Gets original interrupt disable bit value (before update). */ 1563 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled) 1564 { 1565 int i, disabled = pci_irq_disabled(d); 1566 if (disabled == was_irq_disabled) 1567 return; 1568 for (i = 0; i < PCI_NUM_PINS; ++i) { 1569 int state = pci_irq_state(d, i); 1570 pci_change_irq_level(d, i, disabled ? -state : state); 1571 } 1572 } 1573 1574 uint32_t pci_default_read_config(PCIDevice *d, 1575 uint32_t address, int len) 1576 { 1577 uint32_t val = 0; 1578 1579 assert(address + len <= pci_config_size(d)); 1580 1581 if (pci_is_express_downstream_port(d) && 1582 ranges_overlap(address, len, d->exp.exp_cap + PCI_EXP_LNKSTA, 2)) { 1583 pcie_sync_bridge_lnk(d); 1584 } 1585 memcpy(&val, d->config + address, len); 1586 return le32_to_cpu(val); 1587 } 1588 1589 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val_in, int l) 1590 { 1591 int i, was_irq_disabled = pci_irq_disabled(d); 1592 uint32_t val = val_in; 1593 1594 assert(addr + l <= pci_config_size(d)); 1595 1596 for (i = 0; i < l; val >>= 8, ++i) { 1597 uint8_t wmask = d->wmask[addr + i]; 1598 uint8_t w1cmask = d->w1cmask[addr + i]; 1599 assert(!(wmask & w1cmask)); 1600 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask); 1601 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */ 1602 } 1603 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) || 1604 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) || 1605 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) || 1606 range_covers_byte(addr, l, PCI_COMMAND)) 1607 pci_update_mappings(d); 1608 1609 if (ranges_overlap(addr, l, PCI_COMMAND, 2)) { 1610 pci_update_irq_disabled(d, was_irq_disabled); 1611 memory_region_set_enabled(&d->bus_master_enable_region, 1612 (pci_get_word(d->config + PCI_COMMAND) 1613 & PCI_COMMAND_MASTER) && d->has_power); 1614 } 1615 1616 msi_write_config(d, addr, val_in, l); 1617 msix_write_config(d, addr, val_in, l); 1618 pcie_sriov_config_write(d, addr, val_in, l); 1619 } 1620 1621 /***********************************************************/ 1622 /* generic PCI irq support */ 1623 1624 /* 0 <= irq_num <= 3. level must be 0 or 1 */ 1625 static void pci_irq_handler(void *opaque, int irq_num, int level) 1626 { 1627 PCIDevice *pci_dev = opaque; 1628 int change; 1629 1630 assert(0 <= irq_num && irq_num < PCI_NUM_PINS); 1631 assert(level == 0 || level == 1); 1632 change = level - pci_irq_state(pci_dev, irq_num); 1633 if (!change) 1634 return; 1635 1636 pci_set_irq_state(pci_dev, irq_num, level); 1637 pci_update_irq_status(pci_dev); 1638 if (pci_irq_disabled(pci_dev)) 1639 return; 1640 pci_change_irq_level(pci_dev, irq_num, change); 1641 } 1642 1643 qemu_irq pci_allocate_irq(PCIDevice *pci_dev) 1644 { 1645 int intx = pci_intx(pci_dev); 1646 assert(0 <= intx && intx < PCI_NUM_PINS); 1647 1648 return qemu_allocate_irq(pci_irq_handler, pci_dev, intx); 1649 } 1650 1651 void pci_set_irq(PCIDevice *pci_dev, int level) 1652 { 1653 int intx = pci_intx(pci_dev); 1654 pci_irq_handler(pci_dev, intx, level); 1655 } 1656 1657 /* Special hooks used by device assignment */ 1658 void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq) 1659 { 1660 assert(pci_bus_is_root(bus)); 1661 bus->route_intx_to_irq = route_intx_to_irq; 1662 } 1663 1664 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin) 1665 { 1666 PCIBus *bus; 1667 1668 do { 1669 int dev_irq = pin; 1670 bus = pci_get_bus(dev); 1671 pin = bus->map_irq(dev, pin); 1672 trace_pci_route_irq(dev_irq, DEVICE(dev)->canonical_path, pin, 1673 pci_bus_is_root(bus) ? "root-complex" 1674 : DEVICE(bus->parent_dev)->canonical_path); 1675 dev = bus->parent_dev; 1676 } while (dev); 1677 1678 if (!bus->route_intx_to_irq) { 1679 error_report("PCI: Bug - unimplemented PCI INTx routing (%s)", 1680 object_get_typename(OBJECT(bus->qbus.parent))); 1681 return (PCIINTxRoute) { PCI_INTX_DISABLED, -1 }; 1682 } 1683 1684 return bus->route_intx_to_irq(bus->irq_opaque, pin); 1685 } 1686 1687 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new) 1688 { 1689 return old->mode != new->mode || old->irq != new->irq; 1690 } 1691 1692 void pci_bus_fire_intx_routing_notifier(PCIBus *bus) 1693 { 1694 PCIDevice *dev; 1695 PCIBus *sec; 1696 int i; 1697 1698 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 1699 dev = bus->devices[i]; 1700 if (dev && dev->intx_routing_notifier) { 1701 dev->intx_routing_notifier(dev); 1702 } 1703 } 1704 1705 QLIST_FOREACH(sec, &bus->child, sibling) { 1706 pci_bus_fire_intx_routing_notifier(sec); 1707 } 1708 } 1709 1710 void pci_device_set_intx_routing_notifier(PCIDevice *dev, 1711 PCIINTxRoutingNotifier notifier) 1712 { 1713 dev->intx_routing_notifier = notifier; 1714 } 1715 1716 /* 1717 * PCI-to-PCI bridge specification 1718 * 9.1: Interrupt routing. Table 9-1 1719 * 1720 * the PCI Express Base Specification, Revision 2.1 1721 * 2.2.8.1: INTx interrupt signaling - Rules 1722 * the Implementation Note 1723 * Table 2-20 1724 */ 1725 /* 1726 * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD 1727 * 0-origin unlike PCI interrupt pin register. 1728 */ 1729 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin) 1730 { 1731 return pci_swizzle(PCI_SLOT(pci_dev->devfn), pin); 1732 } 1733 1734 /***********************************************************/ 1735 /* monitor info on PCI */ 1736 1737 static const pci_class_desc pci_class_descriptions[] = 1738 { 1739 { 0x0001, "VGA controller", "display"}, 1740 { 0x0100, "SCSI controller", "scsi"}, 1741 { 0x0101, "IDE controller", "ide"}, 1742 { 0x0102, "Floppy controller", "fdc"}, 1743 { 0x0103, "IPI controller", "ipi"}, 1744 { 0x0104, "RAID controller", "raid"}, 1745 { 0x0106, "SATA controller"}, 1746 { 0x0107, "SAS controller"}, 1747 { 0x0180, "Storage controller"}, 1748 { 0x0200, "Ethernet controller", "ethernet"}, 1749 { 0x0201, "Token Ring controller", "token-ring"}, 1750 { 0x0202, "FDDI controller", "fddi"}, 1751 { 0x0203, "ATM controller", "atm"}, 1752 { 0x0280, "Network controller"}, 1753 { 0x0300, "VGA controller", "display", 0x00ff}, 1754 { 0x0301, "XGA controller"}, 1755 { 0x0302, "3D controller"}, 1756 { 0x0380, "Display controller"}, 1757 { 0x0400, "Video controller", "video"}, 1758 { 0x0401, "Audio controller", "sound"}, 1759 { 0x0402, "Phone"}, 1760 { 0x0403, "Audio controller", "sound"}, 1761 { 0x0480, "Multimedia controller"}, 1762 { 0x0500, "RAM controller", "memory"}, 1763 { 0x0501, "Flash controller", "flash"}, 1764 { 0x0580, "Memory controller"}, 1765 { 0x0600, "Host bridge", "host"}, 1766 { 0x0601, "ISA bridge", "isa"}, 1767 { 0x0602, "EISA bridge", "eisa"}, 1768 { 0x0603, "MC bridge", "mca"}, 1769 { 0x0604, "PCI bridge", "pci-bridge"}, 1770 { 0x0605, "PCMCIA bridge", "pcmcia"}, 1771 { 0x0606, "NUBUS bridge", "nubus"}, 1772 { 0x0607, "CARDBUS bridge", "cardbus"}, 1773 { 0x0608, "RACEWAY bridge"}, 1774 { 0x0680, "Bridge"}, 1775 { 0x0700, "Serial port", "serial"}, 1776 { 0x0701, "Parallel port", "parallel"}, 1777 { 0x0800, "Interrupt controller", "interrupt-controller"}, 1778 { 0x0801, "DMA controller", "dma-controller"}, 1779 { 0x0802, "Timer", "timer"}, 1780 { 0x0803, "RTC", "rtc"}, 1781 { 0x0900, "Keyboard", "keyboard"}, 1782 { 0x0901, "Pen", "pen"}, 1783 { 0x0902, "Mouse", "mouse"}, 1784 { 0x0A00, "Dock station", "dock", 0x00ff}, 1785 { 0x0B00, "i386 cpu", "cpu", 0x00ff}, 1786 { 0x0c00, "Firewire controller", "firewire"}, 1787 { 0x0c01, "Access bus controller", "access-bus"}, 1788 { 0x0c02, "SSA controller", "ssa"}, 1789 { 0x0c03, "USB controller", "usb"}, 1790 { 0x0c04, "Fibre channel controller", "fibre-channel"}, 1791 { 0x0c05, "SMBus"}, 1792 { 0, NULL} 1793 }; 1794 1795 void pci_for_each_device_under_bus_reverse(PCIBus *bus, 1796 pci_bus_dev_fn fn, 1797 void *opaque) 1798 { 1799 PCIDevice *d; 1800 int devfn; 1801 1802 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1803 d = bus->devices[ARRAY_SIZE(bus->devices) - 1 - devfn]; 1804 if (d) { 1805 fn(bus, d, opaque); 1806 } 1807 } 1808 } 1809 1810 void pci_for_each_device_reverse(PCIBus *bus, int bus_num, 1811 pci_bus_dev_fn fn, void *opaque) 1812 { 1813 bus = pci_find_bus_nr(bus, bus_num); 1814 1815 if (bus) { 1816 pci_for_each_device_under_bus_reverse(bus, fn, opaque); 1817 } 1818 } 1819 1820 void pci_for_each_device_under_bus(PCIBus *bus, 1821 pci_bus_dev_fn fn, void *opaque) 1822 { 1823 PCIDevice *d; 1824 int devfn; 1825 1826 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1827 d = bus->devices[devfn]; 1828 if (d) { 1829 fn(bus, d, opaque); 1830 } 1831 } 1832 } 1833 1834 void pci_for_each_device(PCIBus *bus, int bus_num, 1835 pci_bus_dev_fn fn, void *opaque) 1836 { 1837 bus = pci_find_bus_nr(bus, bus_num); 1838 1839 if (bus) { 1840 pci_for_each_device_under_bus(bus, fn, opaque); 1841 } 1842 } 1843 1844 const pci_class_desc *get_class_desc(int class) 1845 { 1846 const pci_class_desc *desc; 1847 1848 desc = pci_class_descriptions; 1849 while (desc->desc && class != desc->class) { 1850 desc++; 1851 } 1852 1853 return desc; 1854 } 1855 1856 /* Initialize a PCI NIC. */ 1857 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus, 1858 const char *default_model, 1859 const char *default_devaddr) 1860 { 1861 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr; 1862 GPtrArray *pci_nic_models; 1863 PCIBus *bus; 1864 PCIDevice *pci_dev; 1865 DeviceState *dev; 1866 int devfn; 1867 int i; 1868 int dom, busnr; 1869 unsigned slot; 1870 1871 if (nd->model && !strcmp(nd->model, "virtio")) { 1872 g_free(nd->model); 1873 nd->model = g_strdup("virtio-net-pci"); 1874 } 1875 1876 pci_nic_models = qemu_get_nic_models(TYPE_PCI_DEVICE); 1877 1878 if (qemu_show_nic_models(nd->model, (const char **)pci_nic_models->pdata)) { 1879 exit(0); 1880 } 1881 1882 i = qemu_find_nic_model(nd, (const char **)pci_nic_models->pdata, 1883 default_model); 1884 if (i < 0) { 1885 exit(1); 1886 } 1887 1888 if (!rootbus) { 1889 error_report("No primary PCI bus"); 1890 exit(1); 1891 } 1892 1893 assert(!rootbus->parent_dev); 1894 1895 if (!devaddr) { 1896 devfn = -1; 1897 busnr = 0; 1898 } else { 1899 if (pci_parse_devaddr(devaddr, &dom, &busnr, &slot, NULL) < 0) { 1900 error_report("Invalid PCI device address %s for device %s", 1901 devaddr, nd->model); 1902 exit(1); 1903 } 1904 1905 if (dom != 0) { 1906 error_report("No support for non-zero PCI domains"); 1907 exit(1); 1908 } 1909 1910 devfn = PCI_DEVFN(slot, 0); 1911 } 1912 1913 bus = pci_find_bus_nr(rootbus, busnr); 1914 if (!bus) { 1915 error_report("Invalid PCI device address %s for device %s", 1916 devaddr, nd->model); 1917 exit(1); 1918 } 1919 1920 pci_dev = pci_new(devfn, nd->model); 1921 dev = &pci_dev->qdev; 1922 qdev_set_nic_properties(dev, nd); 1923 pci_realize_and_unref(pci_dev, bus, &error_fatal); 1924 g_ptr_array_free(pci_nic_models, true); 1925 return pci_dev; 1926 } 1927 1928 PCIDevice *pci_vga_init(PCIBus *bus) 1929 { 1930 vga_interface_created = true; 1931 switch (vga_interface_type) { 1932 case VGA_CIRRUS: 1933 return pci_create_simple(bus, -1, "cirrus-vga"); 1934 case VGA_QXL: 1935 return pci_create_simple(bus, -1, "qxl-vga"); 1936 case VGA_STD: 1937 return pci_create_simple(bus, -1, "VGA"); 1938 case VGA_VMWARE: 1939 return pci_create_simple(bus, -1, "vmware-svga"); 1940 case VGA_VIRTIO: 1941 return pci_create_simple(bus, -1, "virtio-vga"); 1942 case VGA_NONE: 1943 default: /* Other non-PCI types. Checking for unsupported types is already 1944 done in vl.c. */ 1945 return NULL; 1946 } 1947 } 1948 1949 /* Whether a given bus number is in range of the secondary 1950 * bus of the given bridge device. */ 1951 static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num) 1952 { 1953 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) & 1954 PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ && 1955 dev->config[PCI_SECONDARY_BUS] <= bus_num && 1956 bus_num <= dev->config[PCI_SUBORDINATE_BUS]; 1957 } 1958 1959 /* Whether a given bus number is in a range of a root bus */ 1960 static bool pci_root_bus_in_range(PCIBus *bus, int bus_num) 1961 { 1962 int i; 1963 1964 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 1965 PCIDevice *dev = bus->devices[i]; 1966 1967 if (dev && IS_PCI_BRIDGE(dev)) { 1968 if (pci_secondary_bus_in_range(dev, bus_num)) { 1969 return true; 1970 } 1971 } 1972 } 1973 1974 return false; 1975 } 1976 1977 PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num) 1978 { 1979 PCIBus *sec; 1980 1981 if (!bus) { 1982 return NULL; 1983 } 1984 1985 if (pci_bus_num(bus) == bus_num) { 1986 return bus; 1987 } 1988 1989 /* Consider all bus numbers in range for the host pci bridge. */ 1990 if (!pci_bus_is_root(bus) && 1991 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) { 1992 return NULL; 1993 } 1994 1995 /* try child bus */ 1996 for (; bus; bus = sec) { 1997 QLIST_FOREACH(sec, &bus->child, sibling) { 1998 if (pci_bus_num(sec) == bus_num) { 1999 return sec; 2000 } 2001 /* PXB buses assumed to be children of bus 0 */ 2002 if (pci_bus_is_root(sec)) { 2003 if (pci_root_bus_in_range(sec, bus_num)) { 2004 break; 2005 } 2006 } else { 2007 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) { 2008 break; 2009 } 2010 } 2011 } 2012 } 2013 2014 return NULL; 2015 } 2016 2017 void pci_for_each_bus_depth_first(PCIBus *bus, pci_bus_ret_fn begin, 2018 pci_bus_fn end, void *parent_state) 2019 { 2020 PCIBus *sec; 2021 void *state; 2022 2023 if (!bus) { 2024 return; 2025 } 2026 2027 if (begin) { 2028 state = begin(bus, parent_state); 2029 } else { 2030 state = parent_state; 2031 } 2032 2033 QLIST_FOREACH(sec, &bus->child, sibling) { 2034 pci_for_each_bus_depth_first(sec, begin, end, state); 2035 } 2036 2037 if (end) { 2038 end(bus, state); 2039 } 2040 } 2041 2042 2043 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn) 2044 { 2045 bus = pci_find_bus_nr(bus, bus_num); 2046 2047 if (!bus) 2048 return NULL; 2049 2050 return bus->devices[devfn]; 2051 } 2052 2053 #define ONBOARD_INDEX_MAX (16 * 1024 - 1) 2054 2055 static void pci_qdev_realize(DeviceState *qdev, Error **errp) 2056 { 2057 PCIDevice *pci_dev = (PCIDevice *)qdev; 2058 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 2059 ObjectClass *klass = OBJECT_CLASS(pc); 2060 Error *local_err = NULL; 2061 bool is_default_rom; 2062 uint16_t class_id; 2063 2064 /* 2065 * capped by systemd (see: udev-builtin-net_id.c) 2066 * as it's the only known user honor it to avoid users 2067 * misconfigure QEMU and then wonder why acpi-index doesn't work 2068 */ 2069 if (pci_dev->acpi_index > ONBOARD_INDEX_MAX) { 2070 error_setg(errp, "acpi-index should be less or equal to %u", 2071 ONBOARD_INDEX_MAX); 2072 return; 2073 } 2074 2075 /* 2076 * make sure that acpi-index is unique across all present PCI devices 2077 */ 2078 if (pci_dev->acpi_index) { 2079 GSequence *used_indexes = pci_acpi_index_list(); 2080 2081 if (g_sequence_lookup(used_indexes, 2082 GINT_TO_POINTER(pci_dev->acpi_index), 2083 g_cmp_uint32, NULL)) { 2084 error_setg(errp, "a PCI device with acpi-index = %" PRIu32 2085 " already exist", pci_dev->acpi_index); 2086 return; 2087 } 2088 g_sequence_insert_sorted(used_indexes, 2089 GINT_TO_POINTER(pci_dev->acpi_index), 2090 g_cmp_uint32, NULL); 2091 } 2092 2093 if (pci_dev->romsize != -1 && !is_power_of_2(pci_dev->romsize)) { 2094 error_setg(errp, "ROM size %u is not a power of two", pci_dev->romsize); 2095 return; 2096 } 2097 2098 /* initialize cap_present for pci_is_express() and pci_config_size(), 2099 * Note that hybrid PCIs are not set automatically and need to manage 2100 * QEMU_PCI_CAP_EXPRESS manually */ 2101 if (object_class_dynamic_cast(klass, INTERFACE_PCIE_DEVICE) && 2102 !object_class_dynamic_cast(klass, INTERFACE_CONVENTIONAL_PCI_DEVICE)) { 2103 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; 2104 } 2105 2106 if (object_class_dynamic_cast(klass, INTERFACE_CXL_DEVICE)) { 2107 pci_dev->cap_present |= QEMU_PCIE_CAP_CXL; 2108 } 2109 2110 pci_dev = do_pci_register_device(pci_dev, 2111 object_get_typename(OBJECT(qdev)), 2112 pci_dev->devfn, errp); 2113 if (pci_dev == NULL) 2114 return; 2115 2116 if (pc->realize) { 2117 pc->realize(pci_dev, &local_err); 2118 if (local_err) { 2119 error_propagate(errp, local_err); 2120 do_pci_unregister_device(pci_dev); 2121 return; 2122 } 2123 } 2124 2125 /* 2126 * A PCIe Downstream Port that do not have ARI Forwarding enabled must 2127 * associate only Device 0 with the device attached to the bus 2128 * representing the Link from the Port (PCIe base spec rev 4.0 ver 0.3, 2129 * sec 7.3.1). 2130 * With ARI, PCI_SLOT() can return non-zero value as the traditional 2131 * 5-bit Device Number and 3-bit Function Number fields in its associated 2132 * Routing IDs, Requester IDs and Completer IDs are interpreted as a 2133 * single 8-bit Function Number. Hence, ignore ARI capable devices. 2134 */ 2135 if (pci_is_express(pci_dev) && 2136 !pcie_find_capability(pci_dev, PCI_EXT_CAP_ID_ARI) && 2137 pcie_has_upstream_port(pci_dev) && 2138 PCI_SLOT(pci_dev->devfn)) { 2139 warn_report("PCI: slot %d is not valid for %s," 2140 " parent device only allows plugging into slot 0.", 2141 PCI_SLOT(pci_dev->devfn), pci_dev->name); 2142 } 2143 2144 if (pci_dev->failover_pair_id) { 2145 if (!pci_bus_is_express(pci_get_bus(pci_dev))) { 2146 error_setg(errp, "failover primary device must be on " 2147 "PCIExpress bus"); 2148 pci_qdev_unrealize(DEVICE(pci_dev)); 2149 return; 2150 } 2151 class_id = pci_get_word(pci_dev->config + PCI_CLASS_DEVICE); 2152 if (class_id != PCI_CLASS_NETWORK_ETHERNET) { 2153 error_setg(errp, "failover primary device is not an " 2154 "Ethernet device"); 2155 pci_qdev_unrealize(DEVICE(pci_dev)); 2156 return; 2157 } 2158 if ((pci_dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) 2159 || (PCI_FUNC(pci_dev->devfn) != 0)) { 2160 error_setg(errp, "failover: primary device must be in its own " 2161 "PCI slot"); 2162 pci_qdev_unrealize(DEVICE(pci_dev)); 2163 return; 2164 } 2165 qdev->allow_unplug_during_migration = true; 2166 } 2167 2168 /* rom loading */ 2169 is_default_rom = false; 2170 if (pci_dev->romfile == NULL && pc->romfile != NULL) { 2171 pci_dev->romfile = g_strdup(pc->romfile); 2172 is_default_rom = true; 2173 } 2174 2175 pci_add_option_rom(pci_dev, is_default_rom, &local_err); 2176 if (local_err) { 2177 error_propagate(errp, local_err); 2178 pci_qdev_unrealize(DEVICE(pci_dev)); 2179 return; 2180 } 2181 2182 pci_set_power(pci_dev, true); 2183 2184 pci_dev->msi_trigger = pci_msi_trigger; 2185 } 2186 2187 static PCIDevice *pci_new_internal(int devfn, bool multifunction, 2188 const char *name) 2189 { 2190 DeviceState *dev; 2191 2192 dev = qdev_new(name); 2193 qdev_prop_set_int32(dev, "addr", devfn); 2194 qdev_prop_set_bit(dev, "multifunction", multifunction); 2195 return PCI_DEVICE(dev); 2196 } 2197 2198 PCIDevice *pci_new_multifunction(int devfn, const char *name) 2199 { 2200 return pci_new_internal(devfn, true, name); 2201 } 2202 2203 PCIDevice *pci_new(int devfn, const char *name) 2204 { 2205 return pci_new_internal(devfn, false, name); 2206 } 2207 2208 bool pci_realize_and_unref(PCIDevice *dev, PCIBus *bus, Error **errp) 2209 { 2210 return qdev_realize_and_unref(&dev->qdev, &bus->qbus, errp); 2211 } 2212 2213 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, 2214 const char *name) 2215 { 2216 PCIDevice *dev = pci_new_multifunction(devfn, name); 2217 pci_realize_and_unref(dev, bus, &error_fatal); 2218 return dev; 2219 } 2220 2221 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name) 2222 { 2223 PCIDevice *dev = pci_new(devfn, name); 2224 pci_realize_and_unref(dev, bus, &error_fatal); 2225 return dev; 2226 } 2227 2228 static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size) 2229 { 2230 int offset = PCI_CONFIG_HEADER_SIZE; 2231 int i; 2232 for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) { 2233 if (pdev->used[i]) 2234 offset = i + 1; 2235 else if (i - offset + 1 == size) 2236 return offset; 2237 } 2238 return 0; 2239 } 2240 2241 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id, 2242 uint8_t *prev_p) 2243 { 2244 uint8_t next, prev; 2245 2246 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST)) 2247 return 0; 2248 2249 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); 2250 prev = next + PCI_CAP_LIST_NEXT) 2251 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id) 2252 break; 2253 2254 if (prev_p) 2255 *prev_p = prev; 2256 return next; 2257 } 2258 2259 static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset) 2260 { 2261 uint8_t next, prev, found = 0; 2262 2263 if (!(pdev->used[offset])) { 2264 return 0; 2265 } 2266 2267 assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST); 2268 2269 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); 2270 prev = next + PCI_CAP_LIST_NEXT) { 2271 if (next <= offset && next > found) { 2272 found = next; 2273 } 2274 } 2275 return found; 2276 } 2277 2278 /* Patch the PCI vendor and device ids in a PCI rom image if necessary. 2279 This is needed for an option rom which is used for more than one device. */ 2280 static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, uint32_t size) 2281 { 2282 uint16_t vendor_id; 2283 uint16_t device_id; 2284 uint16_t rom_vendor_id; 2285 uint16_t rom_device_id; 2286 uint16_t rom_magic; 2287 uint16_t pcir_offset; 2288 uint8_t checksum; 2289 2290 /* Words in rom data are little endian (like in PCI configuration), 2291 so they can be read / written with pci_get_word / pci_set_word. */ 2292 2293 /* Only a valid rom will be patched. */ 2294 rom_magic = pci_get_word(ptr); 2295 if (rom_magic != 0xaa55) { 2296 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic); 2297 return; 2298 } 2299 pcir_offset = pci_get_word(ptr + 0x18); 2300 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) { 2301 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset); 2302 return; 2303 } 2304 2305 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID); 2306 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID); 2307 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4); 2308 rom_device_id = pci_get_word(ptr + pcir_offset + 6); 2309 2310 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile, 2311 vendor_id, device_id, rom_vendor_id, rom_device_id); 2312 2313 checksum = ptr[6]; 2314 2315 if (vendor_id != rom_vendor_id) { 2316 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */ 2317 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8); 2318 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8); 2319 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); 2320 ptr[6] = checksum; 2321 pci_set_word(ptr + pcir_offset + 4, vendor_id); 2322 } 2323 2324 if (device_id != rom_device_id) { 2325 /* Patch device id and checksum (at offset 6 for etherboot roms). */ 2326 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8); 2327 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8); 2328 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); 2329 ptr[6] = checksum; 2330 pci_set_word(ptr + pcir_offset + 6, device_id); 2331 } 2332 } 2333 2334 /* Add an option rom for the device */ 2335 static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, 2336 Error **errp) 2337 { 2338 int64_t size = 0; 2339 g_autofree char *path = NULL; 2340 char name[32]; 2341 const VMStateDescription *vmsd; 2342 2343 /* 2344 * In case of incoming migration ROM will come with migration stream, no 2345 * reason to load the file. Neither we want to fail if local ROM file 2346 * mismatches with specified romsize. 2347 */ 2348 bool load_file = !runstate_check(RUN_STATE_INMIGRATE); 2349 2350 if (!pdev->romfile || !strlen(pdev->romfile)) { 2351 return; 2352 } 2353 2354 if (!pdev->rom_bar) { 2355 /* 2356 * Load rom via fw_cfg instead of creating a rom bar, 2357 * for 0.11 compatibility. 2358 */ 2359 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE); 2360 2361 /* 2362 * Hot-plugged devices can't use the option ROM 2363 * if the rom bar is disabled. 2364 */ 2365 if (DEVICE(pdev)->hotplugged) { 2366 error_setg(errp, "Hot-plugged device without ROM bar" 2367 " can't have an option ROM"); 2368 return; 2369 } 2370 2371 if (class == 0x0300) { 2372 rom_add_vga(pdev->romfile); 2373 } else { 2374 rom_add_option(pdev->romfile, -1); 2375 } 2376 return; 2377 } 2378 2379 if (load_file || pdev->romsize == -1) { 2380 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile); 2381 if (path == NULL) { 2382 path = g_strdup(pdev->romfile); 2383 } 2384 2385 size = get_image_size(path); 2386 if (size < 0) { 2387 error_setg(errp, "failed to find romfile \"%s\"", pdev->romfile); 2388 return; 2389 } else if (size == 0) { 2390 error_setg(errp, "romfile \"%s\" is empty", pdev->romfile); 2391 return; 2392 } else if (size > 2 * GiB) { 2393 error_setg(errp, 2394 "romfile \"%s\" too large (size cannot exceed 2 GiB)", 2395 pdev->romfile); 2396 return; 2397 } 2398 if (pdev->romsize != -1) { 2399 if (size > pdev->romsize) { 2400 error_setg(errp, "romfile \"%s\" (%u bytes) " 2401 "is too large for ROM size %u", 2402 pdev->romfile, (uint32_t)size, pdev->romsize); 2403 return; 2404 } 2405 } else { 2406 pdev->romsize = pow2ceil(size); 2407 } 2408 } 2409 2410 vmsd = qdev_get_vmsd(DEVICE(pdev)); 2411 snprintf(name, sizeof(name), "%s.rom", 2412 vmsd ? vmsd->name : object_get_typename(OBJECT(pdev))); 2413 2414 pdev->has_rom = true; 2415 memory_region_init_rom(&pdev->rom, OBJECT(pdev), name, pdev->romsize, 2416 &error_fatal); 2417 2418 if (load_file) { 2419 void *ptr = memory_region_get_ram_ptr(&pdev->rom); 2420 2421 if (load_image_size(path, ptr, size) < 0) { 2422 error_setg(errp, "failed to load romfile \"%s\"", pdev->romfile); 2423 return; 2424 } 2425 2426 if (is_default_rom) { 2427 /* Only the default rom images will be patched (if needed). */ 2428 pci_patch_ids(pdev, ptr, size); 2429 } 2430 } 2431 2432 pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom); 2433 } 2434 2435 static void pci_del_option_rom(PCIDevice *pdev) 2436 { 2437 if (!pdev->has_rom) 2438 return; 2439 2440 vmstate_unregister_ram(&pdev->rom, &pdev->qdev); 2441 pdev->has_rom = false; 2442 } 2443 2444 /* 2445 * On success, pci_add_capability() returns a positive value 2446 * that the offset of the pci capability. 2447 * On failure, it sets an error and returns a negative error 2448 * code. 2449 */ 2450 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, 2451 uint8_t offset, uint8_t size, 2452 Error **errp) 2453 { 2454 uint8_t *config; 2455 int i, overlapping_cap; 2456 2457 if (!offset) { 2458 offset = pci_find_space(pdev, size); 2459 /* out of PCI config space is programming error */ 2460 assert(offset); 2461 } else { 2462 /* Verify that capabilities don't overlap. Note: device assignment 2463 * depends on this check to verify that the device is not broken. 2464 * Should never trigger for emulated devices, but it's helpful 2465 * for debugging these. */ 2466 for (i = offset; i < offset + size; i++) { 2467 overlapping_cap = pci_find_capability_at_offset(pdev, i); 2468 if (overlapping_cap) { 2469 error_setg(errp, "%s:%02x:%02x.%x " 2470 "Attempt to add PCI capability %x at offset " 2471 "%x overlaps existing capability %x at offset %x", 2472 pci_root_bus_path(pdev), pci_dev_bus_num(pdev), 2473 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), 2474 cap_id, offset, overlapping_cap, i); 2475 return -EINVAL; 2476 } 2477 } 2478 } 2479 2480 config = pdev->config + offset; 2481 config[PCI_CAP_LIST_ID] = cap_id; 2482 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST]; 2483 pdev->config[PCI_CAPABILITY_LIST] = offset; 2484 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST; 2485 memset(pdev->used + offset, 0xFF, QEMU_ALIGN_UP(size, 4)); 2486 /* Make capability read-only by default */ 2487 memset(pdev->wmask + offset, 0, size); 2488 /* Check capability by default */ 2489 memset(pdev->cmask + offset, 0xFF, size); 2490 return offset; 2491 } 2492 2493 /* Unlink capability from the pci config space. */ 2494 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size) 2495 { 2496 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev); 2497 if (!offset) 2498 return; 2499 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT]; 2500 /* Make capability writable again */ 2501 memset(pdev->wmask + offset, 0xff, size); 2502 memset(pdev->w1cmask + offset, 0, size); 2503 /* Clear cmask as device-specific registers can't be checked */ 2504 memset(pdev->cmask + offset, 0, size); 2505 memset(pdev->used + offset, 0, QEMU_ALIGN_UP(size, 4)); 2506 2507 if (!pdev->config[PCI_CAPABILITY_LIST]) 2508 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST; 2509 } 2510 2511 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id) 2512 { 2513 return pci_find_capability_list(pdev, cap_id, NULL); 2514 } 2515 2516 static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len) 2517 { 2518 PCIDevice *d = (PCIDevice *)dev; 2519 const char *name = NULL; 2520 const pci_class_desc *desc = pci_class_descriptions; 2521 int class = pci_get_word(d->config + PCI_CLASS_DEVICE); 2522 2523 while (desc->desc && 2524 (class & ~desc->fw_ign_bits) != 2525 (desc->class & ~desc->fw_ign_bits)) { 2526 desc++; 2527 } 2528 2529 if (desc->desc) { 2530 name = desc->fw_name; 2531 } 2532 2533 if (name) { 2534 pstrcpy(buf, len, name); 2535 } else { 2536 snprintf(buf, len, "pci%04x,%04x", 2537 pci_get_word(d->config + PCI_VENDOR_ID), 2538 pci_get_word(d->config + PCI_DEVICE_ID)); 2539 } 2540 2541 return buf; 2542 } 2543 2544 static char *pcibus_get_fw_dev_path(DeviceState *dev) 2545 { 2546 PCIDevice *d = (PCIDevice *)dev; 2547 char name[33]; 2548 int has_func = !!PCI_FUNC(d->devfn); 2549 2550 return g_strdup_printf("%s@%x%s%.*x", 2551 pci_dev_fw_name(dev, name, sizeof(name)), 2552 PCI_SLOT(d->devfn), 2553 has_func ? "," : "", 2554 has_func, 2555 PCI_FUNC(d->devfn)); 2556 } 2557 2558 static char *pcibus_get_dev_path(DeviceState *dev) 2559 { 2560 PCIDevice *d = container_of(dev, PCIDevice, qdev); 2561 PCIDevice *t; 2562 int slot_depth; 2563 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function. 2564 * 00 is added here to make this format compatible with 2565 * domain:Bus:Slot.Func for systems without nested PCI bridges. 2566 * Slot.Function list specifies the slot and function numbers for all 2567 * devices on the path from root to the specific device. */ 2568 const char *root_bus_path; 2569 int root_bus_len; 2570 char slot[] = ":SS.F"; 2571 int slot_len = sizeof slot - 1 /* For '\0' */; 2572 int path_len; 2573 char *path, *p; 2574 int s; 2575 2576 root_bus_path = pci_root_bus_path(d); 2577 root_bus_len = strlen(root_bus_path); 2578 2579 /* Calculate # of slots on path between device and root. */; 2580 slot_depth = 0; 2581 for (t = d; t; t = pci_get_bus(t)->parent_dev) { 2582 ++slot_depth; 2583 } 2584 2585 path_len = root_bus_len + slot_len * slot_depth; 2586 2587 /* Allocate memory, fill in the terminating null byte. */ 2588 path = g_malloc(path_len + 1 /* For '\0' */); 2589 path[path_len] = '\0'; 2590 2591 memcpy(path, root_bus_path, root_bus_len); 2592 2593 /* Fill in slot numbers. We walk up from device to root, so need to print 2594 * them in the reverse order, last to first. */ 2595 p = path + path_len; 2596 for (t = d; t; t = pci_get_bus(t)->parent_dev) { 2597 p -= slot_len; 2598 s = snprintf(slot, sizeof slot, ":%02x.%x", 2599 PCI_SLOT(t->devfn), PCI_FUNC(t->devfn)); 2600 assert(s == slot_len); 2601 memcpy(p, slot, slot_len); 2602 } 2603 2604 return path; 2605 } 2606 2607 static int pci_qdev_find_recursive(PCIBus *bus, 2608 const char *id, PCIDevice **pdev) 2609 { 2610 DeviceState *qdev = qdev_find_recursive(&bus->qbus, id); 2611 if (!qdev) { 2612 return -ENODEV; 2613 } 2614 2615 /* roughly check if given qdev is pci device */ 2616 if (object_dynamic_cast(OBJECT(qdev), TYPE_PCI_DEVICE)) { 2617 *pdev = PCI_DEVICE(qdev); 2618 return 0; 2619 } 2620 return -EINVAL; 2621 } 2622 2623 int pci_qdev_find_device(const char *id, PCIDevice **pdev) 2624 { 2625 PCIHostState *host_bridge; 2626 int rc = -ENODEV; 2627 2628 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { 2629 int tmp = pci_qdev_find_recursive(host_bridge->bus, id, pdev); 2630 if (!tmp) { 2631 rc = 0; 2632 break; 2633 } 2634 if (tmp != -ENODEV) { 2635 rc = tmp; 2636 } 2637 } 2638 2639 return rc; 2640 } 2641 2642 MemoryRegion *pci_address_space(PCIDevice *dev) 2643 { 2644 return pci_get_bus(dev)->address_space_mem; 2645 } 2646 2647 MemoryRegion *pci_address_space_io(PCIDevice *dev) 2648 { 2649 return pci_get_bus(dev)->address_space_io; 2650 } 2651 2652 static void pci_device_class_init(ObjectClass *klass, void *data) 2653 { 2654 DeviceClass *k = DEVICE_CLASS(klass); 2655 2656 k->realize = pci_qdev_realize; 2657 k->unrealize = pci_qdev_unrealize; 2658 k->bus_type = TYPE_PCI_BUS; 2659 device_class_set_props(k, pci_props); 2660 } 2661 2662 static void pci_device_class_base_init(ObjectClass *klass, void *data) 2663 { 2664 if (!object_class_is_abstract(klass)) { 2665 ObjectClass *conventional = 2666 object_class_dynamic_cast(klass, INTERFACE_CONVENTIONAL_PCI_DEVICE); 2667 ObjectClass *pcie = 2668 object_class_dynamic_cast(klass, INTERFACE_PCIE_DEVICE); 2669 ObjectClass *cxl = 2670 object_class_dynamic_cast(klass, INTERFACE_CXL_DEVICE); 2671 assert(conventional || pcie || cxl); 2672 } 2673 } 2674 2675 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev) 2676 { 2677 PCIBus *bus = pci_get_bus(dev); 2678 PCIBus *iommu_bus = bus; 2679 uint8_t devfn = dev->devfn; 2680 2681 while (iommu_bus && !iommu_bus->iommu_fn && iommu_bus->parent_dev) { 2682 PCIBus *parent_bus = pci_get_bus(iommu_bus->parent_dev); 2683 2684 /* 2685 * The requester ID of the provided device may be aliased, as seen from 2686 * the IOMMU, due to topology limitations. The IOMMU relies on a 2687 * requester ID to provide a unique AddressSpace for devices, but 2688 * conventional PCI buses pre-date such concepts. Instead, the PCIe- 2689 * to-PCI bridge creates and accepts transactions on behalf of down- 2690 * stream devices. When doing so, all downstream devices are masked 2691 * (aliased) behind a single requester ID. The requester ID used 2692 * depends on the format of the bridge devices. Proper PCIe-to-PCI 2693 * bridges, with a PCIe capability indicating such, follow the 2694 * guidelines of chapter 2.3 of the PCIe-to-PCI/X bridge specification, 2695 * where the bridge uses the seconary bus as the bridge portion of the 2696 * requester ID and devfn of 00.0. For other bridges, typically those 2697 * found on the root complex such as the dmi-to-pci-bridge, we follow 2698 * the convention of typical bare-metal hardware, which uses the 2699 * requester ID of the bridge itself. There are device specific 2700 * exceptions to these rules, but these are the defaults that the 2701 * Linux kernel uses when determining DMA aliases itself and believed 2702 * to be true for the bare metal equivalents of the devices emulated 2703 * in QEMU. 2704 */ 2705 if (!pci_bus_is_express(iommu_bus)) { 2706 PCIDevice *parent = iommu_bus->parent_dev; 2707 2708 if (pci_is_express(parent) && 2709 pcie_cap_get_type(parent) == PCI_EXP_TYPE_PCI_BRIDGE) { 2710 devfn = PCI_DEVFN(0, 0); 2711 bus = iommu_bus; 2712 } else { 2713 devfn = parent->devfn; 2714 bus = parent_bus; 2715 } 2716 } 2717 2718 iommu_bus = parent_bus; 2719 } 2720 if (!pci_bus_bypass_iommu(bus) && iommu_bus && iommu_bus->iommu_fn) { 2721 return iommu_bus->iommu_fn(bus, iommu_bus->iommu_opaque, devfn); 2722 } 2723 return &address_space_memory; 2724 } 2725 2726 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque) 2727 { 2728 bus->iommu_fn = fn; 2729 bus->iommu_opaque = opaque; 2730 } 2731 2732 static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque) 2733 { 2734 Range *range = opaque; 2735 uint16_t cmd = pci_get_word(dev->config + PCI_COMMAND); 2736 int i; 2737 2738 if (!(cmd & PCI_COMMAND_MEMORY)) { 2739 return; 2740 } 2741 2742 if (IS_PCI_BRIDGE(dev)) { 2743 pcibus_t base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 2744 pcibus_t limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 2745 2746 base = MAX(base, 0x1ULL << 32); 2747 2748 if (limit >= base) { 2749 Range pref_range; 2750 range_set_bounds(&pref_range, base, limit); 2751 range_extend(range, &pref_range); 2752 } 2753 } 2754 for (i = 0; i < PCI_NUM_REGIONS; ++i) { 2755 PCIIORegion *r = &dev->io_regions[i]; 2756 pcibus_t lob, upb; 2757 Range region_range; 2758 2759 if (!r->size || 2760 (r->type & PCI_BASE_ADDRESS_SPACE_IO) || 2761 !(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64)) { 2762 continue; 2763 } 2764 2765 lob = pci_bar_address(dev, i, r->type, r->size); 2766 upb = lob + r->size - 1; 2767 if (lob == PCI_BAR_UNMAPPED) { 2768 continue; 2769 } 2770 2771 lob = MAX(lob, 0x1ULL << 32); 2772 2773 if (upb >= lob) { 2774 range_set_bounds(®ion_range, lob, upb); 2775 range_extend(range, ®ion_range); 2776 } 2777 } 2778 } 2779 2780 void pci_bus_get_w64_range(PCIBus *bus, Range *range) 2781 { 2782 range_make_empty(range); 2783 pci_for_each_device_under_bus(bus, pci_dev_get_w64, range); 2784 } 2785 2786 static bool pcie_has_upstream_port(PCIDevice *dev) 2787 { 2788 PCIDevice *parent_dev = pci_bridge_get_device(pci_get_bus(dev)); 2789 2790 /* Device associated with an upstream port. 2791 * As there are several types of these, it's easier to check the 2792 * parent device: upstream ports are always connected to 2793 * root or downstream ports. 2794 */ 2795 return parent_dev && 2796 pci_is_express(parent_dev) && 2797 parent_dev->exp.exp_cap && 2798 (pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_ROOT_PORT || 2799 pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_DOWNSTREAM); 2800 } 2801 2802 PCIDevice *pci_get_function_0(PCIDevice *pci_dev) 2803 { 2804 PCIBus *bus = pci_get_bus(pci_dev); 2805 2806 if(pcie_has_upstream_port(pci_dev)) { 2807 /* With an upstream PCIe port, we only support 1 device at slot 0 */ 2808 return bus->devices[0]; 2809 } else { 2810 /* Other bus types might support multiple devices at slots 0-31 */ 2811 return bus->devices[PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 0)]; 2812 } 2813 } 2814 2815 MSIMessage pci_get_msi_message(PCIDevice *dev, int vector) 2816 { 2817 MSIMessage msg; 2818 if (msix_enabled(dev)) { 2819 msg = msix_get_message(dev, vector); 2820 } else if (msi_enabled(dev)) { 2821 msg = msi_get_message(dev, vector); 2822 } else { 2823 /* Should never happen */ 2824 error_report("%s: unknown interrupt type", __func__); 2825 abort(); 2826 } 2827 return msg; 2828 } 2829 2830 void pci_set_power(PCIDevice *d, bool state) 2831 { 2832 if (d->has_power == state) { 2833 return; 2834 } 2835 2836 d->has_power = state; 2837 pci_update_mappings(d); 2838 memory_region_set_enabled(&d->bus_master_enable_region, 2839 (pci_get_word(d->config + PCI_COMMAND) 2840 & PCI_COMMAND_MASTER) && d->has_power); 2841 if (!d->has_power) { 2842 pci_device_reset(d); 2843 } 2844 } 2845 2846 static const TypeInfo pci_device_type_info = { 2847 .name = TYPE_PCI_DEVICE, 2848 .parent = TYPE_DEVICE, 2849 .instance_size = sizeof(PCIDevice), 2850 .abstract = true, 2851 .class_size = sizeof(PCIDeviceClass), 2852 .class_init = pci_device_class_init, 2853 .class_base_init = pci_device_class_base_init, 2854 }; 2855 2856 static void pci_register_types(void) 2857 { 2858 type_register_static(&pci_bus_info); 2859 type_register_static(&pcie_bus_info); 2860 type_register_static(&cxl_bus_info); 2861 type_register_static(&conventional_pci_interface_info); 2862 type_register_static(&cxl_interface_info); 2863 type_register_static(&pcie_interface_info); 2864 type_register_static(&pci_device_type_info); 2865 } 2866 2867 type_init(pci_register_types) 2868