1 /* 2 * QEMU PCI bus manager 3 * 4 * Copyright (c) 2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "qemu/osdep.h" 25 #include "hw/hw.h" 26 #include "hw/pci/pci.h" 27 #include "hw/pci/pci_bridge.h" 28 #include "hw/pci/pci_bus.h" 29 #include "hw/pci/pci_host.h" 30 #include "monitor/monitor.h" 31 #include "net/net.h" 32 #include "sysemu/sysemu.h" 33 #include "hw/loader.h" 34 #include "qemu/error-report.h" 35 #include "qemu/range.h" 36 #include "qmp-commands.h" 37 #include "trace.h" 38 #include "hw/pci/msi.h" 39 #include "hw/pci/msix.h" 40 #include "exec/address-spaces.h" 41 #include "hw/hotplug.h" 42 #include "hw/boards.h" 43 #include "qemu/cutils.h" 44 45 //#define DEBUG_PCI 46 #ifdef DEBUG_PCI 47 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) 48 #else 49 # define PCI_DPRINTF(format, ...) do { } while (0) 50 #endif 51 52 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent); 53 static char *pcibus_get_dev_path(DeviceState *dev); 54 static char *pcibus_get_fw_dev_path(DeviceState *dev); 55 static void pcibus_reset(BusState *qbus); 56 57 static Property pci_props[] = { 58 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1), 59 DEFINE_PROP_STRING("romfile", PCIDevice, romfile), 60 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1), 61 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present, 62 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false), 63 DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present, 64 QEMU_PCI_CAP_SERR_BITNR, true), 65 DEFINE_PROP_END_OF_LIST() 66 }; 67 68 static const VMStateDescription vmstate_pcibus = { 69 .name = "PCIBUS", 70 .version_id = 1, 71 .minimum_version_id = 1, 72 .fields = (VMStateField[]) { 73 VMSTATE_INT32_EQUAL(nirq, PCIBus), 74 VMSTATE_VARRAY_INT32(irq_count, PCIBus, 75 nirq, 0, vmstate_info_int32, 76 int32_t), 77 VMSTATE_END_OF_LIST() 78 } 79 }; 80 81 static void pci_bus_realize(BusState *qbus, Error **errp) 82 { 83 PCIBus *bus = PCI_BUS(qbus); 84 85 vmstate_register(NULL, -1, &vmstate_pcibus, bus); 86 } 87 88 static void pci_bus_unrealize(BusState *qbus, Error **errp) 89 { 90 PCIBus *bus = PCI_BUS(qbus); 91 92 vmstate_unregister(NULL, &vmstate_pcibus, bus); 93 } 94 95 static bool pcibus_is_root(PCIBus *bus) 96 { 97 return !bus->parent_dev; 98 } 99 100 static int pcibus_num(PCIBus *bus) 101 { 102 if (pcibus_is_root(bus)) { 103 return 0; /* pci host bridge */ 104 } 105 return bus->parent_dev->config[PCI_SECONDARY_BUS]; 106 } 107 108 static uint16_t pcibus_numa_node(PCIBus *bus) 109 { 110 return NUMA_NODE_UNASSIGNED; 111 } 112 113 static void pci_bus_class_init(ObjectClass *klass, void *data) 114 { 115 BusClass *k = BUS_CLASS(klass); 116 PCIBusClass *pbc = PCI_BUS_CLASS(klass); 117 118 k->print_dev = pcibus_dev_print; 119 k->get_dev_path = pcibus_get_dev_path; 120 k->get_fw_dev_path = pcibus_get_fw_dev_path; 121 k->realize = pci_bus_realize; 122 k->unrealize = pci_bus_unrealize; 123 k->reset = pcibus_reset; 124 125 pbc->is_root = pcibus_is_root; 126 pbc->bus_num = pcibus_num; 127 pbc->numa_node = pcibus_numa_node; 128 } 129 130 static const TypeInfo pci_bus_info = { 131 .name = TYPE_PCI_BUS, 132 .parent = TYPE_BUS, 133 .instance_size = sizeof(PCIBus), 134 .class_size = sizeof(PCIBusClass), 135 .class_init = pci_bus_class_init, 136 }; 137 138 static const TypeInfo pcie_bus_info = { 139 .name = TYPE_PCIE_BUS, 140 .parent = TYPE_PCI_BUS, 141 }; 142 143 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num); 144 static void pci_update_mappings(PCIDevice *d); 145 static void pci_irq_handler(void *opaque, int irq_num, int level); 146 static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, Error **); 147 static void pci_del_option_rom(PCIDevice *pdev); 148 149 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET; 150 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU; 151 152 static QLIST_HEAD(, PCIHostState) pci_host_bridges; 153 154 int pci_bar(PCIDevice *d, int reg) 155 { 156 uint8_t type; 157 158 if (reg != PCI_ROM_SLOT) 159 return PCI_BASE_ADDRESS_0 + reg * 4; 160 161 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 162 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS; 163 } 164 165 static inline int pci_irq_state(PCIDevice *d, int irq_num) 166 { 167 return (d->irq_state >> irq_num) & 0x1; 168 } 169 170 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level) 171 { 172 d->irq_state &= ~(0x1 << irq_num); 173 d->irq_state |= level << irq_num; 174 } 175 176 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change) 177 { 178 PCIBus *bus; 179 for (;;) { 180 bus = pci_dev->bus; 181 irq_num = bus->map_irq(pci_dev, irq_num); 182 if (bus->set_irq) 183 break; 184 pci_dev = bus->parent_dev; 185 } 186 bus->irq_count[irq_num] += change; 187 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0); 188 } 189 190 int pci_bus_get_irq_level(PCIBus *bus, int irq_num) 191 { 192 assert(irq_num >= 0); 193 assert(irq_num < bus->nirq); 194 return !!bus->irq_count[irq_num]; 195 } 196 197 /* Update interrupt status bit in config space on interrupt 198 * state change. */ 199 static void pci_update_irq_status(PCIDevice *dev) 200 { 201 if (dev->irq_state) { 202 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT; 203 } else { 204 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; 205 } 206 } 207 208 void pci_device_deassert_intx(PCIDevice *dev) 209 { 210 int i; 211 for (i = 0; i < PCI_NUM_PINS; ++i) { 212 pci_irq_handler(dev, i, 0); 213 } 214 } 215 216 static void pci_do_device_reset(PCIDevice *dev) 217 { 218 int r; 219 220 pci_device_deassert_intx(dev); 221 assert(dev->irq_state == 0); 222 223 /* Clear all writable bits */ 224 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND, 225 pci_get_word(dev->wmask + PCI_COMMAND) | 226 pci_get_word(dev->w1cmask + PCI_COMMAND)); 227 pci_word_test_and_clear_mask(dev->config + PCI_STATUS, 228 pci_get_word(dev->wmask + PCI_STATUS) | 229 pci_get_word(dev->w1cmask + PCI_STATUS)); 230 dev->config[PCI_CACHE_LINE_SIZE] = 0x0; 231 dev->config[PCI_INTERRUPT_LINE] = 0x0; 232 for (r = 0; r < PCI_NUM_REGIONS; ++r) { 233 PCIIORegion *region = &dev->io_regions[r]; 234 if (!region->size) { 235 continue; 236 } 237 238 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) && 239 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 240 pci_set_quad(dev->config + pci_bar(dev, r), region->type); 241 } else { 242 pci_set_long(dev->config + pci_bar(dev, r), region->type); 243 } 244 } 245 pci_update_mappings(dev); 246 247 msi_reset(dev); 248 msix_reset(dev); 249 } 250 251 /* 252 * This function is called on #RST and FLR. 253 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set 254 */ 255 void pci_device_reset(PCIDevice *dev) 256 { 257 qdev_reset_all(&dev->qdev); 258 pci_do_device_reset(dev); 259 } 260 261 /* 262 * Trigger pci bus reset under a given bus. 263 * Called via qbus_reset_all on RST# assert, after the devices 264 * have been reset qdev_reset_all-ed already. 265 */ 266 static void pcibus_reset(BusState *qbus) 267 { 268 PCIBus *bus = DO_UPCAST(PCIBus, qbus, qbus); 269 int i; 270 271 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 272 if (bus->devices[i]) { 273 pci_do_device_reset(bus->devices[i]); 274 } 275 } 276 277 for (i = 0; i < bus->nirq; i++) { 278 assert(bus->irq_count[i] == 0); 279 } 280 } 281 282 static void pci_host_bus_register(DeviceState *host) 283 { 284 PCIHostState *host_bridge = PCI_HOST_BRIDGE(host); 285 286 QLIST_INSERT_HEAD(&pci_host_bridges, host_bridge, next); 287 } 288 289 PCIBus *pci_find_primary_bus(void) 290 { 291 PCIBus *primary_bus = NULL; 292 PCIHostState *host; 293 294 QLIST_FOREACH(host, &pci_host_bridges, next) { 295 if (primary_bus) { 296 /* We have multiple root buses, refuse to select a primary */ 297 return NULL; 298 } 299 primary_bus = host->bus; 300 } 301 302 return primary_bus; 303 } 304 305 PCIBus *pci_device_root_bus(const PCIDevice *d) 306 { 307 PCIBus *bus = d->bus; 308 309 while (!pci_bus_is_root(bus)) { 310 d = bus->parent_dev; 311 assert(d != NULL); 312 313 bus = d->bus; 314 } 315 316 return bus; 317 } 318 319 const char *pci_root_bus_path(PCIDevice *dev) 320 { 321 PCIBus *rootbus = pci_device_root_bus(dev); 322 PCIHostState *host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent); 323 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_GET_CLASS(host_bridge); 324 325 assert(host_bridge->bus == rootbus); 326 327 if (hc->root_bus_path) { 328 return (*hc->root_bus_path)(host_bridge, rootbus); 329 } 330 331 return rootbus->qbus.name; 332 } 333 334 static void pci_bus_init(PCIBus *bus, DeviceState *parent, 335 MemoryRegion *address_space_mem, 336 MemoryRegion *address_space_io, 337 uint8_t devfn_min) 338 { 339 assert(PCI_FUNC(devfn_min) == 0); 340 bus->devfn_min = devfn_min; 341 bus->address_space_mem = address_space_mem; 342 bus->address_space_io = address_space_io; 343 344 /* host bridge */ 345 QLIST_INIT(&bus->child); 346 347 pci_host_bus_register(parent); 348 } 349 350 bool pci_bus_is_express(PCIBus *bus) 351 { 352 return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS); 353 } 354 355 bool pci_bus_is_root(PCIBus *bus) 356 { 357 return PCI_BUS_GET_CLASS(bus)->is_root(bus); 358 } 359 360 void pci_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent, 361 const char *name, 362 MemoryRegion *address_space_mem, 363 MemoryRegion *address_space_io, 364 uint8_t devfn_min, const char *typename) 365 { 366 qbus_create_inplace(bus, bus_size, typename, parent, name); 367 pci_bus_init(bus, parent, address_space_mem, address_space_io, devfn_min); 368 } 369 370 PCIBus *pci_bus_new(DeviceState *parent, const char *name, 371 MemoryRegion *address_space_mem, 372 MemoryRegion *address_space_io, 373 uint8_t devfn_min, const char *typename) 374 { 375 PCIBus *bus; 376 377 bus = PCI_BUS(qbus_create(typename, parent, name)); 378 pci_bus_init(bus, parent, address_space_mem, address_space_io, devfn_min); 379 return bus; 380 } 381 382 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 383 void *irq_opaque, int nirq) 384 { 385 bus->set_irq = set_irq; 386 bus->map_irq = map_irq; 387 bus->irq_opaque = irq_opaque; 388 bus->nirq = nirq; 389 bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0])); 390 } 391 392 PCIBus *pci_register_bus(DeviceState *parent, const char *name, 393 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 394 void *irq_opaque, 395 MemoryRegion *address_space_mem, 396 MemoryRegion *address_space_io, 397 uint8_t devfn_min, int nirq, const char *typename) 398 { 399 PCIBus *bus; 400 401 bus = pci_bus_new(parent, name, address_space_mem, 402 address_space_io, devfn_min, typename); 403 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq); 404 return bus; 405 } 406 407 int pci_bus_num(PCIBus *s) 408 { 409 return PCI_BUS_GET_CLASS(s)->bus_num(s); 410 } 411 412 int pci_bus_numa_node(PCIBus *bus) 413 { 414 return PCI_BUS_GET_CLASS(bus)->numa_node(bus); 415 } 416 417 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size) 418 { 419 PCIDevice *s = container_of(pv, PCIDevice, config); 420 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(s); 421 uint8_t *config; 422 int i; 423 424 assert(size == pci_config_size(s)); 425 config = g_malloc(size); 426 427 qemu_get_buffer(f, config, size); 428 for (i = 0; i < size; ++i) { 429 if ((config[i] ^ s->config[i]) & 430 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) { 431 error_report("%s: Bad config data: i=0x%x read: %x device: %x " 432 "cmask: %x wmask: %x w1cmask:%x", __func__, 433 i, config[i], s->config[i], 434 s->cmask[i], s->wmask[i], s->w1cmask[i]); 435 g_free(config); 436 return -EINVAL; 437 } 438 } 439 memcpy(s->config, config, size); 440 441 pci_update_mappings(s); 442 if (pc->is_bridge) { 443 PCIBridge *b = PCI_BRIDGE(s); 444 pci_bridge_update_mappings(b); 445 } 446 447 memory_region_set_enabled(&s->bus_master_enable_region, 448 pci_get_word(s->config + PCI_COMMAND) 449 & PCI_COMMAND_MASTER); 450 451 g_free(config); 452 return 0; 453 } 454 455 /* just put buffer */ 456 static void put_pci_config_device(QEMUFile *f, void *pv, size_t size) 457 { 458 const uint8_t **v = pv; 459 assert(size == pci_config_size(container_of(pv, PCIDevice, config))); 460 qemu_put_buffer(f, *v, size); 461 } 462 463 static VMStateInfo vmstate_info_pci_config = { 464 .name = "pci config", 465 .get = get_pci_config_device, 466 .put = put_pci_config_device, 467 }; 468 469 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size) 470 { 471 PCIDevice *s = container_of(pv, PCIDevice, irq_state); 472 uint32_t irq_state[PCI_NUM_PINS]; 473 int i; 474 for (i = 0; i < PCI_NUM_PINS; ++i) { 475 irq_state[i] = qemu_get_be32(f); 476 if (irq_state[i] != 0x1 && irq_state[i] != 0) { 477 fprintf(stderr, "irq state %d: must be 0 or 1.\n", 478 irq_state[i]); 479 return -EINVAL; 480 } 481 } 482 483 for (i = 0; i < PCI_NUM_PINS; ++i) { 484 pci_set_irq_state(s, i, irq_state[i]); 485 } 486 487 return 0; 488 } 489 490 static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size) 491 { 492 int i; 493 PCIDevice *s = container_of(pv, PCIDevice, irq_state); 494 495 for (i = 0; i < PCI_NUM_PINS; ++i) { 496 qemu_put_be32(f, pci_irq_state(s, i)); 497 } 498 } 499 500 static VMStateInfo vmstate_info_pci_irq_state = { 501 .name = "pci irq state", 502 .get = get_pci_irq_state, 503 .put = put_pci_irq_state, 504 }; 505 506 const VMStateDescription vmstate_pci_device = { 507 .name = "PCIDevice", 508 .version_id = 2, 509 .minimum_version_id = 1, 510 .fields = (VMStateField[]) { 511 VMSTATE_INT32_POSITIVE_LE(version_id, PCIDevice), 512 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0, 513 vmstate_info_pci_config, 514 PCI_CONFIG_SPACE_SIZE), 515 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2, 516 vmstate_info_pci_irq_state, 517 PCI_NUM_PINS * sizeof(int32_t)), 518 VMSTATE_END_OF_LIST() 519 } 520 }; 521 522 const VMStateDescription vmstate_pcie_device = { 523 .name = "PCIEDevice", 524 .version_id = 2, 525 .minimum_version_id = 1, 526 .fields = (VMStateField[]) { 527 VMSTATE_INT32_POSITIVE_LE(version_id, PCIDevice), 528 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0, 529 vmstate_info_pci_config, 530 PCIE_CONFIG_SPACE_SIZE), 531 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2, 532 vmstate_info_pci_irq_state, 533 PCI_NUM_PINS * sizeof(int32_t)), 534 VMSTATE_END_OF_LIST() 535 } 536 }; 537 538 static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s) 539 { 540 return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device; 541 } 542 543 void pci_device_save(PCIDevice *s, QEMUFile *f) 544 { 545 /* Clear interrupt status bit: it is implicit 546 * in irq_state which we are saving. 547 * This makes us compatible with old devices 548 * which never set or clear this bit. */ 549 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; 550 vmstate_save_state(f, pci_get_vmstate(s), s, NULL); 551 /* Restore the interrupt status bit. */ 552 pci_update_irq_status(s); 553 } 554 555 int pci_device_load(PCIDevice *s, QEMUFile *f) 556 { 557 int ret; 558 ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id); 559 /* Restore the interrupt status bit. */ 560 pci_update_irq_status(s); 561 return ret; 562 } 563 564 static void pci_set_default_subsystem_id(PCIDevice *pci_dev) 565 { 566 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, 567 pci_default_sub_vendor_id); 568 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 569 pci_default_sub_device_id); 570 } 571 572 /* 573 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL 574 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error 575 */ 576 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, 577 unsigned int *slotp, unsigned int *funcp) 578 { 579 const char *p; 580 char *e; 581 unsigned long val; 582 unsigned long dom = 0, bus = 0; 583 unsigned int slot = 0; 584 unsigned int func = 0; 585 586 p = addr; 587 val = strtoul(p, &e, 16); 588 if (e == p) 589 return -1; 590 if (*e == ':') { 591 bus = val; 592 p = e + 1; 593 val = strtoul(p, &e, 16); 594 if (e == p) 595 return -1; 596 if (*e == ':') { 597 dom = bus; 598 bus = val; 599 p = e + 1; 600 val = strtoul(p, &e, 16); 601 if (e == p) 602 return -1; 603 } 604 } 605 606 slot = val; 607 608 if (funcp != NULL) { 609 if (*e != '.') 610 return -1; 611 612 p = e + 1; 613 val = strtoul(p, &e, 16); 614 if (e == p) 615 return -1; 616 617 func = val; 618 } 619 620 /* if funcp == NULL func is 0 */ 621 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7) 622 return -1; 623 624 if (*e) 625 return -1; 626 627 *domp = dom; 628 *busp = bus; 629 *slotp = slot; 630 if (funcp != NULL) 631 *funcp = func; 632 return 0; 633 } 634 635 static PCIBus *pci_get_bus_devfn(int *devfnp, PCIBus *root, 636 const char *devaddr) 637 { 638 int dom, bus; 639 unsigned slot; 640 641 if (!root) { 642 fprintf(stderr, "No primary PCI bus\n"); 643 return NULL; 644 } 645 646 assert(!root->parent_dev); 647 648 if (!devaddr) { 649 *devfnp = -1; 650 return pci_find_bus_nr(root, 0); 651 } 652 653 if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) { 654 return NULL; 655 } 656 657 if (dom != 0) { 658 fprintf(stderr, "No support for non-zero PCI domains\n"); 659 return NULL; 660 } 661 662 *devfnp = PCI_DEVFN(slot, 0); 663 return pci_find_bus_nr(root, bus); 664 } 665 666 static void pci_init_cmask(PCIDevice *dev) 667 { 668 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff); 669 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff); 670 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST; 671 dev->cmask[PCI_REVISION_ID] = 0xff; 672 dev->cmask[PCI_CLASS_PROG] = 0xff; 673 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff); 674 dev->cmask[PCI_HEADER_TYPE] = 0xff; 675 dev->cmask[PCI_CAPABILITY_LIST] = 0xff; 676 } 677 678 static void pci_init_wmask(PCIDevice *dev) 679 { 680 int config_size = pci_config_size(dev); 681 682 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff; 683 dev->wmask[PCI_INTERRUPT_LINE] = 0xff; 684 pci_set_word(dev->wmask + PCI_COMMAND, 685 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | 686 PCI_COMMAND_INTX_DISABLE); 687 if (dev->cap_present & QEMU_PCI_CAP_SERR) { 688 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR); 689 } 690 691 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff, 692 config_size - PCI_CONFIG_HEADER_SIZE); 693 } 694 695 static void pci_init_w1cmask(PCIDevice *dev) 696 { 697 /* 698 * Note: It's okay to set w1cmask even for readonly bits as 699 * long as their value is hardwired to 0. 700 */ 701 pci_set_word(dev->w1cmask + PCI_STATUS, 702 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT | 703 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT | 704 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY); 705 } 706 707 static void pci_init_mask_bridge(PCIDevice *d) 708 { 709 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and 710 PCI_SEC_LETENCY_TIMER */ 711 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4); 712 713 /* base and limit */ 714 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff; 715 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff; 716 pci_set_word(d->wmask + PCI_MEMORY_BASE, 717 PCI_MEMORY_RANGE_MASK & 0xffff); 718 pci_set_word(d->wmask + PCI_MEMORY_LIMIT, 719 PCI_MEMORY_RANGE_MASK & 0xffff); 720 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE, 721 PCI_PREF_RANGE_MASK & 0xffff); 722 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT, 723 PCI_PREF_RANGE_MASK & 0xffff); 724 725 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */ 726 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8); 727 728 /* Supported memory and i/o types */ 729 d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16; 730 d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16; 731 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE, 732 PCI_PREF_RANGE_TYPE_64); 733 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT, 734 PCI_PREF_RANGE_TYPE_64); 735 736 /* 737 * TODO: Bridges default to 10-bit VGA decoding but we currently only 738 * implement 16-bit decoding (no alias support). 739 */ 740 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 741 PCI_BRIDGE_CTL_PARITY | 742 PCI_BRIDGE_CTL_SERR | 743 PCI_BRIDGE_CTL_ISA | 744 PCI_BRIDGE_CTL_VGA | 745 PCI_BRIDGE_CTL_VGA_16BIT | 746 PCI_BRIDGE_CTL_MASTER_ABORT | 747 PCI_BRIDGE_CTL_BUS_RESET | 748 PCI_BRIDGE_CTL_FAST_BACK | 749 PCI_BRIDGE_CTL_DISCARD | 750 PCI_BRIDGE_CTL_SEC_DISCARD | 751 PCI_BRIDGE_CTL_DISCARD_SERR); 752 /* Below does not do anything as we never set this bit, put here for 753 * completeness. */ 754 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL, 755 PCI_BRIDGE_CTL_DISCARD_STATUS); 756 d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK; 757 d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK; 758 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE, 759 PCI_PREF_RANGE_TYPE_MASK); 760 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT, 761 PCI_PREF_RANGE_TYPE_MASK); 762 } 763 764 static void pci_init_multifunction(PCIBus *bus, PCIDevice *dev, Error **errp) 765 { 766 uint8_t slot = PCI_SLOT(dev->devfn); 767 uint8_t func; 768 769 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 770 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION; 771 } 772 773 /* 774 * multifunction bit is interpreted in two ways as follows. 775 * - all functions must set the bit to 1. 776 * Example: Intel X53 777 * - function 0 must set the bit, but the rest function (> 0) 778 * is allowed to leave the bit to 0. 779 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10, 780 * 781 * So OS (at least Linux) checks the bit of only function 0, 782 * and doesn't see the bit of function > 0. 783 * 784 * The below check allows both interpretation. 785 */ 786 if (PCI_FUNC(dev->devfn)) { 787 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)]; 788 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) { 789 /* function 0 should set multifunction bit */ 790 error_setg(errp, "PCI: single function device can't be populated " 791 "in function %x.%x", slot, PCI_FUNC(dev->devfn)); 792 return; 793 } 794 return; 795 } 796 797 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 798 return; 799 } 800 /* function 0 indicates single function, so function > 0 must be NULL */ 801 for (func = 1; func < PCI_FUNC_MAX; ++func) { 802 if (bus->devices[PCI_DEVFN(slot, func)]) { 803 error_setg(errp, "PCI: %x.0 indicates single function, " 804 "but %x.%x is already populated.", 805 slot, slot, func); 806 return; 807 } 808 } 809 } 810 811 static void pci_config_alloc(PCIDevice *pci_dev) 812 { 813 int config_size = pci_config_size(pci_dev); 814 815 pci_dev->config = g_malloc0(config_size); 816 pci_dev->cmask = g_malloc0(config_size); 817 pci_dev->wmask = g_malloc0(config_size); 818 pci_dev->w1cmask = g_malloc0(config_size); 819 pci_dev->used = g_malloc0(config_size); 820 } 821 822 static void pci_config_free(PCIDevice *pci_dev) 823 { 824 g_free(pci_dev->config); 825 g_free(pci_dev->cmask); 826 g_free(pci_dev->wmask); 827 g_free(pci_dev->w1cmask); 828 g_free(pci_dev->used); 829 } 830 831 static void do_pci_unregister_device(PCIDevice *pci_dev) 832 { 833 pci_dev->bus->devices[pci_dev->devfn] = NULL; 834 pci_config_free(pci_dev); 835 836 address_space_destroy(&pci_dev->bus_master_as); 837 } 838 839 /* -1 for devfn means auto assign */ 840 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus, 841 const char *name, int devfn, 842 Error **errp) 843 { 844 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 845 PCIConfigReadFunc *config_read = pc->config_read; 846 PCIConfigWriteFunc *config_write = pc->config_write; 847 Error *local_err = NULL; 848 AddressSpace *dma_as; 849 DeviceState *dev = DEVICE(pci_dev); 850 851 pci_dev->bus = bus; 852 /* Only pci bridges can be attached to extra PCI root buses */ 853 if (pci_bus_is_root(bus) && bus->parent_dev && !pc->is_bridge) { 854 error_setg(errp, 855 "PCI: Only PCI/PCIe bridges can be plugged into %s", 856 bus->parent_dev->name); 857 return NULL; 858 } 859 860 if (devfn < 0) { 861 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices); 862 devfn += PCI_FUNC_MAX) { 863 if (!bus->devices[devfn]) 864 goto found; 865 } 866 error_setg(errp, "PCI: no slot/function available for %s, all in use", 867 name); 868 return NULL; 869 found: ; 870 } else if (bus->devices[devfn]) { 871 error_setg(errp, "PCI: slot %d function %d not available for %s," 872 " in use by %s", 873 PCI_SLOT(devfn), PCI_FUNC(devfn), name, 874 bus->devices[devfn]->name); 875 return NULL; 876 } else if (dev->hotplugged && 877 pci_get_function_0(pci_dev)) { 878 error_setg(errp, "PCI: slot %d function 0 already ocuppied by %s," 879 " new func %s cannot be exposed to guest.", 880 PCI_SLOT(devfn), 881 bus->devices[PCI_DEVFN(PCI_SLOT(devfn), 0)]->name, 882 name); 883 884 return NULL; 885 } 886 887 pci_dev->devfn = devfn; 888 dma_as = pci_device_iommu_address_space(pci_dev); 889 890 memory_region_init_alias(&pci_dev->bus_master_enable_region, 891 OBJECT(pci_dev), "bus master", 892 dma_as->root, 0, memory_region_size(dma_as->root)); 893 memory_region_set_enabled(&pci_dev->bus_master_enable_region, false); 894 address_space_init(&pci_dev->bus_master_as, &pci_dev->bus_master_enable_region, 895 name); 896 897 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name); 898 pci_dev->irq_state = 0; 899 pci_config_alloc(pci_dev); 900 901 pci_config_set_vendor_id(pci_dev->config, pc->vendor_id); 902 pci_config_set_device_id(pci_dev->config, pc->device_id); 903 pci_config_set_revision(pci_dev->config, pc->revision); 904 pci_config_set_class(pci_dev->config, pc->class_id); 905 906 if (!pc->is_bridge) { 907 if (pc->subsystem_vendor_id || pc->subsystem_id) { 908 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, 909 pc->subsystem_vendor_id); 910 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 911 pc->subsystem_id); 912 } else { 913 pci_set_default_subsystem_id(pci_dev); 914 } 915 } else { 916 /* subsystem_vendor_id/subsystem_id are only for header type 0 */ 917 assert(!pc->subsystem_vendor_id); 918 assert(!pc->subsystem_id); 919 } 920 pci_init_cmask(pci_dev); 921 pci_init_wmask(pci_dev); 922 pci_init_w1cmask(pci_dev); 923 if (pc->is_bridge) { 924 pci_init_mask_bridge(pci_dev); 925 } 926 pci_init_multifunction(bus, pci_dev, &local_err); 927 if (local_err) { 928 error_propagate(errp, local_err); 929 do_pci_unregister_device(pci_dev); 930 return NULL; 931 } 932 933 if (!config_read) 934 config_read = pci_default_read_config; 935 if (!config_write) 936 config_write = pci_default_write_config; 937 pci_dev->config_read = config_read; 938 pci_dev->config_write = config_write; 939 bus->devices[devfn] = pci_dev; 940 pci_dev->version_id = 2; /* Current pci device vmstate version */ 941 return pci_dev; 942 } 943 944 static void pci_unregister_io_regions(PCIDevice *pci_dev) 945 { 946 PCIIORegion *r; 947 int i; 948 949 for(i = 0; i < PCI_NUM_REGIONS; i++) { 950 r = &pci_dev->io_regions[i]; 951 if (!r->size || r->addr == PCI_BAR_UNMAPPED) 952 continue; 953 memory_region_del_subregion(r->address_space, r->memory); 954 } 955 956 pci_unregister_vga(pci_dev); 957 } 958 959 static void pci_qdev_unrealize(DeviceState *dev, Error **errp) 960 { 961 PCIDevice *pci_dev = PCI_DEVICE(dev); 962 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 963 964 pci_unregister_io_regions(pci_dev); 965 pci_del_option_rom(pci_dev); 966 967 if (pc->exit) { 968 pc->exit(pci_dev); 969 } 970 971 do_pci_unregister_device(pci_dev); 972 } 973 974 void pci_register_bar(PCIDevice *pci_dev, int region_num, 975 uint8_t type, MemoryRegion *memory) 976 { 977 PCIIORegion *r; 978 uint32_t addr; 979 uint64_t wmask; 980 pcibus_t size = memory_region_size(memory); 981 982 assert(region_num >= 0); 983 assert(region_num < PCI_NUM_REGIONS); 984 if (size & (size-1)) { 985 fprintf(stderr, "ERROR: PCI region size must be pow2 " 986 "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size); 987 exit(1); 988 } 989 990 r = &pci_dev->io_regions[region_num]; 991 r->addr = PCI_BAR_UNMAPPED; 992 r->size = size; 993 r->type = type; 994 r->memory = NULL; 995 996 wmask = ~(size - 1); 997 addr = pci_bar(pci_dev, region_num); 998 if (region_num == PCI_ROM_SLOT) { 999 /* ROM enable bit is writable */ 1000 wmask |= PCI_ROM_ADDRESS_ENABLE; 1001 } 1002 pci_set_long(pci_dev->config + addr, type); 1003 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) && 1004 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 1005 pci_set_quad(pci_dev->wmask + addr, wmask); 1006 pci_set_quad(pci_dev->cmask + addr, ~0ULL); 1007 } else { 1008 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff); 1009 pci_set_long(pci_dev->cmask + addr, 0xffffffff); 1010 } 1011 pci_dev->io_regions[region_num].memory = memory; 1012 pci_dev->io_regions[region_num].address_space 1013 = type & PCI_BASE_ADDRESS_SPACE_IO 1014 ? pci_dev->bus->address_space_io 1015 : pci_dev->bus->address_space_mem; 1016 } 1017 1018 static void pci_update_vga(PCIDevice *pci_dev) 1019 { 1020 uint16_t cmd; 1021 1022 if (!pci_dev->has_vga) { 1023 return; 1024 } 1025 1026 cmd = pci_get_word(pci_dev->config + PCI_COMMAND); 1027 1028 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_MEM], 1029 cmd & PCI_COMMAND_MEMORY); 1030 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO], 1031 cmd & PCI_COMMAND_IO); 1032 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI], 1033 cmd & PCI_COMMAND_IO); 1034 } 1035 1036 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, 1037 MemoryRegion *io_lo, MemoryRegion *io_hi) 1038 { 1039 assert(!pci_dev->has_vga); 1040 1041 assert(memory_region_size(mem) == QEMU_PCI_VGA_MEM_SIZE); 1042 pci_dev->vga_regions[QEMU_PCI_VGA_MEM] = mem; 1043 memory_region_add_subregion_overlap(pci_dev->bus->address_space_mem, 1044 QEMU_PCI_VGA_MEM_BASE, mem, 1); 1045 1046 assert(memory_region_size(io_lo) == QEMU_PCI_VGA_IO_LO_SIZE); 1047 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO] = io_lo; 1048 memory_region_add_subregion_overlap(pci_dev->bus->address_space_io, 1049 QEMU_PCI_VGA_IO_LO_BASE, io_lo, 1); 1050 1051 assert(memory_region_size(io_hi) == QEMU_PCI_VGA_IO_HI_SIZE); 1052 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI] = io_hi; 1053 memory_region_add_subregion_overlap(pci_dev->bus->address_space_io, 1054 QEMU_PCI_VGA_IO_HI_BASE, io_hi, 1); 1055 pci_dev->has_vga = true; 1056 1057 pci_update_vga(pci_dev); 1058 } 1059 1060 void pci_unregister_vga(PCIDevice *pci_dev) 1061 { 1062 if (!pci_dev->has_vga) { 1063 return; 1064 } 1065 1066 memory_region_del_subregion(pci_dev->bus->address_space_mem, 1067 pci_dev->vga_regions[QEMU_PCI_VGA_MEM]); 1068 memory_region_del_subregion(pci_dev->bus->address_space_io, 1069 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO]); 1070 memory_region_del_subregion(pci_dev->bus->address_space_io, 1071 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI]); 1072 pci_dev->has_vga = false; 1073 } 1074 1075 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num) 1076 { 1077 return pci_dev->io_regions[region_num].addr; 1078 } 1079 1080 static pcibus_t pci_bar_address(PCIDevice *d, 1081 int reg, uint8_t type, pcibus_t size) 1082 { 1083 pcibus_t new_addr, last_addr; 1084 int bar = pci_bar(d, reg); 1085 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND); 1086 Object *machine = qdev_get_machine(); 1087 ObjectClass *oc = object_get_class(machine); 1088 MachineClass *mc = MACHINE_CLASS(oc); 1089 bool allow_0_address = mc->pci_allow_0_address; 1090 1091 if (type & PCI_BASE_ADDRESS_SPACE_IO) { 1092 if (!(cmd & PCI_COMMAND_IO)) { 1093 return PCI_BAR_UNMAPPED; 1094 } 1095 new_addr = pci_get_long(d->config + bar) & ~(size - 1); 1096 last_addr = new_addr + size - 1; 1097 /* Check if 32 bit BAR wraps around explicitly. 1098 * TODO: make priorities correct and remove this work around. 1099 */ 1100 if (last_addr <= new_addr || last_addr >= UINT32_MAX || 1101 (!allow_0_address && new_addr == 0)) { 1102 return PCI_BAR_UNMAPPED; 1103 } 1104 return new_addr; 1105 } 1106 1107 if (!(cmd & PCI_COMMAND_MEMORY)) { 1108 return PCI_BAR_UNMAPPED; 1109 } 1110 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 1111 new_addr = pci_get_quad(d->config + bar); 1112 } else { 1113 new_addr = pci_get_long(d->config + bar); 1114 } 1115 /* the ROM slot has a specific enable bit */ 1116 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) { 1117 return PCI_BAR_UNMAPPED; 1118 } 1119 new_addr &= ~(size - 1); 1120 last_addr = new_addr + size - 1; 1121 /* NOTE: we do not support wrapping */ 1122 /* XXX: as we cannot support really dynamic 1123 mappings, we handle specific values as invalid 1124 mappings. */ 1125 if (last_addr <= new_addr || last_addr == PCI_BAR_UNMAPPED || 1126 (!allow_0_address && new_addr == 0)) { 1127 return PCI_BAR_UNMAPPED; 1128 } 1129 1130 /* Now pcibus_t is 64bit. 1131 * Check if 32 bit BAR wraps around explicitly. 1132 * Without this, PC ide doesn't work well. 1133 * TODO: remove this work around. 1134 */ 1135 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) { 1136 return PCI_BAR_UNMAPPED; 1137 } 1138 1139 /* 1140 * OS is allowed to set BAR beyond its addressable 1141 * bits. For example, 32 bit OS can set 64bit bar 1142 * to >4G. Check it. TODO: we might need to support 1143 * it in the future for e.g. PAE. 1144 */ 1145 if (last_addr >= HWADDR_MAX) { 1146 return PCI_BAR_UNMAPPED; 1147 } 1148 1149 return new_addr; 1150 } 1151 1152 static void pci_update_mappings(PCIDevice *d) 1153 { 1154 PCIIORegion *r; 1155 int i; 1156 pcibus_t new_addr; 1157 1158 for(i = 0; i < PCI_NUM_REGIONS; i++) { 1159 r = &d->io_regions[i]; 1160 1161 /* this region isn't registered */ 1162 if (!r->size) 1163 continue; 1164 1165 new_addr = pci_bar_address(d, i, r->type, r->size); 1166 1167 /* This bar isn't changed */ 1168 if (new_addr == r->addr) 1169 continue; 1170 1171 /* now do the real mapping */ 1172 if (r->addr != PCI_BAR_UNMAPPED) { 1173 trace_pci_update_mappings_del(d, pci_bus_num(d->bus), 1174 PCI_SLOT(d->devfn), 1175 PCI_FUNC(d->devfn), 1176 i, r->addr, r->size); 1177 memory_region_del_subregion(r->address_space, r->memory); 1178 } 1179 r->addr = new_addr; 1180 if (r->addr != PCI_BAR_UNMAPPED) { 1181 trace_pci_update_mappings_add(d, pci_bus_num(d->bus), 1182 PCI_SLOT(d->devfn), 1183 PCI_FUNC(d->devfn), 1184 i, r->addr, r->size); 1185 memory_region_add_subregion_overlap(r->address_space, 1186 r->addr, r->memory, 1); 1187 } 1188 } 1189 1190 pci_update_vga(d); 1191 } 1192 1193 static inline int pci_irq_disabled(PCIDevice *d) 1194 { 1195 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE; 1196 } 1197 1198 /* Called after interrupt disabled field update in config space, 1199 * assert/deassert interrupts if necessary. 1200 * Gets original interrupt disable bit value (before update). */ 1201 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled) 1202 { 1203 int i, disabled = pci_irq_disabled(d); 1204 if (disabled == was_irq_disabled) 1205 return; 1206 for (i = 0; i < PCI_NUM_PINS; ++i) { 1207 int state = pci_irq_state(d, i); 1208 pci_change_irq_level(d, i, disabled ? -state : state); 1209 } 1210 } 1211 1212 uint32_t pci_default_read_config(PCIDevice *d, 1213 uint32_t address, int len) 1214 { 1215 uint32_t val = 0; 1216 1217 memcpy(&val, d->config + address, len); 1218 return le32_to_cpu(val); 1219 } 1220 1221 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val_in, int l) 1222 { 1223 int i, was_irq_disabled = pci_irq_disabled(d); 1224 uint32_t val = val_in; 1225 1226 for (i = 0; i < l; val >>= 8, ++i) { 1227 uint8_t wmask = d->wmask[addr + i]; 1228 uint8_t w1cmask = d->w1cmask[addr + i]; 1229 assert(!(wmask & w1cmask)); 1230 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask); 1231 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */ 1232 } 1233 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) || 1234 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) || 1235 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) || 1236 range_covers_byte(addr, l, PCI_COMMAND)) 1237 pci_update_mappings(d); 1238 1239 if (range_covers_byte(addr, l, PCI_COMMAND)) { 1240 pci_update_irq_disabled(d, was_irq_disabled); 1241 memory_region_set_enabled(&d->bus_master_enable_region, 1242 pci_get_word(d->config + PCI_COMMAND) 1243 & PCI_COMMAND_MASTER); 1244 } 1245 1246 msi_write_config(d, addr, val_in, l); 1247 msix_write_config(d, addr, val_in, l); 1248 } 1249 1250 /***********************************************************/ 1251 /* generic PCI irq support */ 1252 1253 /* 0 <= irq_num <= 3. level must be 0 or 1 */ 1254 static void pci_irq_handler(void *opaque, int irq_num, int level) 1255 { 1256 PCIDevice *pci_dev = opaque; 1257 int change; 1258 1259 change = level - pci_irq_state(pci_dev, irq_num); 1260 if (!change) 1261 return; 1262 1263 pci_set_irq_state(pci_dev, irq_num, level); 1264 pci_update_irq_status(pci_dev); 1265 if (pci_irq_disabled(pci_dev)) 1266 return; 1267 pci_change_irq_level(pci_dev, irq_num, change); 1268 } 1269 1270 static inline int pci_intx(PCIDevice *pci_dev) 1271 { 1272 return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1; 1273 } 1274 1275 qemu_irq pci_allocate_irq(PCIDevice *pci_dev) 1276 { 1277 int intx = pci_intx(pci_dev); 1278 1279 return qemu_allocate_irq(pci_irq_handler, pci_dev, intx); 1280 } 1281 1282 void pci_set_irq(PCIDevice *pci_dev, int level) 1283 { 1284 int intx = pci_intx(pci_dev); 1285 pci_irq_handler(pci_dev, intx, level); 1286 } 1287 1288 /* Special hooks used by device assignment */ 1289 void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq) 1290 { 1291 assert(pci_bus_is_root(bus)); 1292 bus->route_intx_to_irq = route_intx_to_irq; 1293 } 1294 1295 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin) 1296 { 1297 PCIBus *bus; 1298 1299 do { 1300 bus = dev->bus; 1301 pin = bus->map_irq(dev, pin); 1302 dev = bus->parent_dev; 1303 } while (dev); 1304 1305 if (!bus->route_intx_to_irq) { 1306 error_report("PCI: Bug - unimplemented PCI INTx routing (%s)", 1307 object_get_typename(OBJECT(bus->qbus.parent))); 1308 return (PCIINTxRoute) { PCI_INTX_DISABLED, -1 }; 1309 } 1310 1311 return bus->route_intx_to_irq(bus->irq_opaque, pin); 1312 } 1313 1314 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new) 1315 { 1316 return old->mode != new->mode || old->irq != new->irq; 1317 } 1318 1319 void pci_bus_fire_intx_routing_notifier(PCIBus *bus) 1320 { 1321 PCIDevice *dev; 1322 PCIBus *sec; 1323 int i; 1324 1325 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 1326 dev = bus->devices[i]; 1327 if (dev && dev->intx_routing_notifier) { 1328 dev->intx_routing_notifier(dev); 1329 } 1330 } 1331 1332 QLIST_FOREACH(sec, &bus->child, sibling) { 1333 pci_bus_fire_intx_routing_notifier(sec); 1334 } 1335 } 1336 1337 void pci_device_set_intx_routing_notifier(PCIDevice *dev, 1338 PCIINTxRoutingNotifier notifier) 1339 { 1340 dev->intx_routing_notifier = notifier; 1341 } 1342 1343 /* 1344 * PCI-to-PCI bridge specification 1345 * 9.1: Interrupt routing. Table 9-1 1346 * 1347 * the PCI Express Base Specification, Revision 2.1 1348 * 2.2.8.1: INTx interrutp signaling - Rules 1349 * the Implementation Note 1350 * Table 2-20 1351 */ 1352 /* 1353 * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD 1354 * 0-origin unlike PCI interrupt pin register. 1355 */ 1356 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin) 1357 { 1358 return (pin + PCI_SLOT(pci_dev->devfn)) % PCI_NUM_PINS; 1359 } 1360 1361 /***********************************************************/ 1362 /* monitor info on PCI */ 1363 1364 typedef struct { 1365 uint16_t class; 1366 const char *desc; 1367 const char *fw_name; 1368 uint16_t fw_ign_bits; 1369 } pci_class_desc; 1370 1371 static const pci_class_desc pci_class_descriptions[] = 1372 { 1373 { 0x0001, "VGA controller", "display"}, 1374 { 0x0100, "SCSI controller", "scsi"}, 1375 { 0x0101, "IDE controller", "ide"}, 1376 { 0x0102, "Floppy controller", "fdc"}, 1377 { 0x0103, "IPI controller", "ipi"}, 1378 { 0x0104, "RAID controller", "raid"}, 1379 { 0x0106, "SATA controller"}, 1380 { 0x0107, "SAS controller"}, 1381 { 0x0180, "Storage controller"}, 1382 { 0x0200, "Ethernet controller", "ethernet"}, 1383 { 0x0201, "Token Ring controller", "token-ring"}, 1384 { 0x0202, "FDDI controller", "fddi"}, 1385 { 0x0203, "ATM controller", "atm"}, 1386 { 0x0280, "Network controller"}, 1387 { 0x0300, "VGA controller", "display", 0x00ff}, 1388 { 0x0301, "XGA controller"}, 1389 { 0x0302, "3D controller"}, 1390 { 0x0380, "Display controller"}, 1391 { 0x0400, "Video controller", "video"}, 1392 { 0x0401, "Audio controller", "sound"}, 1393 { 0x0402, "Phone"}, 1394 { 0x0403, "Audio controller", "sound"}, 1395 { 0x0480, "Multimedia controller"}, 1396 { 0x0500, "RAM controller", "memory"}, 1397 { 0x0501, "Flash controller", "flash"}, 1398 { 0x0580, "Memory controller"}, 1399 { 0x0600, "Host bridge", "host"}, 1400 { 0x0601, "ISA bridge", "isa"}, 1401 { 0x0602, "EISA bridge", "eisa"}, 1402 { 0x0603, "MC bridge", "mca"}, 1403 { 0x0604, "PCI bridge", "pci-bridge"}, 1404 { 0x0605, "PCMCIA bridge", "pcmcia"}, 1405 { 0x0606, "NUBUS bridge", "nubus"}, 1406 { 0x0607, "CARDBUS bridge", "cardbus"}, 1407 { 0x0608, "RACEWAY bridge"}, 1408 { 0x0680, "Bridge"}, 1409 { 0x0700, "Serial port", "serial"}, 1410 { 0x0701, "Parallel port", "parallel"}, 1411 { 0x0800, "Interrupt controller", "interrupt-controller"}, 1412 { 0x0801, "DMA controller", "dma-controller"}, 1413 { 0x0802, "Timer", "timer"}, 1414 { 0x0803, "RTC", "rtc"}, 1415 { 0x0900, "Keyboard", "keyboard"}, 1416 { 0x0901, "Pen", "pen"}, 1417 { 0x0902, "Mouse", "mouse"}, 1418 { 0x0A00, "Dock station", "dock", 0x00ff}, 1419 { 0x0B00, "i386 cpu", "cpu", 0x00ff}, 1420 { 0x0c00, "Fireware contorller", "fireware"}, 1421 { 0x0c01, "Access bus controller", "access-bus"}, 1422 { 0x0c02, "SSA controller", "ssa"}, 1423 { 0x0c03, "USB controller", "usb"}, 1424 { 0x0c04, "Fibre channel controller", "fibre-channel"}, 1425 { 0x0c05, "SMBus"}, 1426 { 0, NULL} 1427 }; 1428 1429 static void pci_for_each_device_under_bus(PCIBus *bus, 1430 void (*fn)(PCIBus *b, PCIDevice *d, 1431 void *opaque), 1432 void *opaque) 1433 { 1434 PCIDevice *d; 1435 int devfn; 1436 1437 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1438 d = bus->devices[devfn]; 1439 if (d) { 1440 fn(bus, d, opaque); 1441 } 1442 } 1443 } 1444 1445 void pci_for_each_device(PCIBus *bus, int bus_num, 1446 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque), 1447 void *opaque) 1448 { 1449 bus = pci_find_bus_nr(bus, bus_num); 1450 1451 if (bus) { 1452 pci_for_each_device_under_bus(bus, fn, opaque); 1453 } 1454 } 1455 1456 static const pci_class_desc *get_class_desc(int class) 1457 { 1458 const pci_class_desc *desc; 1459 1460 desc = pci_class_descriptions; 1461 while (desc->desc && class != desc->class) { 1462 desc++; 1463 } 1464 1465 return desc; 1466 } 1467 1468 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num); 1469 1470 static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev) 1471 { 1472 PciMemoryRegionList *head = NULL, *cur_item = NULL; 1473 int i; 1474 1475 for (i = 0; i < PCI_NUM_REGIONS; i++) { 1476 const PCIIORegion *r = &dev->io_regions[i]; 1477 PciMemoryRegionList *region; 1478 1479 if (!r->size) { 1480 continue; 1481 } 1482 1483 region = g_malloc0(sizeof(*region)); 1484 region->value = g_malloc0(sizeof(*region->value)); 1485 1486 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { 1487 region->value->type = g_strdup("io"); 1488 } else { 1489 region->value->type = g_strdup("memory"); 1490 region->value->has_prefetch = true; 1491 region->value->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH); 1492 region->value->has_mem_type_64 = true; 1493 region->value->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64); 1494 } 1495 1496 region->value->bar = i; 1497 region->value->address = r->addr; 1498 region->value->size = r->size; 1499 1500 /* XXX: waiting for the qapi to support GSList */ 1501 if (!cur_item) { 1502 head = cur_item = region; 1503 } else { 1504 cur_item->next = region; 1505 cur_item = region; 1506 } 1507 } 1508 1509 return head; 1510 } 1511 1512 static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus, 1513 int bus_num) 1514 { 1515 PciBridgeInfo *info; 1516 PciMemoryRange *range; 1517 1518 info = g_new0(PciBridgeInfo, 1); 1519 1520 info->bus = g_new0(PciBusInfo, 1); 1521 info->bus->number = dev->config[PCI_PRIMARY_BUS]; 1522 info->bus->secondary = dev->config[PCI_SECONDARY_BUS]; 1523 info->bus->subordinate = dev->config[PCI_SUBORDINATE_BUS]; 1524 1525 range = info->bus->io_range = g_new0(PciMemoryRange, 1); 1526 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO); 1527 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO); 1528 1529 range = info->bus->memory_range = g_new0(PciMemoryRange, 1); 1530 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 1531 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 1532 1533 range = info->bus->prefetchable_range = g_new0(PciMemoryRange, 1); 1534 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 1535 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 1536 1537 if (dev->config[PCI_SECONDARY_BUS] != 0) { 1538 PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]); 1539 if (child_bus) { 1540 info->has_devices = true; 1541 info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]); 1542 } 1543 } 1544 1545 return info; 1546 } 1547 1548 static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus, 1549 int bus_num) 1550 { 1551 const pci_class_desc *desc; 1552 PciDeviceInfo *info; 1553 uint8_t type; 1554 int class; 1555 1556 info = g_new0(PciDeviceInfo, 1); 1557 info->bus = bus_num; 1558 info->slot = PCI_SLOT(dev->devfn); 1559 info->function = PCI_FUNC(dev->devfn); 1560 1561 info->class_info = g_new0(PciDeviceClass, 1); 1562 class = pci_get_word(dev->config + PCI_CLASS_DEVICE); 1563 info->class_info->q_class = class; 1564 desc = get_class_desc(class); 1565 if (desc->desc) { 1566 info->class_info->has_desc = true; 1567 info->class_info->desc = g_strdup(desc->desc); 1568 } 1569 1570 info->id = g_new0(PciDeviceId, 1); 1571 info->id->vendor = pci_get_word(dev->config + PCI_VENDOR_ID); 1572 info->id->device = pci_get_word(dev->config + PCI_DEVICE_ID); 1573 info->regions = qmp_query_pci_regions(dev); 1574 info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : ""); 1575 1576 if (dev->config[PCI_INTERRUPT_PIN] != 0) { 1577 info->has_irq = true; 1578 info->irq = dev->config[PCI_INTERRUPT_LINE]; 1579 } 1580 1581 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 1582 if (type == PCI_HEADER_TYPE_BRIDGE) { 1583 info->has_pci_bridge = true; 1584 info->pci_bridge = qmp_query_pci_bridge(dev, bus, bus_num); 1585 } 1586 1587 return info; 1588 } 1589 1590 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num) 1591 { 1592 PciDeviceInfoList *info, *head = NULL, *cur_item = NULL; 1593 PCIDevice *dev; 1594 int devfn; 1595 1596 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1597 dev = bus->devices[devfn]; 1598 if (dev) { 1599 info = g_malloc0(sizeof(*info)); 1600 info->value = qmp_query_pci_device(dev, bus, bus_num); 1601 1602 /* XXX: waiting for the qapi to support GSList */ 1603 if (!cur_item) { 1604 head = cur_item = info; 1605 } else { 1606 cur_item->next = info; 1607 cur_item = info; 1608 } 1609 } 1610 } 1611 1612 return head; 1613 } 1614 1615 static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num) 1616 { 1617 PciInfo *info = NULL; 1618 1619 bus = pci_find_bus_nr(bus, bus_num); 1620 if (bus) { 1621 info = g_malloc0(sizeof(*info)); 1622 info->bus = bus_num; 1623 info->devices = qmp_query_pci_devices(bus, bus_num); 1624 } 1625 1626 return info; 1627 } 1628 1629 PciInfoList *qmp_query_pci(Error **errp) 1630 { 1631 PciInfoList *info, *head = NULL, *cur_item = NULL; 1632 PCIHostState *host_bridge; 1633 1634 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { 1635 info = g_malloc0(sizeof(*info)); 1636 info->value = qmp_query_pci_bus(host_bridge->bus, 1637 pci_bus_num(host_bridge->bus)); 1638 1639 /* XXX: waiting for the qapi to support GSList */ 1640 if (!cur_item) { 1641 head = cur_item = info; 1642 } else { 1643 cur_item->next = info; 1644 cur_item = info; 1645 } 1646 } 1647 1648 return head; 1649 } 1650 1651 static const char * const pci_nic_models[] = { 1652 "ne2k_pci", 1653 "i82551", 1654 "i82557b", 1655 "i82559er", 1656 "rtl8139", 1657 "e1000", 1658 "pcnet", 1659 "virtio", 1660 NULL 1661 }; 1662 1663 static const char * const pci_nic_names[] = { 1664 "ne2k_pci", 1665 "i82551", 1666 "i82557b", 1667 "i82559er", 1668 "rtl8139", 1669 "e1000", 1670 "pcnet", 1671 "virtio-net-pci", 1672 NULL 1673 }; 1674 1675 /* Initialize a PCI NIC. */ 1676 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus, 1677 const char *default_model, 1678 const char *default_devaddr) 1679 { 1680 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr; 1681 Error *err = NULL; 1682 PCIBus *bus; 1683 PCIDevice *pci_dev; 1684 DeviceState *dev; 1685 int devfn; 1686 int i; 1687 1688 if (qemu_show_nic_models(nd->model, pci_nic_models)) { 1689 exit(0); 1690 } 1691 1692 i = qemu_find_nic_model(nd, pci_nic_models, default_model); 1693 if (i < 0) { 1694 exit(1); 1695 } 1696 1697 bus = pci_get_bus_devfn(&devfn, rootbus, devaddr); 1698 if (!bus) { 1699 error_report("Invalid PCI device address %s for device %s", 1700 devaddr, pci_nic_names[i]); 1701 exit(1); 1702 } 1703 1704 pci_dev = pci_create(bus, devfn, pci_nic_names[i]); 1705 dev = &pci_dev->qdev; 1706 qdev_set_nic_properties(dev, nd); 1707 1708 object_property_set_bool(OBJECT(dev), true, "realized", &err); 1709 if (err) { 1710 error_report_err(err); 1711 object_unparent(OBJECT(dev)); 1712 exit(1); 1713 } 1714 1715 return pci_dev; 1716 } 1717 1718 PCIDevice *pci_vga_init(PCIBus *bus) 1719 { 1720 switch (vga_interface_type) { 1721 case VGA_CIRRUS: 1722 return pci_create_simple(bus, -1, "cirrus-vga"); 1723 case VGA_QXL: 1724 return pci_create_simple(bus, -1, "qxl-vga"); 1725 case VGA_STD: 1726 return pci_create_simple(bus, -1, "VGA"); 1727 case VGA_VMWARE: 1728 return pci_create_simple(bus, -1, "vmware-svga"); 1729 case VGA_VIRTIO: 1730 return pci_create_simple(bus, -1, "virtio-vga"); 1731 case VGA_NONE: 1732 default: /* Other non-PCI types. Checking for unsupported types is already 1733 done in vl.c. */ 1734 return NULL; 1735 } 1736 } 1737 1738 /* Whether a given bus number is in range of the secondary 1739 * bus of the given bridge device. */ 1740 static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num) 1741 { 1742 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) & 1743 PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ && 1744 dev->config[PCI_SECONDARY_BUS] <= bus_num && 1745 bus_num <= dev->config[PCI_SUBORDINATE_BUS]; 1746 } 1747 1748 /* Whether a given bus number is in a range of a root bus */ 1749 static bool pci_root_bus_in_range(PCIBus *bus, int bus_num) 1750 { 1751 int i; 1752 1753 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 1754 PCIDevice *dev = bus->devices[i]; 1755 1756 if (dev && PCI_DEVICE_GET_CLASS(dev)->is_bridge) { 1757 if (pci_secondary_bus_in_range(dev, bus_num)) { 1758 return true; 1759 } 1760 } 1761 } 1762 1763 return false; 1764 } 1765 1766 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num) 1767 { 1768 PCIBus *sec; 1769 1770 if (!bus) { 1771 return NULL; 1772 } 1773 1774 if (pci_bus_num(bus) == bus_num) { 1775 return bus; 1776 } 1777 1778 /* Consider all bus numbers in range for the host pci bridge. */ 1779 if (!pci_bus_is_root(bus) && 1780 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) { 1781 return NULL; 1782 } 1783 1784 /* try child bus */ 1785 for (; bus; bus = sec) { 1786 QLIST_FOREACH(sec, &bus->child, sibling) { 1787 if (pci_bus_num(sec) == bus_num) { 1788 return sec; 1789 } 1790 /* PXB buses assumed to be children of bus 0 */ 1791 if (pci_bus_is_root(sec)) { 1792 if (pci_root_bus_in_range(sec, bus_num)) { 1793 break; 1794 } 1795 } else { 1796 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) { 1797 break; 1798 } 1799 } 1800 } 1801 } 1802 1803 return NULL; 1804 } 1805 1806 void pci_for_each_bus_depth_first(PCIBus *bus, 1807 void *(*begin)(PCIBus *bus, void *parent_state), 1808 void (*end)(PCIBus *bus, void *state), 1809 void *parent_state) 1810 { 1811 PCIBus *sec; 1812 void *state; 1813 1814 if (!bus) { 1815 return; 1816 } 1817 1818 if (begin) { 1819 state = begin(bus, parent_state); 1820 } else { 1821 state = parent_state; 1822 } 1823 1824 QLIST_FOREACH(sec, &bus->child, sibling) { 1825 pci_for_each_bus_depth_first(sec, begin, end, state); 1826 } 1827 1828 if (end) { 1829 end(bus, state); 1830 } 1831 } 1832 1833 1834 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn) 1835 { 1836 bus = pci_find_bus_nr(bus, bus_num); 1837 1838 if (!bus) 1839 return NULL; 1840 1841 return bus->devices[devfn]; 1842 } 1843 1844 static void pci_qdev_realize(DeviceState *qdev, Error **errp) 1845 { 1846 PCIDevice *pci_dev = (PCIDevice *)qdev; 1847 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 1848 Error *local_err = NULL; 1849 PCIBus *bus; 1850 bool is_default_rom; 1851 1852 /* initialize cap_present for pci_is_express() and pci_config_size() */ 1853 if (pc->is_express) { 1854 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; 1855 } 1856 1857 bus = PCI_BUS(qdev_get_parent_bus(qdev)); 1858 pci_dev = do_pci_register_device(pci_dev, bus, 1859 object_get_typename(OBJECT(qdev)), 1860 pci_dev->devfn, errp); 1861 if (pci_dev == NULL) 1862 return; 1863 1864 if (pc->realize) { 1865 pc->realize(pci_dev, &local_err); 1866 if (local_err) { 1867 error_propagate(errp, local_err); 1868 do_pci_unregister_device(pci_dev); 1869 return; 1870 } 1871 } 1872 1873 /* rom loading */ 1874 is_default_rom = false; 1875 if (pci_dev->romfile == NULL && pc->romfile != NULL) { 1876 pci_dev->romfile = g_strdup(pc->romfile); 1877 is_default_rom = true; 1878 } 1879 1880 pci_add_option_rom(pci_dev, is_default_rom, &local_err); 1881 if (local_err) { 1882 error_propagate(errp, local_err); 1883 pci_qdev_unrealize(DEVICE(pci_dev), NULL); 1884 return; 1885 } 1886 } 1887 1888 static void pci_default_realize(PCIDevice *dev, Error **errp) 1889 { 1890 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 1891 1892 if (pc->init) { 1893 if (pc->init(dev) < 0) { 1894 error_setg(errp, "Device initialization failed"); 1895 return; 1896 } 1897 } 1898 } 1899 1900 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction, 1901 const char *name) 1902 { 1903 DeviceState *dev; 1904 1905 dev = qdev_create(&bus->qbus, name); 1906 qdev_prop_set_int32(dev, "addr", devfn); 1907 qdev_prop_set_bit(dev, "multifunction", multifunction); 1908 return PCI_DEVICE(dev); 1909 } 1910 1911 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, 1912 bool multifunction, 1913 const char *name) 1914 { 1915 PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name); 1916 qdev_init_nofail(&dev->qdev); 1917 return dev; 1918 } 1919 1920 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name) 1921 { 1922 return pci_create_multifunction(bus, devfn, false, name); 1923 } 1924 1925 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name) 1926 { 1927 return pci_create_simple_multifunction(bus, devfn, false, name); 1928 } 1929 1930 static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size) 1931 { 1932 int offset = PCI_CONFIG_HEADER_SIZE; 1933 int i; 1934 for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) { 1935 if (pdev->used[i]) 1936 offset = i + 1; 1937 else if (i - offset + 1 == size) 1938 return offset; 1939 } 1940 return 0; 1941 } 1942 1943 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id, 1944 uint8_t *prev_p) 1945 { 1946 uint8_t next, prev; 1947 1948 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST)) 1949 return 0; 1950 1951 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); 1952 prev = next + PCI_CAP_LIST_NEXT) 1953 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id) 1954 break; 1955 1956 if (prev_p) 1957 *prev_p = prev; 1958 return next; 1959 } 1960 1961 static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset) 1962 { 1963 uint8_t next, prev, found = 0; 1964 1965 if (!(pdev->used[offset])) { 1966 return 0; 1967 } 1968 1969 assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST); 1970 1971 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); 1972 prev = next + PCI_CAP_LIST_NEXT) { 1973 if (next <= offset && next > found) { 1974 found = next; 1975 } 1976 } 1977 return found; 1978 } 1979 1980 /* Patch the PCI vendor and device ids in a PCI rom image if necessary. 1981 This is needed for an option rom which is used for more than one device. */ 1982 static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size) 1983 { 1984 uint16_t vendor_id; 1985 uint16_t device_id; 1986 uint16_t rom_vendor_id; 1987 uint16_t rom_device_id; 1988 uint16_t rom_magic; 1989 uint16_t pcir_offset; 1990 uint8_t checksum; 1991 1992 /* Words in rom data are little endian (like in PCI configuration), 1993 so they can be read / written with pci_get_word / pci_set_word. */ 1994 1995 /* Only a valid rom will be patched. */ 1996 rom_magic = pci_get_word(ptr); 1997 if (rom_magic != 0xaa55) { 1998 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic); 1999 return; 2000 } 2001 pcir_offset = pci_get_word(ptr + 0x18); 2002 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) { 2003 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset); 2004 return; 2005 } 2006 2007 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID); 2008 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID); 2009 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4); 2010 rom_device_id = pci_get_word(ptr + pcir_offset + 6); 2011 2012 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile, 2013 vendor_id, device_id, rom_vendor_id, rom_device_id); 2014 2015 checksum = ptr[6]; 2016 2017 if (vendor_id != rom_vendor_id) { 2018 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */ 2019 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8); 2020 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8); 2021 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); 2022 ptr[6] = checksum; 2023 pci_set_word(ptr + pcir_offset + 4, vendor_id); 2024 } 2025 2026 if (device_id != rom_device_id) { 2027 /* Patch device id and checksum (at offset 6 for etherboot roms). */ 2028 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8); 2029 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8); 2030 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); 2031 ptr[6] = checksum; 2032 pci_set_word(ptr + pcir_offset + 6, device_id); 2033 } 2034 } 2035 2036 /* Add an option rom for the device */ 2037 static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, 2038 Error **errp) 2039 { 2040 int size; 2041 char *path; 2042 void *ptr; 2043 char name[32]; 2044 const VMStateDescription *vmsd; 2045 2046 if (!pdev->romfile) 2047 return; 2048 if (strlen(pdev->romfile) == 0) 2049 return; 2050 2051 if (!pdev->rom_bar) { 2052 /* 2053 * Load rom via fw_cfg instead of creating a rom bar, 2054 * for 0.11 compatibility. 2055 */ 2056 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE); 2057 2058 /* 2059 * Hot-plugged devices can't use the option ROM 2060 * if the rom bar is disabled. 2061 */ 2062 if (DEVICE(pdev)->hotplugged) { 2063 error_setg(errp, "Hot-plugged device without ROM bar" 2064 " can't have an option ROM"); 2065 return; 2066 } 2067 2068 if (class == 0x0300) { 2069 rom_add_vga(pdev->romfile); 2070 } else { 2071 rom_add_option(pdev->romfile, -1); 2072 } 2073 return; 2074 } 2075 2076 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile); 2077 if (path == NULL) { 2078 path = g_strdup(pdev->romfile); 2079 } 2080 2081 size = get_image_size(path); 2082 if (size < 0) { 2083 error_setg(errp, "failed to find romfile \"%s\"", pdev->romfile); 2084 g_free(path); 2085 return; 2086 } else if (size == 0) { 2087 error_setg(errp, "romfile \"%s\" is empty", pdev->romfile); 2088 g_free(path); 2089 return; 2090 } 2091 size = pow2ceil(size); 2092 2093 vmsd = qdev_get_vmsd(DEVICE(pdev)); 2094 2095 if (vmsd) { 2096 snprintf(name, sizeof(name), "%s.rom", vmsd->name); 2097 } else { 2098 snprintf(name, sizeof(name), "%s.rom", object_get_typename(OBJECT(pdev))); 2099 } 2100 pdev->has_rom = true; 2101 memory_region_init_ram(&pdev->rom, OBJECT(pdev), name, size, &error_fatal); 2102 vmstate_register_ram(&pdev->rom, &pdev->qdev); 2103 ptr = memory_region_get_ram_ptr(&pdev->rom); 2104 load_image(path, ptr); 2105 g_free(path); 2106 2107 if (is_default_rom) { 2108 /* Only the default rom images will be patched (if needed). */ 2109 pci_patch_ids(pdev, ptr, size); 2110 } 2111 2112 pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom); 2113 } 2114 2115 static void pci_del_option_rom(PCIDevice *pdev) 2116 { 2117 if (!pdev->has_rom) 2118 return; 2119 2120 vmstate_unregister_ram(&pdev->rom, &pdev->qdev); 2121 pdev->has_rom = false; 2122 } 2123 2124 /* 2125 * if offset = 0, 2126 * Find and reserve space and add capability to the linked list 2127 * in pci config space 2128 */ 2129 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, 2130 uint8_t offset, uint8_t size) 2131 { 2132 int ret; 2133 Error *local_err = NULL; 2134 2135 ret = pci_add_capability2(pdev, cap_id, offset, size, &local_err); 2136 if (local_err) { 2137 assert(ret < 0); 2138 error_report_err(local_err); 2139 } else { 2140 /* success implies a positive offset in config space */ 2141 assert(ret > 0); 2142 } 2143 return ret; 2144 } 2145 2146 int pci_add_capability2(PCIDevice *pdev, uint8_t cap_id, 2147 uint8_t offset, uint8_t size, 2148 Error **errp) 2149 { 2150 uint8_t *config; 2151 int i, overlapping_cap; 2152 2153 if (!offset) { 2154 offset = pci_find_space(pdev, size); 2155 if (!offset) { 2156 error_setg(errp, "out of PCI config space"); 2157 return -ENOSPC; 2158 } 2159 } else { 2160 /* Verify that capabilities don't overlap. Note: device assignment 2161 * depends on this check to verify that the device is not broken. 2162 * Should never trigger for emulated devices, but it's helpful 2163 * for debugging these. */ 2164 for (i = offset; i < offset + size; i++) { 2165 overlapping_cap = pci_find_capability_at_offset(pdev, i); 2166 if (overlapping_cap) { 2167 error_setg(errp, "%s:%02x:%02x.%x " 2168 "Attempt to add PCI capability %x at offset " 2169 "%x overlaps existing capability %x at offset %x", 2170 pci_root_bus_path(pdev), pci_bus_num(pdev->bus), 2171 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), 2172 cap_id, offset, overlapping_cap, i); 2173 return -EINVAL; 2174 } 2175 } 2176 } 2177 2178 config = pdev->config + offset; 2179 config[PCI_CAP_LIST_ID] = cap_id; 2180 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST]; 2181 pdev->config[PCI_CAPABILITY_LIST] = offset; 2182 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST; 2183 memset(pdev->used + offset, 0xFF, QEMU_ALIGN_UP(size, 4)); 2184 /* Make capability read-only by default */ 2185 memset(pdev->wmask + offset, 0, size); 2186 /* Check capability by default */ 2187 memset(pdev->cmask + offset, 0xFF, size); 2188 return offset; 2189 } 2190 2191 /* Unlink capability from the pci config space. */ 2192 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size) 2193 { 2194 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev); 2195 if (!offset) 2196 return; 2197 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT]; 2198 /* Make capability writable again */ 2199 memset(pdev->wmask + offset, 0xff, size); 2200 memset(pdev->w1cmask + offset, 0, size); 2201 /* Clear cmask as device-specific registers can't be checked */ 2202 memset(pdev->cmask + offset, 0, size); 2203 memset(pdev->used + offset, 0, QEMU_ALIGN_UP(size, 4)); 2204 2205 if (!pdev->config[PCI_CAPABILITY_LIST]) 2206 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST; 2207 } 2208 2209 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id) 2210 { 2211 return pci_find_capability_list(pdev, cap_id, NULL); 2212 } 2213 2214 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent) 2215 { 2216 PCIDevice *d = (PCIDevice *)dev; 2217 const pci_class_desc *desc; 2218 char ctxt[64]; 2219 PCIIORegion *r; 2220 int i, class; 2221 2222 class = pci_get_word(d->config + PCI_CLASS_DEVICE); 2223 desc = pci_class_descriptions; 2224 while (desc->desc && class != desc->class) 2225 desc++; 2226 if (desc->desc) { 2227 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc); 2228 } else { 2229 snprintf(ctxt, sizeof(ctxt), "Class %04x", class); 2230 } 2231 2232 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, " 2233 "pci id %04x:%04x (sub %04x:%04x)\n", 2234 indent, "", ctxt, pci_bus_num(d->bus), 2235 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn), 2236 pci_get_word(d->config + PCI_VENDOR_ID), 2237 pci_get_word(d->config + PCI_DEVICE_ID), 2238 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID), 2239 pci_get_word(d->config + PCI_SUBSYSTEM_ID)); 2240 for (i = 0; i < PCI_NUM_REGIONS; i++) { 2241 r = &d->io_regions[i]; 2242 if (!r->size) 2243 continue; 2244 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS 2245 " [0x%"FMT_PCIBUS"]\n", 2246 indent, "", 2247 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem", 2248 r->addr, r->addr + r->size - 1); 2249 } 2250 } 2251 2252 static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len) 2253 { 2254 PCIDevice *d = (PCIDevice *)dev; 2255 const char *name = NULL; 2256 const pci_class_desc *desc = pci_class_descriptions; 2257 int class = pci_get_word(d->config + PCI_CLASS_DEVICE); 2258 2259 while (desc->desc && 2260 (class & ~desc->fw_ign_bits) != 2261 (desc->class & ~desc->fw_ign_bits)) { 2262 desc++; 2263 } 2264 2265 if (desc->desc) { 2266 name = desc->fw_name; 2267 } 2268 2269 if (name) { 2270 pstrcpy(buf, len, name); 2271 } else { 2272 snprintf(buf, len, "pci%04x,%04x", 2273 pci_get_word(d->config + PCI_VENDOR_ID), 2274 pci_get_word(d->config + PCI_DEVICE_ID)); 2275 } 2276 2277 return buf; 2278 } 2279 2280 static char *pcibus_get_fw_dev_path(DeviceState *dev) 2281 { 2282 PCIDevice *d = (PCIDevice *)dev; 2283 char path[50], name[33]; 2284 int off; 2285 2286 off = snprintf(path, sizeof(path), "%s@%x", 2287 pci_dev_fw_name(dev, name, sizeof name), 2288 PCI_SLOT(d->devfn)); 2289 if (PCI_FUNC(d->devfn)) 2290 snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn)); 2291 return g_strdup(path); 2292 } 2293 2294 static char *pcibus_get_dev_path(DeviceState *dev) 2295 { 2296 PCIDevice *d = container_of(dev, PCIDevice, qdev); 2297 PCIDevice *t; 2298 int slot_depth; 2299 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function. 2300 * 00 is added here to make this format compatible with 2301 * domain:Bus:Slot.Func for systems without nested PCI bridges. 2302 * Slot.Function list specifies the slot and function numbers for all 2303 * devices on the path from root to the specific device. */ 2304 const char *root_bus_path; 2305 int root_bus_len; 2306 char slot[] = ":SS.F"; 2307 int slot_len = sizeof slot - 1 /* For '\0' */; 2308 int path_len; 2309 char *path, *p; 2310 int s; 2311 2312 root_bus_path = pci_root_bus_path(d); 2313 root_bus_len = strlen(root_bus_path); 2314 2315 /* Calculate # of slots on path between device and root. */; 2316 slot_depth = 0; 2317 for (t = d; t; t = t->bus->parent_dev) { 2318 ++slot_depth; 2319 } 2320 2321 path_len = root_bus_len + slot_len * slot_depth; 2322 2323 /* Allocate memory, fill in the terminating null byte. */ 2324 path = g_malloc(path_len + 1 /* For '\0' */); 2325 path[path_len] = '\0'; 2326 2327 memcpy(path, root_bus_path, root_bus_len); 2328 2329 /* Fill in slot numbers. We walk up from device to root, so need to print 2330 * them in the reverse order, last to first. */ 2331 p = path + path_len; 2332 for (t = d; t; t = t->bus->parent_dev) { 2333 p -= slot_len; 2334 s = snprintf(slot, sizeof slot, ":%02x.%x", 2335 PCI_SLOT(t->devfn), PCI_FUNC(t->devfn)); 2336 assert(s == slot_len); 2337 memcpy(p, slot, slot_len); 2338 } 2339 2340 return path; 2341 } 2342 2343 static int pci_qdev_find_recursive(PCIBus *bus, 2344 const char *id, PCIDevice **pdev) 2345 { 2346 DeviceState *qdev = qdev_find_recursive(&bus->qbus, id); 2347 if (!qdev) { 2348 return -ENODEV; 2349 } 2350 2351 /* roughly check if given qdev is pci device */ 2352 if (object_dynamic_cast(OBJECT(qdev), TYPE_PCI_DEVICE)) { 2353 *pdev = PCI_DEVICE(qdev); 2354 return 0; 2355 } 2356 return -EINVAL; 2357 } 2358 2359 int pci_qdev_find_device(const char *id, PCIDevice **pdev) 2360 { 2361 PCIHostState *host_bridge; 2362 int rc = -ENODEV; 2363 2364 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { 2365 int tmp = pci_qdev_find_recursive(host_bridge->bus, id, pdev); 2366 if (!tmp) { 2367 rc = 0; 2368 break; 2369 } 2370 if (tmp != -ENODEV) { 2371 rc = tmp; 2372 } 2373 } 2374 2375 return rc; 2376 } 2377 2378 MemoryRegion *pci_address_space(PCIDevice *dev) 2379 { 2380 return dev->bus->address_space_mem; 2381 } 2382 2383 MemoryRegion *pci_address_space_io(PCIDevice *dev) 2384 { 2385 return dev->bus->address_space_io; 2386 } 2387 2388 static void pci_device_class_init(ObjectClass *klass, void *data) 2389 { 2390 DeviceClass *k = DEVICE_CLASS(klass); 2391 PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass); 2392 2393 k->realize = pci_qdev_realize; 2394 k->unrealize = pci_qdev_unrealize; 2395 k->bus_type = TYPE_PCI_BUS; 2396 k->props = pci_props; 2397 pc->realize = pci_default_realize; 2398 } 2399 2400 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev) 2401 { 2402 PCIBus *bus = PCI_BUS(dev->bus); 2403 PCIBus *iommu_bus = bus; 2404 2405 while(iommu_bus && !iommu_bus->iommu_fn && iommu_bus->parent_dev) { 2406 iommu_bus = PCI_BUS(iommu_bus->parent_dev->bus); 2407 } 2408 if (iommu_bus && iommu_bus->iommu_fn) { 2409 return iommu_bus->iommu_fn(bus, iommu_bus->iommu_opaque, dev->devfn); 2410 } 2411 return &address_space_memory; 2412 } 2413 2414 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque) 2415 { 2416 bus->iommu_fn = fn; 2417 bus->iommu_opaque = opaque; 2418 } 2419 2420 static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque) 2421 { 2422 Range *range = opaque; 2423 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 2424 uint16_t cmd = pci_get_word(dev->config + PCI_COMMAND); 2425 int i; 2426 2427 if (!(cmd & PCI_COMMAND_MEMORY)) { 2428 return; 2429 } 2430 2431 if (pc->is_bridge) { 2432 pcibus_t base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 2433 pcibus_t limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 2434 2435 base = MAX(base, 0x1ULL << 32); 2436 2437 if (limit >= base) { 2438 Range pref_range; 2439 pref_range.begin = base; 2440 pref_range.end = limit + 1; 2441 range_extend(range, &pref_range); 2442 } 2443 } 2444 for (i = 0; i < PCI_NUM_REGIONS; ++i) { 2445 PCIIORegion *r = &dev->io_regions[i]; 2446 Range region_range; 2447 2448 if (!r->size || 2449 (r->type & PCI_BASE_ADDRESS_SPACE_IO) || 2450 !(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64)) { 2451 continue; 2452 } 2453 region_range.begin = pci_bar_address(dev, i, r->type, r->size); 2454 region_range.end = region_range.begin + r->size; 2455 2456 if (region_range.begin == PCI_BAR_UNMAPPED) { 2457 continue; 2458 } 2459 2460 region_range.begin = MAX(region_range.begin, 0x1ULL << 32); 2461 2462 if (region_range.end - 1 >= region_range.begin) { 2463 range_extend(range, ®ion_range); 2464 } 2465 } 2466 } 2467 2468 void pci_bus_get_w64_range(PCIBus *bus, Range *range) 2469 { 2470 range->begin = range->end = 0; 2471 pci_for_each_device_under_bus(bus, pci_dev_get_w64, range); 2472 } 2473 2474 static bool pcie_has_upstream_port(PCIDevice *dev) 2475 { 2476 PCIDevice *parent_dev = pci_bridge_get_device(dev->bus); 2477 2478 /* Device associated with an upstream port. 2479 * As there are several types of these, it's easier to check the 2480 * parent device: upstream ports are always connected to 2481 * root or downstream ports. 2482 */ 2483 return parent_dev && 2484 pci_is_express(parent_dev) && 2485 parent_dev->exp.exp_cap && 2486 (pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_ROOT_PORT || 2487 pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_DOWNSTREAM); 2488 } 2489 2490 PCIDevice *pci_get_function_0(PCIDevice *pci_dev) 2491 { 2492 if(pcie_has_upstream_port(pci_dev)) { 2493 /* With an upstream PCIe port, we only support 1 device at slot 0 */ 2494 return pci_dev->bus->devices[0]; 2495 } else { 2496 /* Other bus types might support multiple devices at slots 0-31 */ 2497 return pci_dev->bus->devices[PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 0)]; 2498 } 2499 } 2500 2501 static const TypeInfo pci_device_type_info = { 2502 .name = TYPE_PCI_DEVICE, 2503 .parent = TYPE_DEVICE, 2504 .instance_size = sizeof(PCIDevice), 2505 .abstract = true, 2506 .class_size = sizeof(PCIDeviceClass), 2507 .class_init = pci_device_class_init, 2508 }; 2509 2510 static void pci_register_types(void) 2511 { 2512 type_register_static(&pci_bus_info); 2513 type_register_static(&pcie_bus_info); 2514 type_register_static(&pci_device_type_info); 2515 } 2516 2517 type_init(pci_register_types) 2518