1 /* 2 * QEMU PCI bus manager 3 * 4 * Copyright (c) 2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/hw.h" 25 #include "hw/pci/pci.h" 26 #include "hw/pci/pci_bridge.h" 27 #include "hw/pci/pci_bus.h" 28 #include "hw/pci/pci_host.h" 29 #include "monitor/monitor.h" 30 #include "net/net.h" 31 #include "sysemu/sysemu.h" 32 #include "hw/loader.h" 33 #include "qemu/range.h" 34 #include "qmp-commands.h" 35 #include "hw/pci/msi.h" 36 #include "hw/pci/msix.h" 37 #include "exec/address-spaces.h" 38 #include "hw/hotplug.h" 39 40 //#define DEBUG_PCI 41 #ifdef DEBUG_PCI 42 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) 43 #else 44 # define PCI_DPRINTF(format, ...) do { } while (0) 45 #endif 46 47 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent); 48 static char *pcibus_get_dev_path(DeviceState *dev); 49 static char *pcibus_get_fw_dev_path(DeviceState *dev); 50 static void pcibus_reset(BusState *qbus); 51 52 static Property pci_props[] = { 53 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1), 54 DEFINE_PROP_STRING("romfile", PCIDevice, romfile), 55 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1), 56 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present, 57 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false), 58 DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present, 59 QEMU_PCI_CAP_SERR_BITNR, true), 60 DEFINE_PROP_END_OF_LIST() 61 }; 62 63 static const VMStateDescription vmstate_pcibus = { 64 .name = "PCIBUS", 65 .version_id = 1, 66 .minimum_version_id = 1, 67 .minimum_version_id_old = 1, 68 .fields = (VMStateField[]) { 69 VMSTATE_INT32_EQUAL(nirq, PCIBus), 70 VMSTATE_VARRAY_INT32(irq_count, PCIBus, 71 nirq, 0, vmstate_info_int32, 72 int32_t), 73 VMSTATE_END_OF_LIST() 74 } 75 }; 76 77 static void pci_bus_realize(BusState *qbus, Error **errp) 78 { 79 PCIBus *bus = PCI_BUS(qbus); 80 81 vmstate_register(NULL, -1, &vmstate_pcibus, bus); 82 } 83 84 static void pci_bus_unrealize(BusState *qbus, Error **errp) 85 { 86 PCIBus *bus = PCI_BUS(qbus); 87 88 vmstate_unregister(NULL, &vmstate_pcibus, bus); 89 } 90 91 static void pci_bus_class_init(ObjectClass *klass, void *data) 92 { 93 BusClass *k = BUS_CLASS(klass); 94 95 k->print_dev = pcibus_dev_print; 96 k->get_dev_path = pcibus_get_dev_path; 97 k->get_fw_dev_path = pcibus_get_fw_dev_path; 98 k->realize = pci_bus_realize; 99 k->unrealize = pci_bus_unrealize; 100 k->reset = pcibus_reset; 101 } 102 103 static const TypeInfo pci_bus_info = { 104 .name = TYPE_PCI_BUS, 105 .parent = TYPE_BUS, 106 .instance_size = sizeof(PCIBus), 107 .class_init = pci_bus_class_init, 108 }; 109 110 static const TypeInfo pcie_bus_info = { 111 .name = TYPE_PCIE_BUS, 112 .parent = TYPE_PCI_BUS, 113 }; 114 115 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num); 116 static void pci_update_mappings(PCIDevice *d); 117 static void pci_irq_handler(void *opaque, int irq_num, int level); 118 static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom); 119 static void pci_del_option_rom(PCIDevice *pdev); 120 121 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET; 122 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU; 123 124 static QLIST_HEAD(, PCIHostState) pci_host_bridges; 125 126 static int pci_bar(PCIDevice *d, int reg) 127 { 128 uint8_t type; 129 130 if (reg != PCI_ROM_SLOT) 131 return PCI_BASE_ADDRESS_0 + reg * 4; 132 133 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 134 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS; 135 } 136 137 static inline int pci_irq_state(PCIDevice *d, int irq_num) 138 { 139 return (d->irq_state >> irq_num) & 0x1; 140 } 141 142 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level) 143 { 144 d->irq_state &= ~(0x1 << irq_num); 145 d->irq_state |= level << irq_num; 146 } 147 148 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change) 149 { 150 PCIBus *bus; 151 for (;;) { 152 bus = pci_dev->bus; 153 irq_num = bus->map_irq(pci_dev, irq_num); 154 if (bus->set_irq) 155 break; 156 pci_dev = bus->parent_dev; 157 } 158 bus->irq_count[irq_num] += change; 159 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0); 160 } 161 162 int pci_bus_get_irq_level(PCIBus *bus, int irq_num) 163 { 164 assert(irq_num >= 0); 165 assert(irq_num < bus->nirq); 166 return !!bus->irq_count[irq_num]; 167 } 168 169 /* Update interrupt status bit in config space on interrupt 170 * state change. */ 171 static void pci_update_irq_status(PCIDevice *dev) 172 { 173 if (dev->irq_state) { 174 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT; 175 } else { 176 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; 177 } 178 } 179 180 void pci_device_deassert_intx(PCIDevice *dev) 181 { 182 int i; 183 for (i = 0; i < PCI_NUM_PINS; ++i) { 184 pci_irq_handler(dev, i, 0); 185 } 186 } 187 188 static void pci_do_device_reset(PCIDevice *dev) 189 { 190 int r; 191 192 pci_device_deassert_intx(dev); 193 assert(dev->irq_state == 0); 194 195 /* Clear all writable bits */ 196 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND, 197 pci_get_word(dev->wmask + PCI_COMMAND) | 198 pci_get_word(dev->w1cmask + PCI_COMMAND)); 199 pci_word_test_and_clear_mask(dev->config + PCI_STATUS, 200 pci_get_word(dev->wmask + PCI_STATUS) | 201 pci_get_word(dev->w1cmask + PCI_STATUS)); 202 dev->config[PCI_CACHE_LINE_SIZE] = 0x0; 203 dev->config[PCI_INTERRUPT_LINE] = 0x0; 204 for (r = 0; r < PCI_NUM_REGIONS; ++r) { 205 PCIIORegion *region = &dev->io_regions[r]; 206 if (!region->size) { 207 continue; 208 } 209 210 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) && 211 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 212 pci_set_quad(dev->config + pci_bar(dev, r), region->type); 213 } else { 214 pci_set_long(dev->config + pci_bar(dev, r), region->type); 215 } 216 } 217 pci_update_mappings(dev); 218 219 msi_reset(dev); 220 msix_reset(dev); 221 } 222 223 /* 224 * This function is called on #RST and FLR. 225 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set 226 */ 227 void pci_device_reset(PCIDevice *dev) 228 { 229 qdev_reset_all(&dev->qdev); 230 pci_do_device_reset(dev); 231 } 232 233 /* 234 * Trigger pci bus reset under a given bus. 235 * Called via qbus_reset_all on RST# assert, after the devices 236 * have been reset qdev_reset_all-ed already. 237 */ 238 static void pcibus_reset(BusState *qbus) 239 { 240 PCIBus *bus = DO_UPCAST(PCIBus, qbus, qbus); 241 int i; 242 243 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 244 if (bus->devices[i]) { 245 pci_do_device_reset(bus->devices[i]); 246 } 247 } 248 249 for (i = 0; i < bus->nirq; i++) { 250 assert(bus->irq_count[i] == 0); 251 } 252 } 253 254 static void pci_host_bus_register(PCIBus *bus, DeviceState *parent) 255 { 256 PCIHostState *host_bridge = PCI_HOST_BRIDGE(parent); 257 258 QLIST_INSERT_HEAD(&pci_host_bridges, host_bridge, next); 259 } 260 261 PCIBus *pci_find_primary_bus(void) 262 { 263 PCIBus *primary_bus = NULL; 264 PCIHostState *host; 265 266 QLIST_FOREACH(host, &pci_host_bridges, next) { 267 if (primary_bus) { 268 /* We have multiple root buses, refuse to select a primary */ 269 return NULL; 270 } 271 primary_bus = host->bus; 272 } 273 274 return primary_bus; 275 } 276 277 PCIBus *pci_device_root_bus(const PCIDevice *d) 278 { 279 PCIBus *bus = d->bus; 280 281 while ((d = bus->parent_dev) != NULL) { 282 bus = d->bus; 283 } 284 285 return bus; 286 } 287 288 const char *pci_root_bus_path(PCIDevice *dev) 289 { 290 PCIBus *rootbus = pci_device_root_bus(dev); 291 PCIHostState *host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent); 292 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_GET_CLASS(host_bridge); 293 294 assert(!rootbus->parent_dev); 295 assert(host_bridge->bus == rootbus); 296 297 if (hc->root_bus_path) { 298 return (*hc->root_bus_path)(host_bridge, rootbus); 299 } 300 301 return rootbus->qbus.name; 302 } 303 304 static void pci_bus_init(PCIBus *bus, DeviceState *parent, 305 const char *name, 306 MemoryRegion *address_space_mem, 307 MemoryRegion *address_space_io, 308 uint8_t devfn_min) 309 { 310 assert(PCI_FUNC(devfn_min) == 0); 311 bus->devfn_min = devfn_min; 312 bus->address_space_mem = address_space_mem; 313 bus->address_space_io = address_space_io; 314 315 /* host bridge */ 316 QLIST_INIT(&bus->child); 317 318 pci_host_bus_register(bus, parent); 319 } 320 321 bool pci_bus_is_express(PCIBus *bus) 322 { 323 return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS); 324 } 325 326 bool pci_bus_is_root(PCIBus *bus) 327 { 328 return !bus->parent_dev; 329 } 330 331 void pci_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent, 332 const char *name, 333 MemoryRegion *address_space_mem, 334 MemoryRegion *address_space_io, 335 uint8_t devfn_min, const char *typename) 336 { 337 qbus_create_inplace(bus, bus_size, typename, parent, name); 338 pci_bus_init(bus, parent, name, address_space_mem, 339 address_space_io, devfn_min); 340 } 341 342 PCIBus *pci_bus_new(DeviceState *parent, const char *name, 343 MemoryRegion *address_space_mem, 344 MemoryRegion *address_space_io, 345 uint8_t devfn_min, const char *typename) 346 { 347 PCIBus *bus; 348 349 bus = PCI_BUS(qbus_create(typename, parent, name)); 350 pci_bus_init(bus, parent, name, address_space_mem, 351 address_space_io, devfn_min); 352 return bus; 353 } 354 355 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 356 void *irq_opaque, int nirq) 357 { 358 bus->set_irq = set_irq; 359 bus->map_irq = map_irq; 360 bus->irq_opaque = irq_opaque; 361 bus->nirq = nirq; 362 bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0])); 363 } 364 365 PCIBus *pci_register_bus(DeviceState *parent, const char *name, 366 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 367 void *irq_opaque, 368 MemoryRegion *address_space_mem, 369 MemoryRegion *address_space_io, 370 uint8_t devfn_min, int nirq, const char *typename) 371 { 372 PCIBus *bus; 373 374 bus = pci_bus_new(parent, name, address_space_mem, 375 address_space_io, devfn_min, typename); 376 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq); 377 return bus; 378 } 379 380 int pci_bus_num(PCIBus *s) 381 { 382 if (pci_bus_is_root(s)) 383 return 0; /* pci host bridge */ 384 return s->parent_dev->config[PCI_SECONDARY_BUS]; 385 } 386 387 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size) 388 { 389 PCIDevice *s = container_of(pv, PCIDevice, config); 390 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(s); 391 uint8_t *config; 392 int i; 393 394 assert(size == pci_config_size(s)); 395 config = g_malloc(size); 396 397 qemu_get_buffer(f, config, size); 398 for (i = 0; i < size; ++i) { 399 if ((config[i] ^ s->config[i]) & 400 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) { 401 g_free(config); 402 return -EINVAL; 403 } 404 } 405 memcpy(s->config, config, size); 406 407 pci_update_mappings(s); 408 if (pc->is_bridge) { 409 PCIBridge *b = PCI_BRIDGE(s); 410 pci_bridge_update_mappings(b); 411 } 412 413 memory_region_set_enabled(&s->bus_master_enable_region, 414 pci_get_word(s->config + PCI_COMMAND) 415 & PCI_COMMAND_MASTER); 416 417 g_free(config); 418 return 0; 419 } 420 421 /* just put buffer */ 422 static void put_pci_config_device(QEMUFile *f, void *pv, size_t size) 423 { 424 const uint8_t **v = pv; 425 assert(size == pci_config_size(container_of(pv, PCIDevice, config))); 426 qemu_put_buffer(f, *v, size); 427 } 428 429 static VMStateInfo vmstate_info_pci_config = { 430 .name = "pci config", 431 .get = get_pci_config_device, 432 .put = put_pci_config_device, 433 }; 434 435 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size) 436 { 437 PCIDevice *s = container_of(pv, PCIDevice, irq_state); 438 uint32_t irq_state[PCI_NUM_PINS]; 439 int i; 440 for (i = 0; i < PCI_NUM_PINS; ++i) { 441 irq_state[i] = qemu_get_be32(f); 442 if (irq_state[i] != 0x1 && irq_state[i] != 0) { 443 fprintf(stderr, "irq state %d: must be 0 or 1.\n", 444 irq_state[i]); 445 return -EINVAL; 446 } 447 } 448 449 for (i = 0; i < PCI_NUM_PINS; ++i) { 450 pci_set_irq_state(s, i, irq_state[i]); 451 } 452 453 return 0; 454 } 455 456 static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size) 457 { 458 int i; 459 PCIDevice *s = container_of(pv, PCIDevice, irq_state); 460 461 for (i = 0; i < PCI_NUM_PINS; ++i) { 462 qemu_put_be32(f, pci_irq_state(s, i)); 463 } 464 } 465 466 static VMStateInfo vmstate_info_pci_irq_state = { 467 .name = "pci irq state", 468 .get = get_pci_irq_state, 469 .put = put_pci_irq_state, 470 }; 471 472 const VMStateDescription vmstate_pci_device = { 473 .name = "PCIDevice", 474 .version_id = 2, 475 .minimum_version_id = 1, 476 .minimum_version_id_old = 1, 477 .fields = (VMStateField []) { 478 VMSTATE_INT32_POSITIVE_LE(version_id, PCIDevice), 479 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0, 480 vmstate_info_pci_config, 481 PCI_CONFIG_SPACE_SIZE), 482 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2, 483 vmstate_info_pci_irq_state, 484 PCI_NUM_PINS * sizeof(int32_t)), 485 VMSTATE_END_OF_LIST() 486 } 487 }; 488 489 const VMStateDescription vmstate_pcie_device = { 490 .name = "PCIEDevice", 491 .version_id = 2, 492 .minimum_version_id = 1, 493 .minimum_version_id_old = 1, 494 .fields = (VMStateField []) { 495 VMSTATE_INT32_POSITIVE_LE(version_id, PCIDevice), 496 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0, 497 vmstate_info_pci_config, 498 PCIE_CONFIG_SPACE_SIZE), 499 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2, 500 vmstate_info_pci_irq_state, 501 PCI_NUM_PINS * sizeof(int32_t)), 502 VMSTATE_END_OF_LIST() 503 } 504 }; 505 506 static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s) 507 { 508 return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device; 509 } 510 511 void pci_device_save(PCIDevice *s, QEMUFile *f) 512 { 513 /* Clear interrupt status bit: it is implicit 514 * in irq_state which we are saving. 515 * This makes us compatible with old devices 516 * which never set or clear this bit. */ 517 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; 518 vmstate_save_state(f, pci_get_vmstate(s), s); 519 /* Restore the interrupt status bit. */ 520 pci_update_irq_status(s); 521 } 522 523 int pci_device_load(PCIDevice *s, QEMUFile *f) 524 { 525 int ret; 526 ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id); 527 /* Restore the interrupt status bit. */ 528 pci_update_irq_status(s); 529 return ret; 530 } 531 532 static void pci_set_default_subsystem_id(PCIDevice *pci_dev) 533 { 534 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, 535 pci_default_sub_vendor_id); 536 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 537 pci_default_sub_device_id); 538 } 539 540 /* 541 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL 542 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error 543 */ 544 int pci_parse_devaddr(const char *addr, int *domp, int *busp, 545 unsigned int *slotp, unsigned int *funcp) 546 { 547 const char *p; 548 char *e; 549 unsigned long val; 550 unsigned long dom = 0, bus = 0; 551 unsigned int slot = 0; 552 unsigned int func = 0; 553 554 p = addr; 555 val = strtoul(p, &e, 16); 556 if (e == p) 557 return -1; 558 if (*e == ':') { 559 bus = val; 560 p = e + 1; 561 val = strtoul(p, &e, 16); 562 if (e == p) 563 return -1; 564 if (*e == ':') { 565 dom = bus; 566 bus = val; 567 p = e + 1; 568 val = strtoul(p, &e, 16); 569 if (e == p) 570 return -1; 571 } 572 } 573 574 slot = val; 575 576 if (funcp != NULL) { 577 if (*e != '.') 578 return -1; 579 580 p = e + 1; 581 val = strtoul(p, &e, 16); 582 if (e == p) 583 return -1; 584 585 func = val; 586 } 587 588 /* if funcp == NULL func is 0 */ 589 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7) 590 return -1; 591 592 if (*e) 593 return -1; 594 595 *domp = dom; 596 *busp = bus; 597 *slotp = slot; 598 if (funcp != NULL) 599 *funcp = func; 600 return 0; 601 } 602 603 PCIBus *pci_get_bus_devfn(int *devfnp, PCIBus *root, const char *devaddr) 604 { 605 int dom, bus; 606 unsigned slot; 607 608 assert(!root->parent_dev); 609 610 if (!root) { 611 fprintf(stderr, "No primary PCI bus\n"); 612 return NULL; 613 } 614 615 if (!devaddr) { 616 *devfnp = -1; 617 return pci_find_bus_nr(root, 0); 618 } 619 620 if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) { 621 return NULL; 622 } 623 624 if (dom != 0) { 625 fprintf(stderr, "No support for non-zero PCI domains\n"); 626 return NULL; 627 } 628 629 *devfnp = PCI_DEVFN(slot, 0); 630 return pci_find_bus_nr(root, bus); 631 } 632 633 static void pci_init_cmask(PCIDevice *dev) 634 { 635 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff); 636 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff); 637 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST; 638 dev->cmask[PCI_REVISION_ID] = 0xff; 639 dev->cmask[PCI_CLASS_PROG] = 0xff; 640 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff); 641 dev->cmask[PCI_HEADER_TYPE] = 0xff; 642 dev->cmask[PCI_CAPABILITY_LIST] = 0xff; 643 } 644 645 static void pci_init_wmask(PCIDevice *dev) 646 { 647 int config_size = pci_config_size(dev); 648 649 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff; 650 dev->wmask[PCI_INTERRUPT_LINE] = 0xff; 651 pci_set_word(dev->wmask + PCI_COMMAND, 652 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | 653 PCI_COMMAND_INTX_DISABLE); 654 if (dev->cap_present & QEMU_PCI_CAP_SERR) { 655 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR); 656 } 657 658 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff, 659 config_size - PCI_CONFIG_HEADER_SIZE); 660 } 661 662 static void pci_init_w1cmask(PCIDevice *dev) 663 { 664 /* 665 * Note: It's okay to set w1cmask even for readonly bits as 666 * long as their value is hardwired to 0. 667 */ 668 pci_set_word(dev->w1cmask + PCI_STATUS, 669 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT | 670 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT | 671 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY); 672 } 673 674 static void pci_init_mask_bridge(PCIDevice *d) 675 { 676 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and 677 PCI_SEC_LETENCY_TIMER */ 678 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4); 679 680 /* base and limit */ 681 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff; 682 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff; 683 pci_set_word(d->wmask + PCI_MEMORY_BASE, 684 PCI_MEMORY_RANGE_MASK & 0xffff); 685 pci_set_word(d->wmask + PCI_MEMORY_LIMIT, 686 PCI_MEMORY_RANGE_MASK & 0xffff); 687 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE, 688 PCI_PREF_RANGE_MASK & 0xffff); 689 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT, 690 PCI_PREF_RANGE_MASK & 0xffff); 691 692 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */ 693 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8); 694 695 /* Supported memory and i/o types */ 696 d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16; 697 d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16; 698 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE, 699 PCI_PREF_RANGE_TYPE_64); 700 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT, 701 PCI_PREF_RANGE_TYPE_64); 702 703 /* 704 * TODO: Bridges default to 10-bit VGA decoding but we currently only 705 * implement 16-bit decoding (no alias support). 706 */ 707 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 708 PCI_BRIDGE_CTL_PARITY | 709 PCI_BRIDGE_CTL_SERR | 710 PCI_BRIDGE_CTL_ISA | 711 PCI_BRIDGE_CTL_VGA | 712 PCI_BRIDGE_CTL_VGA_16BIT | 713 PCI_BRIDGE_CTL_MASTER_ABORT | 714 PCI_BRIDGE_CTL_BUS_RESET | 715 PCI_BRIDGE_CTL_FAST_BACK | 716 PCI_BRIDGE_CTL_DISCARD | 717 PCI_BRIDGE_CTL_SEC_DISCARD | 718 PCI_BRIDGE_CTL_DISCARD_SERR); 719 /* Below does not do anything as we never set this bit, put here for 720 * completeness. */ 721 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL, 722 PCI_BRIDGE_CTL_DISCARD_STATUS); 723 d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK; 724 d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK; 725 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE, 726 PCI_PREF_RANGE_TYPE_MASK); 727 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT, 728 PCI_PREF_RANGE_TYPE_MASK); 729 } 730 731 static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev) 732 { 733 uint8_t slot = PCI_SLOT(dev->devfn); 734 uint8_t func; 735 736 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 737 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION; 738 } 739 740 /* 741 * multifunction bit is interpreted in two ways as follows. 742 * - all functions must set the bit to 1. 743 * Example: Intel X53 744 * - function 0 must set the bit, but the rest function (> 0) 745 * is allowed to leave the bit to 0. 746 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10, 747 * 748 * So OS (at least Linux) checks the bit of only function 0, 749 * and doesn't see the bit of function > 0. 750 * 751 * The below check allows both interpretation. 752 */ 753 if (PCI_FUNC(dev->devfn)) { 754 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)]; 755 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) { 756 /* function 0 should set multifunction bit */ 757 error_report("PCI: single function device can't be populated " 758 "in function %x.%x", slot, PCI_FUNC(dev->devfn)); 759 return -1; 760 } 761 return 0; 762 } 763 764 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 765 return 0; 766 } 767 /* function 0 indicates single function, so function > 0 must be NULL */ 768 for (func = 1; func < PCI_FUNC_MAX; ++func) { 769 if (bus->devices[PCI_DEVFN(slot, func)]) { 770 error_report("PCI: %x.0 indicates single function, " 771 "but %x.%x is already populated.", 772 slot, slot, func); 773 return -1; 774 } 775 } 776 return 0; 777 } 778 779 static void pci_config_alloc(PCIDevice *pci_dev) 780 { 781 int config_size = pci_config_size(pci_dev); 782 783 pci_dev->config = g_malloc0(config_size); 784 pci_dev->cmask = g_malloc0(config_size); 785 pci_dev->wmask = g_malloc0(config_size); 786 pci_dev->w1cmask = g_malloc0(config_size); 787 pci_dev->used = g_malloc0(config_size); 788 } 789 790 static void pci_config_free(PCIDevice *pci_dev) 791 { 792 g_free(pci_dev->config); 793 g_free(pci_dev->cmask); 794 g_free(pci_dev->wmask); 795 g_free(pci_dev->w1cmask); 796 g_free(pci_dev->used); 797 } 798 799 static void do_pci_unregister_device(PCIDevice *pci_dev) 800 { 801 pci_dev->bus->devices[pci_dev->devfn] = NULL; 802 pci_config_free(pci_dev); 803 804 address_space_destroy(&pci_dev->bus_master_as); 805 memory_region_destroy(&pci_dev->bus_master_enable_region); 806 } 807 808 /* -1 for devfn means auto assign */ 809 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus, 810 const char *name, int devfn) 811 { 812 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 813 PCIConfigReadFunc *config_read = pc->config_read; 814 PCIConfigWriteFunc *config_write = pc->config_write; 815 AddressSpace *dma_as; 816 817 if (devfn < 0) { 818 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices); 819 devfn += PCI_FUNC_MAX) { 820 if (!bus->devices[devfn]) 821 goto found; 822 } 823 error_report("PCI: no slot/function available for %s, all in use", name); 824 return NULL; 825 found: ; 826 } else if (bus->devices[devfn]) { 827 error_report("PCI: slot %d function %d not available for %s, in use by %s", 828 PCI_SLOT(devfn), PCI_FUNC(devfn), name, bus->devices[devfn]->name); 829 return NULL; 830 } 831 832 pci_dev->bus = bus; 833 dma_as = pci_device_iommu_address_space(pci_dev); 834 835 memory_region_init_alias(&pci_dev->bus_master_enable_region, 836 OBJECT(pci_dev), "bus master", 837 dma_as->root, 0, memory_region_size(dma_as->root)); 838 memory_region_set_enabled(&pci_dev->bus_master_enable_region, false); 839 address_space_init(&pci_dev->bus_master_as, &pci_dev->bus_master_enable_region, 840 name); 841 842 pci_dev->devfn = devfn; 843 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name); 844 pci_dev->irq_state = 0; 845 pci_config_alloc(pci_dev); 846 847 pci_config_set_vendor_id(pci_dev->config, pc->vendor_id); 848 pci_config_set_device_id(pci_dev->config, pc->device_id); 849 pci_config_set_revision(pci_dev->config, pc->revision); 850 pci_config_set_class(pci_dev->config, pc->class_id); 851 852 if (!pc->is_bridge) { 853 if (pc->subsystem_vendor_id || pc->subsystem_id) { 854 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, 855 pc->subsystem_vendor_id); 856 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 857 pc->subsystem_id); 858 } else { 859 pci_set_default_subsystem_id(pci_dev); 860 } 861 } else { 862 /* subsystem_vendor_id/subsystem_id are only for header type 0 */ 863 assert(!pc->subsystem_vendor_id); 864 assert(!pc->subsystem_id); 865 } 866 pci_init_cmask(pci_dev); 867 pci_init_wmask(pci_dev); 868 pci_init_w1cmask(pci_dev); 869 if (pc->is_bridge) { 870 pci_init_mask_bridge(pci_dev); 871 } 872 if (pci_init_multifunction(bus, pci_dev)) { 873 do_pci_unregister_device(pci_dev); 874 return NULL; 875 } 876 877 if (!config_read) 878 config_read = pci_default_read_config; 879 if (!config_write) 880 config_write = pci_default_write_config; 881 pci_dev->config_read = config_read; 882 pci_dev->config_write = config_write; 883 bus->devices[devfn] = pci_dev; 884 pci_dev->version_id = 2; /* Current pci device vmstate version */ 885 return pci_dev; 886 } 887 888 static void pci_unregister_io_regions(PCIDevice *pci_dev) 889 { 890 PCIIORegion *r; 891 int i; 892 893 for(i = 0; i < PCI_NUM_REGIONS; i++) { 894 r = &pci_dev->io_regions[i]; 895 if (!r->size || r->addr == PCI_BAR_UNMAPPED) 896 continue; 897 memory_region_del_subregion(r->address_space, r->memory); 898 } 899 900 pci_unregister_vga(pci_dev); 901 } 902 903 static int pci_unregister_device(DeviceState *dev) 904 { 905 PCIDevice *pci_dev = PCI_DEVICE(dev); 906 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 907 908 pci_unregister_io_regions(pci_dev); 909 pci_del_option_rom(pci_dev); 910 911 if (pc->exit) { 912 pc->exit(pci_dev); 913 } 914 915 do_pci_unregister_device(pci_dev); 916 return 0; 917 } 918 919 void pci_register_bar(PCIDevice *pci_dev, int region_num, 920 uint8_t type, MemoryRegion *memory) 921 { 922 PCIIORegion *r; 923 uint32_t addr; 924 uint64_t wmask; 925 pcibus_t size = memory_region_size(memory); 926 927 assert(region_num >= 0); 928 assert(region_num < PCI_NUM_REGIONS); 929 if (size & (size-1)) { 930 fprintf(stderr, "ERROR: PCI region size must be pow2 " 931 "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size); 932 exit(1); 933 } 934 935 r = &pci_dev->io_regions[region_num]; 936 r->addr = PCI_BAR_UNMAPPED; 937 r->size = size; 938 r->type = type; 939 r->memory = NULL; 940 941 wmask = ~(size - 1); 942 addr = pci_bar(pci_dev, region_num); 943 if (region_num == PCI_ROM_SLOT) { 944 /* ROM enable bit is writable */ 945 wmask |= PCI_ROM_ADDRESS_ENABLE; 946 } 947 pci_set_long(pci_dev->config + addr, type); 948 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) && 949 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 950 pci_set_quad(pci_dev->wmask + addr, wmask); 951 pci_set_quad(pci_dev->cmask + addr, ~0ULL); 952 } else { 953 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff); 954 pci_set_long(pci_dev->cmask + addr, 0xffffffff); 955 } 956 pci_dev->io_regions[region_num].memory = memory; 957 pci_dev->io_regions[region_num].address_space 958 = type & PCI_BASE_ADDRESS_SPACE_IO 959 ? pci_dev->bus->address_space_io 960 : pci_dev->bus->address_space_mem; 961 } 962 963 static void pci_update_vga(PCIDevice *pci_dev) 964 { 965 uint16_t cmd; 966 967 if (!pci_dev->has_vga) { 968 return; 969 } 970 971 cmd = pci_get_word(pci_dev->config + PCI_COMMAND); 972 973 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_MEM], 974 cmd & PCI_COMMAND_MEMORY); 975 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO], 976 cmd & PCI_COMMAND_IO); 977 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI], 978 cmd & PCI_COMMAND_IO); 979 } 980 981 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, 982 MemoryRegion *io_lo, MemoryRegion *io_hi) 983 { 984 assert(!pci_dev->has_vga); 985 986 assert(memory_region_size(mem) == QEMU_PCI_VGA_MEM_SIZE); 987 pci_dev->vga_regions[QEMU_PCI_VGA_MEM] = mem; 988 memory_region_add_subregion_overlap(pci_dev->bus->address_space_mem, 989 QEMU_PCI_VGA_MEM_BASE, mem, 1); 990 991 assert(memory_region_size(io_lo) == QEMU_PCI_VGA_IO_LO_SIZE); 992 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO] = io_lo; 993 memory_region_add_subregion_overlap(pci_dev->bus->address_space_io, 994 QEMU_PCI_VGA_IO_LO_BASE, io_lo, 1); 995 996 assert(memory_region_size(io_hi) == QEMU_PCI_VGA_IO_HI_SIZE); 997 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI] = io_hi; 998 memory_region_add_subregion_overlap(pci_dev->bus->address_space_io, 999 QEMU_PCI_VGA_IO_HI_BASE, io_hi, 1); 1000 pci_dev->has_vga = true; 1001 1002 pci_update_vga(pci_dev); 1003 } 1004 1005 void pci_unregister_vga(PCIDevice *pci_dev) 1006 { 1007 if (!pci_dev->has_vga) { 1008 return; 1009 } 1010 1011 memory_region_del_subregion(pci_dev->bus->address_space_mem, 1012 pci_dev->vga_regions[QEMU_PCI_VGA_MEM]); 1013 memory_region_del_subregion(pci_dev->bus->address_space_io, 1014 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO]); 1015 memory_region_del_subregion(pci_dev->bus->address_space_io, 1016 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI]); 1017 pci_dev->has_vga = false; 1018 } 1019 1020 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num) 1021 { 1022 return pci_dev->io_regions[region_num].addr; 1023 } 1024 1025 static pcibus_t pci_bar_address(PCIDevice *d, 1026 int reg, uint8_t type, pcibus_t size) 1027 { 1028 pcibus_t new_addr, last_addr; 1029 int bar = pci_bar(d, reg); 1030 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND); 1031 1032 if (type & PCI_BASE_ADDRESS_SPACE_IO) { 1033 if (!(cmd & PCI_COMMAND_IO)) { 1034 return PCI_BAR_UNMAPPED; 1035 } 1036 new_addr = pci_get_long(d->config + bar) & ~(size - 1); 1037 last_addr = new_addr + size - 1; 1038 /* Check if 32 bit BAR wraps around explicitly. 1039 * TODO: make priorities correct and remove this work around. 1040 */ 1041 if (last_addr <= new_addr || new_addr == 0 || last_addr >= UINT32_MAX) { 1042 return PCI_BAR_UNMAPPED; 1043 } 1044 return new_addr; 1045 } 1046 1047 if (!(cmd & PCI_COMMAND_MEMORY)) { 1048 return PCI_BAR_UNMAPPED; 1049 } 1050 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 1051 new_addr = pci_get_quad(d->config + bar); 1052 } else { 1053 new_addr = pci_get_long(d->config + bar); 1054 } 1055 /* the ROM slot has a specific enable bit */ 1056 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) { 1057 return PCI_BAR_UNMAPPED; 1058 } 1059 new_addr &= ~(size - 1); 1060 last_addr = new_addr + size - 1; 1061 /* NOTE: we do not support wrapping */ 1062 /* XXX: as we cannot support really dynamic 1063 mappings, we handle specific values as invalid 1064 mappings. */ 1065 if (last_addr <= new_addr || new_addr == 0 || 1066 last_addr == PCI_BAR_UNMAPPED) { 1067 return PCI_BAR_UNMAPPED; 1068 } 1069 1070 /* Now pcibus_t is 64bit. 1071 * Check if 32 bit BAR wraps around explicitly. 1072 * Without this, PC ide doesn't work well. 1073 * TODO: remove this work around. 1074 */ 1075 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) { 1076 return PCI_BAR_UNMAPPED; 1077 } 1078 1079 /* 1080 * OS is allowed to set BAR beyond its addressable 1081 * bits. For example, 32 bit OS can set 64bit bar 1082 * to >4G. Check it. TODO: we might need to support 1083 * it in the future for e.g. PAE. 1084 */ 1085 if (last_addr >= HWADDR_MAX) { 1086 return PCI_BAR_UNMAPPED; 1087 } 1088 1089 return new_addr; 1090 } 1091 1092 static void pci_update_mappings(PCIDevice *d) 1093 { 1094 PCIIORegion *r; 1095 int i; 1096 pcibus_t new_addr; 1097 1098 for(i = 0; i < PCI_NUM_REGIONS; i++) { 1099 r = &d->io_regions[i]; 1100 1101 /* this region isn't registered */ 1102 if (!r->size) 1103 continue; 1104 1105 new_addr = pci_bar_address(d, i, r->type, r->size); 1106 1107 /* This bar isn't changed */ 1108 if (new_addr == r->addr) 1109 continue; 1110 1111 /* now do the real mapping */ 1112 if (r->addr != PCI_BAR_UNMAPPED) { 1113 memory_region_del_subregion(r->address_space, r->memory); 1114 } 1115 r->addr = new_addr; 1116 if (r->addr != PCI_BAR_UNMAPPED) { 1117 memory_region_add_subregion_overlap(r->address_space, 1118 r->addr, r->memory, 1); 1119 } 1120 } 1121 1122 pci_update_vga(d); 1123 } 1124 1125 static inline int pci_irq_disabled(PCIDevice *d) 1126 { 1127 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE; 1128 } 1129 1130 /* Called after interrupt disabled field update in config space, 1131 * assert/deassert interrupts if necessary. 1132 * Gets original interrupt disable bit value (before update). */ 1133 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled) 1134 { 1135 int i, disabled = pci_irq_disabled(d); 1136 if (disabled == was_irq_disabled) 1137 return; 1138 for (i = 0; i < PCI_NUM_PINS; ++i) { 1139 int state = pci_irq_state(d, i); 1140 pci_change_irq_level(d, i, disabled ? -state : state); 1141 } 1142 } 1143 1144 uint32_t pci_default_read_config(PCIDevice *d, 1145 uint32_t address, int len) 1146 { 1147 uint32_t val = 0; 1148 1149 memcpy(&val, d->config + address, len); 1150 return le32_to_cpu(val); 1151 } 1152 1153 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l) 1154 { 1155 int i, was_irq_disabled = pci_irq_disabled(d); 1156 1157 for (i = 0; i < l; val >>= 8, ++i) { 1158 uint8_t wmask = d->wmask[addr + i]; 1159 uint8_t w1cmask = d->w1cmask[addr + i]; 1160 assert(!(wmask & w1cmask)); 1161 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask); 1162 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */ 1163 } 1164 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) || 1165 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) || 1166 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) || 1167 range_covers_byte(addr, l, PCI_COMMAND)) 1168 pci_update_mappings(d); 1169 1170 if (range_covers_byte(addr, l, PCI_COMMAND)) { 1171 pci_update_irq_disabled(d, was_irq_disabled); 1172 memory_region_set_enabled(&d->bus_master_enable_region, 1173 pci_get_word(d->config + PCI_COMMAND) 1174 & PCI_COMMAND_MASTER); 1175 } 1176 1177 msi_write_config(d, addr, val, l); 1178 msix_write_config(d, addr, val, l); 1179 } 1180 1181 /***********************************************************/ 1182 /* generic PCI irq support */ 1183 1184 /* 0 <= irq_num <= 3. level must be 0 or 1 */ 1185 static void pci_irq_handler(void *opaque, int irq_num, int level) 1186 { 1187 PCIDevice *pci_dev = opaque; 1188 int change; 1189 1190 change = level - pci_irq_state(pci_dev, irq_num); 1191 if (!change) 1192 return; 1193 1194 pci_set_irq_state(pci_dev, irq_num, level); 1195 pci_update_irq_status(pci_dev); 1196 if (pci_irq_disabled(pci_dev)) 1197 return; 1198 pci_change_irq_level(pci_dev, irq_num, change); 1199 } 1200 1201 static inline int pci_intx(PCIDevice *pci_dev) 1202 { 1203 return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1; 1204 } 1205 1206 qemu_irq pci_allocate_irq(PCIDevice *pci_dev) 1207 { 1208 int intx = pci_intx(pci_dev); 1209 1210 return qemu_allocate_irq(pci_irq_handler, pci_dev, intx); 1211 } 1212 1213 void pci_set_irq(PCIDevice *pci_dev, int level) 1214 { 1215 int intx = pci_intx(pci_dev); 1216 pci_irq_handler(pci_dev, intx, level); 1217 } 1218 1219 /* Special hooks used by device assignment */ 1220 void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq) 1221 { 1222 assert(pci_bus_is_root(bus)); 1223 bus->route_intx_to_irq = route_intx_to_irq; 1224 } 1225 1226 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin) 1227 { 1228 PCIBus *bus; 1229 1230 do { 1231 bus = dev->bus; 1232 pin = bus->map_irq(dev, pin); 1233 dev = bus->parent_dev; 1234 } while (dev); 1235 1236 if (!bus->route_intx_to_irq) { 1237 error_report("PCI: Bug - unimplemented PCI INTx routing (%s)", 1238 object_get_typename(OBJECT(bus->qbus.parent))); 1239 return (PCIINTxRoute) { PCI_INTX_DISABLED, -1 }; 1240 } 1241 1242 return bus->route_intx_to_irq(bus->irq_opaque, pin); 1243 } 1244 1245 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new) 1246 { 1247 return old->mode != new->mode || old->irq != new->irq; 1248 } 1249 1250 void pci_bus_fire_intx_routing_notifier(PCIBus *bus) 1251 { 1252 PCIDevice *dev; 1253 PCIBus *sec; 1254 int i; 1255 1256 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 1257 dev = bus->devices[i]; 1258 if (dev && dev->intx_routing_notifier) { 1259 dev->intx_routing_notifier(dev); 1260 } 1261 } 1262 1263 QLIST_FOREACH(sec, &bus->child, sibling) { 1264 pci_bus_fire_intx_routing_notifier(sec); 1265 } 1266 } 1267 1268 void pci_device_set_intx_routing_notifier(PCIDevice *dev, 1269 PCIINTxRoutingNotifier notifier) 1270 { 1271 dev->intx_routing_notifier = notifier; 1272 } 1273 1274 /* 1275 * PCI-to-PCI bridge specification 1276 * 9.1: Interrupt routing. Table 9-1 1277 * 1278 * the PCI Express Base Specification, Revision 2.1 1279 * 2.2.8.1: INTx interrutp signaling - Rules 1280 * the Implementation Note 1281 * Table 2-20 1282 */ 1283 /* 1284 * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD 1285 * 0-origin unlike PCI interrupt pin register. 1286 */ 1287 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin) 1288 { 1289 return (pin + PCI_SLOT(pci_dev->devfn)) % PCI_NUM_PINS; 1290 } 1291 1292 /***********************************************************/ 1293 /* monitor info on PCI */ 1294 1295 typedef struct { 1296 uint16_t class; 1297 const char *desc; 1298 const char *fw_name; 1299 uint16_t fw_ign_bits; 1300 } pci_class_desc; 1301 1302 static const pci_class_desc pci_class_descriptions[] = 1303 { 1304 { 0x0001, "VGA controller", "display"}, 1305 { 0x0100, "SCSI controller", "scsi"}, 1306 { 0x0101, "IDE controller", "ide"}, 1307 { 0x0102, "Floppy controller", "fdc"}, 1308 { 0x0103, "IPI controller", "ipi"}, 1309 { 0x0104, "RAID controller", "raid"}, 1310 { 0x0106, "SATA controller"}, 1311 { 0x0107, "SAS controller"}, 1312 { 0x0180, "Storage controller"}, 1313 { 0x0200, "Ethernet controller", "ethernet"}, 1314 { 0x0201, "Token Ring controller", "token-ring"}, 1315 { 0x0202, "FDDI controller", "fddi"}, 1316 { 0x0203, "ATM controller", "atm"}, 1317 { 0x0280, "Network controller"}, 1318 { 0x0300, "VGA controller", "display", 0x00ff}, 1319 { 0x0301, "XGA controller"}, 1320 { 0x0302, "3D controller"}, 1321 { 0x0380, "Display controller"}, 1322 { 0x0400, "Video controller", "video"}, 1323 { 0x0401, "Audio controller", "sound"}, 1324 { 0x0402, "Phone"}, 1325 { 0x0403, "Audio controller", "sound"}, 1326 { 0x0480, "Multimedia controller"}, 1327 { 0x0500, "RAM controller", "memory"}, 1328 { 0x0501, "Flash controller", "flash"}, 1329 { 0x0580, "Memory controller"}, 1330 { 0x0600, "Host bridge", "host"}, 1331 { 0x0601, "ISA bridge", "isa"}, 1332 { 0x0602, "EISA bridge", "eisa"}, 1333 { 0x0603, "MC bridge", "mca"}, 1334 { 0x0604, "PCI bridge", "pci-bridge"}, 1335 { 0x0605, "PCMCIA bridge", "pcmcia"}, 1336 { 0x0606, "NUBUS bridge", "nubus"}, 1337 { 0x0607, "CARDBUS bridge", "cardbus"}, 1338 { 0x0608, "RACEWAY bridge"}, 1339 { 0x0680, "Bridge"}, 1340 { 0x0700, "Serial port", "serial"}, 1341 { 0x0701, "Parallel port", "parallel"}, 1342 { 0x0800, "Interrupt controller", "interrupt-controller"}, 1343 { 0x0801, "DMA controller", "dma-controller"}, 1344 { 0x0802, "Timer", "timer"}, 1345 { 0x0803, "RTC", "rtc"}, 1346 { 0x0900, "Keyboard", "keyboard"}, 1347 { 0x0901, "Pen", "pen"}, 1348 { 0x0902, "Mouse", "mouse"}, 1349 { 0x0A00, "Dock station", "dock", 0x00ff}, 1350 { 0x0B00, "i386 cpu", "cpu", 0x00ff}, 1351 { 0x0c00, "Fireware contorller", "fireware"}, 1352 { 0x0c01, "Access bus controller", "access-bus"}, 1353 { 0x0c02, "SSA controller", "ssa"}, 1354 { 0x0c03, "USB controller", "usb"}, 1355 { 0x0c04, "Fibre channel controller", "fibre-channel"}, 1356 { 0x0c05, "SMBus"}, 1357 { 0, NULL} 1358 }; 1359 1360 static void pci_for_each_device_under_bus(PCIBus *bus, 1361 void (*fn)(PCIBus *b, PCIDevice *d, 1362 void *opaque), 1363 void *opaque) 1364 { 1365 PCIDevice *d; 1366 int devfn; 1367 1368 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1369 d = bus->devices[devfn]; 1370 if (d) { 1371 fn(bus, d, opaque); 1372 } 1373 } 1374 } 1375 1376 void pci_for_each_device(PCIBus *bus, int bus_num, 1377 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque), 1378 void *opaque) 1379 { 1380 bus = pci_find_bus_nr(bus, bus_num); 1381 1382 if (bus) { 1383 pci_for_each_device_under_bus(bus, fn, opaque); 1384 } 1385 } 1386 1387 static const pci_class_desc *get_class_desc(int class) 1388 { 1389 const pci_class_desc *desc; 1390 1391 desc = pci_class_descriptions; 1392 while (desc->desc && class != desc->class) { 1393 desc++; 1394 } 1395 1396 return desc; 1397 } 1398 1399 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num); 1400 1401 static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev) 1402 { 1403 PciMemoryRegionList *head = NULL, *cur_item = NULL; 1404 int i; 1405 1406 for (i = 0; i < PCI_NUM_REGIONS; i++) { 1407 const PCIIORegion *r = &dev->io_regions[i]; 1408 PciMemoryRegionList *region; 1409 1410 if (!r->size) { 1411 continue; 1412 } 1413 1414 region = g_malloc0(sizeof(*region)); 1415 region->value = g_malloc0(sizeof(*region->value)); 1416 1417 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { 1418 region->value->type = g_strdup("io"); 1419 } else { 1420 region->value->type = g_strdup("memory"); 1421 region->value->has_prefetch = true; 1422 region->value->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH); 1423 region->value->has_mem_type_64 = true; 1424 region->value->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64); 1425 } 1426 1427 region->value->bar = i; 1428 region->value->address = r->addr; 1429 region->value->size = r->size; 1430 1431 /* XXX: waiting for the qapi to support GSList */ 1432 if (!cur_item) { 1433 head = cur_item = region; 1434 } else { 1435 cur_item->next = region; 1436 cur_item = region; 1437 } 1438 } 1439 1440 return head; 1441 } 1442 1443 static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus, 1444 int bus_num) 1445 { 1446 PciBridgeInfo *info; 1447 1448 info = g_malloc0(sizeof(*info)); 1449 1450 info->bus.number = dev->config[PCI_PRIMARY_BUS]; 1451 info->bus.secondary = dev->config[PCI_SECONDARY_BUS]; 1452 info->bus.subordinate = dev->config[PCI_SUBORDINATE_BUS]; 1453 1454 info->bus.io_range = g_malloc0(sizeof(*info->bus.io_range)); 1455 info->bus.io_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO); 1456 info->bus.io_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO); 1457 1458 info->bus.memory_range = g_malloc0(sizeof(*info->bus.memory_range)); 1459 info->bus.memory_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 1460 info->bus.memory_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 1461 1462 info->bus.prefetchable_range = g_malloc0(sizeof(*info->bus.prefetchable_range)); 1463 info->bus.prefetchable_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 1464 info->bus.prefetchable_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 1465 1466 if (dev->config[PCI_SECONDARY_BUS] != 0) { 1467 PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]); 1468 if (child_bus) { 1469 info->has_devices = true; 1470 info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]); 1471 } 1472 } 1473 1474 return info; 1475 } 1476 1477 static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus, 1478 int bus_num) 1479 { 1480 const pci_class_desc *desc; 1481 PciDeviceInfo *info; 1482 uint8_t type; 1483 int class; 1484 1485 info = g_malloc0(sizeof(*info)); 1486 info->bus = bus_num; 1487 info->slot = PCI_SLOT(dev->devfn); 1488 info->function = PCI_FUNC(dev->devfn); 1489 1490 class = pci_get_word(dev->config + PCI_CLASS_DEVICE); 1491 info->class_info.q_class = class; 1492 desc = get_class_desc(class); 1493 if (desc->desc) { 1494 info->class_info.has_desc = true; 1495 info->class_info.desc = g_strdup(desc->desc); 1496 } 1497 1498 info->id.vendor = pci_get_word(dev->config + PCI_VENDOR_ID); 1499 info->id.device = pci_get_word(dev->config + PCI_DEVICE_ID); 1500 info->regions = qmp_query_pci_regions(dev); 1501 info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : ""); 1502 1503 if (dev->config[PCI_INTERRUPT_PIN] != 0) { 1504 info->has_irq = true; 1505 info->irq = dev->config[PCI_INTERRUPT_LINE]; 1506 } 1507 1508 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 1509 if (type == PCI_HEADER_TYPE_BRIDGE) { 1510 info->has_pci_bridge = true; 1511 info->pci_bridge = qmp_query_pci_bridge(dev, bus, bus_num); 1512 } 1513 1514 return info; 1515 } 1516 1517 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num) 1518 { 1519 PciDeviceInfoList *info, *head = NULL, *cur_item = NULL; 1520 PCIDevice *dev; 1521 int devfn; 1522 1523 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1524 dev = bus->devices[devfn]; 1525 if (dev) { 1526 info = g_malloc0(sizeof(*info)); 1527 info->value = qmp_query_pci_device(dev, bus, bus_num); 1528 1529 /* XXX: waiting for the qapi to support GSList */ 1530 if (!cur_item) { 1531 head = cur_item = info; 1532 } else { 1533 cur_item->next = info; 1534 cur_item = info; 1535 } 1536 } 1537 } 1538 1539 return head; 1540 } 1541 1542 static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num) 1543 { 1544 PciInfo *info = NULL; 1545 1546 bus = pci_find_bus_nr(bus, bus_num); 1547 if (bus) { 1548 info = g_malloc0(sizeof(*info)); 1549 info->bus = bus_num; 1550 info->devices = qmp_query_pci_devices(bus, bus_num); 1551 } 1552 1553 return info; 1554 } 1555 1556 PciInfoList *qmp_query_pci(Error **errp) 1557 { 1558 PciInfoList *info, *head = NULL, *cur_item = NULL; 1559 PCIHostState *host_bridge; 1560 1561 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { 1562 info = g_malloc0(sizeof(*info)); 1563 info->value = qmp_query_pci_bus(host_bridge->bus, 0); 1564 1565 /* XXX: waiting for the qapi to support GSList */ 1566 if (!cur_item) { 1567 head = cur_item = info; 1568 } else { 1569 cur_item->next = info; 1570 cur_item = info; 1571 } 1572 } 1573 1574 return head; 1575 } 1576 1577 static const char * const pci_nic_models[] = { 1578 "ne2k_pci", 1579 "i82551", 1580 "i82557b", 1581 "i82559er", 1582 "rtl8139", 1583 "e1000", 1584 "pcnet", 1585 "virtio", 1586 NULL 1587 }; 1588 1589 static const char * const pci_nic_names[] = { 1590 "ne2k_pci", 1591 "i82551", 1592 "i82557b", 1593 "i82559er", 1594 "rtl8139", 1595 "e1000", 1596 "pcnet", 1597 "virtio-net-pci", 1598 NULL 1599 }; 1600 1601 /* Initialize a PCI NIC. */ 1602 /* FIXME callers should check for failure, but don't */ 1603 PCIDevice *pci_nic_init(NICInfo *nd, PCIBus *rootbus, 1604 const char *default_model, 1605 const char *default_devaddr) 1606 { 1607 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr; 1608 PCIBus *bus; 1609 int devfn; 1610 PCIDevice *pci_dev; 1611 DeviceState *dev; 1612 int i; 1613 1614 i = qemu_find_nic_model(nd, pci_nic_models, default_model); 1615 if (i < 0) 1616 return NULL; 1617 1618 bus = pci_get_bus_devfn(&devfn, rootbus, devaddr); 1619 if (!bus) { 1620 error_report("Invalid PCI device address %s for device %s", 1621 devaddr, pci_nic_names[i]); 1622 return NULL; 1623 } 1624 1625 pci_dev = pci_create(bus, devfn, pci_nic_names[i]); 1626 dev = &pci_dev->qdev; 1627 qdev_set_nic_properties(dev, nd); 1628 if (qdev_init(dev) < 0) 1629 return NULL; 1630 return pci_dev; 1631 } 1632 1633 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus, 1634 const char *default_model, 1635 const char *default_devaddr) 1636 { 1637 PCIDevice *res; 1638 1639 if (qemu_show_nic_models(nd->model, pci_nic_models)) 1640 exit(0); 1641 1642 res = pci_nic_init(nd, rootbus, default_model, default_devaddr); 1643 if (!res) 1644 exit(1); 1645 return res; 1646 } 1647 1648 PCIDevice *pci_vga_init(PCIBus *bus) 1649 { 1650 switch (vga_interface_type) { 1651 case VGA_CIRRUS: 1652 return pci_create_simple(bus, -1, "cirrus-vga"); 1653 case VGA_QXL: 1654 return pci_create_simple(bus, -1, "qxl-vga"); 1655 case VGA_STD: 1656 return pci_create_simple(bus, -1, "VGA"); 1657 case VGA_VMWARE: 1658 return pci_create_simple(bus, -1, "vmware-svga"); 1659 case VGA_NONE: 1660 default: /* Other non-PCI types. Checking for unsupported types is already 1661 done in vl.c. */ 1662 return NULL; 1663 } 1664 } 1665 1666 /* Whether a given bus number is in range of the secondary 1667 * bus of the given bridge device. */ 1668 static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num) 1669 { 1670 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) & 1671 PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ && 1672 dev->config[PCI_SECONDARY_BUS] < bus_num && 1673 bus_num <= dev->config[PCI_SUBORDINATE_BUS]; 1674 } 1675 1676 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num) 1677 { 1678 PCIBus *sec; 1679 1680 if (!bus) { 1681 return NULL; 1682 } 1683 1684 if (pci_bus_num(bus) == bus_num) { 1685 return bus; 1686 } 1687 1688 /* Consider all bus numbers in range for the host pci bridge. */ 1689 if (!pci_bus_is_root(bus) && 1690 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) { 1691 return NULL; 1692 } 1693 1694 /* try child bus */ 1695 for (; bus; bus = sec) { 1696 QLIST_FOREACH(sec, &bus->child, sibling) { 1697 assert(!pci_bus_is_root(sec)); 1698 if (sec->parent_dev->config[PCI_SECONDARY_BUS] == bus_num) { 1699 return sec; 1700 } 1701 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) { 1702 break; 1703 } 1704 } 1705 } 1706 1707 return NULL; 1708 } 1709 1710 void pci_for_each_bus_depth_first(PCIBus *bus, 1711 void *(*begin)(PCIBus *bus, void *parent_state), 1712 void (*end)(PCIBus *bus, void *state), 1713 void *parent_state) 1714 { 1715 PCIBus *sec; 1716 void *state; 1717 1718 if (!bus) { 1719 return; 1720 } 1721 1722 if (begin) { 1723 state = begin(bus, parent_state); 1724 } else { 1725 state = parent_state; 1726 } 1727 1728 QLIST_FOREACH(sec, &bus->child, sibling) { 1729 pci_for_each_bus_depth_first(sec, begin, end, state); 1730 } 1731 1732 if (end) { 1733 end(bus, state); 1734 } 1735 } 1736 1737 1738 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn) 1739 { 1740 bus = pci_find_bus_nr(bus, bus_num); 1741 1742 if (!bus) 1743 return NULL; 1744 1745 return bus->devices[devfn]; 1746 } 1747 1748 static int pci_qdev_init(DeviceState *qdev) 1749 { 1750 PCIDevice *pci_dev = (PCIDevice *)qdev; 1751 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 1752 PCIBus *bus; 1753 int rc; 1754 bool is_default_rom; 1755 1756 /* initialize cap_present for pci_is_express() and pci_config_size() */ 1757 if (pc->is_express) { 1758 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; 1759 } 1760 1761 bus = PCI_BUS(qdev_get_parent_bus(qdev)); 1762 pci_dev = do_pci_register_device(pci_dev, bus, 1763 object_get_typename(OBJECT(qdev)), 1764 pci_dev->devfn); 1765 if (pci_dev == NULL) 1766 return -1; 1767 1768 if (pc->init) { 1769 rc = pc->init(pci_dev); 1770 if (rc != 0) { 1771 do_pci_unregister_device(pci_dev); 1772 return rc; 1773 } 1774 } 1775 1776 /* rom loading */ 1777 is_default_rom = false; 1778 if (pci_dev->romfile == NULL && pc->romfile != NULL) { 1779 pci_dev->romfile = g_strdup(pc->romfile); 1780 is_default_rom = true; 1781 } 1782 pci_add_option_rom(pci_dev, is_default_rom); 1783 1784 return 0; 1785 } 1786 1787 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction, 1788 const char *name) 1789 { 1790 DeviceState *dev; 1791 1792 dev = qdev_create(&bus->qbus, name); 1793 qdev_prop_set_int32(dev, "addr", devfn); 1794 qdev_prop_set_bit(dev, "multifunction", multifunction); 1795 return PCI_DEVICE(dev); 1796 } 1797 1798 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, 1799 bool multifunction, 1800 const char *name) 1801 { 1802 PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name); 1803 qdev_init_nofail(&dev->qdev); 1804 return dev; 1805 } 1806 1807 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name) 1808 { 1809 return pci_create_multifunction(bus, devfn, false, name); 1810 } 1811 1812 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name) 1813 { 1814 return pci_create_simple_multifunction(bus, devfn, false, name); 1815 } 1816 1817 static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size) 1818 { 1819 int offset = PCI_CONFIG_HEADER_SIZE; 1820 int i; 1821 for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) { 1822 if (pdev->used[i]) 1823 offset = i + 1; 1824 else if (i - offset + 1 == size) 1825 return offset; 1826 } 1827 return 0; 1828 } 1829 1830 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id, 1831 uint8_t *prev_p) 1832 { 1833 uint8_t next, prev; 1834 1835 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST)) 1836 return 0; 1837 1838 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); 1839 prev = next + PCI_CAP_LIST_NEXT) 1840 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id) 1841 break; 1842 1843 if (prev_p) 1844 *prev_p = prev; 1845 return next; 1846 } 1847 1848 static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset) 1849 { 1850 uint8_t next, prev, found = 0; 1851 1852 if (!(pdev->used[offset])) { 1853 return 0; 1854 } 1855 1856 assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST); 1857 1858 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); 1859 prev = next + PCI_CAP_LIST_NEXT) { 1860 if (next <= offset && next > found) { 1861 found = next; 1862 } 1863 } 1864 return found; 1865 } 1866 1867 /* Patch the PCI vendor and device ids in a PCI rom image if necessary. 1868 This is needed for an option rom which is used for more than one device. */ 1869 static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size) 1870 { 1871 uint16_t vendor_id; 1872 uint16_t device_id; 1873 uint16_t rom_vendor_id; 1874 uint16_t rom_device_id; 1875 uint16_t rom_magic; 1876 uint16_t pcir_offset; 1877 uint8_t checksum; 1878 1879 /* Words in rom data are little endian (like in PCI configuration), 1880 so they can be read / written with pci_get_word / pci_set_word. */ 1881 1882 /* Only a valid rom will be patched. */ 1883 rom_magic = pci_get_word(ptr); 1884 if (rom_magic != 0xaa55) { 1885 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic); 1886 return; 1887 } 1888 pcir_offset = pci_get_word(ptr + 0x18); 1889 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) { 1890 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset); 1891 return; 1892 } 1893 1894 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID); 1895 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID); 1896 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4); 1897 rom_device_id = pci_get_word(ptr + pcir_offset + 6); 1898 1899 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile, 1900 vendor_id, device_id, rom_vendor_id, rom_device_id); 1901 1902 checksum = ptr[6]; 1903 1904 if (vendor_id != rom_vendor_id) { 1905 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */ 1906 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8); 1907 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8); 1908 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); 1909 ptr[6] = checksum; 1910 pci_set_word(ptr + pcir_offset + 4, vendor_id); 1911 } 1912 1913 if (device_id != rom_device_id) { 1914 /* Patch device id and checksum (at offset 6 for etherboot roms). */ 1915 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8); 1916 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8); 1917 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); 1918 ptr[6] = checksum; 1919 pci_set_word(ptr + pcir_offset + 6, device_id); 1920 } 1921 } 1922 1923 /* Add an option rom for the device */ 1924 static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom) 1925 { 1926 int size; 1927 char *path; 1928 void *ptr; 1929 char name[32]; 1930 const VMStateDescription *vmsd; 1931 1932 if (!pdev->romfile) 1933 return 0; 1934 if (strlen(pdev->romfile) == 0) 1935 return 0; 1936 1937 if (!pdev->rom_bar) { 1938 /* 1939 * Load rom via fw_cfg instead of creating a rom bar, 1940 * for 0.11 compatibility. 1941 */ 1942 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE); 1943 if (class == 0x0300) { 1944 rom_add_vga(pdev->romfile); 1945 } else { 1946 rom_add_option(pdev->romfile, -1); 1947 } 1948 return 0; 1949 } 1950 1951 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile); 1952 if (path == NULL) { 1953 path = g_strdup(pdev->romfile); 1954 } 1955 1956 size = get_image_size(path); 1957 if (size < 0) { 1958 error_report("%s: failed to find romfile \"%s\"", 1959 __func__, pdev->romfile); 1960 g_free(path); 1961 return -1; 1962 } else if (size == 0) { 1963 error_report("%s: ignoring empty romfile \"%s\"", 1964 __func__, pdev->romfile); 1965 g_free(path); 1966 return -1; 1967 } 1968 if (size & (size - 1)) { 1969 size = 1 << qemu_fls(size); 1970 } 1971 1972 vmsd = qdev_get_vmsd(DEVICE(pdev)); 1973 1974 if (vmsd) { 1975 snprintf(name, sizeof(name), "%s.rom", vmsd->name); 1976 } else { 1977 snprintf(name, sizeof(name), "%s.rom", object_get_typename(OBJECT(pdev))); 1978 } 1979 pdev->has_rom = true; 1980 memory_region_init_ram(&pdev->rom, OBJECT(pdev), name, size); 1981 vmstate_register_ram(&pdev->rom, &pdev->qdev); 1982 ptr = memory_region_get_ram_ptr(&pdev->rom); 1983 load_image(path, ptr); 1984 g_free(path); 1985 1986 if (is_default_rom) { 1987 /* Only the default rom images will be patched (if needed). */ 1988 pci_patch_ids(pdev, ptr, size); 1989 } 1990 1991 pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom); 1992 1993 return 0; 1994 } 1995 1996 static void pci_del_option_rom(PCIDevice *pdev) 1997 { 1998 if (!pdev->has_rom) 1999 return; 2000 2001 vmstate_unregister_ram(&pdev->rom, &pdev->qdev); 2002 memory_region_destroy(&pdev->rom); 2003 pdev->has_rom = false; 2004 } 2005 2006 /* 2007 * if !offset 2008 * Reserve space and add capability to the linked list in pci config space 2009 * 2010 * if offset = 0, 2011 * Find and reserve space and add capability to the linked list 2012 * in pci config space */ 2013 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, 2014 uint8_t offset, uint8_t size) 2015 { 2016 int ret; 2017 Error *local_err = NULL; 2018 2019 ret = pci_add_capability2(pdev, cap_id, offset, size, &local_err); 2020 if (local_err) { 2021 assert(ret < 0); 2022 error_report("%s", error_get_pretty(local_err)); 2023 error_free(local_err); 2024 } else { 2025 /* success implies a positive offset in config space */ 2026 assert(ret > 0); 2027 } 2028 return ret; 2029 } 2030 2031 int pci_add_capability2(PCIDevice *pdev, uint8_t cap_id, 2032 uint8_t offset, uint8_t size, 2033 Error **errp) 2034 { 2035 uint8_t *config; 2036 int i, overlapping_cap; 2037 2038 if (!offset) { 2039 offset = pci_find_space(pdev, size); 2040 if (!offset) { 2041 error_setg(errp, "out of PCI config space"); 2042 return -ENOSPC; 2043 } 2044 } else { 2045 /* Verify that capabilities don't overlap. Note: device assignment 2046 * depends on this check to verify that the device is not broken. 2047 * Should never trigger for emulated devices, but it's helpful 2048 * for debugging these. */ 2049 for (i = offset; i < offset + size; i++) { 2050 overlapping_cap = pci_find_capability_at_offset(pdev, i); 2051 if (overlapping_cap) { 2052 error_setg(errp, "%s:%02x:%02x.%x " 2053 "Attempt to add PCI capability %x at offset " 2054 "%x overlaps existing capability %x at offset %x", 2055 pci_root_bus_path(pdev), pci_bus_num(pdev->bus), 2056 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), 2057 cap_id, offset, overlapping_cap, i); 2058 return -EINVAL; 2059 } 2060 } 2061 } 2062 2063 config = pdev->config + offset; 2064 config[PCI_CAP_LIST_ID] = cap_id; 2065 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST]; 2066 pdev->config[PCI_CAPABILITY_LIST] = offset; 2067 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST; 2068 memset(pdev->used + offset, 0xFF, QEMU_ALIGN_UP(size, 4)); 2069 /* Make capability read-only by default */ 2070 memset(pdev->wmask + offset, 0, size); 2071 /* Check capability by default */ 2072 memset(pdev->cmask + offset, 0xFF, size); 2073 return offset; 2074 } 2075 2076 /* Unlink capability from the pci config space. */ 2077 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size) 2078 { 2079 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev); 2080 if (!offset) 2081 return; 2082 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT]; 2083 /* Make capability writable again */ 2084 memset(pdev->wmask + offset, 0xff, size); 2085 memset(pdev->w1cmask + offset, 0, size); 2086 /* Clear cmask as device-specific registers can't be checked */ 2087 memset(pdev->cmask + offset, 0, size); 2088 memset(pdev->used + offset, 0, QEMU_ALIGN_UP(size, 4)); 2089 2090 if (!pdev->config[PCI_CAPABILITY_LIST]) 2091 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST; 2092 } 2093 2094 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id) 2095 { 2096 return pci_find_capability_list(pdev, cap_id, NULL); 2097 } 2098 2099 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent) 2100 { 2101 PCIDevice *d = (PCIDevice *)dev; 2102 const pci_class_desc *desc; 2103 char ctxt[64]; 2104 PCIIORegion *r; 2105 int i, class; 2106 2107 class = pci_get_word(d->config + PCI_CLASS_DEVICE); 2108 desc = pci_class_descriptions; 2109 while (desc->desc && class != desc->class) 2110 desc++; 2111 if (desc->desc) { 2112 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc); 2113 } else { 2114 snprintf(ctxt, sizeof(ctxt), "Class %04x", class); 2115 } 2116 2117 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, " 2118 "pci id %04x:%04x (sub %04x:%04x)\n", 2119 indent, "", ctxt, pci_bus_num(d->bus), 2120 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn), 2121 pci_get_word(d->config + PCI_VENDOR_ID), 2122 pci_get_word(d->config + PCI_DEVICE_ID), 2123 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID), 2124 pci_get_word(d->config + PCI_SUBSYSTEM_ID)); 2125 for (i = 0; i < PCI_NUM_REGIONS; i++) { 2126 r = &d->io_regions[i]; 2127 if (!r->size) 2128 continue; 2129 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS 2130 " [0x%"FMT_PCIBUS"]\n", 2131 indent, "", 2132 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem", 2133 r->addr, r->addr + r->size - 1); 2134 } 2135 } 2136 2137 static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len) 2138 { 2139 PCIDevice *d = (PCIDevice *)dev; 2140 const char *name = NULL; 2141 const pci_class_desc *desc = pci_class_descriptions; 2142 int class = pci_get_word(d->config + PCI_CLASS_DEVICE); 2143 2144 while (desc->desc && 2145 (class & ~desc->fw_ign_bits) != 2146 (desc->class & ~desc->fw_ign_bits)) { 2147 desc++; 2148 } 2149 2150 if (desc->desc) { 2151 name = desc->fw_name; 2152 } 2153 2154 if (name) { 2155 pstrcpy(buf, len, name); 2156 } else { 2157 snprintf(buf, len, "pci%04x,%04x", 2158 pci_get_word(d->config + PCI_VENDOR_ID), 2159 pci_get_word(d->config + PCI_DEVICE_ID)); 2160 } 2161 2162 return buf; 2163 } 2164 2165 static char *pcibus_get_fw_dev_path(DeviceState *dev) 2166 { 2167 PCIDevice *d = (PCIDevice *)dev; 2168 char path[50], name[33]; 2169 int off; 2170 2171 off = snprintf(path, sizeof(path), "%s@%x", 2172 pci_dev_fw_name(dev, name, sizeof name), 2173 PCI_SLOT(d->devfn)); 2174 if (PCI_FUNC(d->devfn)) 2175 snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn)); 2176 return g_strdup(path); 2177 } 2178 2179 static char *pcibus_get_dev_path(DeviceState *dev) 2180 { 2181 PCIDevice *d = container_of(dev, PCIDevice, qdev); 2182 PCIDevice *t; 2183 int slot_depth; 2184 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function. 2185 * 00 is added here to make this format compatible with 2186 * domain:Bus:Slot.Func for systems without nested PCI bridges. 2187 * Slot.Function list specifies the slot and function numbers for all 2188 * devices on the path from root to the specific device. */ 2189 const char *root_bus_path; 2190 int root_bus_len; 2191 char slot[] = ":SS.F"; 2192 int slot_len = sizeof slot - 1 /* For '\0' */; 2193 int path_len; 2194 char *path, *p; 2195 int s; 2196 2197 root_bus_path = pci_root_bus_path(d); 2198 root_bus_len = strlen(root_bus_path); 2199 2200 /* Calculate # of slots on path between device and root. */; 2201 slot_depth = 0; 2202 for (t = d; t; t = t->bus->parent_dev) { 2203 ++slot_depth; 2204 } 2205 2206 path_len = root_bus_len + slot_len * slot_depth; 2207 2208 /* Allocate memory, fill in the terminating null byte. */ 2209 path = g_malloc(path_len + 1 /* For '\0' */); 2210 path[path_len] = '\0'; 2211 2212 memcpy(path, root_bus_path, root_bus_len); 2213 2214 /* Fill in slot numbers. We walk up from device to root, so need to print 2215 * them in the reverse order, last to first. */ 2216 p = path + path_len; 2217 for (t = d; t; t = t->bus->parent_dev) { 2218 p -= slot_len; 2219 s = snprintf(slot, sizeof slot, ":%02x.%x", 2220 PCI_SLOT(t->devfn), PCI_FUNC(t->devfn)); 2221 assert(s == slot_len); 2222 memcpy(p, slot, slot_len); 2223 } 2224 2225 return path; 2226 } 2227 2228 static int pci_qdev_find_recursive(PCIBus *bus, 2229 const char *id, PCIDevice **pdev) 2230 { 2231 DeviceState *qdev = qdev_find_recursive(&bus->qbus, id); 2232 if (!qdev) { 2233 return -ENODEV; 2234 } 2235 2236 /* roughly check if given qdev is pci device */ 2237 if (object_dynamic_cast(OBJECT(qdev), TYPE_PCI_DEVICE)) { 2238 *pdev = PCI_DEVICE(qdev); 2239 return 0; 2240 } 2241 return -EINVAL; 2242 } 2243 2244 int pci_qdev_find_device(const char *id, PCIDevice **pdev) 2245 { 2246 PCIHostState *host_bridge; 2247 int rc = -ENODEV; 2248 2249 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { 2250 int tmp = pci_qdev_find_recursive(host_bridge->bus, id, pdev); 2251 if (!tmp) { 2252 rc = 0; 2253 break; 2254 } 2255 if (tmp != -ENODEV) { 2256 rc = tmp; 2257 } 2258 } 2259 2260 return rc; 2261 } 2262 2263 MemoryRegion *pci_address_space(PCIDevice *dev) 2264 { 2265 return dev->bus->address_space_mem; 2266 } 2267 2268 MemoryRegion *pci_address_space_io(PCIDevice *dev) 2269 { 2270 return dev->bus->address_space_io; 2271 } 2272 2273 static void pci_device_class_init(ObjectClass *klass, void *data) 2274 { 2275 DeviceClass *k = DEVICE_CLASS(klass); 2276 k->init = pci_qdev_init; 2277 k->exit = pci_unregister_device; 2278 k->bus_type = TYPE_PCI_BUS; 2279 k->props = pci_props; 2280 } 2281 2282 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev) 2283 { 2284 PCIBus *bus = PCI_BUS(dev->bus); 2285 2286 if (bus->iommu_fn) { 2287 return bus->iommu_fn(bus, bus->iommu_opaque, dev->devfn); 2288 } 2289 2290 if (bus->parent_dev) { 2291 /** We are ignoring the bus master DMA bit of the bridge 2292 * as it would complicate things such as VFIO for no good reason */ 2293 return pci_device_iommu_address_space(bus->parent_dev); 2294 } 2295 2296 return &address_space_memory; 2297 } 2298 2299 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque) 2300 { 2301 bus->iommu_fn = fn; 2302 bus->iommu_opaque = opaque; 2303 } 2304 2305 static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque) 2306 { 2307 Range *range = opaque; 2308 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 2309 uint16_t cmd = pci_get_word(dev->config + PCI_COMMAND); 2310 int i; 2311 2312 if (!(cmd & PCI_COMMAND_MEMORY)) { 2313 return; 2314 } 2315 2316 if (pc->is_bridge) { 2317 pcibus_t base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 2318 pcibus_t limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 2319 2320 base = MAX(base, 0x1ULL << 32); 2321 2322 if (limit >= base) { 2323 Range pref_range; 2324 pref_range.begin = base; 2325 pref_range.end = limit + 1; 2326 range_extend(range, &pref_range); 2327 } 2328 } 2329 for (i = 0; i < PCI_NUM_REGIONS; ++i) { 2330 PCIIORegion *r = &dev->io_regions[i]; 2331 Range region_range; 2332 2333 if (!r->size || 2334 (r->type & PCI_BASE_ADDRESS_SPACE_IO) || 2335 !(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64)) { 2336 continue; 2337 } 2338 region_range.begin = pci_bar_address(dev, i, r->type, r->size); 2339 region_range.end = region_range.begin + r->size; 2340 2341 if (region_range.begin == PCI_BAR_UNMAPPED) { 2342 continue; 2343 } 2344 2345 region_range.begin = MAX(region_range.begin, 0x1ULL << 32); 2346 2347 if (region_range.end - 1 >= region_range.begin) { 2348 range_extend(range, ®ion_range); 2349 } 2350 } 2351 } 2352 2353 void pci_bus_get_w64_range(PCIBus *bus, Range *range) 2354 { 2355 range->begin = range->end = 0; 2356 pci_for_each_device_under_bus(bus, pci_dev_get_w64, range); 2357 } 2358 2359 static const TypeInfo pci_device_type_info = { 2360 .name = TYPE_PCI_DEVICE, 2361 .parent = TYPE_DEVICE, 2362 .instance_size = sizeof(PCIDevice), 2363 .abstract = true, 2364 .class_size = sizeof(PCIDeviceClass), 2365 .class_init = pci_device_class_init, 2366 }; 2367 2368 static void pci_register_types(void) 2369 { 2370 type_register_static(&pci_bus_info); 2371 type_register_static(&pcie_bus_info); 2372 type_register_static(&pci_device_type_info); 2373 } 2374 2375 type_init(pci_register_types) 2376