1 /* 2 * QEMU PCI bus manager 3 * 4 * Copyright (c) 2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu-common.h" 27 #include "hw/irq.h" 28 #include "hw/pci/pci.h" 29 #include "hw/pci/pci_bridge.h" 30 #include "hw/pci/pci_bus.h" 31 #include "hw/pci/pci_host.h" 32 #include "hw/qdev-properties.h" 33 #include "migration/qemu-file-types.h" 34 #include "migration/vmstate.h" 35 #include "monitor/monitor.h" 36 #include "net/net.h" 37 #include "sysemu/numa.h" 38 #include "hw/loader.h" 39 #include "qemu/error-report.h" 40 #include "qemu/range.h" 41 #include "trace.h" 42 #include "hw/pci/msi.h" 43 #include "hw/pci/msix.h" 44 #include "exec/address-spaces.h" 45 #include "hw/hotplug.h" 46 #include "hw/boards.h" 47 #include "qapi/error.h" 48 #include "qapi/qapi-commands-misc.h" 49 #include "qemu/cutils.h" 50 51 //#define DEBUG_PCI 52 #ifdef DEBUG_PCI 53 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) 54 #else 55 # define PCI_DPRINTF(format, ...) do { } while (0) 56 #endif 57 58 bool pci_available = true; 59 60 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent); 61 static char *pcibus_get_dev_path(DeviceState *dev); 62 static char *pcibus_get_fw_dev_path(DeviceState *dev); 63 static void pcibus_reset(BusState *qbus); 64 65 static Property pci_props[] = { 66 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1), 67 DEFINE_PROP_STRING("romfile", PCIDevice, romfile), 68 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1), 69 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present, 70 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false), 71 DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present, 72 QEMU_PCI_CAP_SERR_BITNR, true), 73 DEFINE_PROP_BIT("x-pcie-lnksta-dllla", PCIDevice, cap_present, 74 QEMU_PCIE_LNKSTA_DLLLA_BITNR, true), 75 DEFINE_PROP_BIT("x-pcie-extcap-init", PCIDevice, cap_present, 76 QEMU_PCIE_EXTCAP_INIT_BITNR, true), 77 DEFINE_PROP_END_OF_LIST() 78 }; 79 80 static const VMStateDescription vmstate_pcibus = { 81 .name = "PCIBUS", 82 .version_id = 1, 83 .minimum_version_id = 1, 84 .fields = (VMStateField[]) { 85 VMSTATE_INT32_EQUAL(nirq, PCIBus, NULL), 86 VMSTATE_VARRAY_INT32(irq_count, PCIBus, 87 nirq, 0, vmstate_info_int32, 88 int32_t), 89 VMSTATE_END_OF_LIST() 90 } 91 }; 92 93 static void pci_init_bus_master(PCIDevice *pci_dev) 94 { 95 AddressSpace *dma_as = pci_device_iommu_address_space(pci_dev); 96 97 memory_region_init_alias(&pci_dev->bus_master_enable_region, 98 OBJECT(pci_dev), "bus master", 99 dma_as->root, 0, memory_region_size(dma_as->root)); 100 memory_region_set_enabled(&pci_dev->bus_master_enable_region, false); 101 memory_region_add_subregion(&pci_dev->bus_master_container_region, 0, 102 &pci_dev->bus_master_enable_region); 103 } 104 105 static void pcibus_machine_done(Notifier *notifier, void *data) 106 { 107 PCIBus *bus = container_of(notifier, PCIBus, machine_done); 108 int i; 109 110 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 111 if (bus->devices[i]) { 112 pci_init_bus_master(bus->devices[i]); 113 } 114 } 115 } 116 117 static void pci_bus_realize(BusState *qbus, Error **errp) 118 { 119 PCIBus *bus = PCI_BUS(qbus); 120 121 bus->machine_done.notify = pcibus_machine_done; 122 qemu_add_machine_init_done_notifier(&bus->machine_done); 123 124 vmstate_register(NULL, -1, &vmstate_pcibus, bus); 125 } 126 127 static void pcie_bus_realize(BusState *qbus, Error **errp) 128 { 129 PCIBus *bus = PCI_BUS(qbus); 130 131 pci_bus_realize(qbus, errp); 132 133 /* 134 * A PCI-E bus can support extended config space if it's the root 135 * bus, or if the bus/bridge above it does as well 136 */ 137 if (pci_bus_is_root(bus)) { 138 bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE; 139 } else { 140 PCIBus *parent_bus = pci_get_bus(bus->parent_dev); 141 142 if (pci_bus_allows_extended_config_space(parent_bus)) { 143 bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE; 144 } 145 } 146 } 147 148 static void pci_bus_unrealize(BusState *qbus, Error **errp) 149 { 150 PCIBus *bus = PCI_BUS(qbus); 151 152 qemu_remove_machine_init_done_notifier(&bus->machine_done); 153 154 vmstate_unregister(NULL, &vmstate_pcibus, bus); 155 } 156 157 static int pcibus_num(PCIBus *bus) 158 { 159 if (pci_bus_is_root(bus)) { 160 return 0; /* pci host bridge */ 161 } 162 return bus->parent_dev->config[PCI_SECONDARY_BUS]; 163 } 164 165 static uint16_t pcibus_numa_node(PCIBus *bus) 166 { 167 return NUMA_NODE_UNASSIGNED; 168 } 169 170 static void pci_bus_class_init(ObjectClass *klass, void *data) 171 { 172 BusClass *k = BUS_CLASS(klass); 173 PCIBusClass *pbc = PCI_BUS_CLASS(klass); 174 175 k->print_dev = pcibus_dev_print; 176 k->get_dev_path = pcibus_get_dev_path; 177 k->get_fw_dev_path = pcibus_get_fw_dev_path; 178 k->realize = pci_bus_realize; 179 k->unrealize = pci_bus_unrealize; 180 k->reset = pcibus_reset; 181 182 pbc->bus_num = pcibus_num; 183 pbc->numa_node = pcibus_numa_node; 184 } 185 186 static const TypeInfo pci_bus_info = { 187 .name = TYPE_PCI_BUS, 188 .parent = TYPE_BUS, 189 .instance_size = sizeof(PCIBus), 190 .class_size = sizeof(PCIBusClass), 191 .class_init = pci_bus_class_init, 192 }; 193 194 static const TypeInfo pcie_interface_info = { 195 .name = INTERFACE_PCIE_DEVICE, 196 .parent = TYPE_INTERFACE, 197 }; 198 199 static const TypeInfo conventional_pci_interface_info = { 200 .name = INTERFACE_CONVENTIONAL_PCI_DEVICE, 201 .parent = TYPE_INTERFACE, 202 }; 203 204 static void pcie_bus_class_init(ObjectClass *klass, void *data) 205 { 206 BusClass *k = BUS_CLASS(klass); 207 208 k->realize = pcie_bus_realize; 209 } 210 211 static const TypeInfo pcie_bus_info = { 212 .name = TYPE_PCIE_BUS, 213 .parent = TYPE_PCI_BUS, 214 .class_init = pcie_bus_class_init, 215 }; 216 217 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num); 218 static void pci_update_mappings(PCIDevice *d); 219 static void pci_irq_handler(void *opaque, int irq_num, int level); 220 static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, Error **); 221 static void pci_del_option_rom(PCIDevice *pdev); 222 223 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET; 224 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU; 225 226 static QLIST_HEAD(, PCIHostState) pci_host_bridges; 227 228 int pci_bar(PCIDevice *d, int reg) 229 { 230 uint8_t type; 231 232 if (reg != PCI_ROM_SLOT) 233 return PCI_BASE_ADDRESS_0 + reg * 4; 234 235 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 236 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS; 237 } 238 239 static inline int pci_irq_state(PCIDevice *d, int irq_num) 240 { 241 return (d->irq_state >> irq_num) & 0x1; 242 } 243 244 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level) 245 { 246 d->irq_state &= ~(0x1 << irq_num); 247 d->irq_state |= level << irq_num; 248 } 249 250 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change) 251 { 252 PCIBus *bus; 253 for (;;) { 254 bus = pci_get_bus(pci_dev); 255 irq_num = bus->map_irq(pci_dev, irq_num); 256 if (bus->set_irq) 257 break; 258 pci_dev = bus->parent_dev; 259 } 260 bus->irq_count[irq_num] += change; 261 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0); 262 } 263 264 int pci_bus_get_irq_level(PCIBus *bus, int irq_num) 265 { 266 assert(irq_num >= 0); 267 assert(irq_num < bus->nirq); 268 return !!bus->irq_count[irq_num]; 269 } 270 271 /* Update interrupt status bit in config space on interrupt 272 * state change. */ 273 static void pci_update_irq_status(PCIDevice *dev) 274 { 275 if (dev->irq_state) { 276 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT; 277 } else { 278 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; 279 } 280 } 281 282 void pci_device_deassert_intx(PCIDevice *dev) 283 { 284 int i; 285 for (i = 0; i < PCI_NUM_PINS; ++i) { 286 pci_irq_handler(dev, i, 0); 287 } 288 } 289 290 static void pci_do_device_reset(PCIDevice *dev) 291 { 292 int r; 293 294 pci_device_deassert_intx(dev); 295 assert(dev->irq_state == 0); 296 297 /* Clear all writable bits */ 298 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND, 299 pci_get_word(dev->wmask + PCI_COMMAND) | 300 pci_get_word(dev->w1cmask + PCI_COMMAND)); 301 pci_word_test_and_clear_mask(dev->config + PCI_STATUS, 302 pci_get_word(dev->wmask + PCI_STATUS) | 303 pci_get_word(dev->w1cmask + PCI_STATUS)); 304 dev->config[PCI_CACHE_LINE_SIZE] = 0x0; 305 dev->config[PCI_INTERRUPT_LINE] = 0x0; 306 for (r = 0; r < PCI_NUM_REGIONS; ++r) { 307 PCIIORegion *region = &dev->io_regions[r]; 308 if (!region->size) { 309 continue; 310 } 311 312 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) && 313 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 314 pci_set_quad(dev->config + pci_bar(dev, r), region->type); 315 } else { 316 pci_set_long(dev->config + pci_bar(dev, r), region->type); 317 } 318 } 319 pci_update_mappings(dev); 320 321 msi_reset(dev); 322 msix_reset(dev); 323 } 324 325 /* 326 * This function is called on #RST and FLR. 327 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set 328 */ 329 void pci_device_reset(PCIDevice *dev) 330 { 331 qdev_reset_all(&dev->qdev); 332 pci_do_device_reset(dev); 333 } 334 335 /* 336 * Trigger pci bus reset under a given bus. 337 * Called via qbus_reset_all on RST# assert, after the devices 338 * have been reset qdev_reset_all-ed already. 339 */ 340 static void pcibus_reset(BusState *qbus) 341 { 342 PCIBus *bus = DO_UPCAST(PCIBus, qbus, qbus); 343 int i; 344 345 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 346 if (bus->devices[i]) { 347 pci_do_device_reset(bus->devices[i]); 348 } 349 } 350 351 for (i = 0; i < bus->nirq; i++) { 352 assert(bus->irq_count[i] == 0); 353 } 354 } 355 356 static void pci_host_bus_register(DeviceState *host) 357 { 358 PCIHostState *host_bridge = PCI_HOST_BRIDGE(host); 359 360 QLIST_INSERT_HEAD(&pci_host_bridges, host_bridge, next); 361 } 362 363 static void pci_host_bus_unregister(DeviceState *host) 364 { 365 PCIHostState *host_bridge = PCI_HOST_BRIDGE(host); 366 367 QLIST_REMOVE(host_bridge, next); 368 } 369 370 PCIBus *pci_device_root_bus(const PCIDevice *d) 371 { 372 PCIBus *bus = pci_get_bus(d); 373 374 while (!pci_bus_is_root(bus)) { 375 d = bus->parent_dev; 376 assert(d != NULL); 377 378 bus = pci_get_bus(d); 379 } 380 381 return bus; 382 } 383 384 const char *pci_root_bus_path(PCIDevice *dev) 385 { 386 PCIBus *rootbus = pci_device_root_bus(dev); 387 PCIHostState *host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent); 388 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_GET_CLASS(host_bridge); 389 390 assert(host_bridge->bus == rootbus); 391 392 if (hc->root_bus_path) { 393 return (*hc->root_bus_path)(host_bridge, rootbus); 394 } 395 396 return rootbus->qbus.name; 397 } 398 399 static void pci_root_bus_init(PCIBus *bus, DeviceState *parent, 400 MemoryRegion *address_space_mem, 401 MemoryRegion *address_space_io, 402 uint8_t devfn_min) 403 { 404 assert(PCI_FUNC(devfn_min) == 0); 405 bus->devfn_min = devfn_min; 406 bus->slot_reserved_mask = 0x0; 407 bus->address_space_mem = address_space_mem; 408 bus->address_space_io = address_space_io; 409 bus->flags |= PCI_BUS_IS_ROOT; 410 411 /* host bridge */ 412 QLIST_INIT(&bus->child); 413 414 pci_host_bus_register(parent); 415 } 416 417 static void pci_bus_uninit(PCIBus *bus) 418 { 419 pci_host_bus_unregister(BUS(bus)->parent); 420 } 421 422 bool pci_bus_is_express(PCIBus *bus) 423 { 424 return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS); 425 } 426 427 void pci_root_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent, 428 const char *name, 429 MemoryRegion *address_space_mem, 430 MemoryRegion *address_space_io, 431 uint8_t devfn_min, const char *typename) 432 { 433 qbus_create_inplace(bus, bus_size, typename, parent, name); 434 pci_root_bus_init(bus, parent, address_space_mem, address_space_io, 435 devfn_min); 436 } 437 438 PCIBus *pci_root_bus_new(DeviceState *parent, const char *name, 439 MemoryRegion *address_space_mem, 440 MemoryRegion *address_space_io, 441 uint8_t devfn_min, const char *typename) 442 { 443 PCIBus *bus; 444 445 bus = PCI_BUS(qbus_create(typename, parent, name)); 446 pci_root_bus_init(bus, parent, address_space_mem, address_space_io, 447 devfn_min); 448 return bus; 449 } 450 451 void pci_root_bus_cleanup(PCIBus *bus) 452 { 453 pci_bus_uninit(bus); 454 /* the caller of the unplug hotplug handler will delete this device */ 455 object_property_set_bool(OBJECT(bus), false, "realized", NULL); 456 } 457 458 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 459 void *irq_opaque, int nirq) 460 { 461 bus->set_irq = set_irq; 462 bus->map_irq = map_irq; 463 bus->irq_opaque = irq_opaque; 464 bus->nirq = nirq; 465 bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0])); 466 } 467 468 void pci_bus_irqs_cleanup(PCIBus *bus) 469 { 470 bus->set_irq = NULL; 471 bus->map_irq = NULL; 472 bus->irq_opaque = NULL; 473 bus->nirq = 0; 474 g_free(bus->irq_count); 475 } 476 477 PCIBus *pci_register_root_bus(DeviceState *parent, const char *name, 478 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 479 void *irq_opaque, 480 MemoryRegion *address_space_mem, 481 MemoryRegion *address_space_io, 482 uint8_t devfn_min, int nirq, 483 const char *typename) 484 { 485 PCIBus *bus; 486 487 bus = pci_root_bus_new(parent, name, address_space_mem, 488 address_space_io, devfn_min, typename); 489 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq); 490 return bus; 491 } 492 493 void pci_unregister_root_bus(PCIBus *bus) 494 { 495 pci_bus_irqs_cleanup(bus); 496 pci_root_bus_cleanup(bus); 497 } 498 499 int pci_bus_num(PCIBus *s) 500 { 501 return PCI_BUS_GET_CLASS(s)->bus_num(s); 502 } 503 504 int pci_bus_numa_node(PCIBus *bus) 505 { 506 return PCI_BUS_GET_CLASS(bus)->numa_node(bus); 507 } 508 509 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size, 510 const VMStateField *field) 511 { 512 PCIDevice *s = container_of(pv, PCIDevice, config); 513 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(s); 514 uint8_t *config; 515 int i; 516 517 assert(size == pci_config_size(s)); 518 config = g_malloc(size); 519 520 qemu_get_buffer(f, config, size); 521 for (i = 0; i < size; ++i) { 522 if ((config[i] ^ s->config[i]) & 523 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) { 524 error_report("%s: Bad config data: i=0x%x read: %x device: %x " 525 "cmask: %x wmask: %x w1cmask:%x", __func__, 526 i, config[i], s->config[i], 527 s->cmask[i], s->wmask[i], s->w1cmask[i]); 528 g_free(config); 529 return -EINVAL; 530 } 531 } 532 memcpy(s->config, config, size); 533 534 pci_update_mappings(s); 535 if (pc->is_bridge) { 536 PCIBridge *b = PCI_BRIDGE(s); 537 pci_bridge_update_mappings(b); 538 } 539 540 memory_region_set_enabled(&s->bus_master_enable_region, 541 pci_get_word(s->config + PCI_COMMAND) 542 & PCI_COMMAND_MASTER); 543 544 g_free(config); 545 return 0; 546 } 547 548 /* just put buffer */ 549 static int put_pci_config_device(QEMUFile *f, void *pv, size_t size, 550 const VMStateField *field, QJSON *vmdesc) 551 { 552 const uint8_t **v = pv; 553 assert(size == pci_config_size(container_of(pv, PCIDevice, config))); 554 qemu_put_buffer(f, *v, size); 555 556 return 0; 557 } 558 559 static VMStateInfo vmstate_info_pci_config = { 560 .name = "pci config", 561 .get = get_pci_config_device, 562 .put = put_pci_config_device, 563 }; 564 565 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size, 566 const VMStateField *field) 567 { 568 PCIDevice *s = container_of(pv, PCIDevice, irq_state); 569 uint32_t irq_state[PCI_NUM_PINS]; 570 int i; 571 for (i = 0; i < PCI_NUM_PINS; ++i) { 572 irq_state[i] = qemu_get_be32(f); 573 if (irq_state[i] != 0x1 && irq_state[i] != 0) { 574 fprintf(stderr, "irq state %d: must be 0 or 1.\n", 575 irq_state[i]); 576 return -EINVAL; 577 } 578 } 579 580 for (i = 0; i < PCI_NUM_PINS; ++i) { 581 pci_set_irq_state(s, i, irq_state[i]); 582 } 583 584 return 0; 585 } 586 587 static int put_pci_irq_state(QEMUFile *f, void *pv, size_t size, 588 const VMStateField *field, QJSON *vmdesc) 589 { 590 int i; 591 PCIDevice *s = container_of(pv, PCIDevice, irq_state); 592 593 for (i = 0; i < PCI_NUM_PINS; ++i) { 594 qemu_put_be32(f, pci_irq_state(s, i)); 595 } 596 597 return 0; 598 } 599 600 static VMStateInfo vmstate_info_pci_irq_state = { 601 .name = "pci irq state", 602 .get = get_pci_irq_state, 603 .put = put_pci_irq_state, 604 }; 605 606 static bool migrate_is_pcie(void *opaque, int version_id) 607 { 608 return pci_is_express((PCIDevice *)opaque); 609 } 610 611 static bool migrate_is_not_pcie(void *opaque, int version_id) 612 { 613 return !pci_is_express((PCIDevice *)opaque); 614 } 615 616 const VMStateDescription vmstate_pci_device = { 617 .name = "PCIDevice", 618 .version_id = 2, 619 .minimum_version_id = 1, 620 .fields = (VMStateField[]) { 621 VMSTATE_INT32_POSITIVE_LE(version_id, PCIDevice), 622 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice, 623 migrate_is_not_pcie, 624 0, vmstate_info_pci_config, 625 PCI_CONFIG_SPACE_SIZE), 626 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice, 627 migrate_is_pcie, 628 0, vmstate_info_pci_config, 629 PCIE_CONFIG_SPACE_SIZE), 630 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2, 631 vmstate_info_pci_irq_state, 632 PCI_NUM_PINS * sizeof(int32_t)), 633 VMSTATE_END_OF_LIST() 634 } 635 }; 636 637 638 void pci_device_save(PCIDevice *s, QEMUFile *f) 639 { 640 /* Clear interrupt status bit: it is implicit 641 * in irq_state which we are saving. 642 * This makes us compatible with old devices 643 * which never set or clear this bit. */ 644 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; 645 vmstate_save_state(f, &vmstate_pci_device, s, NULL); 646 /* Restore the interrupt status bit. */ 647 pci_update_irq_status(s); 648 } 649 650 int pci_device_load(PCIDevice *s, QEMUFile *f) 651 { 652 int ret; 653 ret = vmstate_load_state(f, &vmstate_pci_device, s, s->version_id); 654 /* Restore the interrupt status bit. */ 655 pci_update_irq_status(s); 656 return ret; 657 } 658 659 static void pci_set_default_subsystem_id(PCIDevice *pci_dev) 660 { 661 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, 662 pci_default_sub_vendor_id); 663 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 664 pci_default_sub_device_id); 665 } 666 667 /* 668 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL 669 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error 670 */ 671 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, 672 unsigned int *slotp, unsigned int *funcp) 673 { 674 const char *p; 675 char *e; 676 unsigned long val; 677 unsigned long dom = 0, bus = 0; 678 unsigned int slot = 0; 679 unsigned int func = 0; 680 681 p = addr; 682 val = strtoul(p, &e, 16); 683 if (e == p) 684 return -1; 685 if (*e == ':') { 686 bus = val; 687 p = e + 1; 688 val = strtoul(p, &e, 16); 689 if (e == p) 690 return -1; 691 if (*e == ':') { 692 dom = bus; 693 bus = val; 694 p = e + 1; 695 val = strtoul(p, &e, 16); 696 if (e == p) 697 return -1; 698 } 699 } 700 701 slot = val; 702 703 if (funcp != NULL) { 704 if (*e != '.') 705 return -1; 706 707 p = e + 1; 708 val = strtoul(p, &e, 16); 709 if (e == p) 710 return -1; 711 712 func = val; 713 } 714 715 /* if funcp == NULL func is 0 */ 716 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7) 717 return -1; 718 719 if (*e) 720 return -1; 721 722 *domp = dom; 723 *busp = bus; 724 *slotp = slot; 725 if (funcp != NULL) 726 *funcp = func; 727 return 0; 728 } 729 730 static void pci_init_cmask(PCIDevice *dev) 731 { 732 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff); 733 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff); 734 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST; 735 dev->cmask[PCI_REVISION_ID] = 0xff; 736 dev->cmask[PCI_CLASS_PROG] = 0xff; 737 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff); 738 dev->cmask[PCI_HEADER_TYPE] = 0xff; 739 dev->cmask[PCI_CAPABILITY_LIST] = 0xff; 740 } 741 742 static void pci_init_wmask(PCIDevice *dev) 743 { 744 int config_size = pci_config_size(dev); 745 746 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff; 747 dev->wmask[PCI_INTERRUPT_LINE] = 0xff; 748 pci_set_word(dev->wmask + PCI_COMMAND, 749 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | 750 PCI_COMMAND_INTX_DISABLE); 751 if (dev->cap_present & QEMU_PCI_CAP_SERR) { 752 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR); 753 } 754 755 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff, 756 config_size - PCI_CONFIG_HEADER_SIZE); 757 } 758 759 static void pci_init_w1cmask(PCIDevice *dev) 760 { 761 /* 762 * Note: It's okay to set w1cmask even for readonly bits as 763 * long as their value is hardwired to 0. 764 */ 765 pci_set_word(dev->w1cmask + PCI_STATUS, 766 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT | 767 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT | 768 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY); 769 } 770 771 static void pci_init_mask_bridge(PCIDevice *d) 772 { 773 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and 774 PCI_SEC_LETENCY_TIMER */ 775 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4); 776 777 /* base and limit */ 778 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff; 779 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff; 780 pci_set_word(d->wmask + PCI_MEMORY_BASE, 781 PCI_MEMORY_RANGE_MASK & 0xffff); 782 pci_set_word(d->wmask + PCI_MEMORY_LIMIT, 783 PCI_MEMORY_RANGE_MASK & 0xffff); 784 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE, 785 PCI_PREF_RANGE_MASK & 0xffff); 786 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT, 787 PCI_PREF_RANGE_MASK & 0xffff); 788 789 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */ 790 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8); 791 792 /* Supported memory and i/o types */ 793 d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16; 794 d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16; 795 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE, 796 PCI_PREF_RANGE_TYPE_64); 797 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT, 798 PCI_PREF_RANGE_TYPE_64); 799 800 /* 801 * TODO: Bridges default to 10-bit VGA decoding but we currently only 802 * implement 16-bit decoding (no alias support). 803 */ 804 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 805 PCI_BRIDGE_CTL_PARITY | 806 PCI_BRIDGE_CTL_SERR | 807 PCI_BRIDGE_CTL_ISA | 808 PCI_BRIDGE_CTL_VGA | 809 PCI_BRIDGE_CTL_VGA_16BIT | 810 PCI_BRIDGE_CTL_MASTER_ABORT | 811 PCI_BRIDGE_CTL_BUS_RESET | 812 PCI_BRIDGE_CTL_FAST_BACK | 813 PCI_BRIDGE_CTL_DISCARD | 814 PCI_BRIDGE_CTL_SEC_DISCARD | 815 PCI_BRIDGE_CTL_DISCARD_SERR); 816 /* Below does not do anything as we never set this bit, put here for 817 * completeness. */ 818 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL, 819 PCI_BRIDGE_CTL_DISCARD_STATUS); 820 d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK; 821 d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK; 822 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE, 823 PCI_PREF_RANGE_TYPE_MASK); 824 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT, 825 PCI_PREF_RANGE_TYPE_MASK); 826 } 827 828 static void pci_init_multifunction(PCIBus *bus, PCIDevice *dev, Error **errp) 829 { 830 uint8_t slot = PCI_SLOT(dev->devfn); 831 uint8_t func; 832 833 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 834 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION; 835 } 836 837 /* 838 * multifunction bit is interpreted in two ways as follows. 839 * - all functions must set the bit to 1. 840 * Example: Intel X53 841 * - function 0 must set the bit, but the rest function (> 0) 842 * is allowed to leave the bit to 0. 843 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10, 844 * 845 * So OS (at least Linux) checks the bit of only function 0, 846 * and doesn't see the bit of function > 0. 847 * 848 * The below check allows both interpretation. 849 */ 850 if (PCI_FUNC(dev->devfn)) { 851 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)]; 852 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) { 853 /* function 0 should set multifunction bit */ 854 error_setg(errp, "PCI: single function device can't be populated " 855 "in function %x.%x", slot, PCI_FUNC(dev->devfn)); 856 return; 857 } 858 return; 859 } 860 861 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 862 return; 863 } 864 /* function 0 indicates single function, so function > 0 must be NULL */ 865 for (func = 1; func < PCI_FUNC_MAX; ++func) { 866 if (bus->devices[PCI_DEVFN(slot, func)]) { 867 error_setg(errp, "PCI: %x.0 indicates single function, " 868 "but %x.%x is already populated.", 869 slot, slot, func); 870 return; 871 } 872 } 873 } 874 875 static void pci_config_alloc(PCIDevice *pci_dev) 876 { 877 int config_size = pci_config_size(pci_dev); 878 879 pci_dev->config = g_malloc0(config_size); 880 pci_dev->cmask = g_malloc0(config_size); 881 pci_dev->wmask = g_malloc0(config_size); 882 pci_dev->w1cmask = g_malloc0(config_size); 883 pci_dev->used = g_malloc0(config_size); 884 } 885 886 static void pci_config_free(PCIDevice *pci_dev) 887 { 888 g_free(pci_dev->config); 889 g_free(pci_dev->cmask); 890 g_free(pci_dev->wmask); 891 g_free(pci_dev->w1cmask); 892 g_free(pci_dev->used); 893 } 894 895 static void do_pci_unregister_device(PCIDevice *pci_dev) 896 { 897 pci_get_bus(pci_dev)->devices[pci_dev->devfn] = NULL; 898 pci_config_free(pci_dev); 899 900 if (memory_region_is_mapped(&pci_dev->bus_master_enable_region)) { 901 memory_region_del_subregion(&pci_dev->bus_master_container_region, 902 &pci_dev->bus_master_enable_region); 903 } 904 address_space_destroy(&pci_dev->bus_master_as); 905 } 906 907 /* Extract PCIReqIDCache into BDF format */ 908 static uint16_t pci_req_id_cache_extract(PCIReqIDCache *cache) 909 { 910 uint8_t bus_n; 911 uint16_t result; 912 913 switch (cache->type) { 914 case PCI_REQ_ID_BDF: 915 result = pci_get_bdf(cache->dev); 916 break; 917 case PCI_REQ_ID_SECONDARY_BUS: 918 bus_n = pci_dev_bus_num(cache->dev); 919 result = PCI_BUILD_BDF(bus_n, 0); 920 break; 921 default: 922 error_report("Invalid PCI requester ID cache type: %d", 923 cache->type); 924 exit(1); 925 break; 926 } 927 928 return result; 929 } 930 931 /* Parse bridges up to the root complex and return requester ID 932 * cache for specific device. For full PCIe topology, the cache 933 * result would be exactly the same as getting BDF of the device. 934 * However, several tricks are required when system mixed up with 935 * legacy PCI devices and PCIe-to-PCI bridges. 936 * 937 * Here we cache the proxy device (and type) not requester ID since 938 * bus number might change from time to time. 939 */ 940 static PCIReqIDCache pci_req_id_cache_get(PCIDevice *dev) 941 { 942 PCIDevice *parent; 943 PCIReqIDCache cache = { 944 .dev = dev, 945 .type = PCI_REQ_ID_BDF, 946 }; 947 948 while (!pci_bus_is_root(pci_get_bus(dev))) { 949 /* We are under PCI/PCIe bridges */ 950 parent = pci_get_bus(dev)->parent_dev; 951 if (pci_is_express(parent)) { 952 if (pcie_cap_get_type(parent) == PCI_EXP_TYPE_PCI_BRIDGE) { 953 /* When we pass through PCIe-to-PCI/PCIX bridges, we 954 * override the requester ID using secondary bus 955 * number of parent bridge with zeroed devfn 956 * (pcie-to-pci bridge spec chap 2.3). */ 957 cache.type = PCI_REQ_ID_SECONDARY_BUS; 958 cache.dev = dev; 959 } 960 } else { 961 /* Legacy PCI, override requester ID with the bridge's 962 * BDF upstream. When the root complex connects to 963 * legacy PCI devices (including buses), it can only 964 * obtain requester ID info from directly attached 965 * devices. If devices are attached under bridges, only 966 * the requester ID of the bridge that is directly 967 * attached to the root complex can be recognized. */ 968 cache.type = PCI_REQ_ID_BDF; 969 cache.dev = parent; 970 } 971 dev = parent; 972 } 973 974 return cache; 975 } 976 977 uint16_t pci_requester_id(PCIDevice *dev) 978 { 979 return pci_req_id_cache_extract(&dev->requester_id_cache); 980 } 981 982 static bool pci_bus_devfn_available(PCIBus *bus, int devfn) 983 { 984 return !(bus->devices[devfn]); 985 } 986 987 static bool pci_bus_devfn_reserved(PCIBus *bus, int devfn) 988 { 989 return bus->slot_reserved_mask & (1UL << PCI_SLOT(devfn)); 990 } 991 992 /* -1 for devfn means auto assign */ 993 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, 994 const char *name, int devfn, 995 Error **errp) 996 { 997 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 998 PCIConfigReadFunc *config_read = pc->config_read; 999 PCIConfigWriteFunc *config_write = pc->config_write; 1000 Error *local_err = NULL; 1001 DeviceState *dev = DEVICE(pci_dev); 1002 PCIBus *bus = pci_get_bus(pci_dev); 1003 1004 /* Only pci bridges can be attached to extra PCI root buses */ 1005 if (pci_bus_is_root(bus) && bus->parent_dev && !pc->is_bridge) { 1006 error_setg(errp, 1007 "PCI: Only PCI/PCIe bridges can be plugged into %s", 1008 bus->parent_dev->name); 1009 return NULL; 1010 } 1011 1012 if (devfn < 0) { 1013 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices); 1014 devfn += PCI_FUNC_MAX) { 1015 if (pci_bus_devfn_available(bus, devfn) && 1016 !pci_bus_devfn_reserved(bus, devfn)) { 1017 goto found; 1018 } 1019 } 1020 error_setg(errp, "PCI: no slot/function available for %s, all in use " 1021 "or reserved", name); 1022 return NULL; 1023 found: ; 1024 } else if (pci_bus_devfn_reserved(bus, devfn)) { 1025 error_setg(errp, "PCI: slot %d function %d not available for %s," 1026 " reserved", 1027 PCI_SLOT(devfn), PCI_FUNC(devfn), name); 1028 return NULL; 1029 } else if (!pci_bus_devfn_available(bus, devfn)) { 1030 error_setg(errp, "PCI: slot %d function %d not available for %s," 1031 " in use by %s", 1032 PCI_SLOT(devfn), PCI_FUNC(devfn), name, 1033 bus->devices[devfn]->name); 1034 return NULL; 1035 } else if (dev->hotplugged && 1036 pci_get_function_0(pci_dev)) { 1037 error_setg(errp, "PCI: slot %d function 0 already ocuppied by %s," 1038 " new func %s cannot be exposed to guest.", 1039 PCI_SLOT(pci_get_function_0(pci_dev)->devfn), 1040 pci_get_function_0(pci_dev)->name, 1041 name); 1042 1043 return NULL; 1044 } 1045 1046 pci_dev->devfn = devfn; 1047 pci_dev->requester_id_cache = pci_req_id_cache_get(pci_dev); 1048 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name); 1049 1050 memory_region_init(&pci_dev->bus_master_container_region, OBJECT(pci_dev), 1051 "bus master container", UINT64_MAX); 1052 address_space_init(&pci_dev->bus_master_as, 1053 &pci_dev->bus_master_container_region, pci_dev->name); 1054 1055 if (qdev_hotplug) { 1056 pci_init_bus_master(pci_dev); 1057 } 1058 pci_dev->irq_state = 0; 1059 pci_config_alloc(pci_dev); 1060 1061 pci_config_set_vendor_id(pci_dev->config, pc->vendor_id); 1062 pci_config_set_device_id(pci_dev->config, pc->device_id); 1063 pci_config_set_revision(pci_dev->config, pc->revision); 1064 pci_config_set_class(pci_dev->config, pc->class_id); 1065 1066 if (!pc->is_bridge) { 1067 if (pc->subsystem_vendor_id || pc->subsystem_id) { 1068 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, 1069 pc->subsystem_vendor_id); 1070 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 1071 pc->subsystem_id); 1072 } else { 1073 pci_set_default_subsystem_id(pci_dev); 1074 } 1075 } else { 1076 /* subsystem_vendor_id/subsystem_id are only for header type 0 */ 1077 assert(!pc->subsystem_vendor_id); 1078 assert(!pc->subsystem_id); 1079 } 1080 pci_init_cmask(pci_dev); 1081 pci_init_wmask(pci_dev); 1082 pci_init_w1cmask(pci_dev); 1083 if (pc->is_bridge) { 1084 pci_init_mask_bridge(pci_dev); 1085 } 1086 pci_init_multifunction(bus, pci_dev, &local_err); 1087 if (local_err) { 1088 error_propagate(errp, local_err); 1089 do_pci_unregister_device(pci_dev); 1090 return NULL; 1091 } 1092 1093 if (!config_read) 1094 config_read = pci_default_read_config; 1095 if (!config_write) 1096 config_write = pci_default_write_config; 1097 pci_dev->config_read = config_read; 1098 pci_dev->config_write = config_write; 1099 bus->devices[devfn] = pci_dev; 1100 pci_dev->version_id = 2; /* Current pci device vmstate version */ 1101 return pci_dev; 1102 } 1103 1104 static void pci_unregister_io_regions(PCIDevice *pci_dev) 1105 { 1106 PCIIORegion *r; 1107 int i; 1108 1109 for(i = 0; i < PCI_NUM_REGIONS; i++) { 1110 r = &pci_dev->io_regions[i]; 1111 if (!r->size || r->addr == PCI_BAR_UNMAPPED) 1112 continue; 1113 memory_region_del_subregion(r->address_space, r->memory); 1114 } 1115 1116 pci_unregister_vga(pci_dev); 1117 } 1118 1119 static void pci_qdev_unrealize(DeviceState *dev, Error **errp) 1120 { 1121 PCIDevice *pci_dev = PCI_DEVICE(dev); 1122 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 1123 1124 pci_unregister_io_regions(pci_dev); 1125 pci_del_option_rom(pci_dev); 1126 1127 if (pc->exit) { 1128 pc->exit(pci_dev); 1129 } 1130 1131 pci_device_deassert_intx(pci_dev); 1132 do_pci_unregister_device(pci_dev); 1133 } 1134 1135 void pci_register_bar(PCIDevice *pci_dev, int region_num, 1136 uint8_t type, MemoryRegion *memory) 1137 { 1138 PCIIORegion *r; 1139 uint32_t addr; /* offset in pci config space */ 1140 uint64_t wmask; 1141 pcibus_t size = memory_region_size(memory); 1142 1143 assert(region_num >= 0); 1144 assert(region_num < PCI_NUM_REGIONS); 1145 if (size & (size-1)) { 1146 error_report("ERROR: PCI region size must be pow2 " 1147 "type=0x%x, size=0x%"FMT_PCIBUS"", type, size); 1148 exit(1); 1149 } 1150 1151 r = &pci_dev->io_regions[region_num]; 1152 r->addr = PCI_BAR_UNMAPPED; 1153 r->size = size; 1154 r->type = type; 1155 r->memory = memory; 1156 r->address_space = type & PCI_BASE_ADDRESS_SPACE_IO 1157 ? pci_get_bus(pci_dev)->address_space_io 1158 : pci_get_bus(pci_dev)->address_space_mem; 1159 1160 wmask = ~(size - 1); 1161 if (region_num == PCI_ROM_SLOT) { 1162 /* ROM enable bit is writable */ 1163 wmask |= PCI_ROM_ADDRESS_ENABLE; 1164 } 1165 1166 addr = pci_bar(pci_dev, region_num); 1167 pci_set_long(pci_dev->config + addr, type); 1168 1169 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) && 1170 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 1171 pci_set_quad(pci_dev->wmask + addr, wmask); 1172 pci_set_quad(pci_dev->cmask + addr, ~0ULL); 1173 } else { 1174 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff); 1175 pci_set_long(pci_dev->cmask + addr, 0xffffffff); 1176 } 1177 } 1178 1179 static void pci_update_vga(PCIDevice *pci_dev) 1180 { 1181 uint16_t cmd; 1182 1183 if (!pci_dev->has_vga) { 1184 return; 1185 } 1186 1187 cmd = pci_get_word(pci_dev->config + PCI_COMMAND); 1188 1189 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_MEM], 1190 cmd & PCI_COMMAND_MEMORY); 1191 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO], 1192 cmd & PCI_COMMAND_IO); 1193 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI], 1194 cmd & PCI_COMMAND_IO); 1195 } 1196 1197 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, 1198 MemoryRegion *io_lo, MemoryRegion *io_hi) 1199 { 1200 PCIBus *bus = pci_get_bus(pci_dev); 1201 1202 assert(!pci_dev->has_vga); 1203 1204 assert(memory_region_size(mem) == QEMU_PCI_VGA_MEM_SIZE); 1205 pci_dev->vga_regions[QEMU_PCI_VGA_MEM] = mem; 1206 memory_region_add_subregion_overlap(bus->address_space_mem, 1207 QEMU_PCI_VGA_MEM_BASE, mem, 1); 1208 1209 assert(memory_region_size(io_lo) == QEMU_PCI_VGA_IO_LO_SIZE); 1210 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO] = io_lo; 1211 memory_region_add_subregion_overlap(bus->address_space_io, 1212 QEMU_PCI_VGA_IO_LO_BASE, io_lo, 1); 1213 1214 assert(memory_region_size(io_hi) == QEMU_PCI_VGA_IO_HI_SIZE); 1215 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI] = io_hi; 1216 memory_region_add_subregion_overlap(bus->address_space_io, 1217 QEMU_PCI_VGA_IO_HI_BASE, io_hi, 1); 1218 pci_dev->has_vga = true; 1219 1220 pci_update_vga(pci_dev); 1221 } 1222 1223 void pci_unregister_vga(PCIDevice *pci_dev) 1224 { 1225 PCIBus *bus = pci_get_bus(pci_dev); 1226 1227 if (!pci_dev->has_vga) { 1228 return; 1229 } 1230 1231 memory_region_del_subregion(bus->address_space_mem, 1232 pci_dev->vga_regions[QEMU_PCI_VGA_MEM]); 1233 memory_region_del_subregion(bus->address_space_io, 1234 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO]); 1235 memory_region_del_subregion(bus->address_space_io, 1236 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI]); 1237 pci_dev->has_vga = false; 1238 } 1239 1240 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num) 1241 { 1242 return pci_dev->io_regions[region_num].addr; 1243 } 1244 1245 static pcibus_t pci_bar_address(PCIDevice *d, 1246 int reg, uint8_t type, pcibus_t size) 1247 { 1248 pcibus_t new_addr, last_addr; 1249 int bar = pci_bar(d, reg); 1250 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND); 1251 Object *machine = qdev_get_machine(); 1252 ObjectClass *oc = object_get_class(machine); 1253 MachineClass *mc = MACHINE_CLASS(oc); 1254 bool allow_0_address = mc->pci_allow_0_address; 1255 1256 if (type & PCI_BASE_ADDRESS_SPACE_IO) { 1257 if (!(cmd & PCI_COMMAND_IO)) { 1258 return PCI_BAR_UNMAPPED; 1259 } 1260 new_addr = pci_get_long(d->config + bar) & ~(size - 1); 1261 last_addr = new_addr + size - 1; 1262 /* Check if 32 bit BAR wraps around explicitly. 1263 * TODO: make priorities correct and remove this work around. 1264 */ 1265 if (last_addr <= new_addr || last_addr >= UINT32_MAX || 1266 (!allow_0_address && new_addr == 0)) { 1267 return PCI_BAR_UNMAPPED; 1268 } 1269 return new_addr; 1270 } 1271 1272 if (!(cmd & PCI_COMMAND_MEMORY)) { 1273 return PCI_BAR_UNMAPPED; 1274 } 1275 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 1276 new_addr = pci_get_quad(d->config + bar); 1277 } else { 1278 new_addr = pci_get_long(d->config + bar); 1279 } 1280 /* the ROM slot has a specific enable bit */ 1281 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) { 1282 return PCI_BAR_UNMAPPED; 1283 } 1284 new_addr &= ~(size - 1); 1285 last_addr = new_addr + size - 1; 1286 /* NOTE: we do not support wrapping */ 1287 /* XXX: as we cannot support really dynamic 1288 mappings, we handle specific values as invalid 1289 mappings. */ 1290 if (last_addr <= new_addr || last_addr == PCI_BAR_UNMAPPED || 1291 (!allow_0_address && new_addr == 0)) { 1292 return PCI_BAR_UNMAPPED; 1293 } 1294 1295 /* Now pcibus_t is 64bit. 1296 * Check if 32 bit BAR wraps around explicitly. 1297 * Without this, PC ide doesn't work well. 1298 * TODO: remove this work around. 1299 */ 1300 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) { 1301 return PCI_BAR_UNMAPPED; 1302 } 1303 1304 /* 1305 * OS is allowed to set BAR beyond its addressable 1306 * bits. For example, 32 bit OS can set 64bit bar 1307 * to >4G. Check it. TODO: we might need to support 1308 * it in the future for e.g. PAE. 1309 */ 1310 if (last_addr >= HWADDR_MAX) { 1311 return PCI_BAR_UNMAPPED; 1312 } 1313 1314 return new_addr; 1315 } 1316 1317 static void pci_update_mappings(PCIDevice *d) 1318 { 1319 PCIIORegion *r; 1320 int i; 1321 pcibus_t new_addr; 1322 1323 for(i = 0; i < PCI_NUM_REGIONS; i++) { 1324 r = &d->io_regions[i]; 1325 1326 /* this region isn't registered */ 1327 if (!r->size) 1328 continue; 1329 1330 new_addr = pci_bar_address(d, i, r->type, r->size); 1331 1332 /* This bar isn't changed */ 1333 if (new_addr == r->addr) 1334 continue; 1335 1336 /* now do the real mapping */ 1337 if (r->addr != PCI_BAR_UNMAPPED) { 1338 trace_pci_update_mappings_del(d, pci_dev_bus_num(d), 1339 PCI_SLOT(d->devfn), 1340 PCI_FUNC(d->devfn), 1341 i, r->addr, r->size); 1342 memory_region_del_subregion(r->address_space, r->memory); 1343 } 1344 r->addr = new_addr; 1345 if (r->addr != PCI_BAR_UNMAPPED) { 1346 trace_pci_update_mappings_add(d, pci_dev_bus_num(d), 1347 PCI_SLOT(d->devfn), 1348 PCI_FUNC(d->devfn), 1349 i, r->addr, r->size); 1350 memory_region_add_subregion_overlap(r->address_space, 1351 r->addr, r->memory, 1); 1352 } 1353 } 1354 1355 pci_update_vga(d); 1356 } 1357 1358 static inline int pci_irq_disabled(PCIDevice *d) 1359 { 1360 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE; 1361 } 1362 1363 /* Called after interrupt disabled field update in config space, 1364 * assert/deassert interrupts if necessary. 1365 * Gets original interrupt disable bit value (before update). */ 1366 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled) 1367 { 1368 int i, disabled = pci_irq_disabled(d); 1369 if (disabled == was_irq_disabled) 1370 return; 1371 for (i = 0; i < PCI_NUM_PINS; ++i) { 1372 int state = pci_irq_state(d, i); 1373 pci_change_irq_level(d, i, disabled ? -state : state); 1374 } 1375 } 1376 1377 uint32_t pci_default_read_config(PCIDevice *d, 1378 uint32_t address, int len) 1379 { 1380 uint32_t val = 0; 1381 1382 if (pci_is_express_downstream_port(d) && 1383 ranges_overlap(address, len, d->exp.exp_cap + PCI_EXP_LNKSTA, 2)) { 1384 pcie_sync_bridge_lnk(d); 1385 } 1386 memcpy(&val, d->config + address, len); 1387 return le32_to_cpu(val); 1388 } 1389 1390 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val_in, int l) 1391 { 1392 int i, was_irq_disabled = pci_irq_disabled(d); 1393 uint32_t val = val_in; 1394 1395 for (i = 0; i < l; val >>= 8, ++i) { 1396 uint8_t wmask = d->wmask[addr + i]; 1397 uint8_t w1cmask = d->w1cmask[addr + i]; 1398 assert(!(wmask & w1cmask)); 1399 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask); 1400 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */ 1401 } 1402 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) || 1403 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) || 1404 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) || 1405 range_covers_byte(addr, l, PCI_COMMAND)) 1406 pci_update_mappings(d); 1407 1408 if (range_covers_byte(addr, l, PCI_COMMAND)) { 1409 pci_update_irq_disabled(d, was_irq_disabled); 1410 memory_region_set_enabled(&d->bus_master_enable_region, 1411 pci_get_word(d->config + PCI_COMMAND) 1412 & PCI_COMMAND_MASTER); 1413 } 1414 1415 msi_write_config(d, addr, val_in, l); 1416 msix_write_config(d, addr, val_in, l); 1417 } 1418 1419 /***********************************************************/ 1420 /* generic PCI irq support */ 1421 1422 /* 0 <= irq_num <= 3. level must be 0 or 1 */ 1423 static void pci_irq_handler(void *opaque, int irq_num, int level) 1424 { 1425 PCIDevice *pci_dev = opaque; 1426 int change; 1427 1428 change = level - pci_irq_state(pci_dev, irq_num); 1429 if (!change) 1430 return; 1431 1432 pci_set_irq_state(pci_dev, irq_num, level); 1433 pci_update_irq_status(pci_dev); 1434 if (pci_irq_disabled(pci_dev)) 1435 return; 1436 pci_change_irq_level(pci_dev, irq_num, change); 1437 } 1438 1439 static inline int pci_intx(PCIDevice *pci_dev) 1440 { 1441 return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1; 1442 } 1443 1444 qemu_irq pci_allocate_irq(PCIDevice *pci_dev) 1445 { 1446 int intx = pci_intx(pci_dev); 1447 1448 return qemu_allocate_irq(pci_irq_handler, pci_dev, intx); 1449 } 1450 1451 void pci_set_irq(PCIDevice *pci_dev, int level) 1452 { 1453 int intx = pci_intx(pci_dev); 1454 pci_irq_handler(pci_dev, intx, level); 1455 } 1456 1457 /* Special hooks used by device assignment */ 1458 void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq) 1459 { 1460 assert(pci_bus_is_root(bus)); 1461 bus->route_intx_to_irq = route_intx_to_irq; 1462 } 1463 1464 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin) 1465 { 1466 PCIBus *bus; 1467 1468 do { 1469 bus = pci_get_bus(dev); 1470 pin = bus->map_irq(dev, pin); 1471 dev = bus->parent_dev; 1472 } while (dev); 1473 1474 if (!bus->route_intx_to_irq) { 1475 error_report("PCI: Bug - unimplemented PCI INTx routing (%s)", 1476 object_get_typename(OBJECT(bus->qbus.parent))); 1477 return (PCIINTxRoute) { PCI_INTX_DISABLED, -1 }; 1478 } 1479 1480 return bus->route_intx_to_irq(bus->irq_opaque, pin); 1481 } 1482 1483 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new) 1484 { 1485 return old->mode != new->mode || old->irq != new->irq; 1486 } 1487 1488 void pci_bus_fire_intx_routing_notifier(PCIBus *bus) 1489 { 1490 PCIDevice *dev; 1491 PCIBus *sec; 1492 int i; 1493 1494 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 1495 dev = bus->devices[i]; 1496 if (dev && dev->intx_routing_notifier) { 1497 dev->intx_routing_notifier(dev); 1498 } 1499 } 1500 1501 QLIST_FOREACH(sec, &bus->child, sibling) { 1502 pci_bus_fire_intx_routing_notifier(sec); 1503 } 1504 } 1505 1506 void pci_device_set_intx_routing_notifier(PCIDevice *dev, 1507 PCIINTxRoutingNotifier notifier) 1508 { 1509 dev->intx_routing_notifier = notifier; 1510 } 1511 1512 /* 1513 * PCI-to-PCI bridge specification 1514 * 9.1: Interrupt routing. Table 9-1 1515 * 1516 * the PCI Express Base Specification, Revision 2.1 1517 * 2.2.8.1: INTx interrutp signaling - Rules 1518 * the Implementation Note 1519 * Table 2-20 1520 */ 1521 /* 1522 * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD 1523 * 0-origin unlike PCI interrupt pin register. 1524 */ 1525 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin) 1526 { 1527 return pci_swizzle(PCI_SLOT(pci_dev->devfn), pin); 1528 } 1529 1530 /***********************************************************/ 1531 /* monitor info on PCI */ 1532 1533 typedef struct { 1534 uint16_t class; 1535 const char *desc; 1536 const char *fw_name; 1537 uint16_t fw_ign_bits; 1538 } pci_class_desc; 1539 1540 static const pci_class_desc pci_class_descriptions[] = 1541 { 1542 { 0x0001, "VGA controller", "display"}, 1543 { 0x0100, "SCSI controller", "scsi"}, 1544 { 0x0101, "IDE controller", "ide"}, 1545 { 0x0102, "Floppy controller", "fdc"}, 1546 { 0x0103, "IPI controller", "ipi"}, 1547 { 0x0104, "RAID controller", "raid"}, 1548 { 0x0106, "SATA controller"}, 1549 { 0x0107, "SAS controller"}, 1550 { 0x0180, "Storage controller"}, 1551 { 0x0200, "Ethernet controller", "ethernet"}, 1552 { 0x0201, "Token Ring controller", "token-ring"}, 1553 { 0x0202, "FDDI controller", "fddi"}, 1554 { 0x0203, "ATM controller", "atm"}, 1555 { 0x0280, "Network controller"}, 1556 { 0x0300, "VGA controller", "display", 0x00ff}, 1557 { 0x0301, "XGA controller"}, 1558 { 0x0302, "3D controller"}, 1559 { 0x0380, "Display controller"}, 1560 { 0x0400, "Video controller", "video"}, 1561 { 0x0401, "Audio controller", "sound"}, 1562 { 0x0402, "Phone"}, 1563 { 0x0403, "Audio controller", "sound"}, 1564 { 0x0480, "Multimedia controller"}, 1565 { 0x0500, "RAM controller", "memory"}, 1566 { 0x0501, "Flash controller", "flash"}, 1567 { 0x0580, "Memory controller"}, 1568 { 0x0600, "Host bridge", "host"}, 1569 { 0x0601, "ISA bridge", "isa"}, 1570 { 0x0602, "EISA bridge", "eisa"}, 1571 { 0x0603, "MC bridge", "mca"}, 1572 { 0x0604, "PCI bridge", "pci-bridge"}, 1573 { 0x0605, "PCMCIA bridge", "pcmcia"}, 1574 { 0x0606, "NUBUS bridge", "nubus"}, 1575 { 0x0607, "CARDBUS bridge", "cardbus"}, 1576 { 0x0608, "RACEWAY bridge"}, 1577 { 0x0680, "Bridge"}, 1578 { 0x0700, "Serial port", "serial"}, 1579 { 0x0701, "Parallel port", "parallel"}, 1580 { 0x0800, "Interrupt controller", "interrupt-controller"}, 1581 { 0x0801, "DMA controller", "dma-controller"}, 1582 { 0x0802, "Timer", "timer"}, 1583 { 0x0803, "RTC", "rtc"}, 1584 { 0x0900, "Keyboard", "keyboard"}, 1585 { 0x0901, "Pen", "pen"}, 1586 { 0x0902, "Mouse", "mouse"}, 1587 { 0x0A00, "Dock station", "dock", 0x00ff}, 1588 { 0x0B00, "i386 cpu", "cpu", 0x00ff}, 1589 { 0x0c00, "Fireware contorller", "fireware"}, 1590 { 0x0c01, "Access bus controller", "access-bus"}, 1591 { 0x0c02, "SSA controller", "ssa"}, 1592 { 0x0c03, "USB controller", "usb"}, 1593 { 0x0c04, "Fibre channel controller", "fibre-channel"}, 1594 { 0x0c05, "SMBus"}, 1595 { 0, NULL} 1596 }; 1597 1598 static void pci_for_each_device_under_bus_reverse(PCIBus *bus, 1599 void (*fn)(PCIBus *b, 1600 PCIDevice *d, 1601 void *opaque), 1602 void *opaque) 1603 { 1604 PCIDevice *d; 1605 int devfn; 1606 1607 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1608 d = bus->devices[ARRAY_SIZE(bus->devices) - 1 - devfn]; 1609 if (d) { 1610 fn(bus, d, opaque); 1611 } 1612 } 1613 } 1614 1615 void pci_for_each_device_reverse(PCIBus *bus, int bus_num, 1616 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque), 1617 void *opaque) 1618 { 1619 bus = pci_find_bus_nr(bus, bus_num); 1620 1621 if (bus) { 1622 pci_for_each_device_under_bus_reverse(bus, fn, opaque); 1623 } 1624 } 1625 1626 static void pci_for_each_device_under_bus(PCIBus *bus, 1627 void (*fn)(PCIBus *b, PCIDevice *d, 1628 void *opaque), 1629 void *opaque) 1630 { 1631 PCIDevice *d; 1632 int devfn; 1633 1634 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1635 d = bus->devices[devfn]; 1636 if (d) { 1637 fn(bus, d, opaque); 1638 } 1639 } 1640 } 1641 1642 void pci_for_each_device(PCIBus *bus, int bus_num, 1643 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque), 1644 void *opaque) 1645 { 1646 bus = pci_find_bus_nr(bus, bus_num); 1647 1648 if (bus) { 1649 pci_for_each_device_under_bus(bus, fn, opaque); 1650 } 1651 } 1652 1653 static const pci_class_desc *get_class_desc(int class) 1654 { 1655 const pci_class_desc *desc; 1656 1657 desc = pci_class_descriptions; 1658 while (desc->desc && class != desc->class) { 1659 desc++; 1660 } 1661 1662 return desc; 1663 } 1664 1665 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num); 1666 1667 static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev) 1668 { 1669 PciMemoryRegionList *head = NULL, *cur_item = NULL; 1670 int i; 1671 1672 for (i = 0; i < PCI_NUM_REGIONS; i++) { 1673 const PCIIORegion *r = &dev->io_regions[i]; 1674 PciMemoryRegionList *region; 1675 1676 if (!r->size) { 1677 continue; 1678 } 1679 1680 region = g_malloc0(sizeof(*region)); 1681 region->value = g_malloc0(sizeof(*region->value)); 1682 1683 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { 1684 region->value->type = g_strdup("io"); 1685 } else { 1686 region->value->type = g_strdup("memory"); 1687 region->value->has_prefetch = true; 1688 region->value->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH); 1689 region->value->has_mem_type_64 = true; 1690 region->value->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64); 1691 } 1692 1693 region->value->bar = i; 1694 region->value->address = r->addr; 1695 region->value->size = r->size; 1696 1697 /* XXX: waiting for the qapi to support GSList */ 1698 if (!cur_item) { 1699 head = cur_item = region; 1700 } else { 1701 cur_item->next = region; 1702 cur_item = region; 1703 } 1704 } 1705 1706 return head; 1707 } 1708 1709 static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus, 1710 int bus_num) 1711 { 1712 PciBridgeInfo *info; 1713 PciMemoryRange *range; 1714 1715 info = g_new0(PciBridgeInfo, 1); 1716 1717 info->bus = g_new0(PciBusInfo, 1); 1718 info->bus->number = dev->config[PCI_PRIMARY_BUS]; 1719 info->bus->secondary = dev->config[PCI_SECONDARY_BUS]; 1720 info->bus->subordinate = dev->config[PCI_SUBORDINATE_BUS]; 1721 1722 range = info->bus->io_range = g_new0(PciMemoryRange, 1); 1723 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO); 1724 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO); 1725 1726 range = info->bus->memory_range = g_new0(PciMemoryRange, 1); 1727 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 1728 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 1729 1730 range = info->bus->prefetchable_range = g_new0(PciMemoryRange, 1); 1731 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 1732 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 1733 1734 if (dev->config[PCI_SECONDARY_BUS] != 0) { 1735 PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]); 1736 if (child_bus) { 1737 info->has_devices = true; 1738 info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]); 1739 } 1740 } 1741 1742 return info; 1743 } 1744 1745 static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus, 1746 int bus_num) 1747 { 1748 const pci_class_desc *desc; 1749 PciDeviceInfo *info; 1750 uint8_t type; 1751 int class; 1752 1753 info = g_new0(PciDeviceInfo, 1); 1754 info->bus = bus_num; 1755 info->slot = PCI_SLOT(dev->devfn); 1756 info->function = PCI_FUNC(dev->devfn); 1757 1758 info->class_info = g_new0(PciDeviceClass, 1); 1759 class = pci_get_word(dev->config + PCI_CLASS_DEVICE); 1760 info->class_info->q_class = class; 1761 desc = get_class_desc(class); 1762 if (desc->desc) { 1763 info->class_info->has_desc = true; 1764 info->class_info->desc = g_strdup(desc->desc); 1765 } 1766 1767 info->id = g_new0(PciDeviceId, 1); 1768 info->id->vendor = pci_get_word(dev->config + PCI_VENDOR_ID); 1769 info->id->device = pci_get_word(dev->config + PCI_DEVICE_ID); 1770 info->regions = qmp_query_pci_regions(dev); 1771 info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : ""); 1772 1773 if (dev->config[PCI_INTERRUPT_PIN] != 0) { 1774 info->has_irq = true; 1775 info->irq = dev->config[PCI_INTERRUPT_LINE]; 1776 } 1777 1778 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 1779 if (type == PCI_HEADER_TYPE_BRIDGE) { 1780 info->has_pci_bridge = true; 1781 info->pci_bridge = qmp_query_pci_bridge(dev, bus, bus_num); 1782 } else if (type == PCI_HEADER_TYPE_NORMAL) { 1783 info->id->has_subsystem = info->id->has_subsystem_vendor = true; 1784 info->id->subsystem = pci_get_word(dev->config + PCI_SUBSYSTEM_ID); 1785 info->id->subsystem_vendor = 1786 pci_get_word(dev->config + PCI_SUBSYSTEM_VENDOR_ID); 1787 } else if (type == PCI_HEADER_TYPE_CARDBUS) { 1788 info->id->has_subsystem = info->id->has_subsystem_vendor = true; 1789 info->id->subsystem = pci_get_word(dev->config + PCI_CB_SUBSYSTEM_ID); 1790 info->id->subsystem_vendor = 1791 pci_get_word(dev->config + PCI_CB_SUBSYSTEM_VENDOR_ID); 1792 } 1793 1794 return info; 1795 } 1796 1797 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num) 1798 { 1799 PciDeviceInfoList *info, *head = NULL, *cur_item = NULL; 1800 PCIDevice *dev; 1801 int devfn; 1802 1803 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1804 dev = bus->devices[devfn]; 1805 if (dev) { 1806 info = g_malloc0(sizeof(*info)); 1807 info->value = qmp_query_pci_device(dev, bus, bus_num); 1808 1809 /* XXX: waiting for the qapi to support GSList */ 1810 if (!cur_item) { 1811 head = cur_item = info; 1812 } else { 1813 cur_item->next = info; 1814 cur_item = info; 1815 } 1816 } 1817 } 1818 1819 return head; 1820 } 1821 1822 static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num) 1823 { 1824 PciInfo *info = NULL; 1825 1826 bus = pci_find_bus_nr(bus, bus_num); 1827 if (bus) { 1828 info = g_malloc0(sizeof(*info)); 1829 info->bus = bus_num; 1830 info->devices = qmp_query_pci_devices(bus, bus_num); 1831 } 1832 1833 return info; 1834 } 1835 1836 PciInfoList *qmp_query_pci(Error **errp) 1837 { 1838 PciInfoList *info, *head = NULL, *cur_item = NULL; 1839 PCIHostState *host_bridge; 1840 1841 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { 1842 info = g_malloc0(sizeof(*info)); 1843 info->value = qmp_query_pci_bus(host_bridge->bus, 1844 pci_bus_num(host_bridge->bus)); 1845 1846 /* XXX: waiting for the qapi to support GSList */ 1847 if (!cur_item) { 1848 head = cur_item = info; 1849 } else { 1850 cur_item->next = info; 1851 cur_item = info; 1852 } 1853 } 1854 1855 return head; 1856 } 1857 1858 /* Initialize a PCI NIC. */ 1859 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus, 1860 const char *default_model, 1861 const char *default_devaddr) 1862 { 1863 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr; 1864 GSList *list; 1865 GPtrArray *pci_nic_models; 1866 PCIBus *bus; 1867 PCIDevice *pci_dev; 1868 DeviceState *dev; 1869 int devfn; 1870 int i; 1871 int dom, busnr; 1872 unsigned slot; 1873 1874 if (nd->model && !strcmp(nd->model, "virtio")) { 1875 g_free(nd->model); 1876 nd->model = g_strdup("virtio-net-pci"); 1877 } 1878 1879 list = object_class_get_list_sorted(TYPE_PCI_DEVICE, false); 1880 pci_nic_models = g_ptr_array_new(); 1881 while (list) { 1882 DeviceClass *dc = OBJECT_CLASS_CHECK(DeviceClass, list->data, 1883 TYPE_DEVICE); 1884 GSList *next; 1885 if (test_bit(DEVICE_CATEGORY_NETWORK, dc->categories) && 1886 dc->user_creatable) { 1887 const char *name = object_class_get_name(list->data); 1888 g_ptr_array_add(pci_nic_models, (gpointer)name); 1889 } 1890 next = list->next; 1891 g_slist_free_1(list); 1892 list = next; 1893 } 1894 g_ptr_array_add(pci_nic_models, NULL); 1895 1896 if (qemu_show_nic_models(nd->model, (const char **)pci_nic_models->pdata)) { 1897 exit(0); 1898 } 1899 1900 i = qemu_find_nic_model(nd, (const char **)pci_nic_models->pdata, 1901 default_model); 1902 if (i < 0) { 1903 exit(1); 1904 } 1905 1906 if (!rootbus) { 1907 error_report("No primary PCI bus"); 1908 exit(1); 1909 } 1910 1911 assert(!rootbus->parent_dev); 1912 1913 if (!devaddr) { 1914 devfn = -1; 1915 busnr = 0; 1916 } else { 1917 if (pci_parse_devaddr(devaddr, &dom, &busnr, &slot, NULL) < 0) { 1918 error_report("Invalid PCI device address %s for device %s", 1919 devaddr, nd->model); 1920 exit(1); 1921 } 1922 1923 if (dom != 0) { 1924 error_report("No support for non-zero PCI domains"); 1925 exit(1); 1926 } 1927 1928 devfn = PCI_DEVFN(slot, 0); 1929 } 1930 1931 bus = pci_find_bus_nr(rootbus, busnr); 1932 if (!bus) { 1933 error_report("Invalid PCI device address %s for device %s", 1934 devaddr, nd->model); 1935 exit(1); 1936 } 1937 1938 pci_dev = pci_create(bus, devfn, nd->model); 1939 dev = &pci_dev->qdev; 1940 qdev_set_nic_properties(dev, nd); 1941 qdev_init_nofail(dev); 1942 g_ptr_array_free(pci_nic_models, true); 1943 return pci_dev; 1944 } 1945 1946 PCIDevice *pci_vga_init(PCIBus *bus) 1947 { 1948 switch (vga_interface_type) { 1949 case VGA_CIRRUS: 1950 return pci_create_simple(bus, -1, "cirrus-vga"); 1951 case VGA_QXL: 1952 return pci_create_simple(bus, -1, "qxl-vga"); 1953 case VGA_STD: 1954 return pci_create_simple(bus, -1, "VGA"); 1955 case VGA_VMWARE: 1956 return pci_create_simple(bus, -1, "vmware-svga"); 1957 case VGA_VIRTIO: 1958 return pci_create_simple(bus, -1, "virtio-vga"); 1959 case VGA_NONE: 1960 default: /* Other non-PCI types. Checking for unsupported types is already 1961 done in vl.c. */ 1962 return NULL; 1963 } 1964 } 1965 1966 /* Whether a given bus number is in range of the secondary 1967 * bus of the given bridge device. */ 1968 static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num) 1969 { 1970 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) & 1971 PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ && 1972 dev->config[PCI_SECONDARY_BUS] <= bus_num && 1973 bus_num <= dev->config[PCI_SUBORDINATE_BUS]; 1974 } 1975 1976 /* Whether a given bus number is in a range of a root bus */ 1977 static bool pci_root_bus_in_range(PCIBus *bus, int bus_num) 1978 { 1979 int i; 1980 1981 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 1982 PCIDevice *dev = bus->devices[i]; 1983 1984 if (dev && PCI_DEVICE_GET_CLASS(dev)->is_bridge) { 1985 if (pci_secondary_bus_in_range(dev, bus_num)) { 1986 return true; 1987 } 1988 } 1989 } 1990 1991 return false; 1992 } 1993 1994 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num) 1995 { 1996 PCIBus *sec; 1997 1998 if (!bus) { 1999 return NULL; 2000 } 2001 2002 if (pci_bus_num(bus) == bus_num) { 2003 return bus; 2004 } 2005 2006 /* Consider all bus numbers in range for the host pci bridge. */ 2007 if (!pci_bus_is_root(bus) && 2008 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) { 2009 return NULL; 2010 } 2011 2012 /* try child bus */ 2013 for (; bus; bus = sec) { 2014 QLIST_FOREACH(sec, &bus->child, sibling) { 2015 if (pci_bus_num(sec) == bus_num) { 2016 return sec; 2017 } 2018 /* PXB buses assumed to be children of bus 0 */ 2019 if (pci_bus_is_root(sec)) { 2020 if (pci_root_bus_in_range(sec, bus_num)) { 2021 break; 2022 } 2023 } else { 2024 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) { 2025 break; 2026 } 2027 } 2028 } 2029 } 2030 2031 return NULL; 2032 } 2033 2034 void pci_for_each_bus_depth_first(PCIBus *bus, 2035 void *(*begin)(PCIBus *bus, void *parent_state), 2036 void (*end)(PCIBus *bus, void *state), 2037 void *parent_state) 2038 { 2039 PCIBus *sec; 2040 void *state; 2041 2042 if (!bus) { 2043 return; 2044 } 2045 2046 if (begin) { 2047 state = begin(bus, parent_state); 2048 } else { 2049 state = parent_state; 2050 } 2051 2052 QLIST_FOREACH(sec, &bus->child, sibling) { 2053 pci_for_each_bus_depth_first(sec, begin, end, state); 2054 } 2055 2056 if (end) { 2057 end(bus, state); 2058 } 2059 } 2060 2061 2062 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn) 2063 { 2064 bus = pci_find_bus_nr(bus, bus_num); 2065 2066 if (!bus) 2067 return NULL; 2068 2069 return bus->devices[devfn]; 2070 } 2071 2072 static void pci_qdev_realize(DeviceState *qdev, Error **errp) 2073 { 2074 PCIDevice *pci_dev = (PCIDevice *)qdev; 2075 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 2076 ObjectClass *klass = OBJECT_CLASS(pc); 2077 Error *local_err = NULL; 2078 bool is_default_rom; 2079 2080 /* initialize cap_present for pci_is_express() and pci_config_size(), 2081 * Note that hybrid PCIs are not set automatically and need to manage 2082 * QEMU_PCI_CAP_EXPRESS manually */ 2083 if (object_class_dynamic_cast(klass, INTERFACE_PCIE_DEVICE) && 2084 !object_class_dynamic_cast(klass, INTERFACE_CONVENTIONAL_PCI_DEVICE)) { 2085 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; 2086 } 2087 2088 pci_dev = do_pci_register_device(pci_dev, 2089 object_get_typename(OBJECT(qdev)), 2090 pci_dev->devfn, errp); 2091 if (pci_dev == NULL) 2092 return; 2093 2094 if (pc->realize) { 2095 pc->realize(pci_dev, &local_err); 2096 if (local_err) { 2097 error_propagate(errp, local_err); 2098 do_pci_unregister_device(pci_dev); 2099 return; 2100 } 2101 } 2102 2103 /* rom loading */ 2104 is_default_rom = false; 2105 if (pci_dev->romfile == NULL && pc->romfile != NULL) { 2106 pci_dev->romfile = g_strdup(pc->romfile); 2107 is_default_rom = true; 2108 } 2109 2110 pci_add_option_rom(pci_dev, is_default_rom, &local_err); 2111 if (local_err) { 2112 error_propagate(errp, local_err); 2113 pci_qdev_unrealize(DEVICE(pci_dev), NULL); 2114 return; 2115 } 2116 } 2117 2118 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction, 2119 const char *name) 2120 { 2121 DeviceState *dev; 2122 2123 dev = qdev_create(&bus->qbus, name); 2124 qdev_prop_set_int32(dev, "addr", devfn); 2125 qdev_prop_set_bit(dev, "multifunction", multifunction); 2126 return PCI_DEVICE(dev); 2127 } 2128 2129 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, 2130 bool multifunction, 2131 const char *name) 2132 { 2133 PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name); 2134 qdev_init_nofail(&dev->qdev); 2135 return dev; 2136 } 2137 2138 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name) 2139 { 2140 return pci_create_multifunction(bus, devfn, false, name); 2141 } 2142 2143 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name) 2144 { 2145 return pci_create_simple_multifunction(bus, devfn, false, name); 2146 } 2147 2148 static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size) 2149 { 2150 int offset = PCI_CONFIG_HEADER_SIZE; 2151 int i; 2152 for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) { 2153 if (pdev->used[i]) 2154 offset = i + 1; 2155 else if (i - offset + 1 == size) 2156 return offset; 2157 } 2158 return 0; 2159 } 2160 2161 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id, 2162 uint8_t *prev_p) 2163 { 2164 uint8_t next, prev; 2165 2166 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST)) 2167 return 0; 2168 2169 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); 2170 prev = next + PCI_CAP_LIST_NEXT) 2171 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id) 2172 break; 2173 2174 if (prev_p) 2175 *prev_p = prev; 2176 return next; 2177 } 2178 2179 static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset) 2180 { 2181 uint8_t next, prev, found = 0; 2182 2183 if (!(pdev->used[offset])) { 2184 return 0; 2185 } 2186 2187 assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST); 2188 2189 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); 2190 prev = next + PCI_CAP_LIST_NEXT) { 2191 if (next <= offset && next > found) { 2192 found = next; 2193 } 2194 } 2195 return found; 2196 } 2197 2198 /* Patch the PCI vendor and device ids in a PCI rom image if necessary. 2199 This is needed for an option rom which is used for more than one device. */ 2200 static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size) 2201 { 2202 uint16_t vendor_id; 2203 uint16_t device_id; 2204 uint16_t rom_vendor_id; 2205 uint16_t rom_device_id; 2206 uint16_t rom_magic; 2207 uint16_t pcir_offset; 2208 uint8_t checksum; 2209 2210 /* Words in rom data are little endian (like in PCI configuration), 2211 so they can be read / written with pci_get_word / pci_set_word. */ 2212 2213 /* Only a valid rom will be patched. */ 2214 rom_magic = pci_get_word(ptr); 2215 if (rom_magic != 0xaa55) { 2216 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic); 2217 return; 2218 } 2219 pcir_offset = pci_get_word(ptr + 0x18); 2220 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) { 2221 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset); 2222 return; 2223 } 2224 2225 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID); 2226 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID); 2227 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4); 2228 rom_device_id = pci_get_word(ptr + pcir_offset + 6); 2229 2230 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile, 2231 vendor_id, device_id, rom_vendor_id, rom_device_id); 2232 2233 checksum = ptr[6]; 2234 2235 if (vendor_id != rom_vendor_id) { 2236 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */ 2237 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8); 2238 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8); 2239 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); 2240 ptr[6] = checksum; 2241 pci_set_word(ptr + pcir_offset + 4, vendor_id); 2242 } 2243 2244 if (device_id != rom_device_id) { 2245 /* Patch device id and checksum (at offset 6 for etherboot roms). */ 2246 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8); 2247 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8); 2248 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); 2249 ptr[6] = checksum; 2250 pci_set_word(ptr + pcir_offset + 6, device_id); 2251 } 2252 } 2253 2254 /* Add an option rom for the device */ 2255 static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, 2256 Error **errp) 2257 { 2258 int size; 2259 char *path; 2260 void *ptr; 2261 char name[32]; 2262 const VMStateDescription *vmsd; 2263 2264 if (!pdev->romfile) 2265 return; 2266 if (strlen(pdev->romfile) == 0) 2267 return; 2268 2269 if (!pdev->rom_bar) { 2270 /* 2271 * Load rom via fw_cfg instead of creating a rom bar, 2272 * for 0.11 compatibility. 2273 */ 2274 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE); 2275 2276 /* 2277 * Hot-plugged devices can't use the option ROM 2278 * if the rom bar is disabled. 2279 */ 2280 if (DEVICE(pdev)->hotplugged) { 2281 error_setg(errp, "Hot-plugged device without ROM bar" 2282 " can't have an option ROM"); 2283 return; 2284 } 2285 2286 if (class == 0x0300) { 2287 rom_add_vga(pdev->romfile); 2288 } else { 2289 rom_add_option(pdev->romfile, -1); 2290 } 2291 return; 2292 } 2293 2294 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile); 2295 if (path == NULL) { 2296 path = g_strdup(pdev->romfile); 2297 } 2298 2299 size = get_image_size(path); 2300 if (size < 0) { 2301 error_setg(errp, "failed to find romfile \"%s\"", pdev->romfile); 2302 g_free(path); 2303 return; 2304 } else if (size == 0) { 2305 error_setg(errp, "romfile \"%s\" is empty", pdev->romfile); 2306 g_free(path); 2307 return; 2308 } 2309 size = pow2ceil(size); 2310 2311 vmsd = qdev_get_vmsd(DEVICE(pdev)); 2312 2313 if (vmsd) { 2314 snprintf(name, sizeof(name), "%s.rom", vmsd->name); 2315 } else { 2316 snprintf(name, sizeof(name), "%s.rom", object_get_typename(OBJECT(pdev))); 2317 } 2318 pdev->has_rom = true; 2319 memory_region_init_rom(&pdev->rom, OBJECT(pdev), name, size, &error_fatal); 2320 ptr = memory_region_get_ram_ptr(&pdev->rom); 2321 if (load_image_size(path, ptr, size) < 0) { 2322 error_setg(errp, "failed to load romfile \"%s\"", pdev->romfile); 2323 g_free(path); 2324 return; 2325 } 2326 g_free(path); 2327 2328 if (is_default_rom) { 2329 /* Only the default rom images will be patched (if needed). */ 2330 pci_patch_ids(pdev, ptr, size); 2331 } 2332 2333 pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom); 2334 } 2335 2336 static void pci_del_option_rom(PCIDevice *pdev) 2337 { 2338 if (!pdev->has_rom) 2339 return; 2340 2341 vmstate_unregister_ram(&pdev->rom, &pdev->qdev); 2342 pdev->has_rom = false; 2343 } 2344 2345 /* 2346 * On success, pci_add_capability() returns a positive value 2347 * that the offset of the pci capability. 2348 * On failure, it sets an error and returns a negative error 2349 * code. 2350 */ 2351 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, 2352 uint8_t offset, uint8_t size, 2353 Error **errp) 2354 { 2355 uint8_t *config; 2356 int i, overlapping_cap; 2357 2358 if (!offset) { 2359 offset = pci_find_space(pdev, size); 2360 /* out of PCI config space is programming error */ 2361 assert(offset); 2362 } else { 2363 /* Verify that capabilities don't overlap. Note: device assignment 2364 * depends on this check to verify that the device is not broken. 2365 * Should never trigger for emulated devices, but it's helpful 2366 * for debugging these. */ 2367 for (i = offset; i < offset + size; i++) { 2368 overlapping_cap = pci_find_capability_at_offset(pdev, i); 2369 if (overlapping_cap) { 2370 error_setg(errp, "%s:%02x:%02x.%x " 2371 "Attempt to add PCI capability %x at offset " 2372 "%x overlaps existing capability %x at offset %x", 2373 pci_root_bus_path(pdev), pci_dev_bus_num(pdev), 2374 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), 2375 cap_id, offset, overlapping_cap, i); 2376 return -EINVAL; 2377 } 2378 } 2379 } 2380 2381 config = pdev->config + offset; 2382 config[PCI_CAP_LIST_ID] = cap_id; 2383 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST]; 2384 pdev->config[PCI_CAPABILITY_LIST] = offset; 2385 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST; 2386 memset(pdev->used + offset, 0xFF, QEMU_ALIGN_UP(size, 4)); 2387 /* Make capability read-only by default */ 2388 memset(pdev->wmask + offset, 0, size); 2389 /* Check capability by default */ 2390 memset(pdev->cmask + offset, 0xFF, size); 2391 return offset; 2392 } 2393 2394 /* Unlink capability from the pci config space. */ 2395 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size) 2396 { 2397 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev); 2398 if (!offset) 2399 return; 2400 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT]; 2401 /* Make capability writable again */ 2402 memset(pdev->wmask + offset, 0xff, size); 2403 memset(pdev->w1cmask + offset, 0, size); 2404 /* Clear cmask as device-specific registers can't be checked */ 2405 memset(pdev->cmask + offset, 0, size); 2406 memset(pdev->used + offset, 0, QEMU_ALIGN_UP(size, 4)); 2407 2408 if (!pdev->config[PCI_CAPABILITY_LIST]) 2409 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST; 2410 } 2411 2412 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id) 2413 { 2414 return pci_find_capability_list(pdev, cap_id, NULL); 2415 } 2416 2417 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent) 2418 { 2419 PCIDevice *d = (PCIDevice *)dev; 2420 const pci_class_desc *desc; 2421 char ctxt[64]; 2422 PCIIORegion *r; 2423 int i, class; 2424 2425 class = pci_get_word(d->config + PCI_CLASS_DEVICE); 2426 desc = pci_class_descriptions; 2427 while (desc->desc && class != desc->class) 2428 desc++; 2429 if (desc->desc) { 2430 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc); 2431 } else { 2432 snprintf(ctxt, sizeof(ctxt), "Class %04x", class); 2433 } 2434 2435 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, " 2436 "pci id %04x:%04x (sub %04x:%04x)\n", 2437 indent, "", ctxt, pci_dev_bus_num(d), 2438 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn), 2439 pci_get_word(d->config + PCI_VENDOR_ID), 2440 pci_get_word(d->config + PCI_DEVICE_ID), 2441 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID), 2442 pci_get_word(d->config + PCI_SUBSYSTEM_ID)); 2443 for (i = 0; i < PCI_NUM_REGIONS; i++) { 2444 r = &d->io_regions[i]; 2445 if (!r->size) 2446 continue; 2447 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS 2448 " [0x%"FMT_PCIBUS"]\n", 2449 indent, "", 2450 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem", 2451 r->addr, r->addr + r->size - 1); 2452 } 2453 } 2454 2455 static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len) 2456 { 2457 PCIDevice *d = (PCIDevice *)dev; 2458 const char *name = NULL; 2459 const pci_class_desc *desc = pci_class_descriptions; 2460 int class = pci_get_word(d->config + PCI_CLASS_DEVICE); 2461 2462 while (desc->desc && 2463 (class & ~desc->fw_ign_bits) != 2464 (desc->class & ~desc->fw_ign_bits)) { 2465 desc++; 2466 } 2467 2468 if (desc->desc) { 2469 name = desc->fw_name; 2470 } 2471 2472 if (name) { 2473 pstrcpy(buf, len, name); 2474 } else { 2475 snprintf(buf, len, "pci%04x,%04x", 2476 pci_get_word(d->config + PCI_VENDOR_ID), 2477 pci_get_word(d->config + PCI_DEVICE_ID)); 2478 } 2479 2480 return buf; 2481 } 2482 2483 static char *pcibus_get_fw_dev_path(DeviceState *dev) 2484 { 2485 PCIDevice *d = (PCIDevice *)dev; 2486 char path[50], name[33]; 2487 int off; 2488 2489 off = snprintf(path, sizeof(path), "%s@%x", 2490 pci_dev_fw_name(dev, name, sizeof name), 2491 PCI_SLOT(d->devfn)); 2492 if (PCI_FUNC(d->devfn)) 2493 snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn)); 2494 return g_strdup(path); 2495 } 2496 2497 static char *pcibus_get_dev_path(DeviceState *dev) 2498 { 2499 PCIDevice *d = container_of(dev, PCIDevice, qdev); 2500 PCIDevice *t; 2501 int slot_depth; 2502 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function. 2503 * 00 is added here to make this format compatible with 2504 * domain:Bus:Slot.Func for systems without nested PCI bridges. 2505 * Slot.Function list specifies the slot and function numbers for all 2506 * devices on the path from root to the specific device. */ 2507 const char *root_bus_path; 2508 int root_bus_len; 2509 char slot[] = ":SS.F"; 2510 int slot_len = sizeof slot - 1 /* For '\0' */; 2511 int path_len; 2512 char *path, *p; 2513 int s; 2514 2515 root_bus_path = pci_root_bus_path(d); 2516 root_bus_len = strlen(root_bus_path); 2517 2518 /* Calculate # of slots on path between device and root. */; 2519 slot_depth = 0; 2520 for (t = d; t; t = pci_get_bus(t)->parent_dev) { 2521 ++slot_depth; 2522 } 2523 2524 path_len = root_bus_len + slot_len * slot_depth; 2525 2526 /* Allocate memory, fill in the terminating null byte. */ 2527 path = g_malloc(path_len + 1 /* For '\0' */); 2528 path[path_len] = '\0'; 2529 2530 memcpy(path, root_bus_path, root_bus_len); 2531 2532 /* Fill in slot numbers. We walk up from device to root, so need to print 2533 * them in the reverse order, last to first. */ 2534 p = path + path_len; 2535 for (t = d; t; t = pci_get_bus(t)->parent_dev) { 2536 p -= slot_len; 2537 s = snprintf(slot, sizeof slot, ":%02x.%x", 2538 PCI_SLOT(t->devfn), PCI_FUNC(t->devfn)); 2539 assert(s == slot_len); 2540 memcpy(p, slot, slot_len); 2541 } 2542 2543 return path; 2544 } 2545 2546 static int pci_qdev_find_recursive(PCIBus *bus, 2547 const char *id, PCIDevice **pdev) 2548 { 2549 DeviceState *qdev = qdev_find_recursive(&bus->qbus, id); 2550 if (!qdev) { 2551 return -ENODEV; 2552 } 2553 2554 /* roughly check if given qdev is pci device */ 2555 if (object_dynamic_cast(OBJECT(qdev), TYPE_PCI_DEVICE)) { 2556 *pdev = PCI_DEVICE(qdev); 2557 return 0; 2558 } 2559 return -EINVAL; 2560 } 2561 2562 int pci_qdev_find_device(const char *id, PCIDevice **pdev) 2563 { 2564 PCIHostState *host_bridge; 2565 int rc = -ENODEV; 2566 2567 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { 2568 int tmp = pci_qdev_find_recursive(host_bridge->bus, id, pdev); 2569 if (!tmp) { 2570 rc = 0; 2571 break; 2572 } 2573 if (tmp != -ENODEV) { 2574 rc = tmp; 2575 } 2576 } 2577 2578 return rc; 2579 } 2580 2581 MemoryRegion *pci_address_space(PCIDevice *dev) 2582 { 2583 return pci_get_bus(dev)->address_space_mem; 2584 } 2585 2586 MemoryRegion *pci_address_space_io(PCIDevice *dev) 2587 { 2588 return pci_get_bus(dev)->address_space_io; 2589 } 2590 2591 static void pci_device_class_init(ObjectClass *klass, void *data) 2592 { 2593 DeviceClass *k = DEVICE_CLASS(klass); 2594 2595 k->realize = pci_qdev_realize; 2596 k->unrealize = pci_qdev_unrealize; 2597 k->bus_type = TYPE_PCI_BUS; 2598 k->props = pci_props; 2599 } 2600 2601 static void pci_device_class_base_init(ObjectClass *klass, void *data) 2602 { 2603 if (!object_class_is_abstract(klass)) { 2604 ObjectClass *conventional = 2605 object_class_dynamic_cast(klass, INTERFACE_CONVENTIONAL_PCI_DEVICE); 2606 ObjectClass *pcie = 2607 object_class_dynamic_cast(klass, INTERFACE_PCIE_DEVICE); 2608 assert(conventional || pcie); 2609 } 2610 } 2611 2612 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev) 2613 { 2614 PCIBus *bus = pci_get_bus(dev); 2615 PCIBus *iommu_bus = bus; 2616 2617 while(iommu_bus && !iommu_bus->iommu_fn && iommu_bus->parent_dev) { 2618 iommu_bus = pci_get_bus(iommu_bus->parent_dev); 2619 } 2620 if (iommu_bus && iommu_bus->iommu_fn) { 2621 return iommu_bus->iommu_fn(bus, iommu_bus->iommu_opaque, dev->devfn); 2622 } 2623 return &address_space_memory; 2624 } 2625 2626 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque) 2627 { 2628 bus->iommu_fn = fn; 2629 bus->iommu_opaque = opaque; 2630 } 2631 2632 static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque) 2633 { 2634 Range *range = opaque; 2635 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 2636 uint16_t cmd = pci_get_word(dev->config + PCI_COMMAND); 2637 int i; 2638 2639 if (!(cmd & PCI_COMMAND_MEMORY)) { 2640 return; 2641 } 2642 2643 if (pc->is_bridge) { 2644 pcibus_t base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 2645 pcibus_t limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 2646 2647 base = MAX(base, 0x1ULL << 32); 2648 2649 if (limit >= base) { 2650 Range pref_range; 2651 range_set_bounds(&pref_range, base, limit); 2652 range_extend(range, &pref_range); 2653 } 2654 } 2655 for (i = 0; i < PCI_NUM_REGIONS; ++i) { 2656 PCIIORegion *r = &dev->io_regions[i]; 2657 pcibus_t lob, upb; 2658 Range region_range; 2659 2660 if (!r->size || 2661 (r->type & PCI_BASE_ADDRESS_SPACE_IO) || 2662 !(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64)) { 2663 continue; 2664 } 2665 2666 lob = pci_bar_address(dev, i, r->type, r->size); 2667 upb = lob + r->size - 1; 2668 if (lob == PCI_BAR_UNMAPPED) { 2669 continue; 2670 } 2671 2672 lob = MAX(lob, 0x1ULL << 32); 2673 2674 if (upb >= lob) { 2675 range_set_bounds(®ion_range, lob, upb); 2676 range_extend(range, ®ion_range); 2677 } 2678 } 2679 } 2680 2681 void pci_bus_get_w64_range(PCIBus *bus, Range *range) 2682 { 2683 range_make_empty(range); 2684 pci_for_each_device_under_bus(bus, pci_dev_get_w64, range); 2685 } 2686 2687 static bool pcie_has_upstream_port(PCIDevice *dev) 2688 { 2689 PCIDevice *parent_dev = pci_bridge_get_device(pci_get_bus(dev)); 2690 2691 /* Device associated with an upstream port. 2692 * As there are several types of these, it's easier to check the 2693 * parent device: upstream ports are always connected to 2694 * root or downstream ports. 2695 */ 2696 return parent_dev && 2697 pci_is_express(parent_dev) && 2698 parent_dev->exp.exp_cap && 2699 (pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_ROOT_PORT || 2700 pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_DOWNSTREAM); 2701 } 2702 2703 PCIDevice *pci_get_function_0(PCIDevice *pci_dev) 2704 { 2705 PCIBus *bus = pci_get_bus(pci_dev); 2706 2707 if(pcie_has_upstream_port(pci_dev)) { 2708 /* With an upstream PCIe port, we only support 1 device at slot 0 */ 2709 return bus->devices[0]; 2710 } else { 2711 /* Other bus types might support multiple devices at slots 0-31 */ 2712 return bus->devices[PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 0)]; 2713 } 2714 } 2715 2716 MSIMessage pci_get_msi_message(PCIDevice *dev, int vector) 2717 { 2718 MSIMessage msg; 2719 if (msix_enabled(dev)) { 2720 msg = msix_get_message(dev, vector); 2721 } else if (msi_enabled(dev)) { 2722 msg = msi_get_message(dev, vector); 2723 } else { 2724 /* Should never happen */ 2725 error_report("%s: unknown interrupt type", __func__); 2726 abort(); 2727 } 2728 return msg; 2729 } 2730 2731 static const TypeInfo pci_device_type_info = { 2732 .name = TYPE_PCI_DEVICE, 2733 .parent = TYPE_DEVICE, 2734 .instance_size = sizeof(PCIDevice), 2735 .abstract = true, 2736 .class_size = sizeof(PCIDeviceClass), 2737 .class_init = pci_device_class_init, 2738 .class_base_init = pci_device_class_base_init, 2739 }; 2740 2741 static void pci_register_types(void) 2742 { 2743 type_register_static(&pci_bus_info); 2744 type_register_static(&pcie_bus_info); 2745 type_register_static(&conventional_pci_interface_info); 2746 type_register_static(&pcie_interface_info); 2747 type_register_static(&pci_device_type_info); 2748 } 2749 2750 type_init(pci_register_types) 2751