xref: /openbmc/qemu/hw/pci/pci.c (revision d49805ae)
1 /*
2  * QEMU PCI bus manager
3  *
4  * Copyright (c) 2004 Fabrice Bellard
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a copy
7  * of this software and associated documentation files (the "Software"), to deal
8  * in the Software without restriction, including without limitation the rights
9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10  * copies of the Software, and to permit persons to whom the Software is
11  * furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22  * THE SOFTWARE.
23  */
24 #include "hw/hw.h"
25 #include "hw/pci/pci.h"
26 #include "hw/pci/pci_bridge.h"
27 #include "hw/pci/pci_bus.h"
28 #include "hw/pci/pci_host.h"
29 #include "monitor/monitor.h"
30 #include "net/net.h"
31 #include "sysemu/sysemu.h"
32 #include "hw/loader.h"
33 #include "qemu/range.h"
34 #include "qmp-commands.h"
35 #include "hw/pci/msi.h"
36 #include "hw/pci/msix.h"
37 #include "exec/address-spaces.h"
38 #include "hw/hotplug.h"
39 
40 //#define DEBUG_PCI
41 #ifdef DEBUG_PCI
42 # define PCI_DPRINTF(format, ...)       printf(format, ## __VA_ARGS__)
43 #else
44 # define PCI_DPRINTF(format, ...)       do { } while (0)
45 #endif
46 
47 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
48 static char *pcibus_get_dev_path(DeviceState *dev);
49 static char *pcibus_get_fw_dev_path(DeviceState *dev);
50 static void pcibus_reset(BusState *qbus);
51 
52 static Property pci_props[] = {
53     DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
54     DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
55     DEFINE_PROP_UINT32("rombar",  PCIDevice, rom_bar, 1),
56     DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present,
57                     QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
58     DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present,
59                     QEMU_PCI_CAP_SERR_BITNR, true),
60     DEFINE_PROP_END_OF_LIST()
61 };
62 
63 static const VMStateDescription vmstate_pcibus = {
64     .name = "PCIBUS",
65     .version_id = 1,
66     .minimum_version_id = 1,
67     .fields = (VMStateField[]) {
68         VMSTATE_INT32_EQUAL(nirq, PCIBus),
69         VMSTATE_VARRAY_INT32(irq_count, PCIBus,
70                              nirq, 0, vmstate_info_int32,
71                              int32_t),
72         VMSTATE_END_OF_LIST()
73     }
74 };
75 
76 static void pci_bus_realize(BusState *qbus, Error **errp)
77 {
78     PCIBus *bus = PCI_BUS(qbus);
79 
80     vmstate_register(NULL, -1, &vmstate_pcibus, bus);
81 }
82 
83 static void pci_bus_unrealize(BusState *qbus, Error **errp)
84 {
85     PCIBus *bus = PCI_BUS(qbus);
86 
87     vmstate_unregister(NULL, &vmstate_pcibus, bus);
88 }
89 
90 static void pci_bus_class_init(ObjectClass *klass, void *data)
91 {
92     BusClass *k = BUS_CLASS(klass);
93 
94     k->print_dev = pcibus_dev_print;
95     k->get_dev_path = pcibus_get_dev_path;
96     k->get_fw_dev_path = pcibus_get_fw_dev_path;
97     k->realize = pci_bus_realize;
98     k->unrealize = pci_bus_unrealize;
99     k->reset = pcibus_reset;
100 }
101 
102 static const TypeInfo pci_bus_info = {
103     .name = TYPE_PCI_BUS,
104     .parent = TYPE_BUS,
105     .instance_size = sizeof(PCIBus),
106     .class_init = pci_bus_class_init,
107 };
108 
109 static const TypeInfo pcie_bus_info = {
110     .name = TYPE_PCIE_BUS,
111     .parent = TYPE_PCI_BUS,
112 };
113 
114 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num);
115 static void pci_update_mappings(PCIDevice *d);
116 static void pci_irq_handler(void *opaque, int irq_num, int level);
117 static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom);
118 static void pci_del_option_rom(PCIDevice *pdev);
119 
120 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
121 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
122 
123 static QLIST_HEAD(, PCIHostState) pci_host_bridges;
124 
125 static int pci_bar(PCIDevice *d, int reg)
126 {
127     uint8_t type;
128 
129     if (reg != PCI_ROM_SLOT)
130         return PCI_BASE_ADDRESS_0 + reg * 4;
131 
132     type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
133     return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
134 }
135 
136 static inline int pci_irq_state(PCIDevice *d, int irq_num)
137 {
138 	return (d->irq_state >> irq_num) & 0x1;
139 }
140 
141 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
142 {
143 	d->irq_state &= ~(0x1 << irq_num);
144 	d->irq_state |= level << irq_num;
145 }
146 
147 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
148 {
149     PCIBus *bus;
150     for (;;) {
151         bus = pci_dev->bus;
152         irq_num = bus->map_irq(pci_dev, irq_num);
153         if (bus->set_irq)
154             break;
155         pci_dev = bus->parent_dev;
156     }
157     bus->irq_count[irq_num] += change;
158     bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
159 }
160 
161 int pci_bus_get_irq_level(PCIBus *bus, int irq_num)
162 {
163     assert(irq_num >= 0);
164     assert(irq_num < bus->nirq);
165     return !!bus->irq_count[irq_num];
166 }
167 
168 /* Update interrupt status bit in config space on interrupt
169  * state change. */
170 static void pci_update_irq_status(PCIDevice *dev)
171 {
172     if (dev->irq_state) {
173         dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;
174     } else {
175         dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
176     }
177 }
178 
179 void pci_device_deassert_intx(PCIDevice *dev)
180 {
181     int i;
182     for (i = 0; i < PCI_NUM_PINS; ++i) {
183         pci_irq_handler(dev, i, 0);
184     }
185 }
186 
187 static void pci_do_device_reset(PCIDevice *dev)
188 {
189     int r;
190 
191     pci_device_deassert_intx(dev);
192     assert(dev->irq_state == 0);
193 
194     /* Clear all writable bits */
195     pci_word_test_and_clear_mask(dev->config + PCI_COMMAND,
196                                  pci_get_word(dev->wmask + PCI_COMMAND) |
197                                  pci_get_word(dev->w1cmask + PCI_COMMAND));
198     pci_word_test_and_clear_mask(dev->config + PCI_STATUS,
199                                  pci_get_word(dev->wmask + PCI_STATUS) |
200                                  pci_get_word(dev->w1cmask + PCI_STATUS));
201     dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
202     dev->config[PCI_INTERRUPT_LINE] = 0x0;
203     for (r = 0; r < PCI_NUM_REGIONS; ++r) {
204         PCIIORegion *region = &dev->io_regions[r];
205         if (!region->size) {
206             continue;
207         }
208 
209         if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) &&
210             region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
211             pci_set_quad(dev->config + pci_bar(dev, r), region->type);
212         } else {
213             pci_set_long(dev->config + pci_bar(dev, r), region->type);
214         }
215     }
216     pci_update_mappings(dev);
217 
218     msi_reset(dev);
219     msix_reset(dev);
220 }
221 
222 /*
223  * This function is called on #RST and FLR.
224  * FLR if PCI_EXP_DEVCTL_BCR_FLR is set
225  */
226 void pci_device_reset(PCIDevice *dev)
227 {
228     qdev_reset_all(&dev->qdev);
229     pci_do_device_reset(dev);
230 }
231 
232 /*
233  * Trigger pci bus reset under a given bus.
234  * Called via qbus_reset_all on RST# assert, after the devices
235  * have been reset qdev_reset_all-ed already.
236  */
237 static void pcibus_reset(BusState *qbus)
238 {
239     PCIBus *bus = DO_UPCAST(PCIBus, qbus, qbus);
240     int i;
241 
242     for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
243         if (bus->devices[i]) {
244             pci_do_device_reset(bus->devices[i]);
245         }
246     }
247 
248     for (i = 0; i < bus->nirq; i++) {
249         assert(bus->irq_count[i] == 0);
250     }
251 }
252 
253 static void pci_host_bus_register(PCIBus *bus, DeviceState *parent)
254 {
255     PCIHostState *host_bridge = PCI_HOST_BRIDGE(parent);
256 
257     QLIST_INSERT_HEAD(&pci_host_bridges, host_bridge, next);
258 }
259 
260 PCIBus *pci_find_primary_bus(void)
261 {
262     PCIBus *primary_bus = NULL;
263     PCIHostState *host;
264 
265     QLIST_FOREACH(host, &pci_host_bridges, next) {
266         if (primary_bus) {
267             /* We have multiple root buses, refuse to select a primary */
268             return NULL;
269         }
270         primary_bus = host->bus;
271     }
272 
273     return primary_bus;
274 }
275 
276 PCIBus *pci_device_root_bus(const PCIDevice *d)
277 {
278     PCIBus *bus = d->bus;
279 
280     while ((d = bus->parent_dev) != NULL) {
281         bus = d->bus;
282     }
283 
284     return bus;
285 }
286 
287 const char *pci_root_bus_path(PCIDevice *dev)
288 {
289     PCIBus *rootbus = pci_device_root_bus(dev);
290     PCIHostState *host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent);
291     PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_GET_CLASS(host_bridge);
292 
293     assert(!rootbus->parent_dev);
294     assert(host_bridge->bus == rootbus);
295 
296     if (hc->root_bus_path) {
297         return (*hc->root_bus_path)(host_bridge, rootbus);
298     }
299 
300     return rootbus->qbus.name;
301 }
302 
303 static void pci_bus_init(PCIBus *bus, DeviceState *parent,
304                          const char *name,
305                          MemoryRegion *address_space_mem,
306                          MemoryRegion *address_space_io,
307                          uint8_t devfn_min)
308 {
309     assert(PCI_FUNC(devfn_min) == 0);
310     bus->devfn_min = devfn_min;
311     bus->address_space_mem = address_space_mem;
312     bus->address_space_io = address_space_io;
313 
314     /* host bridge */
315     QLIST_INIT(&bus->child);
316 
317     pci_host_bus_register(bus, parent);
318 }
319 
320 bool pci_bus_is_express(PCIBus *bus)
321 {
322     return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS);
323 }
324 
325 bool pci_bus_is_root(PCIBus *bus)
326 {
327     return !bus->parent_dev;
328 }
329 
330 void pci_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent,
331                          const char *name,
332                          MemoryRegion *address_space_mem,
333                          MemoryRegion *address_space_io,
334                          uint8_t devfn_min, const char *typename)
335 {
336     qbus_create_inplace(bus, bus_size, typename, parent, name);
337     pci_bus_init(bus, parent, name, address_space_mem,
338                  address_space_io, devfn_min);
339 }
340 
341 PCIBus *pci_bus_new(DeviceState *parent, const char *name,
342                     MemoryRegion *address_space_mem,
343                     MemoryRegion *address_space_io,
344                     uint8_t devfn_min, const char *typename)
345 {
346     PCIBus *bus;
347 
348     bus = PCI_BUS(qbus_create(typename, parent, name));
349     pci_bus_init(bus, parent, name, address_space_mem,
350                  address_space_io, devfn_min);
351     return bus;
352 }
353 
354 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
355                   void *irq_opaque, int nirq)
356 {
357     bus->set_irq = set_irq;
358     bus->map_irq = map_irq;
359     bus->irq_opaque = irq_opaque;
360     bus->nirq = nirq;
361     bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0]));
362 }
363 
364 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
365                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
366                          void *irq_opaque,
367                          MemoryRegion *address_space_mem,
368                          MemoryRegion *address_space_io,
369                          uint8_t devfn_min, int nirq, const char *typename)
370 {
371     PCIBus *bus;
372 
373     bus = pci_bus_new(parent, name, address_space_mem,
374                       address_space_io, devfn_min, typename);
375     pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
376     return bus;
377 }
378 
379 int pci_bus_num(PCIBus *s)
380 {
381     if (pci_bus_is_root(s))
382         return 0;       /* pci host bridge */
383     return s->parent_dev->config[PCI_SECONDARY_BUS];
384 }
385 
386 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
387 {
388     PCIDevice *s = container_of(pv, PCIDevice, config);
389     PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(s);
390     uint8_t *config;
391     int i;
392 
393     assert(size == pci_config_size(s));
394     config = g_malloc(size);
395 
396     qemu_get_buffer(f, config, size);
397     for (i = 0; i < size; ++i) {
398         if ((config[i] ^ s->config[i]) &
399             s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) {
400             g_free(config);
401             return -EINVAL;
402         }
403     }
404     memcpy(s->config, config, size);
405 
406     pci_update_mappings(s);
407     if (pc->is_bridge) {
408         PCIBridge *b = PCI_BRIDGE(s);
409         pci_bridge_update_mappings(b);
410     }
411 
412     memory_region_set_enabled(&s->bus_master_enable_region,
413                               pci_get_word(s->config + PCI_COMMAND)
414                               & PCI_COMMAND_MASTER);
415 
416     g_free(config);
417     return 0;
418 }
419 
420 /* just put buffer */
421 static void put_pci_config_device(QEMUFile *f, void *pv, size_t size)
422 {
423     const uint8_t **v = pv;
424     assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
425     qemu_put_buffer(f, *v, size);
426 }
427 
428 static VMStateInfo vmstate_info_pci_config = {
429     .name = "pci config",
430     .get  = get_pci_config_device,
431     .put  = put_pci_config_device,
432 };
433 
434 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size)
435 {
436     PCIDevice *s = container_of(pv, PCIDevice, irq_state);
437     uint32_t irq_state[PCI_NUM_PINS];
438     int i;
439     for (i = 0; i < PCI_NUM_PINS; ++i) {
440         irq_state[i] = qemu_get_be32(f);
441         if (irq_state[i] != 0x1 && irq_state[i] != 0) {
442             fprintf(stderr, "irq state %d: must be 0 or 1.\n",
443                     irq_state[i]);
444             return -EINVAL;
445         }
446     }
447 
448     for (i = 0; i < PCI_NUM_PINS; ++i) {
449         pci_set_irq_state(s, i, irq_state[i]);
450     }
451 
452     return 0;
453 }
454 
455 static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size)
456 {
457     int i;
458     PCIDevice *s = container_of(pv, PCIDevice, irq_state);
459 
460     for (i = 0; i < PCI_NUM_PINS; ++i) {
461         qemu_put_be32(f, pci_irq_state(s, i));
462     }
463 }
464 
465 static VMStateInfo vmstate_info_pci_irq_state = {
466     .name = "pci irq state",
467     .get  = get_pci_irq_state,
468     .put  = put_pci_irq_state,
469 };
470 
471 const VMStateDescription vmstate_pci_device = {
472     .name = "PCIDevice",
473     .version_id = 2,
474     .minimum_version_id = 1,
475     .fields = (VMStateField[]) {
476         VMSTATE_INT32_POSITIVE_LE(version_id, PCIDevice),
477         VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
478                                    vmstate_info_pci_config,
479                                    PCI_CONFIG_SPACE_SIZE),
480         VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
481 				   vmstate_info_pci_irq_state,
482 				   PCI_NUM_PINS * sizeof(int32_t)),
483         VMSTATE_END_OF_LIST()
484     }
485 };
486 
487 const VMStateDescription vmstate_pcie_device = {
488     .name = "PCIEDevice",
489     .version_id = 2,
490     .minimum_version_id = 1,
491     .fields = (VMStateField[]) {
492         VMSTATE_INT32_POSITIVE_LE(version_id, PCIDevice),
493         VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
494                                    vmstate_info_pci_config,
495                                    PCIE_CONFIG_SPACE_SIZE),
496         VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
497 				   vmstate_info_pci_irq_state,
498 				   PCI_NUM_PINS * sizeof(int32_t)),
499         VMSTATE_END_OF_LIST()
500     }
501 };
502 
503 static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s)
504 {
505     return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device;
506 }
507 
508 void pci_device_save(PCIDevice *s, QEMUFile *f)
509 {
510     /* Clear interrupt status bit: it is implicit
511      * in irq_state which we are saving.
512      * This makes us compatible with old devices
513      * which never set or clear this bit. */
514     s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
515     vmstate_save_state(f, pci_get_vmstate(s), s);
516     /* Restore the interrupt status bit. */
517     pci_update_irq_status(s);
518 }
519 
520 int pci_device_load(PCIDevice *s, QEMUFile *f)
521 {
522     int ret;
523     ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id);
524     /* Restore the interrupt status bit. */
525     pci_update_irq_status(s);
526     return ret;
527 }
528 
529 static void pci_set_default_subsystem_id(PCIDevice *pci_dev)
530 {
531     pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
532                  pci_default_sub_vendor_id);
533     pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
534                  pci_default_sub_device_id);
535 }
536 
537 /*
538  * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
539  *       [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
540  */
541 int pci_parse_devaddr(const char *addr, int *domp, int *busp,
542                       unsigned int *slotp, unsigned int *funcp)
543 {
544     const char *p;
545     char *e;
546     unsigned long val;
547     unsigned long dom = 0, bus = 0;
548     unsigned int slot = 0;
549     unsigned int func = 0;
550 
551     p = addr;
552     val = strtoul(p, &e, 16);
553     if (e == p)
554 	return -1;
555     if (*e == ':') {
556 	bus = val;
557 	p = e + 1;
558 	val = strtoul(p, &e, 16);
559 	if (e == p)
560 	    return -1;
561 	if (*e == ':') {
562 	    dom = bus;
563 	    bus = val;
564 	    p = e + 1;
565 	    val = strtoul(p, &e, 16);
566 	    if (e == p)
567 		return -1;
568 	}
569     }
570 
571     slot = val;
572 
573     if (funcp != NULL) {
574         if (*e != '.')
575             return -1;
576 
577         p = e + 1;
578         val = strtoul(p, &e, 16);
579         if (e == p)
580             return -1;
581 
582         func = val;
583     }
584 
585     /* if funcp == NULL func is 0 */
586     if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7)
587 	return -1;
588 
589     if (*e)
590 	return -1;
591 
592     *domp = dom;
593     *busp = bus;
594     *slotp = slot;
595     if (funcp != NULL)
596         *funcp = func;
597     return 0;
598 }
599 
600 PCIBus *pci_get_bus_devfn(int *devfnp, PCIBus *root, const char *devaddr)
601 {
602     int dom, bus;
603     unsigned slot;
604 
605     if (!root) {
606         fprintf(stderr, "No primary PCI bus\n");
607         return NULL;
608     }
609 
610     assert(!root->parent_dev);
611 
612     if (!devaddr) {
613         *devfnp = -1;
614         return pci_find_bus_nr(root, 0);
615     }
616 
617     if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) {
618         return NULL;
619     }
620 
621     if (dom != 0) {
622         fprintf(stderr, "No support for non-zero PCI domains\n");
623         return NULL;
624     }
625 
626     *devfnp = PCI_DEVFN(slot, 0);
627     return pci_find_bus_nr(root, bus);
628 }
629 
630 static void pci_init_cmask(PCIDevice *dev)
631 {
632     pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
633     pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
634     dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
635     dev->cmask[PCI_REVISION_ID] = 0xff;
636     dev->cmask[PCI_CLASS_PROG] = 0xff;
637     pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
638     dev->cmask[PCI_HEADER_TYPE] = 0xff;
639     dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
640 }
641 
642 static void pci_init_wmask(PCIDevice *dev)
643 {
644     int config_size = pci_config_size(dev);
645 
646     dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
647     dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
648     pci_set_word(dev->wmask + PCI_COMMAND,
649                  PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
650                  PCI_COMMAND_INTX_DISABLE);
651     if (dev->cap_present & QEMU_PCI_CAP_SERR) {
652         pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR);
653     }
654 
655     memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
656            config_size - PCI_CONFIG_HEADER_SIZE);
657 }
658 
659 static void pci_init_w1cmask(PCIDevice *dev)
660 {
661     /*
662      * Note: It's okay to set w1cmask even for readonly bits as
663      * long as their value is hardwired to 0.
664      */
665     pci_set_word(dev->w1cmask + PCI_STATUS,
666                  PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT |
667                  PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT |
668                  PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
669 }
670 
671 static void pci_init_mask_bridge(PCIDevice *d)
672 {
673     /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
674        PCI_SEC_LETENCY_TIMER */
675     memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
676 
677     /* base and limit */
678     d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
679     d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
680     pci_set_word(d->wmask + PCI_MEMORY_BASE,
681                  PCI_MEMORY_RANGE_MASK & 0xffff);
682     pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
683                  PCI_MEMORY_RANGE_MASK & 0xffff);
684     pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
685                  PCI_PREF_RANGE_MASK & 0xffff);
686     pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
687                  PCI_PREF_RANGE_MASK & 0xffff);
688 
689     /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
690     memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
691 
692     /* Supported memory and i/o types */
693     d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16;
694     d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16;
695     pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE,
696                                PCI_PREF_RANGE_TYPE_64);
697     pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT,
698                                PCI_PREF_RANGE_TYPE_64);
699 
700     /*
701      * TODO: Bridges default to 10-bit VGA decoding but we currently only
702      * implement 16-bit decoding (no alias support).
703      */
704     pci_set_word(d->wmask + PCI_BRIDGE_CONTROL,
705                  PCI_BRIDGE_CTL_PARITY |
706                  PCI_BRIDGE_CTL_SERR |
707                  PCI_BRIDGE_CTL_ISA |
708                  PCI_BRIDGE_CTL_VGA |
709                  PCI_BRIDGE_CTL_VGA_16BIT |
710                  PCI_BRIDGE_CTL_MASTER_ABORT |
711                  PCI_BRIDGE_CTL_BUS_RESET |
712                  PCI_BRIDGE_CTL_FAST_BACK |
713                  PCI_BRIDGE_CTL_DISCARD |
714                  PCI_BRIDGE_CTL_SEC_DISCARD |
715                  PCI_BRIDGE_CTL_DISCARD_SERR);
716     /* Below does not do anything as we never set this bit, put here for
717      * completeness. */
718     pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL,
719                  PCI_BRIDGE_CTL_DISCARD_STATUS);
720     d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK;
721     d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK;
722     pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE,
723                                PCI_PREF_RANGE_TYPE_MASK);
724     pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT,
725                                PCI_PREF_RANGE_TYPE_MASK);
726 }
727 
728 static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev)
729 {
730     uint8_t slot = PCI_SLOT(dev->devfn);
731     uint8_t func;
732 
733     if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
734         dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
735     }
736 
737     /*
738      * multifunction bit is interpreted in two ways as follows.
739      *   - all functions must set the bit to 1.
740      *     Example: Intel X53
741      *   - function 0 must set the bit, but the rest function (> 0)
742      *     is allowed to leave the bit to 0.
743      *     Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
744      *
745      * So OS (at least Linux) checks the bit of only function 0,
746      * and doesn't see the bit of function > 0.
747      *
748      * The below check allows both interpretation.
749      */
750     if (PCI_FUNC(dev->devfn)) {
751         PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)];
752         if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) {
753             /* function 0 should set multifunction bit */
754             error_report("PCI: single function device can't be populated "
755                          "in function %x.%x", slot, PCI_FUNC(dev->devfn));
756             return -1;
757         }
758         return 0;
759     }
760 
761     if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
762         return 0;
763     }
764     /* function 0 indicates single function, so function > 0 must be NULL */
765     for (func = 1; func < PCI_FUNC_MAX; ++func) {
766         if (bus->devices[PCI_DEVFN(slot, func)]) {
767             error_report("PCI: %x.0 indicates single function, "
768                          "but %x.%x is already populated.",
769                          slot, slot, func);
770             return -1;
771         }
772     }
773     return 0;
774 }
775 
776 static void pci_config_alloc(PCIDevice *pci_dev)
777 {
778     int config_size = pci_config_size(pci_dev);
779 
780     pci_dev->config = g_malloc0(config_size);
781     pci_dev->cmask = g_malloc0(config_size);
782     pci_dev->wmask = g_malloc0(config_size);
783     pci_dev->w1cmask = g_malloc0(config_size);
784     pci_dev->used = g_malloc0(config_size);
785 }
786 
787 static void pci_config_free(PCIDevice *pci_dev)
788 {
789     g_free(pci_dev->config);
790     g_free(pci_dev->cmask);
791     g_free(pci_dev->wmask);
792     g_free(pci_dev->w1cmask);
793     g_free(pci_dev->used);
794 }
795 
796 static void do_pci_unregister_device(PCIDevice *pci_dev)
797 {
798     pci_dev->bus->devices[pci_dev->devfn] = NULL;
799     pci_config_free(pci_dev);
800 
801     address_space_destroy(&pci_dev->bus_master_as);
802     memory_region_destroy(&pci_dev->bus_master_enable_region);
803 }
804 
805 /* -1 for devfn means auto assign */
806 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
807                                          const char *name, int devfn)
808 {
809     PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
810     PCIConfigReadFunc *config_read = pc->config_read;
811     PCIConfigWriteFunc *config_write = pc->config_write;
812     AddressSpace *dma_as;
813 
814     if (devfn < 0) {
815         for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
816             devfn += PCI_FUNC_MAX) {
817             if (!bus->devices[devfn])
818                 goto found;
819         }
820         error_report("PCI: no slot/function available for %s, all in use", name);
821         return NULL;
822     found: ;
823     } else if (bus->devices[devfn]) {
824         error_report("PCI: slot %d function %d not available for %s, in use by %s",
825                      PCI_SLOT(devfn), PCI_FUNC(devfn), name, bus->devices[devfn]->name);
826         return NULL;
827     }
828 
829     pci_dev->bus = bus;
830     dma_as = pci_device_iommu_address_space(pci_dev);
831 
832     memory_region_init_alias(&pci_dev->bus_master_enable_region,
833                              OBJECT(pci_dev), "bus master",
834                              dma_as->root, 0, memory_region_size(dma_as->root));
835     memory_region_set_enabled(&pci_dev->bus_master_enable_region, false);
836     address_space_init(&pci_dev->bus_master_as, &pci_dev->bus_master_enable_region,
837                        name);
838 
839     pci_dev->devfn = devfn;
840     pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
841     pci_dev->irq_state = 0;
842     pci_config_alloc(pci_dev);
843 
844     pci_config_set_vendor_id(pci_dev->config, pc->vendor_id);
845     pci_config_set_device_id(pci_dev->config, pc->device_id);
846     pci_config_set_revision(pci_dev->config, pc->revision);
847     pci_config_set_class(pci_dev->config, pc->class_id);
848 
849     if (!pc->is_bridge) {
850         if (pc->subsystem_vendor_id || pc->subsystem_id) {
851             pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
852                          pc->subsystem_vendor_id);
853             pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
854                          pc->subsystem_id);
855         } else {
856             pci_set_default_subsystem_id(pci_dev);
857         }
858     } else {
859         /* subsystem_vendor_id/subsystem_id are only for header type 0 */
860         assert(!pc->subsystem_vendor_id);
861         assert(!pc->subsystem_id);
862     }
863     pci_init_cmask(pci_dev);
864     pci_init_wmask(pci_dev);
865     pci_init_w1cmask(pci_dev);
866     if (pc->is_bridge) {
867         pci_init_mask_bridge(pci_dev);
868     }
869     if (pci_init_multifunction(bus, pci_dev)) {
870         do_pci_unregister_device(pci_dev);
871         return NULL;
872     }
873 
874     if (!config_read)
875         config_read = pci_default_read_config;
876     if (!config_write)
877         config_write = pci_default_write_config;
878     pci_dev->config_read = config_read;
879     pci_dev->config_write = config_write;
880     bus->devices[devfn] = pci_dev;
881     pci_dev->version_id = 2; /* Current pci device vmstate version */
882     return pci_dev;
883 }
884 
885 static void pci_unregister_io_regions(PCIDevice *pci_dev)
886 {
887     PCIIORegion *r;
888     int i;
889 
890     for(i = 0; i < PCI_NUM_REGIONS; i++) {
891         r = &pci_dev->io_regions[i];
892         if (!r->size || r->addr == PCI_BAR_UNMAPPED)
893             continue;
894         memory_region_del_subregion(r->address_space, r->memory);
895     }
896 
897     pci_unregister_vga(pci_dev);
898 }
899 
900 static int pci_unregister_device(DeviceState *dev)
901 {
902     PCIDevice *pci_dev = PCI_DEVICE(dev);
903     PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
904 
905     pci_unregister_io_regions(pci_dev);
906     pci_del_option_rom(pci_dev);
907 
908     if (pc->exit) {
909         pc->exit(pci_dev);
910     }
911 
912     do_pci_unregister_device(pci_dev);
913     return 0;
914 }
915 
916 void pci_register_bar(PCIDevice *pci_dev, int region_num,
917                       uint8_t type, MemoryRegion *memory)
918 {
919     PCIIORegion *r;
920     uint32_t addr;
921     uint64_t wmask;
922     pcibus_t size = memory_region_size(memory);
923 
924     assert(region_num >= 0);
925     assert(region_num < PCI_NUM_REGIONS);
926     if (size & (size-1)) {
927         fprintf(stderr, "ERROR: PCI region size must be pow2 "
928                     "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
929         exit(1);
930     }
931 
932     r = &pci_dev->io_regions[region_num];
933     r->addr = PCI_BAR_UNMAPPED;
934     r->size = size;
935     r->type = type;
936     r->memory = NULL;
937 
938     wmask = ~(size - 1);
939     addr = pci_bar(pci_dev, region_num);
940     if (region_num == PCI_ROM_SLOT) {
941         /* ROM enable bit is writable */
942         wmask |= PCI_ROM_ADDRESS_ENABLE;
943     }
944     pci_set_long(pci_dev->config + addr, type);
945     if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
946         r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
947         pci_set_quad(pci_dev->wmask + addr, wmask);
948         pci_set_quad(pci_dev->cmask + addr, ~0ULL);
949     } else {
950         pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
951         pci_set_long(pci_dev->cmask + addr, 0xffffffff);
952     }
953     pci_dev->io_regions[region_num].memory = memory;
954     pci_dev->io_regions[region_num].address_space
955         = type & PCI_BASE_ADDRESS_SPACE_IO
956         ? pci_dev->bus->address_space_io
957         : pci_dev->bus->address_space_mem;
958 }
959 
960 static void pci_update_vga(PCIDevice *pci_dev)
961 {
962     uint16_t cmd;
963 
964     if (!pci_dev->has_vga) {
965         return;
966     }
967 
968     cmd = pci_get_word(pci_dev->config + PCI_COMMAND);
969 
970     memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_MEM],
971                               cmd & PCI_COMMAND_MEMORY);
972     memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO],
973                               cmd & PCI_COMMAND_IO);
974     memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI],
975                               cmd & PCI_COMMAND_IO);
976 }
977 
978 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
979                       MemoryRegion *io_lo, MemoryRegion *io_hi)
980 {
981     assert(!pci_dev->has_vga);
982 
983     assert(memory_region_size(mem) == QEMU_PCI_VGA_MEM_SIZE);
984     pci_dev->vga_regions[QEMU_PCI_VGA_MEM] = mem;
985     memory_region_add_subregion_overlap(pci_dev->bus->address_space_mem,
986                                         QEMU_PCI_VGA_MEM_BASE, mem, 1);
987 
988     assert(memory_region_size(io_lo) == QEMU_PCI_VGA_IO_LO_SIZE);
989     pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO] = io_lo;
990     memory_region_add_subregion_overlap(pci_dev->bus->address_space_io,
991                                         QEMU_PCI_VGA_IO_LO_BASE, io_lo, 1);
992 
993     assert(memory_region_size(io_hi) == QEMU_PCI_VGA_IO_HI_SIZE);
994     pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI] = io_hi;
995     memory_region_add_subregion_overlap(pci_dev->bus->address_space_io,
996                                         QEMU_PCI_VGA_IO_HI_BASE, io_hi, 1);
997     pci_dev->has_vga = true;
998 
999     pci_update_vga(pci_dev);
1000 }
1001 
1002 void pci_unregister_vga(PCIDevice *pci_dev)
1003 {
1004     if (!pci_dev->has_vga) {
1005         return;
1006     }
1007 
1008     memory_region_del_subregion(pci_dev->bus->address_space_mem,
1009                                 pci_dev->vga_regions[QEMU_PCI_VGA_MEM]);
1010     memory_region_del_subregion(pci_dev->bus->address_space_io,
1011                                 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO]);
1012     memory_region_del_subregion(pci_dev->bus->address_space_io,
1013                                 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI]);
1014     pci_dev->has_vga = false;
1015 }
1016 
1017 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num)
1018 {
1019     return pci_dev->io_regions[region_num].addr;
1020 }
1021 
1022 static pcibus_t pci_bar_address(PCIDevice *d,
1023 				int reg, uint8_t type, pcibus_t size)
1024 {
1025     pcibus_t new_addr, last_addr;
1026     int bar = pci_bar(d, reg);
1027     uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
1028 
1029     if (type & PCI_BASE_ADDRESS_SPACE_IO) {
1030         if (!(cmd & PCI_COMMAND_IO)) {
1031             return PCI_BAR_UNMAPPED;
1032         }
1033         new_addr = pci_get_long(d->config + bar) & ~(size - 1);
1034         last_addr = new_addr + size - 1;
1035         /* Check if 32 bit BAR wraps around explicitly.
1036          * TODO: make priorities correct and remove this work around.
1037          */
1038         if (last_addr <= new_addr || new_addr == 0 || last_addr >= UINT32_MAX) {
1039             return PCI_BAR_UNMAPPED;
1040         }
1041         return new_addr;
1042     }
1043 
1044     if (!(cmd & PCI_COMMAND_MEMORY)) {
1045         return PCI_BAR_UNMAPPED;
1046     }
1047     if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
1048         new_addr = pci_get_quad(d->config + bar);
1049     } else {
1050         new_addr = pci_get_long(d->config + bar);
1051     }
1052     /* the ROM slot has a specific enable bit */
1053     if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
1054         return PCI_BAR_UNMAPPED;
1055     }
1056     new_addr &= ~(size - 1);
1057     last_addr = new_addr + size - 1;
1058     /* NOTE: we do not support wrapping */
1059     /* XXX: as we cannot support really dynamic
1060        mappings, we handle specific values as invalid
1061        mappings. */
1062     if (last_addr <= new_addr || new_addr == 0 ||
1063         last_addr == PCI_BAR_UNMAPPED) {
1064         return PCI_BAR_UNMAPPED;
1065     }
1066 
1067     /* Now pcibus_t is 64bit.
1068      * Check if 32 bit BAR wraps around explicitly.
1069      * Without this, PC ide doesn't work well.
1070      * TODO: remove this work around.
1071      */
1072     if  (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
1073         return PCI_BAR_UNMAPPED;
1074     }
1075 
1076     /*
1077      * OS is allowed to set BAR beyond its addressable
1078      * bits. For example, 32 bit OS can set 64bit bar
1079      * to >4G. Check it. TODO: we might need to support
1080      * it in the future for e.g. PAE.
1081      */
1082     if (last_addr >= HWADDR_MAX) {
1083         return PCI_BAR_UNMAPPED;
1084     }
1085 
1086     return new_addr;
1087 }
1088 
1089 static void pci_update_mappings(PCIDevice *d)
1090 {
1091     PCIIORegion *r;
1092     int i;
1093     pcibus_t new_addr;
1094 
1095     for(i = 0; i < PCI_NUM_REGIONS; i++) {
1096         r = &d->io_regions[i];
1097 
1098         /* this region isn't registered */
1099         if (!r->size)
1100             continue;
1101 
1102         new_addr = pci_bar_address(d, i, r->type, r->size);
1103 
1104         /* This bar isn't changed */
1105         if (new_addr == r->addr)
1106             continue;
1107 
1108         /* now do the real mapping */
1109         if (r->addr != PCI_BAR_UNMAPPED) {
1110             memory_region_del_subregion(r->address_space, r->memory);
1111         }
1112         r->addr = new_addr;
1113         if (r->addr != PCI_BAR_UNMAPPED) {
1114             memory_region_add_subregion_overlap(r->address_space,
1115                                                 r->addr, r->memory, 1);
1116         }
1117     }
1118 
1119     pci_update_vga(d);
1120 }
1121 
1122 static inline int pci_irq_disabled(PCIDevice *d)
1123 {
1124     return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE;
1125 }
1126 
1127 /* Called after interrupt disabled field update in config space,
1128  * assert/deassert interrupts if necessary.
1129  * Gets original interrupt disable bit value (before update). */
1130 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled)
1131 {
1132     int i, disabled = pci_irq_disabled(d);
1133     if (disabled == was_irq_disabled)
1134         return;
1135     for (i = 0; i < PCI_NUM_PINS; ++i) {
1136         int state = pci_irq_state(d, i);
1137         pci_change_irq_level(d, i, disabled ? -state : state);
1138     }
1139 }
1140 
1141 uint32_t pci_default_read_config(PCIDevice *d,
1142                                  uint32_t address, int len)
1143 {
1144     uint32_t val = 0;
1145 
1146     memcpy(&val, d->config + address, len);
1147     return le32_to_cpu(val);
1148 }
1149 
1150 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
1151 {
1152     int i, was_irq_disabled = pci_irq_disabled(d);
1153 
1154     for (i = 0; i < l; val >>= 8, ++i) {
1155         uint8_t wmask = d->wmask[addr + i];
1156         uint8_t w1cmask = d->w1cmask[addr + i];
1157         assert(!(wmask & w1cmask));
1158         d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
1159         d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
1160     }
1161     if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
1162         ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
1163         ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
1164         range_covers_byte(addr, l, PCI_COMMAND))
1165         pci_update_mappings(d);
1166 
1167     if (range_covers_byte(addr, l, PCI_COMMAND)) {
1168         pci_update_irq_disabled(d, was_irq_disabled);
1169         memory_region_set_enabled(&d->bus_master_enable_region,
1170                                   pci_get_word(d->config + PCI_COMMAND)
1171                                     & PCI_COMMAND_MASTER);
1172     }
1173 
1174     msi_write_config(d, addr, val, l);
1175     msix_write_config(d, addr, val, l);
1176 }
1177 
1178 /***********************************************************/
1179 /* generic PCI irq support */
1180 
1181 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1182 static void pci_irq_handler(void *opaque, int irq_num, int level)
1183 {
1184     PCIDevice *pci_dev = opaque;
1185     int change;
1186 
1187     change = level - pci_irq_state(pci_dev, irq_num);
1188     if (!change)
1189         return;
1190 
1191     pci_set_irq_state(pci_dev, irq_num, level);
1192     pci_update_irq_status(pci_dev);
1193     if (pci_irq_disabled(pci_dev))
1194         return;
1195     pci_change_irq_level(pci_dev, irq_num, change);
1196 }
1197 
1198 static inline int pci_intx(PCIDevice *pci_dev)
1199 {
1200     return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1;
1201 }
1202 
1203 qemu_irq pci_allocate_irq(PCIDevice *pci_dev)
1204 {
1205     int intx = pci_intx(pci_dev);
1206 
1207     return qemu_allocate_irq(pci_irq_handler, pci_dev, intx);
1208 }
1209 
1210 void pci_set_irq(PCIDevice *pci_dev, int level)
1211 {
1212     int intx = pci_intx(pci_dev);
1213     pci_irq_handler(pci_dev, intx, level);
1214 }
1215 
1216 /* Special hooks used by device assignment */
1217 void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq)
1218 {
1219     assert(pci_bus_is_root(bus));
1220     bus->route_intx_to_irq = route_intx_to_irq;
1221 }
1222 
1223 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin)
1224 {
1225     PCIBus *bus;
1226 
1227     do {
1228          bus = dev->bus;
1229          pin = bus->map_irq(dev, pin);
1230          dev = bus->parent_dev;
1231     } while (dev);
1232 
1233     if (!bus->route_intx_to_irq) {
1234         error_report("PCI: Bug - unimplemented PCI INTx routing (%s)",
1235                      object_get_typename(OBJECT(bus->qbus.parent)));
1236         return (PCIINTxRoute) { PCI_INTX_DISABLED, -1 };
1237     }
1238 
1239     return bus->route_intx_to_irq(bus->irq_opaque, pin);
1240 }
1241 
1242 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new)
1243 {
1244     return old->mode != new->mode || old->irq != new->irq;
1245 }
1246 
1247 void pci_bus_fire_intx_routing_notifier(PCIBus *bus)
1248 {
1249     PCIDevice *dev;
1250     PCIBus *sec;
1251     int i;
1252 
1253     for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
1254         dev = bus->devices[i];
1255         if (dev && dev->intx_routing_notifier) {
1256             dev->intx_routing_notifier(dev);
1257         }
1258     }
1259 
1260     QLIST_FOREACH(sec, &bus->child, sibling) {
1261         pci_bus_fire_intx_routing_notifier(sec);
1262     }
1263 }
1264 
1265 void pci_device_set_intx_routing_notifier(PCIDevice *dev,
1266                                           PCIINTxRoutingNotifier notifier)
1267 {
1268     dev->intx_routing_notifier = notifier;
1269 }
1270 
1271 /*
1272  * PCI-to-PCI bridge specification
1273  * 9.1: Interrupt routing. Table 9-1
1274  *
1275  * the PCI Express Base Specification, Revision 2.1
1276  * 2.2.8.1: INTx interrutp signaling - Rules
1277  *          the Implementation Note
1278  *          Table 2-20
1279  */
1280 /*
1281  * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD
1282  * 0-origin unlike PCI interrupt pin register.
1283  */
1284 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin)
1285 {
1286     return (pin + PCI_SLOT(pci_dev->devfn)) % PCI_NUM_PINS;
1287 }
1288 
1289 /***********************************************************/
1290 /* monitor info on PCI */
1291 
1292 typedef struct {
1293     uint16_t class;
1294     const char *desc;
1295     const char *fw_name;
1296     uint16_t fw_ign_bits;
1297 } pci_class_desc;
1298 
1299 static const pci_class_desc pci_class_descriptions[] =
1300 {
1301     { 0x0001, "VGA controller", "display"},
1302     { 0x0100, "SCSI controller", "scsi"},
1303     { 0x0101, "IDE controller", "ide"},
1304     { 0x0102, "Floppy controller", "fdc"},
1305     { 0x0103, "IPI controller", "ipi"},
1306     { 0x0104, "RAID controller", "raid"},
1307     { 0x0106, "SATA controller"},
1308     { 0x0107, "SAS controller"},
1309     { 0x0180, "Storage controller"},
1310     { 0x0200, "Ethernet controller", "ethernet"},
1311     { 0x0201, "Token Ring controller", "token-ring"},
1312     { 0x0202, "FDDI controller", "fddi"},
1313     { 0x0203, "ATM controller", "atm"},
1314     { 0x0280, "Network controller"},
1315     { 0x0300, "VGA controller", "display", 0x00ff},
1316     { 0x0301, "XGA controller"},
1317     { 0x0302, "3D controller"},
1318     { 0x0380, "Display controller"},
1319     { 0x0400, "Video controller", "video"},
1320     { 0x0401, "Audio controller", "sound"},
1321     { 0x0402, "Phone"},
1322     { 0x0403, "Audio controller", "sound"},
1323     { 0x0480, "Multimedia controller"},
1324     { 0x0500, "RAM controller", "memory"},
1325     { 0x0501, "Flash controller", "flash"},
1326     { 0x0580, "Memory controller"},
1327     { 0x0600, "Host bridge", "host"},
1328     { 0x0601, "ISA bridge", "isa"},
1329     { 0x0602, "EISA bridge", "eisa"},
1330     { 0x0603, "MC bridge", "mca"},
1331     { 0x0604, "PCI bridge", "pci-bridge"},
1332     { 0x0605, "PCMCIA bridge", "pcmcia"},
1333     { 0x0606, "NUBUS bridge", "nubus"},
1334     { 0x0607, "CARDBUS bridge", "cardbus"},
1335     { 0x0608, "RACEWAY bridge"},
1336     { 0x0680, "Bridge"},
1337     { 0x0700, "Serial port", "serial"},
1338     { 0x0701, "Parallel port", "parallel"},
1339     { 0x0800, "Interrupt controller", "interrupt-controller"},
1340     { 0x0801, "DMA controller", "dma-controller"},
1341     { 0x0802, "Timer", "timer"},
1342     { 0x0803, "RTC", "rtc"},
1343     { 0x0900, "Keyboard", "keyboard"},
1344     { 0x0901, "Pen", "pen"},
1345     { 0x0902, "Mouse", "mouse"},
1346     { 0x0A00, "Dock station", "dock", 0x00ff},
1347     { 0x0B00, "i386 cpu", "cpu", 0x00ff},
1348     { 0x0c00, "Fireware contorller", "fireware"},
1349     { 0x0c01, "Access bus controller", "access-bus"},
1350     { 0x0c02, "SSA controller", "ssa"},
1351     { 0x0c03, "USB controller", "usb"},
1352     { 0x0c04, "Fibre channel controller", "fibre-channel"},
1353     { 0x0c05, "SMBus"},
1354     { 0, NULL}
1355 };
1356 
1357 static void pci_for_each_device_under_bus(PCIBus *bus,
1358                                           void (*fn)(PCIBus *b, PCIDevice *d,
1359                                                      void *opaque),
1360                                           void *opaque)
1361 {
1362     PCIDevice *d;
1363     int devfn;
1364 
1365     for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1366         d = bus->devices[devfn];
1367         if (d) {
1368             fn(bus, d, opaque);
1369         }
1370     }
1371 }
1372 
1373 void pci_for_each_device(PCIBus *bus, int bus_num,
1374                          void (*fn)(PCIBus *b, PCIDevice *d, void *opaque),
1375                          void *opaque)
1376 {
1377     bus = pci_find_bus_nr(bus, bus_num);
1378 
1379     if (bus) {
1380         pci_for_each_device_under_bus(bus, fn, opaque);
1381     }
1382 }
1383 
1384 static const pci_class_desc *get_class_desc(int class)
1385 {
1386     const pci_class_desc *desc;
1387 
1388     desc = pci_class_descriptions;
1389     while (desc->desc && class != desc->class) {
1390         desc++;
1391     }
1392 
1393     return desc;
1394 }
1395 
1396 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num);
1397 
1398 static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev)
1399 {
1400     PciMemoryRegionList *head = NULL, *cur_item = NULL;
1401     int i;
1402 
1403     for (i = 0; i < PCI_NUM_REGIONS; i++) {
1404         const PCIIORegion *r = &dev->io_regions[i];
1405         PciMemoryRegionList *region;
1406 
1407         if (!r->size) {
1408             continue;
1409         }
1410 
1411         region = g_malloc0(sizeof(*region));
1412         region->value = g_malloc0(sizeof(*region->value));
1413 
1414         if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1415             region->value->type = g_strdup("io");
1416         } else {
1417             region->value->type = g_strdup("memory");
1418             region->value->has_prefetch = true;
1419             region->value->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH);
1420             region->value->has_mem_type_64 = true;
1421             region->value->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64);
1422         }
1423 
1424         region->value->bar = i;
1425         region->value->address = r->addr;
1426         region->value->size = r->size;
1427 
1428         /* XXX: waiting for the qapi to support GSList */
1429         if (!cur_item) {
1430             head = cur_item = region;
1431         } else {
1432             cur_item->next = region;
1433             cur_item = region;
1434         }
1435     }
1436 
1437     return head;
1438 }
1439 
1440 static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus,
1441                                            int bus_num)
1442 {
1443     PciBridgeInfo *info;
1444 
1445     info = g_malloc0(sizeof(*info));
1446 
1447     info->bus.number = dev->config[PCI_PRIMARY_BUS];
1448     info->bus.secondary = dev->config[PCI_SECONDARY_BUS];
1449     info->bus.subordinate = dev->config[PCI_SUBORDINATE_BUS];
1450 
1451     info->bus.io_range = g_malloc0(sizeof(*info->bus.io_range));
1452     info->bus.io_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
1453     info->bus.io_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
1454 
1455     info->bus.memory_range = g_malloc0(sizeof(*info->bus.memory_range));
1456     info->bus.memory_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
1457     info->bus.memory_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
1458 
1459     info->bus.prefetchable_range = g_malloc0(sizeof(*info->bus.prefetchable_range));
1460     info->bus.prefetchable_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
1461     info->bus.prefetchable_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
1462 
1463     if (dev->config[PCI_SECONDARY_BUS] != 0) {
1464         PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]);
1465         if (child_bus) {
1466             info->has_devices = true;
1467             info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]);
1468         }
1469     }
1470 
1471     return info;
1472 }
1473 
1474 static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus,
1475                                            int bus_num)
1476 {
1477     const pci_class_desc *desc;
1478     PciDeviceInfo *info;
1479     uint8_t type;
1480     int class;
1481 
1482     info = g_malloc0(sizeof(*info));
1483     info->bus = bus_num;
1484     info->slot = PCI_SLOT(dev->devfn);
1485     info->function = PCI_FUNC(dev->devfn);
1486 
1487     class = pci_get_word(dev->config + PCI_CLASS_DEVICE);
1488     info->class_info.q_class = class;
1489     desc = get_class_desc(class);
1490     if (desc->desc) {
1491         info->class_info.has_desc = true;
1492         info->class_info.desc = g_strdup(desc->desc);
1493     }
1494 
1495     info->id.vendor = pci_get_word(dev->config + PCI_VENDOR_ID);
1496     info->id.device = pci_get_word(dev->config + PCI_DEVICE_ID);
1497     info->regions = qmp_query_pci_regions(dev);
1498     info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : "");
1499 
1500     if (dev->config[PCI_INTERRUPT_PIN] != 0) {
1501         info->has_irq = true;
1502         info->irq = dev->config[PCI_INTERRUPT_LINE];
1503     }
1504 
1505     type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
1506     if (type == PCI_HEADER_TYPE_BRIDGE) {
1507         info->has_pci_bridge = true;
1508         info->pci_bridge = qmp_query_pci_bridge(dev, bus, bus_num);
1509     }
1510 
1511     return info;
1512 }
1513 
1514 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num)
1515 {
1516     PciDeviceInfoList *info, *head = NULL, *cur_item = NULL;
1517     PCIDevice *dev;
1518     int devfn;
1519 
1520     for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1521         dev = bus->devices[devfn];
1522         if (dev) {
1523             info = g_malloc0(sizeof(*info));
1524             info->value = qmp_query_pci_device(dev, bus, bus_num);
1525 
1526             /* XXX: waiting for the qapi to support GSList */
1527             if (!cur_item) {
1528                 head = cur_item = info;
1529             } else {
1530                 cur_item->next = info;
1531                 cur_item = info;
1532             }
1533         }
1534     }
1535 
1536     return head;
1537 }
1538 
1539 static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num)
1540 {
1541     PciInfo *info = NULL;
1542 
1543     bus = pci_find_bus_nr(bus, bus_num);
1544     if (bus) {
1545         info = g_malloc0(sizeof(*info));
1546         info->bus = bus_num;
1547         info->devices = qmp_query_pci_devices(bus, bus_num);
1548     }
1549 
1550     return info;
1551 }
1552 
1553 PciInfoList *qmp_query_pci(Error **errp)
1554 {
1555     PciInfoList *info, *head = NULL, *cur_item = NULL;
1556     PCIHostState *host_bridge;
1557 
1558     QLIST_FOREACH(host_bridge, &pci_host_bridges, next) {
1559         info = g_malloc0(sizeof(*info));
1560         info->value = qmp_query_pci_bus(host_bridge->bus, 0);
1561 
1562         /* XXX: waiting for the qapi to support GSList */
1563         if (!cur_item) {
1564             head = cur_item = info;
1565         } else {
1566             cur_item->next = info;
1567             cur_item = info;
1568         }
1569     }
1570 
1571     return head;
1572 }
1573 
1574 static const char * const pci_nic_models[] = {
1575     "ne2k_pci",
1576     "i82551",
1577     "i82557b",
1578     "i82559er",
1579     "rtl8139",
1580     "e1000",
1581     "pcnet",
1582     "virtio",
1583     NULL
1584 };
1585 
1586 static const char * const pci_nic_names[] = {
1587     "ne2k_pci",
1588     "i82551",
1589     "i82557b",
1590     "i82559er",
1591     "rtl8139",
1592     "e1000",
1593     "pcnet",
1594     "virtio-net-pci",
1595     NULL
1596 };
1597 
1598 /* Initialize a PCI NIC.  */
1599 /* FIXME callers should check for failure, but don't */
1600 PCIDevice *pci_nic_init(NICInfo *nd, PCIBus *rootbus,
1601                         const char *default_model,
1602                         const char *default_devaddr)
1603 {
1604     const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
1605     PCIBus *bus;
1606     int devfn;
1607     PCIDevice *pci_dev;
1608     DeviceState *dev;
1609     int i;
1610 
1611     i = qemu_find_nic_model(nd, pci_nic_models, default_model);
1612     if (i < 0)
1613         return NULL;
1614 
1615     bus = pci_get_bus_devfn(&devfn, rootbus, devaddr);
1616     if (!bus) {
1617         error_report("Invalid PCI device address %s for device %s",
1618                      devaddr, pci_nic_names[i]);
1619         return NULL;
1620     }
1621 
1622     pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
1623     dev = &pci_dev->qdev;
1624     qdev_set_nic_properties(dev, nd);
1625     if (qdev_init(dev) < 0)
1626         return NULL;
1627     return pci_dev;
1628 }
1629 
1630 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus,
1631                                const char *default_model,
1632                                const char *default_devaddr)
1633 {
1634     PCIDevice *res;
1635 
1636     if (qemu_show_nic_models(nd->model, pci_nic_models))
1637         exit(0);
1638 
1639     res = pci_nic_init(nd, rootbus, default_model, default_devaddr);
1640     if (!res)
1641         exit(1);
1642     return res;
1643 }
1644 
1645 PCIDevice *pci_vga_init(PCIBus *bus)
1646 {
1647     switch (vga_interface_type) {
1648     case VGA_CIRRUS:
1649         return pci_create_simple(bus, -1, "cirrus-vga");
1650     case VGA_QXL:
1651         return pci_create_simple(bus, -1, "qxl-vga");
1652     case VGA_STD:
1653         return pci_create_simple(bus, -1, "VGA");
1654     case VGA_VMWARE:
1655         return pci_create_simple(bus, -1, "vmware-svga");
1656     case VGA_NONE:
1657     default: /* Other non-PCI types. Checking for unsupported types is already
1658                 done in vl.c. */
1659         return NULL;
1660     }
1661 }
1662 
1663 /* Whether a given bus number is in range of the secondary
1664  * bus of the given bridge device. */
1665 static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num)
1666 {
1667     return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) &
1668              PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ &&
1669         dev->config[PCI_SECONDARY_BUS] < bus_num &&
1670         bus_num <= dev->config[PCI_SUBORDINATE_BUS];
1671 }
1672 
1673 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num)
1674 {
1675     PCIBus *sec;
1676 
1677     if (!bus) {
1678         return NULL;
1679     }
1680 
1681     if (pci_bus_num(bus) == bus_num) {
1682         return bus;
1683     }
1684 
1685     /* Consider all bus numbers in range for the host pci bridge. */
1686     if (!pci_bus_is_root(bus) &&
1687         !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) {
1688         return NULL;
1689     }
1690 
1691     /* try child bus */
1692     for (; bus; bus = sec) {
1693         QLIST_FOREACH(sec, &bus->child, sibling) {
1694             assert(!pci_bus_is_root(sec));
1695             if (sec->parent_dev->config[PCI_SECONDARY_BUS] == bus_num) {
1696                 return sec;
1697             }
1698             if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) {
1699                 break;
1700             }
1701         }
1702     }
1703 
1704     return NULL;
1705 }
1706 
1707 void pci_for_each_bus_depth_first(PCIBus *bus,
1708                                   void *(*begin)(PCIBus *bus, void *parent_state),
1709                                   void (*end)(PCIBus *bus, void *state),
1710                                   void *parent_state)
1711 {
1712     PCIBus *sec;
1713     void *state;
1714 
1715     if (!bus) {
1716         return;
1717     }
1718 
1719     if (begin) {
1720         state = begin(bus, parent_state);
1721     } else {
1722         state = parent_state;
1723     }
1724 
1725     QLIST_FOREACH(sec, &bus->child, sibling) {
1726         pci_for_each_bus_depth_first(sec, begin, end, state);
1727     }
1728 
1729     if (end) {
1730         end(bus, state);
1731     }
1732 }
1733 
1734 
1735 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn)
1736 {
1737     bus = pci_find_bus_nr(bus, bus_num);
1738 
1739     if (!bus)
1740         return NULL;
1741 
1742     return bus->devices[devfn];
1743 }
1744 
1745 static int pci_qdev_init(DeviceState *qdev)
1746 {
1747     PCIDevice *pci_dev = (PCIDevice *)qdev;
1748     PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
1749     PCIBus *bus;
1750     int rc;
1751     bool is_default_rom;
1752 
1753     /* initialize cap_present for pci_is_express() and pci_config_size() */
1754     if (pc->is_express) {
1755         pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
1756     }
1757 
1758     bus = PCI_BUS(qdev_get_parent_bus(qdev));
1759     pci_dev = do_pci_register_device(pci_dev, bus,
1760                                      object_get_typename(OBJECT(qdev)),
1761                                      pci_dev->devfn);
1762     if (pci_dev == NULL)
1763         return -1;
1764 
1765     if (pc->init) {
1766         rc = pc->init(pci_dev);
1767         if (rc != 0) {
1768             do_pci_unregister_device(pci_dev);
1769             return rc;
1770         }
1771     }
1772 
1773     /* rom loading */
1774     is_default_rom = false;
1775     if (pci_dev->romfile == NULL && pc->romfile != NULL) {
1776         pci_dev->romfile = g_strdup(pc->romfile);
1777         is_default_rom = true;
1778     }
1779     pci_add_option_rom(pci_dev, is_default_rom);
1780 
1781     return 0;
1782 }
1783 
1784 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
1785                                     const char *name)
1786 {
1787     DeviceState *dev;
1788 
1789     dev = qdev_create(&bus->qbus, name);
1790     qdev_prop_set_int32(dev, "addr", devfn);
1791     qdev_prop_set_bit(dev, "multifunction", multifunction);
1792     return PCI_DEVICE(dev);
1793 }
1794 
1795 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
1796                                            bool multifunction,
1797                                            const char *name)
1798 {
1799     PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name);
1800     qdev_init_nofail(&dev->qdev);
1801     return dev;
1802 }
1803 
1804 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
1805 {
1806     return pci_create_multifunction(bus, devfn, false, name);
1807 }
1808 
1809 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
1810 {
1811     return pci_create_simple_multifunction(bus, devfn, false, name);
1812 }
1813 
1814 static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size)
1815 {
1816     int offset = PCI_CONFIG_HEADER_SIZE;
1817     int i;
1818     for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) {
1819         if (pdev->used[i])
1820             offset = i + 1;
1821         else if (i - offset + 1 == size)
1822             return offset;
1823     }
1824     return 0;
1825 }
1826 
1827 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
1828                                         uint8_t *prev_p)
1829 {
1830     uint8_t next, prev;
1831 
1832     if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
1833         return 0;
1834 
1835     for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1836          prev = next + PCI_CAP_LIST_NEXT)
1837         if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
1838             break;
1839 
1840     if (prev_p)
1841         *prev_p = prev;
1842     return next;
1843 }
1844 
1845 static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset)
1846 {
1847     uint8_t next, prev, found = 0;
1848 
1849     if (!(pdev->used[offset])) {
1850         return 0;
1851     }
1852 
1853     assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST);
1854 
1855     for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1856          prev = next + PCI_CAP_LIST_NEXT) {
1857         if (next <= offset && next > found) {
1858             found = next;
1859         }
1860     }
1861     return found;
1862 }
1863 
1864 /* Patch the PCI vendor and device ids in a PCI rom image if necessary.
1865    This is needed for an option rom which is used for more than one device. */
1866 static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size)
1867 {
1868     uint16_t vendor_id;
1869     uint16_t device_id;
1870     uint16_t rom_vendor_id;
1871     uint16_t rom_device_id;
1872     uint16_t rom_magic;
1873     uint16_t pcir_offset;
1874     uint8_t checksum;
1875 
1876     /* Words in rom data are little endian (like in PCI configuration),
1877        so they can be read / written with pci_get_word / pci_set_word. */
1878 
1879     /* Only a valid rom will be patched. */
1880     rom_magic = pci_get_word(ptr);
1881     if (rom_magic != 0xaa55) {
1882         PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic);
1883         return;
1884     }
1885     pcir_offset = pci_get_word(ptr + 0x18);
1886     if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) {
1887         PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset);
1888         return;
1889     }
1890 
1891     vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID);
1892     device_id = pci_get_word(pdev->config + PCI_DEVICE_ID);
1893     rom_vendor_id = pci_get_word(ptr + pcir_offset + 4);
1894     rom_device_id = pci_get_word(ptr + pcir_offset + 6);
1895 
1896     PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile,
1897                 vendor_id, device_id, rom_vendor_id, rom_device_id);
1898 
1899     checksum = ptr[6];
1900 
1901     if (vendor_id != rom_vendor_id) {
1902         /* Patch vendor id and checksum (at offset 6 for etherboot roms). */
1903         checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8);
1904         checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8);
1905         PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
1906         ptr[6] = checksum;
1907         pci_set_word(ptr + pcir_offset + 4, vendor_id);
1908     }
1909 
1910     if (device_id != rom_device_id) {
1911         /* Patch device id and checksum (at offset 6 for etherboot roms). */
1912         checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8);
1913         checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8);
1914         PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
1915         ptr[6] = checksum;
1916         pci_set_word(ptr + pcir_offset + 6, device_id);
1917     }
1918 }
1919 
1920 /* Add an option rom for the device */
1921 static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom)
1922 {
1923     int size;
1924     char *path;
1925     void *ptr;
1926     char name[32];
1927     const VMStateDescription *vmsd;
1928 
1929     if (!pdev->romfile)
1930         return 0;
1931     if (strlen(pdev->romfile) == 0)
1932         return 0;
1933 
1934     if (!pdev->rom_bar) {
1935         /*
1936          * Load rom via fw_cfg instead of creating a rom bar,
1937          * for 0.11 compatibility.
1938          */
1939         int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
1940         if (class == 0x0300) {
1941             rom_add_vga(pdev->romfile);
1942         } else {
1943             rom_add_option(pdev->romfile, -1);
1944         }
1945         return 0;
1946     }
1947 
1948     path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile);
1949     if (path == NULL) {
1950         path = g_strdup(pdev->romfile);
1951     }
1952 
1953     size = get_image_size(path);
1954     if (size < 0) {
1955         error_report("%s: failed to find romfile \"%s\"",
1956                      __func__, pdev->romfile);
1957         g_free(path);
1958         return -1;
1959     } else if (size == 0) {
1960         error_report("%s: ignoring empty romfile \"%s\"",
1961                      __func__, pdev->romfile);
1962         g_free(path);
1963         return -1;
1964     }
1965     if (size & (size - 1)) {
1966         size = 1 << qemu_fls(size);
1967     }
1968 
1969     vmsd = qdev_get_vmsd(DEVICE(pdev));
1970 
1971     if (vmsd) {
1972         snprintf(name, sizeof(name), "%s.rom", vmsd->name);
1973     } else {
1974         snprintf(name, sizeof(name), "%s.rom", object_get_typename(OBJECT(pdev)));
1975     }
1976     pdev->has_rom = true;
1977     memory_region_init_ram(&pdev->rom, OBJECT(pdev), name, size);
1978     vmstate_register_ram(&pdev->rom, &pdev->qdev);
1979     ptr = memory_region_get_ram_ptr(&pdev->rom);
1980     load_image(path, ptr);
1981     g_free(path);
1982 
1983     if (is_default_rom) {
1984         /* Only the default rom images will be patched (if needed). */
1985         pci_patch_ids(pdev, ptr, size);
1986     }
1987 
1988     pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom);
1989 
1990     return 0;
1991 }
1992 
1993 static void pci_del_option_rom(PCIDevice *pdev)
1994 {
1995     if (!pdev->has_rom)
1996         return;
1997 
1998     vmstate_unregister_ram(&pdev->rom, &pdev->qdev);
1999     memory_region_destroy(&pdev->rom);
2000     pdev->has_rom = false;
2001 }
2002 
2003 /*
2004  * if !offset
2005  * Reserve space and add capability to the linked list in pci config space
2006  *
2007  * if offset = 0,
2008  * Find and reserve space and add capability to the linked list
2009  * in pci config space */
2010 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
2011                        uint8_t offset, uint8_t size)
2012 {
2013     int ret;
2014     Error *local_err = NULL;
2015 
2016     ret = pci_add_capability2(pdev, cap_id, offset, size, &local_err);
2017     if (local_err) {
2018         assert(ret < 0);
2019         error_report("%s", error_get_pretty(local_err));
2020         error_free(local_err);
2021     } else {
2022         /* success implies a positive offset in config space */
2023         assert(ret > 0);
2024     }
2025     return ret;
2026 }
2027 
2028 int pci_add_capability2(PCIDevice *pdev, uint8_t cap_id,
2029                        uint8_t offset, uint8_t size,
2030                        Error **errp)
2031 {
2032     uint8_t *config;
2033     int i, overlapping_cap;
2034 
2035     if (!offset) {
2036         offset = pci_find_space(pdev, size);
2037         if (!offset) {
2038             error_setg(errp, "out of PCI config space");
2039             return -ENOSPC;
2040         }
2041     } else {
2042         /* Verify that capabilities don't overlap.  Note: device assignment
2043          * depends on this check to verify that the device is not broken.
2044          * Should never trigger for emulated devices, but it's helpful
2045          * for debugging these. */
2046         for (i = offset; i < offset + size; i++) {
2047             overlapping_cap = pci_find_capability_at_offset(pdev, i);
2048             if (overlapping_cap) {
2049                 error_setg(errp, "%s:%02x:%02x.%x "
2050                            "Attempt to add PCI capability %x at offset "
2051                            "%x overlaps existing capability %x at offset %x",
2052                            pci_root_bus_path(pdev), pci_bus_num(pdev->bus),
2053                            PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
2054                            cap_id, offset, overlapping_cap, i);
2055                 return -EINVAL;
2056             }
2057         }
2058     }
2059 
2060     config = pdev->config + offset;
2061     config[PCI_CAP_LIST_ID] = cap_id;
2062     config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
2063     pdev->config[PCI_CAPABILITY_LIST] = offset;
2064     pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
2065     memset(pdev->used + offset, 0xFF, QEMU_ALIGN_UP(size, 4));
2066     /* Make capability read-only by default */
2067     memset(pdev->wmask + offset, 0, size);
2068     /* Check capability by default */
2069     memset(pdev->cmask + offset, 0xFF, size);
2070     return offset;
2071 }
2072 
2073 /* Unlink capability from the pci config space. */
2074 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
2075 {
2076     uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
2077     if (!offset)
2078         return;
2079     pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
2080     /* Make capability writable again */
2081     memset(pdev->wmask + offset, 0xff, size);
2082     memset(pdev->w1cmask + offset, 0, size);
2083     /* Clear cmask as device-specific registers can't be checked */
2084     memset(pdev->cmask + offset, 0, size);
2085     memset(pdev->used + offset, 0, QEMU_ALIGN_UP(size, 4));
2086 
2087     if (!pdev->config[PCI_CAPABILITY_LIST])
2088         pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
2089 }
2090 
2091 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
2092 {
2093     return pci_find_capability_list(pdev, cap_id, NULL);
2094 }
2095 
2096 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
2097 {
2098     PCIDevice *d = (PCIDevice *)dev;
2099     const pci_class_desc *desc;
2100     char ctxt[64];
2101     PCIIORegion *r;
2102     int i, class;
2103 
2104     class = pci_get_word(d->config + PCI_CLASS_DEVICE);
2105     desc = pci_class_descriptions;
2106     while (desc->desc && class != desc->class)
2107         desc++;
2108     if (desc->desc) {
2109         snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
2110     } else {
2111         snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
2112     }
2113 
2114     monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
2115                    "pci id %04x:%04x (sub %04x:%04x)\n",
2116                    indent, "", ctxt, pci_bus_num(d->bus),
2117                    PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
2118                    pci_get_word(d->config + PCI_VENDOR_ID),
2119                    pci_get_word(d->config + PCI_DEVICE_ID),
2120                    pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
2121                    pci_get_word(d->config + PCI_SUBSYSTEM_ID));
2122     for (i = 0; i < PCI_NUM_REGIONS; i++) {
2123         r = &d->io_regions[i];
2124         if (!r->size)
2125             continue;
2126         monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
2127                        " [0x%"FMT_PCIBUS"]\n",
2128                        indent, "",
2129                        i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
2130                        r->addr, r->addr + r->size - 1);
2131     }
2132 }
2133 
2134 static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len)
2135 {
2136     PCIDevice *d = (PCIDevice *)dev;
2137     const char *name = NULL;
2138     const pci_class_desc *desc =  pci_class_descriptions;
2139     int class = pci_get_word(d->config + PCI_CLASS_DEVICE);
2140 
2141     while (desc->desc &&
2142           (class & ~desc->fw_ign_bits) !=
2143           (desc->class & ~desc->fw_ign_bits)) {
2144         desc++;
2145     }
2146 
2147     if (desc->desc) {
2148         name = desc->fw_name;
2149     }
2150 
2151     if (name) {
2152         pstrcpy(buf, len, name);
2153     } else {
2154         snprintf(buf, len, "pci%04x,%04x",
2155                  pci_get_word(d->config + PCI_VENDOR_ID),
2156                  pci_get_word(d->config + PCI_DEVICE_ID));
2157     }
2158 
2159     return buf;
2160 }
2161 
2162 static char *pcibus_get_fw_dev_path(DeviceState *dev)
2163 {
2164     PCIDevice *d = (PCIDevice *)dev;
2165     char path[50], name[33];
2166     int off;
2167 
2168     off = snprintf(path, sizeof(path), "%s@%x",
2169                    pci_dev_fw_name(dev, name, sizeof name),
2170                    PCI_SLOT(d->devfn));
2171     if (PCI_FUNC(d->devfn))
2172         snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn));
2173     return g_strdup(path);
2174 }
2175 
2176 static char *pcibus_get_dev_path(DeviceState *dev)
2177 {
2178     PCIDevice *d = container_of(dev, PCIDevice, qdev);
2179     PCIDevice *t;
2180     int slot_depth;
2181     /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function.
2182      * 00 is added here to make this format compatible with
2183      * domain:Bus:Slot.Func for systems without nested PCI bridges.
2184      * Slot.Function list specifies the slot and function numbers for all
2185      * devices on the path from root to the specific device. */
2186     const char *root_bus_path;
2187     int root_bus_len;
2188     char slot[] = ":SS.F";
2189     int slot_len = sizeof slot - 1 /* For '\0' */;
2190     int path_len;
2191     char *path, *p;
2192     int s;
2193 
2194     root_bus_path = pci_root_bus_path(d);
2195     root_bus_len = strlen(root_bus_path);
2196 
2197     /* Calculate # of slots on path between device and root. */;
2198     slot_depth = 0;
2199     for (t = d; t; t = t->bus->parent_dev) {
2200         ++slot_depth;
2201     }
2202 
2203     path_len = root_bus_len + slot_len * slot_depth;
2204 
2205     /* Allocate memory, fill in the terminating null byte. */
2206     path = g_malloc(path_len + 1 /* For '\0' */);
2207     path[path_len] = '\0';
2208 
2209     memcpy(path, root_bus_path, root_bus_len);
2210 
2211     /* Fill in slot numbers. We walk up from device to root, so need to print
2212      * them in the reverse order, last to first. */
2213     p = path + path_len;
2214     for (t = d; t; t = t->bus->parent_dev) {
2215         p -= slot_len;
2216         s = snprintf(slot, sizeof slot, ":%02x.%x",
2217                      PCI_SLOT(t->devfn), PCI_FUNC(t->devfn));
2218         assert(s == slot_len);
2219         memcpy(p, slot, slot_len);
2220     }
2221 
2222     return path;
2223 }
2224 
2225 static int pci_qdev_find_recursive(PCIBus *bus,
2226                                    const char *id, PCIDevice **pdev)
2227 {
2228     DeviceState *qdev = qdev_find_recursive(&bus->qbus, id);
2229     if (!qdev) {
2230         return -ENODEV;
2231     }
2232 
2233     /* roughly check if given qdev is pci device */
2234     if (object_dynamic_cast(OBJECT(qdev), TYPE_PCI_DEVICE)) {
2235         *pdev = PCI_DEVICE(qdev);
2236         return 0;
2237     }
2238     return -EINVAL;
2239 }
2240 
2241 int pci_qdev_find_device(const char *id, PCIDevice **pdev)
2242 {
2243     PCIHostState *host_bridge;
2244     int rc = -ENODEV;
2245 
2246     QLIST_FOREACH(host_bridge, &pci_host_bridges, next) {
2247         int tmp = pci_qdev_find_recursive(host_bridge->bus, id, pdev);
2248         if (!tmp) {
2249             rc = 0;
2250             break;
2251         }
2252         if (tmp != -ENODEV) {
2253             rc = tmp;
2254         }
2255     }
2256 
2257     return rc;
2258 }
2259 
2260 MemoryRegion *pci_address_space(PCIDevice *dev)
2261 {
2262     return dev->bus->address_space_mem;
2263 }
2264 
2265 MemoryRegion *pci_address_space_io(PCIDevice *dev)
2266 {
2267     return dev->bus->address_space_io;
2268 }
2269 
2270 static void pci_device_class_init(ObjectClass *klass, void *data)
2271 {
2272     DeviceClass *k = DEVICE_CLASS(klass);
2273     k->init = pci_qdev_init;
2274     k->exit = pci_unregister_device;
2275     k->bus_type = TYPE_PCI_BUS;
2276     k->props = pci_props;
2277 }
2278 
2279 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev)
2280 {
2281     PCIBus *bus = PCI_BUS(dev->bus);
2282 
2283     if (bus->iommu_fn) {
2284         return bus->iommu_fn(bus, bus->iommu_opaque, dev->devfn);
2285     }
2286 
2287     if (bus->parent_dev) {
2288         /** We are ignoring the bus master DMA bit of the bridge
2289          *  as it would complicate things such as VFIO for no good reason */
2290         return pci_device_iommu_address_space(bus->parent_dev);
2291     }
2292 
2293     return &address_space_memory;
2294 }
2295 
2296 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque)
2297 {
2298     bus->iommu_fn = fn;
2299     bus->iommu_opaque = opaque;
2300 }
2301 
2302 static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque)
2303 {
2304     Range *range = opaque;
2305     PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
2306     uint16_t cmd = pci_get_word(dev->config + PCI_COMMAND);
2307     int i;
2308 
2309     if (!(cmd & PCI_COMMAND_MEMORY)) {
2310         return;
2311     }
2312 
2313     if (pc->is_bridge) {
2314         pcibus_t base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
2315         pcibus_t limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
2316 
2317         base = MAX(base, 0x1ULL << 32);
2318 
2319         if (limit >= base) {
2320             Range pref_range;
2321             pref_range.begin = base;
2322             pref_range.end = limit + 1;
2323             range_extend(range, &pref_range);
2324         }
2325     }
2326     for (i = 0; i < PCI_NUM_REGIONS; ++i) {
2327         PCIIORegion *r = &dev->io_regions[i];
2328         Range region_range;
2329 
2330         if (!r->size ||
2331             (r->type & PCI_BASE_ADDRESS_SPACE_IO) ||
2332             !(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64)) {
2333             continue;
2334         }
2335         region_range.begin = pci_bar_address(dev, i, r->type, r->size);
2336         region_range.end = region_range.begin + r->size;
2337 
2338         if (region_range.begin == PCI_BAR_UNMAPPED) {
2339             continue;
2340         }
2341 
2342         region_range.begin = MAX(region_range.begin, 0x1ULL << 32);
2343 
2344         if (region_range.end - 1 >= region_range.begin) {
2345             range_extend(range, &region_range);
2346         }
2347     }
2348 }
2349 
2350 void pci_bus_get_w64_range(PCIBus *bus, Range *range)
2351 {
2352     range->begin = range->end = 0;
2353     pci_for_each_device_under_bus(bus, pci_dev_get_w64, range);
2354 }
2355 
2356 static const TypeInfo pci_device_type_info = {
2357     .name = TYPE_PCI_DEVICE,
2358     .parent = TYPE_DEVICE,
2359     .instance_size = sizeof(PCIDevice),
2360     .abstract = true,
2361     .class_size = sizeof(PCIDeviceClass),
2362     .class_init = pci_device_class_init,
2363 };
2364 
2365 static void pci_register_types(void)
2366 {
2367     type_register_static(&pci_bus_info);
2368     type_register_static(&pcie_bus_info);
2369     type_register_static(&pci_device_type_info);
2370 }
2371 
2372 type_init(pci_register_types)
2373