1 /* 2 * QEMU PCI bus manager 3 * 4 * Copyright (c) 2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/datadir.h" 27 #include "qemu/units.h" 28 #include "hw/irq.h" 29 #include "hw/pci/pci.h" 30 #include "hw/pci/pci_bridge.h" 31 #include "hw/pci/pci_bus.h" 32 #include "hw/pci/pci_host.h" 33 #include "hw/qdev-properties.h" 34 #include "hw/qdev-properties-system.h" 35 #include "migration/qemu-file-types.h" 36 #include "migration/vmstate.h" 37 #include "net/net.h" 38 #include "sysemu/numa.h" 39 #include "sysemu/runstate.h" 40 #include "sysemu/sysemu.h" 41 #include "hw/loader.h" 42 #include "qemu/error-report.h" 43 #include "qemu/range.h" 44 #include "trace.h" 45 #include "hw/pci/msi.h" 46 #include "hw/pci/msix.h" 47 #include "hw/hotplug.h" 48 #include "hw/boards.h" 49 #include "qapi/error.h" 50 #include "qemu/cutils.h" 51 #include "pci-internal.h" 52 53 #include "hw/xen/xen.h" 54 #include "hw/i386/kvm/xen_evtchn.h" 55 56 //#define DEBUG_PCI 57 #ifdef DEBUG_PCI 58 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) 59 #else 60 # define PCI_DPRINTF(format, ...) do { } while (0) 61 #endif 62 63 bool pci_available = true; 64 65 static char *pcibus_get_dev_path(DeviceState *dev); 66 static char *pcibus_get_fw_dev_path(DeviceState *dev); 67 static void pcibus_reset(BusState *qbus); 68 static bool pcie_has_upstream_port(PCIDevice *dev); 69 70 static Property pci_props[] = { 71 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1), 72 DEFINE_PROP_STRING("romfile", PCIDevice, romfile), 73 DEFINE_PROP_UINT32("romsize", PCIDevice, romsize, -1), 74 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1), 75 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present, 76 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false), 77 DEFINE_PROP_BIT("x-pcie-lnksta-dllla", PCIDevice, cap_present, 78 QEMU_PCIE_LNKSTA_DLLLA_BITNR, true), 79 DEFINE_PROP_BIT("x-pcie-extcap-init", PCIDevice, cap_present, 80 QEMU_PCIE_EXTCAP_INIT_BITNR, true), 81 DEFINE_PROP_STRING("failover_pair_id", PCIDevice, 82 failover_pair_id), 83 DEFINE_PROP_UINT32("acpi-index", PCIDevice, acpi_index, 0), 84 DEFINE_PROP_BIT("x-pcie-err-unc-mask", PCIDevice, cap_present, 85 QEMU_PCIE_ERR_UNC_MASK_BITNR, true), 86 DEFINE_PROP_BIT("x-pcie-ari-nextfn-1", PCIDevice, cap_present, 87 QEMU_PCIE_ARI_NEXTFN_1_BITNR, false), 88 DEFINE_PROP_END_OF_LIST() 89 }; 90 91 static const VMStateDescription vmstate_pcibus = { 92 .name = "PCIBUS", 93 .version_id = 1, 94 .minimum_version_id = 1, 95 .fields = (VMStateField[]) { 96 VMSTATE_INT32_EQUAL(nirq, PCIBus, NULL), 97 VMSTATE_VARRAY_INT32(irq_count, PCIBus, 98 nirq, 0, vmstate_info_int32, 99 int32_t), 100 VMSTATE_END_OF_LIST() 101 } 102 }; 103 104 static gint g_cmp_uint32(gconstpointer a, gconstpointer b, gpointer user_data) 105 { 106 return a - b; 107 } 108 109 static GSequence *pci_acpi_index_list(void) 110 { 111 static GSequence *used_acpi_index_list; 112 113 if (!used_acpi_index_list) { 114 used_acpi_index_list = g_sequence_new(NULL); 115 } 116 return used_acpi_index_list; 117 } 118 119 static void pci_init_bus_master(PCIDevice *pci_dev) 120 { 121 AddressSpace *dma_as = pci_device_iommu_address_space(pci_dev); 122 123 memory_region_init_alias(&pci_dev->bus_master_enable_region, 124 OBJECT(pci_dev), "bus master", 125 dma_as->root, 0, memory_region_size(dma_as->root)); 126 memory_region_set_enabled(&pci_dev->bus_master_enable_region, false); 127 memory_region_add_subregion(&pci_dev->bus_master_container_region, 0, 128 &pci_dev->bus_master_enable_region); 129 } 130 131 static void pcibus_machine_done(Notifier *notifier, void *data) 132 { 133 PCIBus *bus = container_of(notifier, PCIBus, machine_done); 134 int i; 135 136 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 137 if (bus->devices[i]) { 138 pci_init_bus_master(bus->devices[i]); 139 } 140 } 141 } 142 143 static void pci_bus_realize(BusState *qbus, Error **errp) 144 { 145 PCIBus *bus = PCI_BUS(qbus); 146 147 bus->machine_done.notify = pcibus_machine_done; 148 qemu_add_machine_init_done_notifier(&bus->machine_done); 149 150 vmstate_register(NULL, VMSTATE_INSTANCE_ID_ANY, &vmstate_pcibus, bus); 151 } 152 153 static void pcie_bus_realize(BusState *qbus, Error **errp) 154 { 155 PCIBus *bus = PCI_BUS(qbus); 156 Error *local_err = NULL; 157 158 pci_bus_realize(qbus, &local_err); 159 if (local_err) { 160 error_propagate(errp, local_err); 161 return; 162 } 163 164 /* 165 * A PCI-E bus can support extended config space if it's the root 166 * bus, or if the bus/bridge above it does as well 167 */ 168 if (pci_bus_is_root(bus)) { 169 bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE; 170 } else { 171 PCIBus *parent_bus = pci_get_bus(bus->parent_dev); 172 173 if (pci_bus_allows_extended_config_space(parent_bus)) { 174 bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE; 175 } 176 } 177 } 178 179 static void pci_bus_unrealize(BusState *qbus) 180 { 181 PCIBus *bus = PCI_BUS(qbus); 182 183 qemu_remove_machine_init_done_notifier(&bus->machine_done); 184 185 vmstate_unregister(NULL, &vmstate_pcibus, bus); 186 } 187 188 static int pcibus_num(PCIBus *bus) 189 { 190 if (pci_bus_is_root(bus)) { 191 return 0; /* pci host bridge */ 192 } 193 return bus->parent_dev->config[PCI_SECONDARY_BUS]; 194 } 195 196 static uint16_t pcibus_numa_node(PCIBus *bus) 197 { 198 return NUMA_NODE_UNASSIGNED; 199 } 200 201 static void pci_bus_class_init(ObjectClass *klass, void *data) 202 { 203 BusClass *k = BUS_CLASS(klass); 204 PCIBusClass *pbc = PCI_BUS_CLASS(klass); 205 206 k->print_dev = pcibus_dev_print; 207 k->get_dev_path = pcibus_get_dev_path; 208 k->get_fw_dev_path = pcibus_get_fw_dev_path; 209 k->realize = pci_bus_realize; 210 k->unrealize = pci_bus_unrealize; 211 k->reset = pcibus_reset; 212 213 pbc->bus_num = pcibus_num; 214 pbc->numa_node = pcibus_numa_node; 215 } 216 217 static const TypeInfo pci_bus_info = { 218 .name = TYPE_PCI_BUS, 219 .parent = TYPE_BUS, 220 .instance_size = sizeof(PCIBus), 221 .class_size = sizeof(PCIBusClass), 222 .class_init = pci_bus_class_init, 223 }; 224 225 static const TypeInfo cxl_interface_info = { 226 .name = INTERFACE_CXL_DEVICE, 227 .parent = TYPE_INTERFACE, 228 }; 229 230 static const TypeInfo pcie_interface_info = { 231 .name = INTERFACE_PCIE_DEVICE, 232 .parent = TYPE_INTERFACE, 233 }; 234 235 static const TypeInfo conventional_pci_interface_info = { 236 .name = INTERFACE_CONVENTIONAL_PCI_DEVICE, 237 .parent = TYPE_INTERFACE, 238 }; 239 240 static void pcie_bus_class_init(ObjectClass *klass, void *data) 241 { 242 BusClass *k = BUS_CLASS(klass); 243 244 k->realize = pcie_bus_realize; 245 } 246 247 static const TypeInfo pcie_bus_info = { 248 .name = TYPE_PCIE_BUS, 249 .parent = TYPE_PCI_BUS, 250 .class_init = pcie_bus_class_init, 251 }; 252 253 static const TypeInfo cxl_bus_info = { 254 .name = TYPE_CXL_BUS, 255 .parent = TYPE_PCIE_BUS, 256 .class_init = pcie_bus_class_init, 257 }; 258 259 static void pci_update_mappings(PCIDevice *d); 260 static void pci_irq_handler(void *opaque, int irq_num, int level); 261 static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, Error **); 262 static void pci_del_option_rom(PCIDevice *pdev); 263 264 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET; 265 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU; 266 267 PCIHostStateList pci_host_bridges; 268 269 int pci_bar(PCIDevice *d, int reg) 270 { 271 uint8_t type; 272 273 /* PCIe virtual functions do not have their own BARs */ 274 assert(!pci_is_vf(d)); 275 276 if (reg != PCI_ROM_SLOT) 277 return PCI_BASE_ADDRESS_0 + reg * 4; 278 279 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 280 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS; 281 } 282 283 static inline int pci_irq_state(PCIDevice *d, int irq_num) 284 { 285 return (d->irq_state >> irq_num) & 0x1; 286 } 287 288 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level) 289 { 290 d->irq_state &= ~(0x1 << irq_num); 291 d->irq_state |= level << irq_num; 292 } 293 294 static void pci_bus_change_irq_level(PCIBus *bus, int irq_num, int change) 295 { 296 assert(irq_num >= 0); 297 assert(irq_num < bus->nirq); 298 bus->irq_count[irq_num] += change; 299 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0); 300 } 301 302 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change) 303 { 304 PCIBus *bus; 305 for (;;) { 306 int dev_irq = irq_num; 307 bus = pci_get_bus(pci_dev); 308 assert(bus->map_irq); 309 irq_num = bus->map_irq(pci_dev, irq_num); 310 trace_pci_route_irq(dev_irq, DEVICE(pci_dev)->canonical_path, irq_num, 311 pci_bus_is_root(bus) ? "root-complex" 312 : DEVICE(bus->parent_dev)->canonical_path); 313 if (bus->set_irq) 314 break; 315 pci_dev = bus->parent_dev; 316 } 317 pci_bus_change_irq_level(bus, irq_num, change); 318 } 319 320 int pci_bus_get_irq_level(PCIBus *bus, int irq_num) 321 { 322 assert(irq_num >= 0); 323 assert(irq_num < bus->nirq); 324 return !!bus->irq_count[irq_num]; 325 } 326 327 /* Update interrupt status bit in config space on interrupt 328 * state change. */ 329 static void pci_update_irq_status(PCIDevice *dev) 330 { 331 if (dev->irq_state) { 332 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT; 333 } else { 334 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; 335 } 336 } 337 338 void pci_device_deassert_intx(PCIDevice *dev) 339 { 340 int i; 341 for (i = 0; i < PCI_NUM_PINS; ++i) { 342 pci_irq_handler(dev, i, 0); 343 } 344 } 345 346 static void pci_msi_trigger(PCIDevice *dev, MSIMessage msg) 347 { 348 MemTxAttrs attrs = {}; 349 350 /* 351 * Xen uses the high bits of the address to contain some of the bits 352 * of the PIRQ#. Therefore we can't just send the write cycle and 353 * trust that it's caught by the APIC at 0xfee00000 because the 354 * target of the write might be e.g. 0x0x1000fee46000 for PIRQ#4166. 355 * So we intercept the delivery here instead of in kvm_send_msi(). 356 */ 357 if (xen_mode == XEN_EMULATE && 358 xen_evtchn_deliver_pirq_msi(msg.address, msg.data)) { 359 return; 360 } 361 attrs.requester_id = pci_requester_id(dev); 362 address_space_stl_le(&dev->bus_master_as, msg.address, msg.data, 363 attrs, NULL); 364 } 365 366 static void pci_reset_regions(PCIDevice *dev) 367 { 368 int r; 369 if (pci_is_vf(dev)) { 370 return; 371 } 372 373 for (r = 0; r < PCI_NUM_REGIONS; ++r) { 374 PCIIORegion *region = &dev->io_regions[r]; 375 if (!region->size) { 376 continue; 377 } 378 379 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) && 380 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 381 pci_set_quad(dev->config + pci_bar(dev, r), region->type); 382 } else { 383 pci_set_long(dev->config + pci_bar(dev, r), region->type); 384 } 385 } 386 } 387 388 static void pci_do_device_reset(PCIDevice *dev) 389 { 390 pci_device_deassert_intx(dev); 391 assert(dev->irq_state == 0); 392 393 /* Clear all writable bits */ 394 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND, 395 pci_get_word(dev->wmask + PCI_COMMAND) | 396 pci_get_word(dev->w1cmask + PCI_COMMAND)); 397 pci_word_test_and_clear_mask(dev->config + PCI_STATUS, 398 pci_get_word(dev->wmask + PCI_STATUS) | 399 pci_get_word(dev->w1cmask + PCI_STATUS)); 400 /* Some devices make bits of PCI_INTERRUPT_LINE read only */ 401 pci_byte_test_and_clear_mask(dev->config + PCI_INTERRUPT_LINE, 402 pci_get_word(dev->wmask + PCI_INTERRUPT_LINE) | 403 pci_get_word(dev->w1cmask + PCI_INTERRUPT_LINE)); 404 dev->config[PCI_CACHE_LINE_SIZE] = 0x0; 405 pci_reset_regions(dev); 406 pci_update_mappings(dev); 407 408 msi_reset(dev); 409 msix_reset(dev); 410 } 411 412 /* 413 * This function is called on #RST and FLR. 414 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set 415 */ 416 void pci_device_reset(PCIDevice *dev) 417 { 418 device_cold_reset(&dev->qdev); 419 pci_do_device_reset(dev); 420 } 421 422 /* 423 * Trigger pci bus reset under a given bus. 424 * Called via bus_cold_reset on RST# assert, after the devices 425 * have been reset device_cold_reset-ed already. 426 */ 427 static void pcibus_reset(BusState *qbus) 428 { 429 PCIBus *bus = DO_UPCAST(PCIBus, qbus, qbus); 430 int i; 431 432 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 433 if (bus->devices[i]) { 434 pci_do_device_reset(bus->devices[i]); 435 } 436 } 437 438 for (i = 0; i < bus->nirq; i++) { 439 assert(bus->irq_count[i] == 0); 440 } 441 } 442 443 static void pci_host_bus_register(DeviceState *host) 444 { 445 PCIHostState *host_bridge = PCI_HOST_BRIDGE(host); 446 447 QLIST_INSERT_HEAD(&pci_host_bridges, host_bridge, next); 448 } 449 450 static void pci_host_bus_unregister(DeviceState *host) 451 { 452 PCIHostState *host_bridge = PCI_HOST_BRIDGE(host); 453 454 QLIST_REMOVE(host_bridge, next); 455 } 456 457 PCIBus *pci_device_root_bus(const PCIDevice *d) 458 { 459 PCIBus *bus = pci_get_bus(d); 460 461 while (!pci_bus_is_root(bus)) { 462 d = bus->parent_dev; 463 assert(d != NULL); 464 465 bus = pci_get_bus(d); 466 } 467 468 return bus; 469 } 470 471 const char *pci_root_bus_path(PCIDevice *dev) 472 { 473 PCIBus *rootbus = pci_device_root_bus(dev); 474 PCIHostState *host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent); 475 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_GET_CLASS(host_bridge); 476 477 assert(host_bridge->bus == rootbus); 478 479 if (hc->root_bus_path) { 480 return (*hc->root_bus_path)(host_bridge, rootbus); 481 } 482 483 return rootbus->qbus.name; 484 } 485 486 bool pci_bus_bypass_iommu(PCIBus *bus) 487 { 488 PCIBus *rootbus = bus; 489 PCIHostState *host_bridge; 490 491 if (!pci_bus_is_root(bus)) { 492 rootbus = pci_device_root_bus(bus->parent_dev); 493 } 494 495 host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent); 496 497 assert(host_bridge->bus == rootbus); 498 499 return host_bridge->bypass_iommu; 500 } 501 502 static void pci_root_bus_internal_init(PCIBus *bus, DeviceState *parent, 503 MemoryRegion *address_space_mem, 504 MemoryRegion *address_space_io, 505 uint8_t devfn_min) 506 { 507 assert(PCI_FUNC(devfn_min) == 0); 508 bus->devfn_min = devfn_min; 509 bus->slot_reserved_mask = 0x0; 510 bus->address_space_mem = address_space_mem; 511 bus->address_space_io = address_space_io; 512 bus->flags |= PCI_BUS_IS_ROOT; 513 514 /* host bridge */ 515 QLIST_INIT(&bus->child); 516 517 pci_host_bus_register(parent); 518 } 519 520 static void pci_bus_uninit(PCIBus *bus) 521 { 522 pci_host_bus_unregister(BUS(bus)->parent); 523 } 524 525 bool pci_bus_is_express(const PCIBus *bus) 526 { 527 return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS); 528 } 529 530 void pci_root_bus_init(PCIBus *bus, size_t bus_size, DeviceState *parent, 531 const char *name, 532 MemoryRegion *address_space_mem, 533 MemoryRegion *address_space_io, 534 uint8_t devfn_min, const char *typename) 535 { 536 qbus_init(bus, bus_size, typename, parent, name); 537 pci_root_bus_internal_init(bus, parent, address_space_mem, 538 address_space_io, devfn_min); 539 } 540 541 PCIBus *pci_root_bus_new(DeviceState *parent, const char *name, 542 MemoryRegion *address_space_mem, 543 MemoryRegion *address_space_io, 544 uint8_t devfn_min, const char *typename) 545 { 546 PCIBus *bus; 547 548 bus = PCI_BUS(qbus_new(typename, parent, name)); 549 pci_root_bus_internal_init(bus, parent, address_space_mem, 550 address_space_io, devfn_min); 551 return bus; 552 } 553 554 void pci_root_bus_cleanup(PCIBus *bus) 555 { 556 pci_bus_uninit(bus); 557 /* the caller of the unplug hotplug handler will delete this device */ 558 qbus_unrealize(BUS(bus)); 559 } 560 561 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, 562 void *irq_opaque, int nirq) 563 { 564 bus->set_irq = set_irq; 565 bus->irq_opaque = irq_opaque; 566 bus->nirq = nirq; 567 g_free(bus->irq_count); 568 bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0])); 569 } 570 571 void pci_bus_map_irqs(PCIBus *bus, pci_map_irq_fn map_irq) 572 { 573 bus->map_irq = map_irq; 574 } 575 576 void pci_bus_irqs_cleanup(PCIBus *bus) 577 { 578 bus->set_irq = NULL; 579 bus->map_irq = NULL; 580 bus->irq_opaque = NULL; 581 bus->nirq = 0; 582 g_free(bus->irq_count); 583 bus->irq_count = NULL; 584 } 585 586 PCIBus *pci_register_root_bus(DeviceState *parent, const char *name, 587 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 588 void *irq_opaque, 589 MemoryRegion *address_space_mem, 590 MemoryRegion *address_space_io, 591 uint8_t devfn_min, int nirq, 592 const char *typename) 593 { 594 PCIBus *bus; 595 596 bus = pci_root_bus_new(parent, name, address_space_mem, 597 address_space_io, devfn_min, typename); 598 pci_bus_irqs(bus, set_irq, irq_opaque, nirq); 599 pci_bus_map_irqs(bus, map_irq); 600 return bus; 601 } 602 603 void pci_unregister_root_bus(PCIBus *bus) 604 { 605 pci_bus_irqs_cleanup(bus); 606 pci_root_bus_cleanup(bus); 607 } 608 609 int pci_bus_num(PCIBus *s) 610 { 611 return PCI_BUS_GET_CLASS(s)->bus_num(s); 612 } 613 614 /* Returns the min and max bus numbers of a PCI bus hierarchy */ 615 void pci_bus_range(PCIBus *bus, int *min_bus, int *max_bus) 616 { 617 int i; 618 *min_bus = *max_bus = pci_bus_num(bus); 619 620 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 621 PCIDevice *dev = bus->devices[i]; 622 623 if (dev && IS_PCI_BRIDGE(dev)) { 624 *min_bus = MIN(*min_bus, dev->config[PCI_SECONDARY_BUS]); 625 *max_bus = MAX(*max_bus, dev->config[PCI_SUBORDINATE_BUS]); 626 } 627 } 628 } 629 630 int pci_bus_numa_node(PCIBus *bus) 631 { 632 return PCI_BUS_GET_CLASS(bus)->numa_node(bus); 633 } 634 635 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size, 636 const VMStateField *field) 637 { 638 PCIDevice *s = container_of(pv, PCIDevice, config); 639 uint8_t *config; 640 int i; 641 642 assert(size == pci_config_size(s)); 643 config = g_malloc(size); 644 645 qemu_get_buffer(f, config, size); 646 for (i = 0; i < size; ++i) { 647 if ((config[i] ^ s->config[i]) & 648 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) { 649 error_report("%s: Bad config data: i=0x%x read: %x device: %x " 650 "cmask: %x wmask: %x w1cmask:%x", __func__, 651 i, config[i], s->config[i], 652 s->cmask[i], s->wmask[i], s->w1cmask[i]); 653 g_free(config); 654 return -EINVAL; 655 } 656 } 657 memcpy(s->config, config, size); 658 659 pci_update_mappings(s); 660 if (IS_PCI_BRIDGE(s)) { 661 pci_bridge_update_mappings(PCI_BRIDGE(s)); 662 } 663 664 memory_region_set_enabled(&s->bus_master_enable_region, 665 pci_get_word(s->config + PCI_COMMAND) 666 & PCI_COMMAND_MASTER); 667 668 g_free(config); 669 return 0; 670 } 671 672 /* just put buffer */ 673 static int put_pci_config_device(QEMUFile *f, void *pv, size_t size, 674 const VMStateField *field, JSONWriter *vmdesc) 675 { 676 const uint8_t **v = pv; 677 assert(size == pci_config_size(container_of(pv, PCIDevice, config))); 678 qemu_put_buffer(f, *v, size); 679 680 return 0; 681 } 682 683 static VMStateInfo vmstate_info_pci_config = { 684 .name = "pci config", 685 .get = get_pci_config_device, 686 .put = put_pci_config_device, 687 }; 688 689 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size, 690 const VMStateField *field) 691 { 692 PCIDevice *s = container_of(pv, PCIDevice, irq_state); 693 uint32_t irq_state[PCI_NUM_PINS]; 694 int i; 695 for (i = 0; i < PCI_NUM_PINS; ++i) { 696 irq_state[i] = qemu_get_be32(f); 697 if (irq_state[i] != 0x1 && irq_state[i] != 0) { 698 fprintf(stderr, "irq state %d: must be 0 or 1.\n", 699 irq_state[i]); 700 return -EINVAL; 701 } 702 } 703 704 for (i = 0; i < PCI_NUM_PINS; ++i) { 705 pci_set_irq_state(s, i, irq_state[i]); 706 } 707 708 return 0; 709 } 710 711 static int put_pci_irq_state(QEMUFile *f, void *pv, size_t size, 712 const VMStateField *field, JSONWriter *vmdesc) 713 { 714 int i; 715 PCIDevice *s = container_of(pv, PCIDevice, irq_state); 716 717 for (i = 0; i < PCI_NUM_PINS; ++i) { 718 qemu_put_be32(f, pci_irq_state(s, i)); 719 } 720 721 return 0; 722 } 723 724 static VMStateInfo vmstate_info_pci_irq_state = { 725 .name = "pci irq state", 726 .get = get_pci_irq_state, 727 .put = put_pci_irq_state, 728 }; 729 730 static bool migrate_is_pcie(void *opaque, int version_id) 731 { 732 return pci_is_express((PCIDevice *)opaque); 733 } 734 735 static bool migrate_is_not_pcie(void *opaque, int version_id) 736 { 737 return !pci_is_express((PCIDevice *)opaque); 738 } 739 740 const VMStateDescription vmstate_pci_device = { 741 .name = "PCIDevice", 742 .version_id = 2, 743 .minimum_version_id = 1, 744 .fields = (VMStateField[]) { 745 VMSTATE_INT32_POSITIVE_LE(version_id, PCIDevice), 746 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice, 747 migrate_is_not_pcie, 748 0, vmstate_info_pci_config, 749 PCI_CONFIG_SPACE_SIZE), 750 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice, 751 migrate_is_pcie, 752 0, vmstate_info_pci_config, 753 PCIE_CONFIG_SPACE_SIZE), 754 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2, 755 vmstate_info_pci_irq_state, 756 PCI_NUM_PINS * sizeof(int32_t)), 757 VMSTATE_END_OF_LIST() 758 } 759 }; 760 761 762 void pci_device_save(PCIDevice *s, QEMUFile *f) 763 { 764 /* Clear interrupt status bit: it is implicit 765 * in irq_state which we are saving. 766 * This makes us compatible with old devices 767 * which never set or clear this bit. */ 768 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; 769 vmstate_save_state(f, &vmstate_pci_device, s, NULL); 770 /* Restore the interrupt status bit. */ 771 pci_update_irq_status(s); 772 } 773 774 int pci_device_load(PCIDevice *s, QEMUFile *f) 775 { 776 int ret; 777 ret = vmstate_load_state(f, &vmstate_pci_device, s, s->version_id); 778 /* Restore the interrupt status bit. */ 779 pci_update_irq_status(s); 780 return ret; 781 } 782 783 static void pci_set_default_subsystem_id(PCIDevice *pci_dev) 784 { 785 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, 786 pci_default_sub_vendor_id); 787 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 788 pci_default_sub_device_id); 789 } 790 791 /* 792 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL 793 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error 794 */ 795 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, 796 unsigned int *slotp, unsigned int *funcp) 797 { 798 const char *p; 799 char *e; 800 unsigned long val; 801 unsigned long dom = 0, bus = 0; 802 unsigned int slot = 0; 803 unsigned int func = 0; 804 805 p = addr; 806 val = strtoul(p, &e, 16); 807 if (e == p) 808 return -1; 809 if (*e == ':') { 810 bus = val; 811 p = e + 1; 812 val = strtoul(p, &e, 16); 813 if (e == p) 814 return -1; 815 if (*e == ':') { 816 dom = bus; 817 bus = val; 818 p = e + 1; 819 val = strtoul(p, &e, 16); 820 if (e == p) 821 return -1; 822 } 823 } 824 825 slot = val; 826 827 if (funcp != NULL) { 828 if (*e != '.') 829 return -1; 830 831 p = e + 1; 832 val = strtoul(p, &e, 16); 833 if (e == p) 834 return -1; 835 836 func = val; 837 } 838 839 /* if funcp == NULL func is 0 */ 840 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7) 841 return -1; 842 843 if (*e) 844 return -1; 845 846 *domp = dom; 847 *busp = bus; 848 *slotp = slot; 849 if (funcp != NULL) 850 *funcp = func; 851 return 0; 852 } 853 854 static void pci_init_cmask(PCIDevice *dev) 855 { 856 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff); 857 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff); 858 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST; 859 dev->cmask[PCI_REVISION_ID] = 0xff; 860 dev->cmask[PCI_CLASS_PROG] = 0xff; 861 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff); 862 dev->cmask[PCI_HEADER_TYPE] = 0xff; 863 dev->cmask[PCI_CAPABILITY_LIST] = 0xff; 864 } 865 866 static void pci_init_wmask(PCIDevice *dev) 867 { 868 int config_size = pci_config_size(dev); 869 870 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff; 871 dev->wmask[PCI_INTERRUPT_LINE] = 0xff; 872 pci_set_word(dev->wmask + PCI_COMMAND, 873 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | 874 PCI_COMMAND_INTX_DISABLE); 875 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR); 876 877 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff, 878 config_size - PCI_CONFIG_HEADER_SIZE); 879 } 880 881 static void pci_init_w1cmask(PCIDevice *dev) 882 { 883 /* 884 * Note: It's okay to set w1cmask even for readonly bits as 885 * long as their value is hardwired to 0. 886 */ 887 pci_set_word(dev->w1cmask + PCI_STATUS, 888 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT | 889 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT | 890 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY); 891 } 892 893 static void pci_init_mask_bridge(PCIDevice *d) 894 { 895 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and 896 PCI_SEC_LETENCY_TIMER */ 897 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4); 898 899 /* base and limit */ 900 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff; 901 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff; 902 pci_set_word(d->wmask + PCI_MEMORY_BASE, 903 PCI_MEMORY_RANGE_MASK & 0xffff); 904 pci_set_word(d->wmask + PCI_MEMORY_LIMIT, 905 PCI_MEMORY_RANGE_MASK & 0xffff); 906 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE, 907 PCI_PREF_RANGE_MASK & 0xffff); 908 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT, 909 PCI_PREF_RANGE_MASK & 0xffff); 910 911 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */ 912 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8); 913 914 /* Supported memory and i/o types */ 915 d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16; 916 d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16; 917 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE, 918 PCI_PREF_RANGE_TYPE_64); 919 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT, 920 PCI_PREF_RANGE_TYPE_64); 921 922 /* 923 * TODO: Bridges default to 10-bit VGA decoding but we currently only 924 * implement 16-bit decoding (no alias support). 925 */ 926 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 927 PCI_BRIDGE_CTL_PARITY | 928 PCI_BRIDGE_CTL_SERR | 929 PCI_BRIDGE_CTL_ISA | 930 PCI_BRIDGE_CTL_VGA | 931 PCI_BRIDGE_CTL_VGA_16BIT | 932 PCI_BRIDGE_CTL_MASTER_ABORT | 933 PCI_BRIDGE_CTL_BUS_RESET | 934 PCI_BRIDGE_CTL_FAST_BACK | 935 PCI_BRIDGE_CTL_DISCARD | 936 PCI_BRIDGE_CTL_SEC_DISCARD | 937 PCI_BRIDGE_CTL_DISCARD_SERR); 938 /* Below does not do anything as we never set this bit, put here for 939 * completeness. */ 940 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL, 941 PCI_BRIDGE_CTL_DISCARD_STATUS); 942 d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK; 943 d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK; 944 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE, 945 PCI_PREF_RANGE_TYPE_MASK); 946 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT, 947 PCI_PREF_RANGE_TYPE_MASK); 948 } 949 950 static void pci_init_multifunction(PCIBus *bus, PCIDevice *dev, Error **errp) 951 { 952 uint8_t slot = PCI_SLOT(dev->devfn); 953 uint8_t func; 954 955 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 956 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION; 957 } 958 959 /* 960 * With SR/IOV and ARI, a device at function 0 need not be a multifunction 961 * device, as it may just be a VF that ended up with function 0 in 962 * the legacy PCI interpretation. Avoid failing in such cases: 963 */ 964 if (pci_is_vf(dev) && 965 dev->exp.sriov_vf.pf->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 966 return; 967 } 968 969 /* 970 * multifunction bit is interpreted in two ways as follows. 971 * - all functions must set the bit to 1. 972 * Example: Intel X53 973 * - function 0 must set the bit, but the rest function (> 0) 974 * is allowed to leave the bit to 0. 975 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10, 976 * 977 * So OS (at least Linux) checks the bit of only function 0, 978 * and doesn't see the bit of function > 0. 979 * 980 * The below check allows both interpretation. 981 */ 982 if (PCI_FUNC(dev->devfn)) { 983 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)]; 984 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) { 985 /* function 0 should set multifunction bit */ 986 error_setg(errp, "PCI: single function device can't be populated " 987 "in function %x.%x", slot, PCI_FUNC(dev->devfn)); 988 return; 989 } 990 return; 991 } 992 993 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 994 return; 995 } 996 /* function 0 indicates single function, so function > 0 must be NULL */ 997 for (func = 1; func < PCI_FUNC_MAX; ++func) { 998 if (bus->devices[PCI_DEVFN(slot, func)]) { 999 error_setg(errp, "PCI: %x.0 indicates single function, " 1000 "but %x.%x is already populated.", 1001 slot, slot, func); 1002 return; 1003 } 1004 } 1005 } 1006 1007 static void pci_config_alloc(PCIDevice *pci_dev) 1008 { 1009 int config_size = pci_config_size(pci_dev); 1010 1011 pci_dev->config = g_malloc0(config_size); 1012 pci_dev->cmask = g_malloc0(config_size); 1013 pci_dev->wmask = g_malloc0(config_size); 1014 pci_dev->w1cmask = g_malloc0(config_size); 1015 pci_dev->used = g_malloc0(config_size); 1016 } 1017 1018 static void pci_config_free(PCIDevice *pci_dev) 1019 { 1020 g_free(pci_dev->config); 1021 g_free(pci_dev->cmask); 1022 g_free(pci_dev->wmask); 1023 g_free(pci_dev->w1cmask); 1024 g_free(pci_dev->used); 1025 } 1026 1027 static void do_pci_unregister_device(PCIDevice *pci_dev) 1028 { 1029 pci_get_bus(pci_dev)->devices[pci_dev->devfn] = NULL; 1030 pci_config_free(pci_dev); 1031 1032 if (xen_mode == XEN_EMULATE) { 1033 xen_evtchn_remove_pci_device(pci_dev); 1034 } 1035 if (memory_region_is_mapped(&pci_dev->bus_master_enable_region)) { 1036 memory_region_del_subregion(&pci_dev->bus_master_container_region, 1037 &pci_dev->bus_master_enable_region); 1038 } 1039 address_space_destroy(&pci_dev->bus_master_as); 1040 } 1041 1042 /* Extract PCIReqIDCache into BDF format */ 1043 static uint16_t pci_req_id_cache_extract(PCIReqIDCache *cache) 1044 { 1045 uint8_t bus_n; 1046 uint16_t result; 1047 1048 switch (cache->type) { 1049 case PCI_REQ_ID_BDF: 1050 result = pci_get_bdf(cache->dev); 1051 break; 1052 case PCI_REQ_ID_SECONDARY_BUS: 1053 bus_n = pci_dev_bus_num(cache->dev); 1054 result = PCI_BUILD_BDF(bus_n, 0); 1055 break; 1056 default: 1057 error_report("Invalid PCI requester ID cache type: %d", 1058 cache->type); 1059 exit(1); 1060 break; 1061 } 1062 1063 return result; 1064 } 1065 1066 /* Parse bridges up to the root complex and return requester ID 1067 * cache for specific device. For full PCIe topology, the cache 1068 * result would be exactly the same as getting BDF of the device. 1069 * However, several tricks are required when system mixed up with 1070 * legacy PCI devices and PCIe-to-PCI bridges. 1071 * 1072 * Here we cache the proxy device (and type) not requester ID since 1073 * bus number might change from time to time. 1074 */ 1075 static PCIReqIDCache pci_req_id_cache_get(PCIDevice *dev) 1076 { 1077 PCIDevice *parent; 1078 PCIReqIDCache cache = { 1079 .dev = dev, 1080 .type = PCI_REQ_ID_BDF, 1081 }; 1082 1083 while (!pci_bus_is_root(pci_get_bus(dev))) { 1084 /* We are under PCI/PCIe bridges */ 1085 parent = pci_get_bus(dev)->parent_dev; 1086 if (pci_is_express(parent)) { 1087 if (pcie_cap_get_type(parent) == PCI_EXP_TYPE_PCI_BRIDGE) { 1088 /* When we pass through PCIe-to-PCI/PCIX bridges, we 1089 * override the requester ID using secondary bus 1090 * number of parent bridge with zeroed devfn 1091 * (pcie-to-pci bridge spec chap 2.3). */ 1092 cache.type = PCI_REQ_ID_SECONDARY_BUS; 1093 cache.dev = dev; 1094 } 1095 } else { 1096 /* Legacy PCI, override requester ID with the bridge's 1097 * BDF upstream. When the root complex connects to 1098 * legacy PCI devices (including buses), it can only 1099 * obtain requester ID info from directly attached 1100 * devices. If devices are attached under bridges, only 1101 * the requester ID of the bridge that is directly 1102 * attached to the root complex can be recognized. */ 1103 cache.type = PCI_REQ_ID_BDF; 1104 cache.dev = parent; 1105 } 1106 dev = parent; 1107 } 1108 1109 return cache; 1110 } 1111 1112 uint16_t pci_requester_id(PCIDevice *dev) 1113 { 1114 return pci_req_id_cache_extract(&dev->requester_id_cache); 1115 } 1116 1117 static bool pci_bus_devfn_available(PCIBus *bus, int devfn) 1118 { 1119 return !(bus->devices[devfn]); 1120 } 1121 1122 static bool pci_bus_devfn_reserved(PCIBus *bus, int devfn) 1123 { 1124 return bus->slot_reserved_mask & (1UL << PCI_SLOT(devfn)); 1125 } 1126 1127 uint32_t pci_bus_get_slot_reserved_mask(PCIBus *bus) 1128 { 1129 return bus->slot_reserved_mask; 1130 } 1131 1132 void pci_bus_set_slot_reserved_mask(PCIBus *bus, uint32_t mask) 1133 { 1134 bus->slot_reserved_mask |= mask; 1135 } 1136 1137 void pci_bus_clear_slot_reserved_mask(PCIBus *bus, uint32_t mask) 1138 { 1139 bus->slot_reserved_mask &= ~mask; 1140 } 1141 1142 /* -1 for devfn means auto assign */ 1143 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, 1144 const char *name, int devfn, 1145 Error **errp) 1146 { 1147 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 1148 PCIConfigReadFunc *config_read = pc->config_read; 1149 PCIConfigWriteFunc *config_write = pc->config_write; 1150 Error *local_err = NULL; 1151 DeviceState *dev = DEVICE(pci_dev); 1152 PCIBus *bus = pci_get_bus(pci_dev); 1153 bool is_bridge = IS_PCI_BRIDGE(pci_dev); 1154 1155 /* Only pci bridges can be attached to extra PCI root buses */ 1156 if (pci_bus_is_root(bus) && bus->parent_dev && !is_bridge) { 1157 error_setg(errp, 1158 "PCI: Only PCI/PCIe bridges can be plugged into %s", 1159 bus->parent_dev->name); 1160 return NULL; 1161 } 1162 1163 if (devfn < 0) { 1164 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices); 1165 devfn += PCI_FUNC_MAX) { 1166 if (pci_bus_devfn_available(bus, devfn) && 1167 !pci_bus_devfn_reserved(bus, devfn)) { 1168 goto found; 1169 } 1170 } 1171 error_setg(errp, "PCI: no slot/function available for %s, all in use " 1172 "or reserved", name); 1173 return NULL; 1174 found: ; 1175 } else if (pci_bus_devfn_reserved(bus, devfn)) { 1176 error_setg(errp, "PCI: slot %d function %d not available for %s," 1177 " reserved", 1178 PCI_SLOT(devfn), PCI_FUNC(devfn), name); 1179 return NULL; 1180 } else if (!pci_bus_devfn_available(bus, devfn)) { 1181 error_setg(errp, "PCI: slot %d function %d not available for %s," 1182 " in use by %s,id=%s", 1183 PCI_SLOT(devfn), PCI_FUNC(devfn), name, 1184 bus->devices[devfn]->name, bus->devices[devfn]->qdev.id); 1185 return NULL; 1186 } /* 1187 * Populating function 0 triggers a scan from the guest that 1188 * exposes other non-zero functions. Hence we need to ensure that 1189 * function 0 wasn't added yet. 1190 */ 1191 else if (dev->hotplugged && 1192 !pci_is_vf(pci_dev) && 1193 pci_get_function_0(pci_dev)) { 1194 error_setg(errp, "PCI: slot %d function 0 already occupied by %s," 1195 " new func %s cannot be exposed to guest.", 1196 PCI_SLOT(pci_get_function_0(pci_dev)->devfn), 1197 pci_get_function_0(pci_dev)->name, 1198 name); 1199 1200 return NULL; 1201 } 1202 1203 pci_dev->devfn = devfn; 1204 pci_dev->requester_id_cache = pci_req_id_cache_get(pci_dev); 1205 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name); 1206 1207 memory_region_init(&pci_dev->bus_master_container_region, OBJECT(pci_dev), 1208 "bus master container", UINT64_MAX); 1209 address_space_init(&pci_dev->bus_master_as, 1210 &pci_dev->bus_master_container_region, pci_dev->name); 1211 1212 if (phase_check(PHASE_MACHINE_READY)) { 1213 pci_init_bus_master(pci_dev); 1214 } 1215 pci_dev->irq_state = 0; 1216 pci_config_alloc(pci_dev); 1217 1218 pci_config_set_vendor_id(pci_dev->config, pc->vendor_id); 1219 pci_config_set_device_id(pci_dev->config, pc->device_id); 1220 pci_config_set_revision(pci_dev->config, pc->revision); 1221 pci_config_set_class(pci_dev->config, pc->class_id); 1222 1223 if (!is_bridge) { 1224 if (pc->subsystem_vendor_id || pc->subsystem_id) { 1225 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, 1226 pc->subsystem_vendor_id); 1227 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 1228 pc->subsystem_id); 1229 } else { 1230 pci_set_default_subsystem_id(pci_dev); 1231 } 1232 } else { 1233 /* subsystem_vendor_id/subsystem_id are only for header type 0 */ 1234 assert(!pc->subsystem_vendor_id); 1235 assert(!pc->subsystem_id); 1236 } 1237 pci_init_cmask(pci_dev); 1238 pci_init_wmask(pci_dev); 1239 pci_init_w1cmask(pci_dev); 1240 if (is_bridge) { 1241 pci_init_mask_bridge(pci_dev); 1242 } 1243 pci_init_multifunction(bus, pci_dev, &local_err); 1244 if (local_err) { 1245 error_propagate(errp, local_err); 1246 do_pci_unregister_device(pci_dev); 1247 return NULL; 1248 } 1249 1250 if (!config_read) 1251 config_read = pci_default_read_config; 1252 if (!config_write) 1253 config_write = pci_default_write_config; 1254 pci_dev->config_read = config_read; 1255 pci_dev->config_write = config_write; 1256 bus->devices[devfn] = pci_dev; 1257 pci_dev->version_id = 2; /* Current pci device vmstate version */ 1258 return pci_dev; 1259 } 1260 1261 static void pci_unregister_io_regions(PCIDevice *pci_dev) 1262 { 1263 PCIIORegion *r; 1264 int i; 1265 1266 for(i = 0; i < PCI_NUM_REGIONS; i++) { 1267 r = &pci_dev->io_regions[i]; 1268 if (!r->size || r->addr == PCI_BAR_UNMAPPED) 1269 continue; 1270 memory_region_del_subregion(r->address_space, r->memory); 1271 } 1272 1273 pci_unregister_vga(pci_dev); 1274 } 1275 1276 static void pci_qdev_unrealize(DeviceState *dev) 1277 { 1278 PCIDevice *pci_dev = PCI_DEVICE(dev); 1279 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 1280 1281 pci_unregister_io_regions(pci_dev); 1282 pci_del_option_rom(pci_dev); 1283 1284 if (pc->exit) { 1285 pc->exit(pci_dev); 1286 } 1287 1288 pci_device_deassert_intx(pci_dev); 1289 do_pci_unregister_device(pci_dev); 1290 1291 pci_dev->msi_trigger = NULL; 1292 1293 /* 1294 * clean up acpi-index so it could reused by another device 1295 */ 1296 if (pci_dev->acpi_index) { 1297 GSequence *used_indexes = pci_acpi_index_list(); 1298 1299 g_sequence_remove(g_sequence_lookup(used_indexes, 1300 GINT_TO_POINTER(pci_dev->acpi_index), 1301 g_cmp_uint32, NULL)); 1302 } 1303 } 1304 1305 void pci_register_bar(PCIDevice *pci_dev, int region_num, 1306 uint8_t type, MemoryRegion *memory) 1307 { 1308 PCIIORegion *r; 1309 uint32_t addr; /* offset in pci config space */ 1310 uint64_t wmask; 1311 pcibus_t size = memory_region_size(memory); 1312 uint8_t hdr_type; 1313 1314 assert(!pci_is_vf(pci_dev)); /* VFs must use pcie_sriov_vf_register_bar */ 1315 assert(region_num >= 0); 1316 assert(region_num < PCI_NUM_REGIONS); 1317 assert(is_power_of_2(size)); 1318 1319 /* A PCI bridge device (with Type 1 header) may only have at most 2 BARs */ 1320 hdr_type = 1321 pci_dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 1322 assert(hdr_type != PCI_HEADER_TYPE_BRIDGE || region_num < 2); 1323 1324 r = &pci_dev->io_regions[region_num]; 1325 r->addr = PCI_BAR_UNMAPPED; 1326 r->size = size; 1327 r->type = type; 1328 r->memory = memory; 1329 r->address_space = type & PCI_BASE_ADDRESS_SPACE_IO 1330 ? pci_get_bus(pci_dev)->address_space_io 1331 : pci_get_bus(pci_dev)->address_space_mem; 1332 1333 wmask = ~(size - 1); 1334 if (region_num == PCI_ROM_SLOT) { 1335 /* ROM enable bit is writable */ 1336 wmask |= PCI_ROM_ADDRESS_ENABLE; 1337 } 1338 1339 addr = pci_bar(pci_dev, region_num); 1340 pci_set_long(pci_dev->config + addr, type); 1341 1342 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) && 1343 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 1344 pci_set_quad(pci_dev->wmask + addr, wmask); 1345 pci_set_quad(pci_dev->cmask + addr, ~0ULL); 1346 } else { 1347 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff); 1348 pci_set_long(pci_dev->cmask + addr, 0xffffffff); 1349 } 1350 } 1351 1352 static void pci_update_vga(PCIDevice *pci_dev) 1353 { 1354 uint16_t cmd; 1355 1356 if (!pci_dev->has_vga) { 1357 return; 1358 } 1359 1360 cmd = pci_get_word(pci_dev->config + PCI_COMMAND); 1361 1362 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_MEM], 1363 cmd & PCI_COMMAND_MEMORY); 1364 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO], 1365 cmd & PCI_COMMAND_IO); 1366 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI], 1367 cmd & PCI_COMMAND_IO); 1368 } 1369 1370 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, 1371 MemoryRegion *io_lo, MemoryRegion *io_hi) 1372 { 1373 PCIBus *bus = pci_get_bus(pci_dev); 1374 1375 assert(!pci_dev->has_vga); 1376 1377 assert(memory_region_size(mem) == QEMU_PCI_VGA_MEM_SIZE); 1378 pci_dev->vga_regions[QEMU_PCI_VGA_MEM] = mem; 1379 memory_region_add_subregion_overlap(bus->address_space_mem, 1380 QEMU_PCI_VGA_MEM_BASE, mem, 1); 1381 1382 assert(memory_region_size(io_lo) == QEMU_PCI_VGA_IO_LO_SIZE); 1383 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO] = io_lo; 1384 memory_region_add_subregion_overlap(bus->address_space_io, 1385 QEMU_PCI_VGA_IO_LO_BASE, io_lo, 1); 1386 1387 assert(memory_region_size(io_hi) == QEMU_PCI_VGA_IO_HI_SIZE); 1388 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI] = io_hi; 1389 memory_region_add_subregion_overlap(bus->address_space_io, 1390 QEMU_PCI_VGA_IO_HI_BASE, io_hi, 1); 1391 pci_dev->has_vga = true; 1392 1393 pci_update_vga(pci_dev); 1394 } 1395 1396 void pci_unregister_vga(PCIDevice *pci_dev) 1397 { 1398 PCIBus *bus = pci_get_bus(pci_dev); 1399 1400 if (!pci_dev->has_vga) { 1401 return; 1402 } 1403 1404 memory_region_del_subregion(bus->address_space_mem, 1405 pci_dev->vga_regions[QEMU_PCI_VGA_MEM]); 1406 memory_region_del_subregion(bus->address_space_io, 1407 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO]); 1408 memory_region_del_subregion(bus->address_space_io, 1409 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI]); 1410 pci_dev->has_vga = false; 1411 } 1412 1413 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num) 1414 { 1415 return pci_dev->io_regions[region_num].addr; 1416 } 1417 1418 static pcibus_t pci_config_get_bar_addr(PCIDevice *d, int reg, 1419 uint8_t type, pcibus_t size) 1420 { 1421 pcibus_t new_addr; 1422 if (!pci_is_vf(d)) { 1423 int bar = pci_bar(d, reg); 1424 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 1425 new_addr = pci_get_quad(d->config + bar); 1426 } else { 1427 new_addr = pci_get_long(d->config + bar); 1428 } 1429 } else { 1430 PCIDevice *pf = d->exp.sriov_vf.pf; 1431 uint16_t sriov_cap = pf->exp.sriov_cap; 1432 int bar = sriov_cap + PCI_SRIOV_BAR + reg * 4; 1433 uint16_t vf_offset = 1434 pci_get_word(pf->config + sriov_cap + PCI_SRIOV_VF_OFFSET); 1435 uint16_t vf_stride = 1436 pci_get_word(pf->config + sriov_cap + PCI_SRIOV_VF_STRIDE); 1437 uint32_t vf_num = (d->devfn - (pf->devfn + vf_offset)) / vf_stride; 1438 1439 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 1440 new_addr = pci_get_quad(pf->config + bar); 1441 } else { 1442 new_addr = pci_get_long(pf->config + bar); 1443 } 1444 new_addr += vf_num * size; 1445 } 1446 /* The ROM slot has a specific enable bit, keep it intact */ 1447 if (reg != PCI_ROM_SLOT) { 1448 new_addr &= ~(size - 1); 1449 } 1450 return new_addr; 1451 } 1452 1453 pcibus_t pci_bar_address(PCIDevice *d, 1454 int reg, uint8_t type, pcibus_t size) 1455 { 1456 pcibus_t new_addr, last_addr; 1457 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND); 1458 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); 1459 bool allow_0_address = mc->pci_allow_0_address; 1460 1461 if (type & PCI_BASE_ADDRESS_SPACE_IO) { 1462 if (!(cmd & PCI_COMMAND_IO)) { 1463 return PCI_BAR_UNMAPPED; 1464 } 1465 new_addr = pci_config_get_bar_addr(d, reg, type, size); 1466 last_addr = new_addr + size - 1; 1467 /* Check if 32 bit BAR wraps around explicitly. 1468 * TODO: make priorities correct and remove this work around. 1469 */ 1470 if (last_addr <= new_addr || last_addr >= UINT32_MAX || 1471 (!allow_0_address && new_addr == 0)) { 1472 return PCI_BAR_UNMAPPED; 1473 } 1474 return new_addr; 1475 } 1476 1477 if (!(cmd & PCI_COMMAND_MEMORY)) { 1478 return PCI_BAR_UNMAPPED; 1479 } 1480 new_addr = pci_config_get_bar_addr(d, reg, type, size); 1481 /* the ROM slot has a specific enable bit */ 1482 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) { 1483 return PCI_BAR_UNMAPPED; 1484 } 1485 new_addr &= ~(size - 1); 1486 last_addr = new_addr + size - 1; 1487 /* NOTE: we do not support wrapping */ 1488 /* XXX: as we cannot support really dynamic 1489 mappings, we handle specific values as invalid 1490 mappings. */ 1491 if (last_addr <= new_addr || last_addr == PCI_BAR_UNMAPPED || 1492 (!allow_0_address && new_addr == 0)) { 1493 return PCI_BAR_UNMAPPED; 1494 } 1495 1496 /* Now pcibus_t is 64bit. 1497 * Check if 32 bit BAR wraps around explicitly. 1498 * Without this, PC ide doesn't work well. 1499 * TODO: remove this work around. 1500 */ 1501 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) { 1502 return PCI_BAR_UNMAPPED; 1503 } 1504 1505 /* 1506 * OS is allowed to set BAR beyond its addressable 1507 * bits. For example, 32 bit OS can set 64bit bar 1508 * to >4G. Check it. TODO: we might need to support 1509 * it in the future for e.g. PAE. 1510 */ 1511 if (last_addr >= HWADDR_MAX) { 1512 return PCI_BAR_UNMAPPED; 1513 } 1514 1515 return new_addr; 1516 } 1517 1518 static void pci_update_mappings(PCIDevice *d) 1519 { 1520 PCIIORegion *r; 1521 int i; 1522 pcibus_t new_addr; 1523 1524 for(i = 0; i < PCI_NUM_REGIONS; i++) { 1525 r = &d->io_regions[i]; 1526 1527 /* this region isn't registered */ 1528 if (!r->size) 1529 continue; 1530 1531 new_addr = pci_bar_address(d, i, r->type, r->size); 1532 if (!d->has_power) { 1533 new_addr = PCI_BAR_UNMAPPED; 1534 } 1535 1536 /* This bar isn't changed */ 1537 if (new_addr == r->addr) 1538 continue; 1539 1540 /* now do the real mapping */ 1541 if (r->addr != PCI_BAR_UNMAPPED) { 1542 trace_pci_update_mappings_del(d->name, pci_dev_bus_num(d), 1543 PCI_SLOT(d->devfn), 1544 PCI_FUNC(d->devfn), 1545 i, r->addr, r->size); 1546 memory_region_del_subregion(r->address_space, r->memory); 1547 } 1548 r->addr = new_addr; 1549 if (r->addr != PCI_BAR_UNMAPPED) { 1550 trace_pci_update_mappings_add(d->name, pci_dev_bus_num(d), 1551 PCI_SLOT(d->devfn), 1552 PCI_FUNC(d->devfn), 1553 i, r->addr, r->size); 1554 memory_region_add_subregion_overlap(r->address_space, 1555 r->addr, r->memory, 1); 1556 } 1557 } 1558 1559 pci_update_vga(d); 1560 } 1561 1562 static inline int pci_irq_disabled(PCIDevice *d) 1563 { 1564 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE; 1565 } 1566 1567 /* Called after interrupt disabled field update in config space, 1568 * assert/deassert interrupts if necessary. 1569 * Gets original interrupt disable bit value (before update). */ 1570 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled) 1571 { 1572 int i, disabled = pci_irq_disabled(d); 1573 if (disabled == was_irq_disabled) 1574 return; 1575 for (i = 0; i < PCI_NUM_PINS; ++i) { 1576 int state = pci_irq_state(d, i); 1577 pci_change_irq_level(d, i, disabled ? -state : state); 1578 } 1579 } 1580 1581 uint32_t pci_default_read_config(PCIDevice *d, 1582 uint32_t address, int len) 1583 { 1584 uint32_t val = 0; 1585 1586 assert(address + len <= pci_config_size(d)); 1587 1588 if (pci_is_express_downstream_port(d) && 1589 ranges_overlap(address, len, d->exp.exp_cap + PCI_EXP_LNKSTA, 2)) { 1590 pcie_sync_bridge_lnk(d); 1591 } 1592 memcpy(&val, d->config + address, len); 1593 return le32_to_cpu(val); 1594 } 1595 1596 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val_in, int l) 1597 { 1598 int i, was_irq_disabled = pci_irq_disabled(d); 1599 uint32_t val = val_in; 1600 1601 assert(addr + l <= pci_config_size(d)); 1602 1603 for (i = 0; i < l; val >>= 8, ++i) { 1604 uint8_t wmask = d->wmask[addr + i]; 1605 uint8_t w1cmask = d->w1cmask[addr + i]; 1606 assert(!(wmask & w1cmask)); 1607 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask); 1608 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */ 1609 } 1610 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) || 1611 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) || 1612 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) || 1613 range_covers_byte(addr, l, PCI_COMMAND)) 1614 pci_update_mappings(d); 1615 1616 if (range_covers_byte(addr, l, PCI_COMMAND)) { 1617 pci_update_irq_disabled(d, was_irq_disabled); 1618 memory_region_set_enabled(&d->bus_master_enable_region, 1619 (pci_get_word(d->config + PCI_COMMAND) 1620 & PCI_COMMAND_MASTER) && d->has_power); 1621 } 1622 1623 msi_write_config(d, addr, val_in, l); 1624 msix_write_config(d, addr, val_in, l); 1625 pcie_sriov_config_write(d, addr, val_in, l); 1626 } 1627 1628 /***********************************************************/ 1629 /* generic PCI irq support */ 1630 1631 /* 0 <= irq_num <= 3. level must be 0 or 1 */ 1632 static void pci_irq_handler(void *opaque, int irq_num, int level) 1633 { 1634 PCIDevice *pci_dev = opaque; 1635 int change; 1636 1637 assert(0 <= irq_num && irq_num < PCI_NUM_PINS); 1638 assert(level == 0 || level == 1); 1639 change = level - pci_irq_state(pci_dev, irq_num); 1640 if (!change) 1641 return; 1642 1643 pci_set_irq_state(pci_dev, irq_num, level); 1644 pci_update_irq_status(pci_dev); 1645 if (pci_irq_disabled(pci_dev)) 1646 return; 1647 pci_change_irq_level(pci_dev, irq_num, change); 1648 } 1649 1650 qemu_irq pci_allocate_irq(PCIDevice *pci_dev) 1651 { 1652 int intx = pci_intx(pci_dev); 1653 assert(0 <= intx && intx < PCI_NUM_PINS); 1654 1655 return qemu_allocate_irq(pci_irq_handler, pci_dev, intx); 1656 } 1657 1658 void pci_set_irq(PCIDevice *pci_dev, int level) 1659 { 1660 int intx = pci_intx(pci_dev); 1661 pci_irq_handler(pci_dev, intx, level); 1662 } 1663 1664 /* Special hooks used by device assignment */ 1665 void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq) 1666 { 1667 assert(pci_bus_is_root(bus)); 1668 bus->route_intx_to_irq = route_intx_to_irq; 1669 } 1670 1671 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin) 1672 { 1673 PCIBus *bus; 1674 1675 do { 1676 int dev_irq = pin; 1677 bus = pci_get_bus(dev); 1678 pin = bus->map_irq(dev, pin); 1679 trace_pci_route_irq(dev_irq, DEVICE(dev)->canonical_path, pin, 1680 pci_bus_is_root(bus) ? "root-complex" 1681 : DEVICE(bus->parent_dev)->canonical_path); 1682 dev = bus->parent_dev; 1683 } while (dev); 1684 1685 if (!bus->route_intx_to_irq) { 1686 error_report("PCI: Bug - unimplemented PCI INTx routing (%s)", 1687 object_get_typename(OBJECT(bus->qbus.parent))); 1688 return (PCIINTxRoute) { PCI_INTX_DISABLED, -1 }; 1689 } 1690 1691 return bus->route_intx_to_irq(bus->irq_opaque, pin); 1692 } 1693 1694 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new) 1695 { 1696 return old->mode != new->mode || old->irq != new->irq; 1697 } 1698 1699 void pci_bus_fire_intx_routing_notifier(PCIBus *bus) 1700 { 1701 PCIDevice *dev; 1702 PCIBus *sec; 1703 int i; 1704 1705 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 1706 dev = bus->devices[i]; 1707 if (dev && dev->intx_routing_notifier) { 1708 dev->intx_routing_notifier(dev); 1709 } 1710 } 1711 1712 QLIST_FOREACH(sec, &bus->child, sibling) { 1713 pci_bus_fire_intx_routing_notifier(sec); 1714 } 1715 } 1716 1717 void pci_device_set_intx_routing_notifier(PCIDevice *dev, 1718 PCIINTxRoutingNotifier notifier) 1719 { 1720 dev->intx_routing_notifier = notifier; 1721 } 1722 1723 /* 1724 * PCI-to-PCI bridge specification 1725 * 9.1: Interrupt routing. Table 9-1 1726 * 1727 * the PCI Express Base Specification, Revision 2.1 1728 * 2.2.8.1: INTx interrupt signaling - Rules 1729 * the Implementation Note 1730 * Table 2-20 1731 */ 1732 /* 1733 * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD 1734 * 0-origin unlike PCI interrupt pin register. 1735 */ 1736 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin) 1737 { 1738 return pci_swizzle(PCI_SLOT(pci_dev->devfn), pin); 1739 } 1740 1741 /***********************************************************/ 1742 /* monitor info on PCI */ 1743 1744 static const pci_class_desc pci_class_descriptions[] = 1745 { 1746 { 0x0001, "VGA controller", "display"}, 1747 { 0x0100, "SCSI controller", "scsi"}, 1748 { 0x0101, "IDE controller", "ide"}, 1749 { 0x0102, "Floppy controller", "fdc"}, 1750 { 0x0103, "IPI controller", "ipi"}, 1751 { 0x0104, "RAID controller", "raid"}, 1752 { 0x0106, "SATA controller"}, 1753 { 0x0107, "SAS controller"}, 1754 { 0x0180, "Storage controller"}, 1755 { 0x0200, "Ethernet controller", "ethernet"}, 1756 { 0x0201, "Token Ring controller", "token-ring"}, 1757 { 0x0202, "FDDI controller", "fddi"}, 1758 { 0x0203, "ATM controller", "atm"}, 1759 { 0x0280, "Network controller"}, 1760 { 0x0300, "VGA controller", "display", 0x00ff}, 1761 { 0x0301, "XGA controller"}, 1762 { 0x0302, "3D controller"}, 1763 { 0x0380, "Display controller"}, 1764 { 0x0400, "Video controller", "video"}, 1765 { 0x0401, "Audio controller", "sound"}, 1766 { 0x0402, "Phone"}, 1767 { 0x0403, "Audio controller", "sound"}, 1768 { 0x0480, "Multimedia controller"}, 1769 { 0x0500, "RAM controller", "memory"}, 1770 { 0x0501, "Flash controller", "flash"}, 1771 { 0x0580, "Memory controller"}, 1772 { 0x0600, "Host bridge", "host"}, 1773 { 0x0601, "ISA bridge", "isa"}, 1774 { 0x0602, "EISA bridge", "eisa"}, 1775 { 0x0603, "MC bridge", "mca"}, 1776 { 0x0604, "PCI bridge", "pci-bridge"}, 1777 { 0x0605, "PCMCIA bridge", "pcmcia"}, 1778 { 0x0606, "NUBUS bridge", "nubus"}, 1779 { 0x0607, "CARDBUS bridge", "cardbus"}, 1780 { 0x0608, "RACEWAY bridge"}, 1781 { 0x0680, "Bridge"}, 1782 { 0x0700, "Serial port", "serial"}, 1783 { 0x0701, "Parallel port", "parallel"}, 1784 { 0x0800, "Interrupt controller", "interrupt-controller"}, 1785 { 0x0801, "DMA controller", "dma-controller"}, 1786 { 0x0802, "Timer", "timer"}, 1787 { 0x0803, "RTC", "rtc"}, 1788 { 0x0900, "Keyboard", "keyboard"}, 1789 { 0x0901, "Pen", "pen"}, 1790 { 0x0902, "Mouse", "mouse"}, 1791 { 0x0A00, "Dock station", "dock", 0x00ff}, 1792 { 0x0B00, "i386 cpu", "cpu", 0x00ff}, 1793 { 0x0c00, "Firewire controller", "firewire"}, 1794 { 0x0c01, "Access bus controller", "access-bus"}, 1795 { 0x0c02, "SSA controller", "ssa"}, 1796 { 0x0c03, "USB controller", "usb"}, 1797 { 0x0c04, "Fibre channel controller", "fibre-channel"}, 1798 { 0x0c05, "SMBus"}, 1799 { 0, NULL} 1800 }; 1801 1802 void pci_for_each_device_under_bus_reverse(PCIBus *bus, 1803 pci_bus_dev_fn fn, 1804 void *opaque) 1805 { 1806 PCIDevice *d; 1807 int devfn; 1808 1809 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1810 d = bus->devices[ARRAY_SIZE(bus->devices) - 1 - devfn]; 1811 if (d) { 1812 fn(bus, d, opaque); 1813 } 1814 } 1815 } 1816 1817 void pci_for_each_device_reverse(PCIBus *bus, int bus_num, 1818 pci_bus_dev_fn fn, void *opaque) 1819 { 1820 bus = pci_find_bus_nr(bus, bus_num); 1821 1822 if (bus) { 1823 pci_for_each_device_under_bus_reverse(bus, fn, opaque); 1824 } 1825 } 1826 1827 void pci_for_each_device_under_bus(PCIBus *bus, 1828 pci_bus_dev_fn fn, void *opaque) 1829 { 1830 PCIDevice *d; 1831 int devfn; 1832 1833 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1834 d = bus->devices[devfn]; 1835 if (d) { 1836 fn(bus, d, opaque); 1837 } 1838 } 1839 } 1840 1841 void pci_for_each_device(PCIBus *bus, int bus_num, 1842 pci_bus_dev_fn fn, void *opaque) 1843 { 1844 bus = pci_find_bus_nr(bus, bus_num); 1845 1846 if (bus) { 1847 pci_for_each_device_under_bus(bus, fn, opaque); 1848 } 1849 } 1850 1851 const pci_class_desc *get_class_desc(int class) 1852 { 1853 const pci_class_desc *desc; 1854 1855 desc = pci_class_descriptions; 1856 while (desc->desc && class != desc->class) { 1857 desc++; 1858 } 1859 1860 return desc; 1861 } 1862 1863 /* Initialize a PCI NIC. */ 1864 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus, 1865 const char *default_model, 1866 const char *default_devaddr) 1867 { 1868 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr; 1869 GPtrArray *pci_nic_models; 1870 PCIBus *bus; 1871 PCIDevice *pci_dev; 1872 DeviceState *dev; 1873 int devfn; 1874 int i; 1875 int dom, busnr; 1876 unsigned slot; 1877 1878 if (nd->model && !strcmp(nd->model, "virtio")) { 1879 g_free(nd->model); 1880 nd->model = g_strdup("virtio-net-pci"); 1881 } 1882 1883 pci_nic_models = qemu_get_nic_models(TYPE_PCI_DEVICE); 1884 1885 if (qemu_show_nic_models(nd->model, (const char **)pci_nic_models->pdata)) { 1886 exit(0); 1887 } 1888 1889 i = qemu_find_nic_model(nd, (const char **)pci_nic_models->pdata, 1890 default_model); 1891 if (i < 0) { 1892 exit(1); 1893 } 1894 1895 if (!rootbus) { 1896 error_report("No primary PCI bus"); 1897 exit(1); 1898 } 1899 1900 assert(!rootbus->parent_dev); 1901 1902 if (!devaddr) { 1903 devfn = -1; 1904 busnr = 0; 1905 } else { 1906 if (pci_parse_devaddr(devaddr, &dom, &busnr, &slot, NULL) < 0) { 1907 error_report("Invalid PCI device address %s for device %s", 1908 devaddr, nd->model); 1909 exit(1); 1910 } 1911 1912 if (dom != 0) { 1913 error_report("No support for non-zero PCI domains"); 1914 exit(1); 1915 } 1916 1917 devfn = PCI_DEVFN(slot, 0); 1918 } 1919 1920 bus = pci_find_bus_nr(rootbus, busnr); 1921 if (!bus) { 1922 error_report("Invalid PCI device address %s for device %s", 1923 devaddr, nd->model); 1924 exit(1); 1925 } 1926 1927 pci_dev = pci_new(devfn, nd->model); 1928 dev = &pci_dev->qdev; 1929 qdev_set_nic_properties(dev, nd); 1930 pci_realize_and_unref(pci_dev, bus, &error_fatal); 1931 g_ptr_array_free(pci_nic_models, true); 1932 return pci_dev; 1933 } 1934 1935 PCIDevice *pci_vga_init(PCIBus *bus) 1936 { 1937 vga_interface_created = true; 1938 switch (vga_interface_type) { 1939 case VGA_CIRRUS: 1940 return pci_create_simple(bus, -1, "cirrus-vga"); 1941 case VGA_QXL: 1942 return pci_create_simple(bus, -1, "qxl-vga"); 1943 case VGA_STD: 1944 return pci_create_simple(bus, -1, "VGA"); 1945 case VGA_VMWARE: 1946 return pci_create_simple(bus, -1, "vmware-svga"); 1947 case VGA_VIRTIO: 1948 return pci_create_simple(bus, -1, "virtio-vga"); 1949 case VGA_NONE: 1950 default: /* Other non-PCI types. Checking for unsupported types is already 1951 done in vl.c. */ 1952 return NULL; 1953 } 1954 } 1955 1956 /* Whether a given bus number is in range of the secondary 1957 * bus of the given bridge device. */ 1958 static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num) 1959 { 1960 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) & 1961 PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ && 1962 dev->config[PCI_SECONDARY_BUS] <= bus_num && 1963 bus_num <= dev->config[PCI_SUBORDINATE_BUS]; 1964 } 1965 1966 /* Whether a given bus number is in a range of a root bus */ 1967 static bool pci_root_bus_in_range(PCIBus *bus, int bus_num) 1968 { 1969 int i; 1970 1971 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 1972 PCIDevice *dev = bus->devices[i]; 1973 1974 if (dev && IS_PCI_BRIDGE(dev)) { 1975 if (pci_secondary_bus_in_range(dev, bus_num)) { 1976 return true; 1977 } 1978 } 1979 } 1980 1981 return false; 1982 } 1983 1984 PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num) 1985 { 1986 PCIBus *sec; 1987 1988 if (!bus) { 1989 return NULL; 1990 } 1991 1992 if (pci_bus_num(bus) == bus_num) { 1993 return bus; 1994 } 1995 1996 /* Consider all bus numbers in range for the host pci bridge. */ 1997 if (!pci_bus_is_root(bus) && 1998 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) { 1999 return NULL; 2000 } 2001 2002 /* try child bus */ 2003 for (; bus; bus = sec) { 2004 QLIST_FOREACH(sec, &bus->child, sibling) { 2005 if (pci_bus_num(sec) == bus_num) { 2006 return sec; 2007 } 2008 /* PXB buses assumed to be children of bus 0 */ 2009 if (pci_bus_is_root(sec)) { 2010 if (pci_root_bus_in_range(sec, bus_num)) { 2011 break; 2012 } 2013 } else { 2014 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) { 2015 break; 2016 } 2017 } 2018 } 2019 } 2020 2021 return NULL; 2022 } 2023 2024 void pci_for_each_bus_depth_first(PCIBus *bus, pci_bus_ret_fn begin, 2025 pci_bus_fn end, void *parent_state) 2026 { 2027 PCIBus *sec; 2028 void *state; 2029 2030 if (!bus) { 2031 return; 2032 } 2033 2034 if (begin) { 2035 state = begin(bus, parent_state); 2036 } else { 2037 state = parent_state; 2038 } 2039 2040 QLIST_FOREACH(sec, &bus->child, sibling) { 2041 pci_for_each_bus_depth_first(sec, begin, end, state); 2042 } 2043 2044 if (end) { 2045 end(bus, state); 2046 } 2047 } 2048 2049 2050 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn) 2051 { 2052 bus = pci_find_bus_nr(bus, bus_num); 2053 2054 if (!bus) 2055 return NULL; 2056 2057 return bus->devices[devfn]; 2058 } 2059 2060 #define ONBOARD_INDEX_MAX (16 * 1024 - 1) 2061 2062 static void pci_qdev_realize(DeviceState *qdev, Error **errp) 2063 { 2064 PCIDevice *pci_dev = (PCIDevice *)qdev; 2065 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 2066 ObjectClass *klass = OBJECT_CLASS(pc); 2067 Error *local_err = NULL; 2068 bool is_default_rom; 2069 uint16_t class_id; 2070 2071 /* 2072 * capped by systemd (see: udev-builtin-net_id.c) 2073 * as it's the only known user honor it to avoid users 2074 * misconfigure QEMU and then wonder why acpi-index doesn't work 2075 */ 2076 if (pci_dev->acpi_index > ONBOARD_INDEX_MAX) { 2077 error_setg(errp, "acpi-index should be less or equal to %u", 2078 ONBOARD_INDEX_MAX); 2079 return; 2080 } 2081 2082 /* 2083 * make sure that acpi-index is unique across all present PCI devices 2084 */ 2085 if (pci_dev->acpi_index) { 2086 GSequence *used_indexes = pci_acpi_index_list(); 2087 2088 if (g_sequence_lookup(used_indexes, 2089 GINT_TO_POINTER(pci_dev->acpi_index), 2090 g_cmp_uint32, NULL)) { 2091 error_setg(errp, "a PCI device with acpi-index = %" PRIu32 2092 " already exist", pci_dev->acpi_index); 2093 return; 2094 } 2095 g_sequence_insert_sorted(used_indexes, 2096 GINT_TO_POINTER(pci_dev->acpi_index), 2097 g_cmp_uint32, NULL); 2098 } 2099 2100 if (pci_dev->romsize != -1 && !is_power_of_2(pci_dev->romsize)) { 2101 error_setg(errp, "ROM size %u is not a power of two", pci_dev->romsize); 2102 return; 2103 } 2104 2105 /* initialize cap_present for pci_is_express() and pci_config_size(), 2106 * Note that hybrid PCIs are not set automatically and need to manage 2107 * QEMU_PCI_CAP_EXPRESS manually */ 2108 if (object_class_dynamic_cast(klass, INTERFACE_PCIE_DEVICE) && 2109 !object_class_dynamic_cast(klass, INTERFACE_CONVENTIONAL_PCI_DEVICE)) { 2110 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; 2111 } 2112 2113 if (object_class_dynamic_cast(klass, INTERFACE_CXL_DEVICE)) { 2114 pci_dev->cap_present |= QEMU_PCIE_CAP_CXL; 2115 } 2116 2117 pci_dev = do_pci_register_device(pci_dev, 2118 object_get_typename(OBJECT(qdev)), 2119 pci_dev->devfn, errp); 2120 if (pci_dev == NULL) 2121 return; 2122 2123 if (pc->realize) { 2124 pc->realize(pci_dev, &local_err); 2125 if (local_err) { 2126 error_propagate(errp, local_err); 2127 do_pci_unregister_device(pci_dev); 2128 return; 2129 } 2130 } 2131 2132 /* 2133 * A PCIe Downstream Port that do not have ARI Forwarding enabled must 2134 * associate only Device 0 with the device attached to the bus 2135 * representing the Link from the Port (PCIe base spec rev 4.0 ver 0.3, 2136 * sec 7.3.1). 2137 * With ARI, PCI_SLOT() can return non-zero value as the traditional 2138 * 5-bit Device Number and 3-bit Function Number fields in its associated 2139 * Routing IDs, Requester IDs and Completer IDs are interpreted as a 2140 * single 8-bit Function Number. Hence, ignore ARI capable devices. 2141 */ 2142 if (pci_is_express(pci_dev) && 2143 !pcie_find_capability(pci_dev, PCI_EXT_CAP_ID_ARI) && 2144 pcie_has_upstream_port(pci_dev) && 2145 PCI_SLOT(pci_dev->devfn)) { 2146 warn_report("PCI: slot %d is not valid for %s," 2147 " parent device only allows plugging into slot 0.", 2148 PCI_SLOT(pci_dev->devfn), pci_dev->name); 2149 } 2150 2151 if (pci_dev->failover_pair_id) { 2152 if (!pci_bus_is_express(pci_get_bus(pci_dev))) { 2153 error_setg(errp, "failover primary device must be on " 2154 "PCIExpress bus"); 2155 pci_qdev_unrealize(DEVICE(pci_dev)); 2156 return; 2157 } 2158 class_id = pci_get_word(pci_dev->config + PCI_CLASS_DEVICE); 2159 if (class_id != PCI_CLASS_NETWORK_ETHERNET) { 2160 error_setg(errp, "failover primary device is not an " 2161 "Ethernet device"); 2162 pci_qdev_unrealize(DEVICE(pci_dev)); 2163 return; 2164 } 2165 if ((pci_dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) 2166 || (PCI_FUNC(pci_dev->devfn) != 0)) { 2167 error_setg(errp, "failover: primary device must be in its own " 2168 "PCI slot"); 2169 pci_qdev_unrealize(DEVICE(pci_dev)); 2170 return; 2171 } 2172 qdev->allow_unplug_during_migration = true; 2173 } 2174 2175 /* rom loading */ 2176 is_default_rom = false; 2177 if (pci_dev->romfile == NULL && pc->romfile != NULL) { 2178 pci_dev->romfile = g_strdup(pc->romfile); 2179 is_default_rom = true; 2180 } 2181 2182 pci_add_option_rom(pci_dev, is_default_rom, &local_err); 2183 if (local_err) { 2184 error_propagate(errp, local_err); 2185 pci_qdev_unrealize(DEVICE(pci_dev)); 2186 return; 2187 } 2188 2189 pci_set_power(pci_dev, true); 2190 2191 pci_dev->msi_trigger = pci_msi_trigger; 2192 } 2193 2194 static PCIDevice *pci_new_internal(int devfn, bool multifunction, 2195 const char *name) 2196 { 2197 DeviceState *dev; 2198 2199 dev = qdev_new(name); 2200 qdev_prop_set_int32(dev, "addr", devfn); 2201 qdev_prop_set_bit(dev, "multifunction", multifunction); 2202 return PCI_DEVICE(dev); 2203 } 2204 2205 PCIDevice *pci_new_multifunction(int devfn, const char *name) 2206 { 2207 return pci_new_internal(devfn, true, name); 2208 } 2209 2210 PCIDevice *pci_new(int devfn, const char *name) 2211 { 2212 return pci_new_internal(devfn, false, name); 2213 } 2214 2215 bool pci_realize_and_unref(PCIDevice *dev, PCIBus *bus, Error **errp) 2216 { 2217 return qdev_realize_and_unref(&dev->qdev, &bus->qbus, errp); 2218 } 2219 2220 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, 2221 const char *name) 2222 { 2223 PCIDevice *dev = pci_new_multifunction(devfn, name); 2224 pci_realize_and_unref(dev, bus, &error_fatal); 2225 return dev; 2226 } 2227 2228 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name) 2229 { 2230 PCIDevice *dev = pci_new(devfn, name); 2231 pci_realize_and_unref(dev, bus, &error_fatal); 2232 return dev; 2233 } 2234 2235 static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size) 2236 { 2237 int offset = PCI_CONFIG_HEADER_SIZE; 2238 int i; 2239 for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) { 2240 if (pdev->used[i]) 2241 offset = i + 1; 2242 else if (i - offset + 1 == size) 2243 return offset; 2244 } 2245 return 0; 2246 } 2247 2248 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id, 2249 uint8_t *prev_p) 2250 { 2251 uint8_t next, prev; 2252 2253 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST)) 2254 return 0; 2255 2256 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); 2257 prev = next + PCI_CAP_LIST_NEXT) 2258 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id) 2259 break; 2260 2261 if (prev_p) 2262 *prev_p = prev; 2263 return next; 2264 } 2265 2266 static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset) 2267 { 2268 uint8_t next, prev, found = 0; 2269 2270 if (!(pdev->used[offset])) { 2271 return 0; 2272 } 2273 2274 assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST); 2275 2276 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); 2277 prev = next + PCI_CAP_LIST_NEXT) { 2278 if (next <= offset && next > found) { 2279 found = next; 2280 } 2281 } 2282 return found; 2283 } 2284 2285 /* Patch the PCI vendor and device ids in a PCI rom image if necessary. 2286 This is needed for an option rom which is used for more than one device. */ 2287 static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, uint32_t size) 2288 { 2289 uint16_t vendor_id; 2290 uint16_t device_id; 2291 uint16_t rom_vendor_id; 2292 uint16_t rom_device_id; 2293 uint16_t rom_magic; 2294 uint16_t pcir_offset; 2295 uint8_t checksum; 2296 2297 /* Words in rom data are little endian (like in PCI configuration), 2298 so they can be read / written with pci_get_word / pci_set_word. */ 2299 2300 /* Only a valid rom will be patched. */ 2301 rom_magic = pci_get_word(ptr); 2302 if (rom_magic != 0xaa55) { 2303 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic); 2304 return; 2305 } 2306 pcir_offset = pci_get_word(ptr + 0x18); 2307 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) { 2308 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset); 2309 return; 2310 } 2311 2312 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID); 2313 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID); 2314 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4); 2315 rom_device_id = pci_get_word(ptr + pcir_offset + 6); 2316 2317 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile, 2318 vendor_id, device_id, rom_vendor_id, rom_device_id); 2319 2320 checksum = ptr[6]; 2321 2322 if (vendor_id != rom_vendor_id) { 2323 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */ 2324 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8); 2325 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8); 2326 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); 2327 ptr[6] = checksum; 2328 pci_set_word(ptr + pcir_offset + 4, vendor_id); 2329 } 2330 2331 if (device_id != rom_device_id) { 2332 /* Patch device id and checksum (at offset 6 for etherboot roms). */ 2333 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8); 2334 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8); 2335 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); 2336 ptr[6] = checksum; 2337 pci_set_word(ptr + pcir_offset + 6, device_id); 2338 } 2339 } 2340 2341 /* Add an option rom for the device */ 2342 static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, 2343 Error **errp) 2344 { 2345 int64_t size = 0; 2346 g_autofree char *path = NULL; 2347 char name[32]; 2348 const VMStateDescription *vmsd; 2349 2350 /* 2351 * In case of incoming migration ROM will come with migration stream, no 2352 * reason to load the file. Neither we want to fail if local ROM file 2353 * mismatches with specified romsize. 2354 */ 2355 bool load_file = !runstate_check(RUN_STATE_INMIGRATE); 2356 2357 if (!pdev->romfile || !strlen(pdev->romfile)) { 2358 return; 2359 } 2360 2361 if (!pdev->rom_bar) { 2362 /* 2363 * Load rom via fw_cfg instead of creating a rom bar, 2364 * for 0.11 compatibility. 2365 */ 2366 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE); 2367 2368 /* 2369 * Hot-plugged devices can't use the option ROM 2370 * if the rom bar is disabled. 2371 */ 2372 if (DEVICE(pdev)->hotplugged) { 2373 error_setg(errp, "Hot-plugged device without ROM bar" 2374 " can't have an option ROM"); 2375 return; 2376 } 2377 2378 if (class == 0x0300) { 2379 rom_add_vga(pdev->romfile); 2380 } else { 2381 rom_add_option(pdev->romfile, -1); 2382 } 2383 return; 2384 } 2385 2386 if (load_file || pdev->romsize == -1) { 2387 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile); 2388 if (path == NULL) { 2389 path = g_strdup(pdev->romfile); 2390 } 2391 2392 size = get_image_size(path); 2393 if (size < 0) { 2394 error_setg(errp, "failed to find romfile \"%s\"", pdev->romfile); 2395 return; 2396 } else if (size == 0) { 2397 error_setg(errp, "romfile \"%s\" is empty", pdev->romfile); 2398 return; 2399 } else if (size > 2 * GiB) { 2400 error_setg(errp, 2401 "romfile \"%s\" too large (size cannot exceed 2 GiB)", 2402 pdev->romfile); 2403 return; 2404 } 2405 if (pdev->romsize != -1) { 2406 if (size > pdev->romsize) { 2407 error_setg(errp, "romfile \"%s\" (%u bytes) " 2408 "is too large for ROM size %u", 2409 pdev->romfile, (uint32_t)size, pdev->romsize); 2410 return; 2411 } 2412 } else { 2413 pdev->romsize = pow2ceil(size); 2414 } 2415 } 2416 2417 vmsd = qdev_get_vmsd(DEVICE(pdev)); 2418 snprintf(name, sizeof(name), "%s.rom", 2419 vmsd ? vmsd->name : object_get_typename(OBJECT(pdev))); 2420 2421 pdev->has_rom = true; 2422 memory_region_init_rom(&pdev->rom, OBJECT(pdev), name, pdev->romsize, 2423 &error_fatal); 2424 2425 if (load_file) { 2426 void *ptr = memory_region_get_ram_ptr(&pdev->rom); 2427 2428 if (load_image_size(path, ptr, size) < 0) { 2429 error_setg(errp, "failed to load romfile \"%s\"", pdev->romfile); 2430 return; 2431 } 2432 2433 if (is_default_rom) { 2434 /* Only the default rom images will be patched (if needed). */ 2435 pci_patch_ids(pdev, ptr, size); 2436 } 2437 } 2438 2439 pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom); 2440 } 2441 2442 static void pci_del_option_rom(PCIDevice *pdev) 2443 { 2444 if (!pdev->has_rom) 2445 return; 2446 2447 vmstate_unregister_ram(&pdev->rom, &pdev->qdev); 2448 pdev->has_rom = false; 2449 } 2450 2451 /* 2452 * On success, pci_add_capability() returns a positive value 2453 * that the offset of the pci capability. 2454 * On failure, it sets an error and returns a negative error 2455 * code. 2456 */ 2457 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, 2458 uint8_t offset, uint8_t size, 2459 Error **errp) 2460 { 2461 uint8_t *config; 2462 int i, overlapping_cap; 2463 2464 if (!offset) { 2465 offset = pci_find_space(pdev, size); 2466 /* out of PCI config space is programming error */ 2467 assert(offset); 2468 } else { 2469 /* Verify that capabilities don't overlap. Note: device assignment 2470 * depends on this check to verify that the device is not broken. 2471 * Should never trigger for emulated devices, but it's helpful 2472 * for debugging these. */ 2473 for (i = offset; i < offset + size; i++) { 2474 overlapping_cap = pci_find_capability_at_offset(pdev, i); 2475 if (overlapping_cap) { 2476 error_setg(errp, "%s:%02x:%02x.%x " 2477 "Attempt to add PCI capability %x at offset " 2478 "%x overlaps existing capability %x at offset %x", 2479 pci_root_bus_path(pdev), pci_dev_bus_num(pdev), 2480 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), 2481 cap_id, offset, overlapping_cap, i); 2482 return -EINVAL; 2483 } 2484 } 2485 } 2486 2487 config = pdev->config + offset; 2488 config[PCI_CAP_LIST_ID] = cap_id; 2489 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST]; 2490 pdev->config[PCI_CAPABILITY_LIST] = offset; 2491 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST; 2492 memset(pdev->used + offset, 0xFF, QEMU_ALIGN_UP(size, 4)); 2493 /* Make capability read-only by default */ 2494 memset(pdev->wmask + offset, 0, size); 2495 /* Check capability by default */ 2496 memset(pdev->cmask + offset, 0xFF, size); 2497 return offset; 2498 } 2499 2500 /* Unlink capability from the pci config space. */ 2501 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size) 2502 { 2503 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev); 2504 if (!offset) 2505 return; 2506 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT]; 2507 /* Make capability writable again */ 2508 memset(pdev->wmask + offset, 0xff, size); 2509 memset(pdev->w1cmask + offset, 0, size); 2510 /* Clear cmask as device-specific registers can't be checked */ 2511 memset(pdev->cmask + offset, 0, size); 2512 memset(pdev->used + offset, 0, QEMU_ALIGN_UP(size, 4)); 2513 2514 if (!pdev->config[PCI_CAPABILITY_LIST]) 2515 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST; 2516 } 2517 2518 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id) 2519 { 2520 return pci_find_capability_list(pdev, cap_id, NULL); 2521 } 2522 2523 static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len) 2524 { 2525 PCIDevice *d = (PCIDevice *)dev; 2526 const char *name = NULL; 2527 const pci_class_desc *desc = pci_class_descriptions; 2528 int class = pci_get_word(d->config + PCI_CLASS_DEVICE); 2529 2530 while (desc->desc && 2531 (class & ~desc->fw_ign_bits) != 2532 (desc->class & ~desc->fw_ign_bits)) { 2533 desc++; 2534 } 2535 2536 if (desc->desc) { 2537 name = desc->fw_name; 2538 } 2539 2540 if (name) { 2541 pstrcpy(buf, len, name); 2542 } else { 2543 snprintf(buf, len, "pci%04x,%04x", 2544 pci_get_word(d->config + PCI_VENDOR_ID), 2545 pci_get_word(d->config + PCI_DEVICE_ID)); 2546 } 2547 2548 return buf; 2549 } 2550 2551 static char *pcibus_get_fw_dev_path(DeviceState *dev) 2552 { 2553 PCIDevice *d = (PCIDevice *)dev; 2554 char name[33]; 2555 int has_func = !!PCI_FUNC(d->devfn); 2556 2557 return g_strdup_printf("%s@%x%s%.*x", 2558 pci_dev_fw_name(dev, name, sizeof(name)), 2559 PCI_SLOT(d->devfn), 2560 has_func ? "," : "", 2561 has_func, 2562 PCI_FUNC(d->devfn)); 2563 } 2564 2565 static char *pcibus_get_dev_path(DeviceState *dev) 2566 { 2567 PCIDevice *d = container_of(dev, PCIDevice, qdev); 2568 PCIDevice *t; 2569 int slot_depth; 2570 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function. 2571 * 00 is added here to make this format compatible with 2572 * domain:Bus:Slot.Func for systems without nested PCI bridges. 2573 * Slot.Function list specifies the slot and function numbers for all 2574 * devices on the path from root to the specific device. */ 2575 const char *root_bus_path; 2576 int root_bus_len; 2577 char slot[] = ":SS.F"; 2578 int slot_len = sizeof slot - 1 /* For '\0' */; 2579 int path_len; 2580 char *path, *p; 2581 int s; 2582 2583 root_bus_path = pci_root_bus_path(d); 2584 root_bus_len = strlen(root_bus_path); 2585 2586 /* Calculate # of slots on path between device and root. */; 2587 slot_depth = 0; 2588 for (t = d; t; t = pci_get_bus(t)->parent_dev) { 2589 ++slot_depth; 2590 } 2591 2592 path_len = root_bus_len + slot_len * slot_depth; 2593 2594 /* Allocate memory, fill in the terminating null byte. */ 2595 path = g_malloc(path_len + 1 /* For '\0' */); 2596 path[path_len] = '\0'; 2597 2598 memcpy(path, root_bus_path, root_bus_len); 2599 2600 /* Fill in slot numbers. We walk up from device to root, so need to print 2601 * them in the reverse order, last to first. */ 2602 p = path + path_len; 2603 for (t = d; t; t = pci_get_bus(t)->parent_dev) { 2604 p -= slot_len; 2605 s = snprintf(slot, sizeof slot, ":%02x.%x", 2606 PCI_SLOT(t->devfn), PCI_FUNC(t->devfn)); 2607 assert(s == slot_len); 2608 memcpy(p, slot, slot_len); 2609 } 2610 2611 return path; 2612 } 2613 2614 static int pci_qdev_find_recursive(PCIBus *bus, 2615 const char *id, PCIDevice **pdev) 2616 { 2617 DeviceState *qdev = qdev_find_recursive(&bus->qbus, id); 2618 if (!qdev) { 2619 return -ENODEV; 2620 } 2621 2622 /* roughly check if given qdev is pci device */ 2623 if (object_dynamic_cast(OBJECT(qdev), TYPE_PCI_DEVICE)) { 2624 *pdev = PCI_DEVICE(qdev); 2625 return 0; 2626 } 2627 return -EINVAL; 2628 } 2629 2630 int pci_qdev_find_device(const char *id, PCIDevice **pdev) 2631 { 2632 PCIHostState *host_bridge; 2633 int rc = -ENODEV; 2634 2635 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { 2636 int tmp = pci_qdev_find_recursive(host_bridge->bus, id, pdev); 2637 if (!tmp) { 2638 rc = 0; 2639 break; 2640 } 2641 if (tmp != -ENODEV) { 2642 rc = tmp; 2643 } 2644 } 2645 2646 return rc; 2647 } 2648 2649 MemoryRegion *pci_address_space(PCIDevice *dev) 2650 { 2651 return pci_get_bus(dev)->address_space_mem; 2652 } 2653 2654 MemoryRegion *pci_address_space_io(PCIDevice *dev) 2655 { 2656 return pci_get_bus(dev)->address_space_io; 2657 } 2658 2659 static void pci_device_class_init(ObjectClass *klass, void *data) 2660 { 2661 DeviceClass *k = DEVICE_CLASS(klass); 2662 2663 k->realize = pci_qdev_realize; 2664 k->unrealize = pci_qdev_unrealize; 2665 k->bus_type = TYPE_PCI_BUS; 2666 device_class_set_props(k, pci_props); 2667 } 2668 2669 static void pci_device_class_base_init(ObjectClass *klass, void *data) 2670 { 2671 if (!object_class_is_abstract(klass)) { 2672 ObjectClass *conventional = 2673 object_class_dynamic_cast(klass, INTERFACE_CONVENTIONAL_PCI_DEVICE); 2674 ObjectClass *pcie = 2675 object_class_dynamic_cast(klass, INTERFACE_PCIE_DEVICE); 2676 ObjectClass *cxl = 2677 object_class_dynamic_cast(klass, INTERFACE_CXL_DEVICE); 2678 assert(conventional || pcie || cxl); 2679 } 2680 } 2681 2682 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev) 2683 { 2684 PCIBus *bus = pci_get_bus(dev); 2685 PCIBus *iommu_bus = bus; 2686 uint8_t devfn = dev->devfn; 2687 2688 while (iommu_bus && !iommu_bus->iommu_fn && iommu_bus->parent_dev) { 2689 PCIBus *parent_bus = pci_get_bus(iommu_bus->parent_dev); 2690 2691 /* 2692 * The requester ID of the provided device may be aliased, as seen from 2693 * the IOMMU, due to topology limitations. The IOMMU relies on a 2694 * requester ID to provide a unique AddressSpace for devices, but 2695 * conventional PCI buses pre-date such concepts. Instead, the PCIe- 2696 * to-PCI bridge creates and accepts transactions on behalf of down- 2697 * stream devices. When doing so, all downstream devices are masked 2698 * (aliased) behind a single requester ID. The requester ID used 2699 * depends on the format of the bridge devices. Proper PCIe-to-PCI 2700 * bridges, with a PCIe capability indicating such, follow the 2701 * guidelines of chapter 2.3 of the PCIe-to-PCI/X bridge specification, 2702 * where the bridge uses the seconary bus as the bridge portion of the 2703 * requester ID and devfn of 00.0. For other bridges, typically those 2704 * found on the root complex such as the dmi-to-pci-bridge, we follow 2705 * the convention of typical bare-metal hardware, which uses the 2706 * requester ID of the bridge itself. There are device specific 2707 * exceptions to these rules, but these are the defaults that the 2708 * Linux kernel uses when determining DMA aliases itself and believed 2709 * to be true for the bare metal equivalents of the devices emulated 2710 * in QEMU. 2711 */ 2712 if (!pci_bus_is_express(iommu_bus)) { 2713 PCIDevice *parent = iommu_bus->parent_dev; 2714 2715 if (pci_is_express(parent) && 2716 pcie_cap_get_type(parent) == PCI_EXP_TYPE_PCI_BRIDGE) { 2717 devfn = PCI_DEVFN(0, 0); 2718 bus = iommu_bus; 2719 } else { 2720 devfn = parent->devfn; 2721 bus = parent_bus; 2722 } 2723 } 2724 2725 iommu_bus = parent_bus; 2726 } 2727 if (!pci_bus_bypass_iommu(bus) && iommu_bus && iommu_bus->iommu_fn) { 2728 return iommu_bus->iommu_fn(bus, iommu_bus->iommu_opaque, devfn); 2729 } 2730 return &address_space_memory; 2731 } 2732 2733 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque) 2734 { 2735 bus->iommu_fn = fn; 2736 bus->iommu_opaque = opaque; 2737 } 2738 2739 static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque) 2740 { 2741 Range *range = opaque; 2742 uint16_t cmd = pci_get_word(dev->config + PCI_COMMAND); 2743 int i; 2744 2745 if (!(cmd & PCI_COMMAND_MEMORY)) { 2746 return; 2747 } 2748 2749 if (IS_PCI_BRIDGE(dev)) { 2750 pcibus_t base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 2751 pcibus_t limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 2752 2753 base = MAX(base, 0x1ULL << 32); 2754 2755 if (limit >= base) { 2756 Range pref_range; 2757 range_set_bounds(&pref_range, base, limit); 2758 range_extend(range, &pref_range); 2759 } 2760 } 2761 for (i = 0; i < PCI_NUM_REGIONS; ++i) { 2762 PCIIORegion *r = &dev->io_regions[i]; 2763 pcibus_t lob, upb; 2764 Range region_range; 2765 2766 if (!r->size || 2767 (r->type & PCI_BASE_ADDRESS_SPACE_IO) || 2768 !(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64)) { 2769 continue; 2770 } 2771 2772 lob = pci_bar_address(dev, i, r->type, r->size); 2773 upb = lob + r->size - 1; 2774 if (lob == PCI_BAR_UNMAPPED) { 2775 continue; 2776 } 2777 2778 lob = MAX(lob, 0x1ULL << 32); 2779 2780 if (upb >= lob) { 2781 range_set_bounds(®ion_range, lob, upb); 2782 range_extend(range, ®ion_range); 2783 } 2784 } 2785 } 2786 2787 void pci_bus_get_w64_range(PCIBus *bus, Range *range) 2788 { 2789 range_make_empty(range); 2790 pci_for_each_device_under_bus(bus, pci_dev_get_w64, range); 2791 } 2792 2793 static bool pcie_has_upstream_port(PCIDevice *dev) 2794 { 2795 PCIDevice *parent_dev = pci_bridge_get_device(pci_get_bus(dev)); 2796 2797 /* Device associated with an upstream port. 2798 * As there are several types of these, it's easier to check the 2799 * parent device: upstream ports are always connected to 2800 * root or downstream ports. 2801 */ 2802 return parent_dev && 2803 pci_is_express(parent_dev) && 2804 parent_dev->exp.exp_cap && 2805 (pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_ROOT_PORT || 2806 pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_DOWNSTREAM); 2807 } 2808 2809 PCIDevice *pci_get_function_0(PCIDevice *pci_dev) 2810 { 2811 PCIBus *bus = pci_get_bus(pci_dev); 2812 2813 if(pcie_has_upstream_port(pci_dev)) { 2814 /* With an upstream PCIe port, we only support 1 device at slot 0 */ 2815 return bus->devices[0]; 2816 } else { 2817 /* Other bus types might support multiple devices at slots 0-31 */ 2818 return bus->devices[PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 0)]; 2819 } 2820 } 2821 2822 MSIMessage pci_get_msi_message(PCIDevice *dev, int vector) 2823 { 2824 MSIMessage msg; 2825 if (msix_enabled(dev)) { 2826 msg = msix_get_message(dev, vector); 2827 } else if (msi_enabled(dev)) { 2828 msg = msi_get_message(dev, vector); 2829 } else { 2830 /* Should never happen */ 2831 error_report("%s: unknown interrupt type", __func__); 2832 abort(); 2833 } 2834 return msg; 2835 } 2836 2837 void pci_set_power(PCIDevice *d, bool state) 2838 { 2839 if (d->has_power == state) { 2840 return; 2841 } 2842 2843 d->has_power = state; 2844 pci_update_mappings(d); 2845 memory_region_set_enabled(&d->bus_master_enable_region, 2846 (pci_get_word(d->config + PCI_COMMAND) 2847 & PCI_COMMAND_MASTER) && d->has_power); 2848 if (!d->has_power) { 2849 pci_device_reset(d); 2850 } 2851 } 2852 2853 static const TypeInfo pci_device_type_info = { 2854 .name = TYPE_PCI_DEVICE, 2855 .parent = TYPE_DEVICE, 2856 .instance_size = sizeof(PCIDevice), 2857 .abstract = true, 2858 .class_size = sizeof(PCIDeviceClass), 2859 .class_init = pci_device_class_init, 2860 .class_base_init = pci_device_class_base_init, 2861 }; 2862 2863 static void pci_register_types(void) 2864 { 2865 type_register_static(&pci_bus_info); 2866 type_register_static(&pcie_bus_info); 2867 type_register_static(&cxl_bus_info); 2868 type_register_static(&conventional_pci_interface_info); 2869 type_register_static(&cxl_interface_info); 2870 type_register_static(&pcie_interface_info); 2871 type_register_static(&pci_device_type_info); 2872 } 2873 2874 type_init(pci_register_types) 2875