1 /* 2 * QEMU PCI bus manager 3 * 4 * Copyright (c) 2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/datadir.h" 27 #include "qemu/units.h" 28 #include "hw/irq.h" 29 #include "hw/pci/pci.h" 30 #include "hw/pci/pci_bridge.h" 31 #include "hw/pci/pci_bus.h" 32 #include "hw/pci/pci_host.h" 33 #include "hw/qdev-properties.h" 34 #include "hw/qdev-properties-system.h" 35 #include "migration/qemu-file-types.h" 36 #include "migration/vmstate.h" 37 #include "monitor/monitor.h" 38 #include "net/net.h" 39 #include "sysemu/numa.h" 40 #include "sysemu/sysemu.h" 41 #include "hw/loader.h" 42 #include "qemu/error-report.h" 43 #include "qemu/range.h" 44 #include "trace.h" 45 #include "hw/pci/msi.h" 46 #include "hw/pci/msix.h" 47 #include "hw/hotplug.h" 48 #include "hw/boards.h" 49 #include "qapi/error.h" 50 #include "qapi/qapi-commands-pci.h" 51 #include "qemu/cutils.h" 52 53 //#define DEBUG_PCI 54 #ifdef DEBUG_PCI 55 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) 56 #else 57 # define PCI_DPRINTF(format, ...) do { } while (0) 58 #endif 59 60 bool pci_available = true; 61 62 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent); 63 static char *pcibus_get_dev_path(DeviceState *dev); 64 static char *pcibus_get_fw_dev_path(DeviceState *dev); 65 static void pcibus_reset(BusState *qbus); 66 67 static Property pci_props[] = { 68 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1), 69 DEFINE_PROP_STRING("romfile", PCIDevice, romfile), 70 DEFINE_PROP_UINT32("romsize", PCIDevice, romsize, -1), 71 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1), 72 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present, 73 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false), 74 DEFINE_PROP_BIT("x-pcie-lnksta-dllla", PCIDevice, cap_present, 75 QEMU_PCIE_LNKSTA_DLLLA_BITNR, true), 76 DEFINE_PROP_BIT("x-pcie-extcap-init", PCIDevice, cap_present, 77 QEMU_PCIE_EXTCAP_INIT_BITNR, true), 78 DEFINE_PROP_STRING("failover_pair_id", PCIDevice, 79 failover_pair_id), 80 DEFINE_PROP_UINT32("acpi-index", PCIDevice, acpi_index, 0), 81 DEFINE_PROP_END_OF_LIST() 82 }; 83 84 static const VMStateDescription vmstate_pcibus = { 85 .name = "PCIBUS", 86 .version_id = 1, 87 .minimum_version_id = 1, 88 .fields = (VMStateField[]) { 89 VMSTATE_INT32_EQUAL(nirq, PCIBus, NULL), 90 VMSTATE_VARRAY_INT32(irq_count, PCIBus, 91 nirq, 0, vmstate_info_int32, 92 int32_t), 93 VMSTATE_END_OF_LIST() 94 } 95 }; 96 97 static void pci_init_bus_master(PCIDevice *pci_dev) 98 { 99 AddressSpace *dma_as = pci_device_iommu_address_space(pci_dev); 100 101 memory_region_init_alias(&pci_dev->bus_master_enable_region, 102 OBJECT(pci_dev), "bus master", 103 dma_as->root, 0, memory_region_size(dma_as->root)); 104 memory_region_set_enabled(&pci_dev->bus_master_enable_region, false); 105 memory_region_add_subregion(&pci_dev->bus_master_container_region, 0, 106 &pci_dev->bus_master_enable_region); 107 } 108 109 static void pcibus_machine_done(Notifier *notifier, void *data) 110 { 111 PCIBus *bus = container_of(notifier, PCIBus, machine_done); 112 int i; 113 114 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 115 if (bus->devices[i]) { 116 pci_init_bus_master(bus->devices[i]); 117 } 118 } 119 } 120 121 static void pci_bus_realize(BusState *qbus, Error **errp) 122 { 123 PCIBus *bus = PCI_BUS(qbus); 124 125 bus->machine_done.notify = pcibus_machine_done; 126 qemu_add_machine_init_done_notifier(&bus->machine_done); 127 128 vmstate_register(NULL, VMSTATE_INSTANCE_ID_ANY, &vmstate_pcibus, bus); 129 } 130 131 static void pcie_bus_realize(BusState *qbus, Error **errp) 132 { 133 PCIBus *bus = PCI_BUS(qbus); 134 Error *local_err = NULL; 135 136 pci_bus_realize(qbus, &local_err); 137 if (local_err) { 138 error_propagate(errp, local_err); 139 return; 140 } 141 142 /* 143 * A PCI-E bus can support extended config space if it's the root 144 * bus, or if the bus/bridge above it does as well 145 */ 146 if (pci_bus_is_root(bus)) { 147 bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE; 148 } else { 149 PCIBus *parent_bus = pci_get_bus(bus->parent_dev); 150 151 if (pci_bus_allows_extended_config_space(parent_bus)) { 152 bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE; 153 } 154 } 155 } 156 157 static void pci_bus_unrealize(BusState *qbus) 158 { 159 PCIBus *bus = PCI_BUS(qbus); 160 161 qemu_remove_machine_init_done_notifier(&bus->machine_done); 162 163 vmstate_unregister(NULL, &vmstate_pcibus, bus); 164 } 165 166 static int pcibus_num(PCIBus *bus) 167 { 168 if (pci_bus_is_root(bus)) { 169 return 0; /* pci host bridge */ 170 } 171 return bus->parent_dev->config[PCI_SECONDARY_BUS]; 172 } 173 174 static uint16_t pcibus_numa_node(PCIBus *bus) 175 { 176 return NUMA_NODE_UNASSIGNED; 177 } 178 179 static void pci_bus_class_init(ObjectClass *klass, void *data) 180 { 181 BusClass *k = BUS_CLASS(klass); 182 PCIBusClass *pbc = PCI_BUS_CLASS(klass); 183 184 k->print_dev = pcibus_dev_print; 185 k->get_dev_path = pcibus_get_dev_path; 186 k->get_fw_dev_path = pcibus_get_fw_dev_path; 187 k->realize = pci_bus_realize; 188 k->unrealize = pci_bus_unrealize; 189 k->reset = pcibus_reset; 190 191 pbc->bus_num = pcibus_num; 192 pbc->numa_node = pcibus_numa_node; 193 } 194 195 static const TypeInfo pci_bus_info = { 196 .name = TYPE_PCI_BUS, 197 .parent = TYPE_BUS, 198 .instance_size = sizeof(PCIBus), 199 .class_size = sizeof(PCIBusClass), 200 .class_init = pci_bus_class_init, 201 }; 202 203 static const TypeInfo cxl_interface_info = { 204 .name = INTERFACE_CXL_DEVICE, 205 .parent = TYPE_INTERFACE, 206 }; 207 208 static const TypeInfo pcie_interface_info = { 209 .name = INTERFACE_PCIE_DEVICE, 210 .parent = TYPE_INTERFACE, 211 }; 212 213 static const TypeInfo conventional_pci_interface_info = { 214 .name = INTERFACE_CONVENTIONAL_PCI_DEVICE, 215 .parent = TYPE_INTERFACE, 216 }; 217 218 static void pcie_bus_class_init(ObjectClass *klass, void *data) 219 { 220 BusClass *k = BUS_CLASS(klass); 221 222 k->realize = pcie_bus_realize; 223 } 224 225 static const TypeInfo pcie_bus_info = { 226 .name = TYPE_PCIE_BUS, 227 .parent = TYPE_PCI_BUS, 228 .class_init = pcie_bus_class_init, 229 }; 230 231 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num); 232 static void pci_update_mappings(PCIDevice *d); 233 static void pci_irq_handler(void *opaque, int irq_num, int level); 234 static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, Error **); 235 static void pci_del_option_rom(PCIDevice *pdev); 236 237 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET; 238 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU; 239 240 static QLIST_HEAD(, PCIHostState) pci_host_bridges; 241 242 int pci_bar(PCIDevice *d, int reg) 243 { 244 uint8_t type; 245 246 /* PCIe virtual functions do not have their own BARs */ 247 assert(!pci_is_vf(d)); 248 249 if (reg != PCI_ROM_SLOT) 250 return PCI_BASE_ADDRESS_0 + reg * 4; 251 252 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 253 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS; 254 } 255 256 static inline int pci_irq_state(PCIDevice *d, int irq_num) 257 { 258 return (d->irq_state >> irq_num) & 0x1; 259 } 260 261 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level) 262 { 263 d->irq_state &= ~(0x1 << irq_num); 264 d->irq_state |= level << irq_num; 265 } 266 267 static void pci_bus_change_irq_level(PCIBus *bus, int irq_num, int change) 268 { 269 assert(irq_num >= 0); 270 assert(irq_num < bus->nirq); 271 bus->irq_count[irq_num] += change; 272 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0); 273 } 274 275 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change) 276 { 277 PCIBus *bus; 278 for (;;) { 279 bus = pci_get_bus(pci_dev); 280 irq_num = bus->map_irq(pci_dev, irq_num); 281 if (bus->set_irq) 282 break; 283 pci_dev = bus->parent_dev; 284 } 285 pci_bus_change_irq_level(bus, irq_num, change); 286 } 287 288 int pci_bus_get_irq_level(PCIBus *bus, int irq_num) 289 { 290 assert(irq_num >= 0); 291 assert(irq_num < bus->nirq); 292 return !!bus->irq_count[irq_num]; 293 } 294 295 /* Update interrupt status bit in config space on interrupt 296 * state change. */ 297 static void pci_update_irq_status(PCIDevice *dev) 298 { 299 if (dev->irq_state) { 300 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT; 301 } else { 302 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; 303 } 304 } 305 306 void pci_device_deassert_intx(PCIDevice *dev) 307 { 308 int i; 309 for (i = 0; i < PCI_NUM_PINS; ++i) { 310 pci_irq_handler(dev, i, 0); 311 } 312 } 313 314 static void pci_reset_regions(PCIDevice *dev) 315 { 316 int r; 317 if (pci_is_vf(dev)) { 318 return; 319 } 320 321 for (r = 0; r < PCI_NUM_REGIONS; ++r) { 322 PCIIORegion *region = &dev->io_regions[r]; 323 if (!region->size) { 324 continue; 325 } 326 327 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) && 328 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 329 pci_set_quad(dev->config + pci_bar(dev, r), region->type); 330 } else { 331 pci_set_long(dev->config + pci_bar(dev, r), region->type); 332 } 333 } 334 } 335 336 static void pci_do_device_reset(PCIDevice *dev) 337 { 338 pci_device_deassert_intx(dev); 339 assert(dev->irq_state == 0); 340 341 /* Clear all writable bits */ 342 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND, 343 pci_get_word(dev->wmask + PCI_COMMAND) | 344 pci_get_word(dev->w1cmask + PCI_COMMAND)); 345 pci_word_test_and_clear_mask(dev->config + PCI_STATUS, 346 pci_get_word(dev->wmask + PCI_STATUS) | 347 pci_get_word(dev->w1cmask + PCI_STATUS)); 348 /* Some devices make bits of PCI_INTERRUPT_LINE read only */ 349 pci_byte_test_and_clear_mask(dev->config + PCI_INTERRUPT_LINE, 350 pci_get_word(dev->wmask + PCI_INTERRUPT_LINE) | 351 pci_get_word(dev->w1cmask + PCI_INTERRUPT_LINE)); 352 dev->config[PCI_CACHE_LINE_SIZE] = 0x0; 353 pci_reset_regions(dev); 354 pci_update_mappings(dev); 355 356 msi_reset(dev); 357 msix_reset(dev); 358 } 359 360 /* 361 * This function is called on #RST and FLR. 362 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set 363 */ 364 void pci_device_reset(PCIDevice *dev) 365 { 366 qdev_reset_all(&dev->qdev); 367 pci_do_device_reset(dev); 368 } 369 370 /* 371 * Trigger pci bus reset under a given bus. 372 * Called via qbus_reset_all on RST# assert, after the devices 373 * have been reset qdev_reset_all-ed already. 374 */ 375 static void pcibus_reset(BusState *qbus) 376 { 377 PCIBus *bus = DO_UPCAST(PCIBus, qbus, qbus); 378 int i; 379 380 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 381 if (bus->devices[i]) { 382 pci_do_device_reset(bus->devices[i]); 383 } 384 } 385 386 for (i = 0; i < bus->nirq; i++) { 387 assert(bus->irq_count[i] == 0); 388 } 389 } 390 391 static void pci_host_bus_register(DeviceState *host) 392 { 393 PCIHostState *host_bridge = PCI_HOST_BRIDGE(host); 394 395 QLIST_INSERT_HEAD(&pci_host_bridges, host_bridge, next); 396 } 397 398 static void pci_host_bus_unregister(DeviceState *host) 399 { 400 PCIHostState *host_bridge = PCI_HOST_BRIDGE(host); 401 402 QLIST_REMOVE(host_bridge, next); 403 } 404 405 PCIBus *pci_device_root_bus(const PCIDevice *d) 406 { 407 PCIBus *bus = pci_get_bus(d); 408 409 while (!pci_bus_is_root(bus)) { 410 d = bus->parent_dev; 411 assert(d != NULL); 412 413 bus = pci_get_bus(d); 414 } 415 416 return bus; 417 } 418 419 const char *pci_root_bus_path(PCIDevice *dev) 420 { 421 PCIBus *rootbus = pci_device_root_bus(dev); 422 PCIHostState *host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent); 423 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_GET_CLASS(host_bridge); 424 425 assert(host_bridge->bus == rootbus); 426 427 if (hc->root_bus_path) { 428 return (*hc->root_bus_path)(host_bridge, rootbus); 429 } 430 431 return rootbus->qbus.name; 432 } 433 434 bool pci_bus_bypass_iommu(PCIBus *bus) 435 { 436 PCIBus *rootbus = bus; 437 PCIHostState *host_bridge; 438 439 if (!pci_bus_is_root(bus)) { 440 rootbus = pci_device_root_bus(bus->parent_dev); 441 } 442 443 host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent); 444 445 assert(host_bridge->bus == rootbus); 446 447 return host_bridge->bypass_iommu; 448 } 449 450 static void pci_root_bus_internal_init(PCIBus *bus, DeviceState *parent, 451 MemoryRegion *address_space_mem, 452 MemoryRegion *address_space_io, 453 uint8_t devfn_min) 454 { 455 assert(PCI_FUNC(devfn_min) == 0); 456 bus->devfn_min = devfn_min; 457 bus->slot_reserved_mask = 0x0; 458 bus->address_space_mem = address_space_mem; 459 bus->address_space_io = address_space_io; 460 bus->flags |= PCI_BUS_IS_ROOT; 461 462 /* host bridge */ 463 QLIST_INIT(&bus->child); 464 465 pci_host_bus_register(parent); 466 } 467 468 static void pci_bus_uninit(PCIBus *bus) 469 { 470 pci_host_bus_unregister(BUS(bus)->parent); 471 } 472 473 bool pci_bus_is_express(PCIBus *bus) 474 { 475 return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS); 476 } 477 478 void pci_root_bus_init(PCIBus *bus, size_t bus_size, DeviceState *parent, 479 const char *name, 480 MemoryRegion *address_space_mem, 481 MemoryRegion *address_space_io, 482 uint8_t devfn_min, const char *typename) 483 { 484 qbus_init(bus, bus_size, typename, parent, name); 485 pci_root_bus_internal_init(bus, parent, address_space_mem, 486 address_space_io, devfn_min); 487 } 488 489 PCIBus *pci_root_bus_new(DeviceState *parent, const char *name, 490 MemoryRegion *address_space_mem, 491 MemoryRegion *address_space_io, 492 uint8_t devfn_min, const char *typename) 493 { 494 PCIBus *bus; 495 496 bus = PCI_BUS(qbus_new(typename, parent, name)); 497 pci_root_bus_internal_init(bus, parent, address_space_mem, 498 address_space_io, devfn_min); 499 return bus; 500 } 501 502 void pci_root_bus_cleanup(PCIBus *bus) 503 { 504 pci_bus_uninit(bus); 505 /* the caller of the unplug hotplug handler will delete this device */ 506 qbus_unrealize(BUS(bus)); 507 } 508 509 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 510 void *irq_opaque, int nirq) 511 { 512 bus->set_irq = set_irq; 513 bus->map_irq = map_irq; 514 bus->irq_opaque = irq_opaque; 515 bus->nirq = nirq; 516 bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0])); 517 } 518 519 void pci_bus_irqs_cleanup(PCIBus *bus) 520 { 521 bus->set_irq = NULL; 522 bus->map_irq = NULL; 523 bus->irq_opaque = NULL; 524 bus->nirq = 0; 525 g_free(bus->irq_count); 526 } 527 528 PCIBus *pci_register_root_bus(DeviceState *parent, const char *name, 529 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 530 void *irq_opaque, 531 MemoryRegion *address_space_mem, 532 MemoryRegion *address_space_io, 533 uint8_t devfn_min, int nirq, 534 const char *typename) 535 { 536 PCIBus *bus; 537 538 bus = pci_root_bus_new(parent, name, address_space_mem, 539 address_space_io, devfn_min, typename); 540 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq); 541 return bus; 542 } 543 544 void pci_unregister_root_bus(PCIBus *bus) 545 { 546 pci_bus_irqs_cleanup(bus); 547 pci_root_bus_cleanup(bus); 548 } 549 550 int pci_bus_num(PCIBus *s) 551 { 552 return PCI_BUS_GET_CLASS(s)->bus_num(s); 553 } 554 555 /* Returns the min and max bus numbers of a PCI bus hierarchy */ 556 void pci_bus_range(PCIBus *bus, int *min_bus, int *max_bus) 557 { 558 int i; 559 *min_bus = *max_bus = pci_bus_num(bus); 560 561 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 562 PCIDevice *dev = bus->devices[i]; 563 564 if (dev && PCI_DEVICE_GET_CLASS(dev)->is_bridge) { 565 *min_bus = MIN(*min_bus, dev->config[PCI_SECONDARY_BUS]); 566 *max_bus = MAX(*max_bus, dev->config[PCI_SUBORDINATE_BUS]); 567 } 568 } 569 } 570 571 int pci_bus_numa_node(PCIBus *bus) 572 { 573 return PCI_BUS_GET_CLASS(bus)->numa_node(bus); 574 } 575 576 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size, 577 const VMStateField *field) 578 { 579 PCIDevice *s = container_of(pv, PCIDevice, config); 580 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(s); 581 uint8_t *config; 582 int i; 583 584 assert(size == pci_config_size(s)); 585 config = g_malloc(size); 586 587 qemu_get_buffer(f, config, size); 588 for (i = 0; i < size; ++i) { 589 if ((config[i] ^ s->config[i]) & 590 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) { 591 error_report("%s: Bad config data: i=0x%x read: %x device: %x " 592 "cmask: %x wmask: %x w1cmask:%x", __func__, 593 i, config[i], s->config[i], 594 s->cmask[i], s->wmask[i], s->w1cmask[i]); 595 g_free(config); 596 return -EINVAL; 597 } 598 } 599 memcpy(s->config, config, size); 600 601 pci_update_mappings(s); 602 if (pc->is_bridge) { 603 PCIBridge *b = PCI_BRIDGE(s); 604 pci_bridge_update_mappings(b); 605 } 606 607 memory_region_set_enabled(&s->bus_master_enable_region, 608 pci_get_word(s->config + PCI_COMMAND) 609 & PCI_COMMAND_MASTER); 610 611 g_free(config); 612 return 0; 613 } 614 615 /* just put buffer */ 616 static int put_pci_config_device(QEMUFile *f, void *pv, size_t size, 617 const VMStateField *field, JSONWriter *vmdesc) 618 { 619 const uint8_t **v = pv; 620 assert(size == pci_config_size(container_of(pv, PCIDevice, config))); 621 qemu_put_buffer(f, *v, size); 622 623 return 0; 624 } 625 626 static VMStateInfo vmstate_info_pci_config = { 627 .name = "pci config", 628 .get = get_pci_config_device, 629 .put = put_pci_config_device, 630 }; 631 632 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size, 633 const VMStateField *field) 634 { 635 PCIDevice *s = container_of(pv, PCIDevice, irq_state); 636 uint32_t irq_state[PCI_NUM_PINS]; 637 int i; 638 for (i = 0; i < PCI_NUM_PINS; ++i) { 639 irq_state[i] = qemu_get_be32(f); 640 if (irq_state[i] != 0x1 && irq_state[i] != 0) { 641 fprintf(stderr, "irq state %d: must be 0 or 1.\n", 642 irq_state[i]); 643 return -EINVAL; 644 } 645 } 646 647 for (i = 0; i < PCI_NUM_PINS; ++i) { 648 pci_set_irq_state(s, i, irq_state[i]); 649 } 650 651 return 0; 652 } 653 654 static int put_pci_irq_state(QEMUFile *f, void *pv, size_t size, 655 const VMStateField *field, JSONWriter *vmdesc) 656 { 657 int i; 658 PCIDevice *s = container_of(pv, PCIDevice, irq_state); 659 660 for (i = 0; i < PCI_NUM_PINS; ++i) { 661 qemu_put_be32(f, pci_irq_state(s, i)); 662 } 663 664 return 0; 665 } 666 667 static VMStateInfo vmstate_info_pci_irq_state = { 668 .name = "pci irq state", 669 .get = get_pci_irq_state, 670 .put = put_pci_irq_state, 671 }; 672 673 static bool migrate_is_pcie(void *opaque, int version_id) 674 { 675 return pci_is_express((PCIDevice *)opaque); 676 } 677 678 static bool migrate_is_not_pcie(void *opaque, int version_id) 679 { 680 return !pci_is_express((PCIDevice *)opaque); 681 } 682 683 const VMStateDescription vmstate_pci_device = { 684 .name = "PCIDevice", 685 .version_id = 2, 686 .minimum_version_id = 1, 687 .fields = (VMStateField[]) { 688 VMSTATE_INT32_POSITIVE_LE(version_id, PCIDevice), 689 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice, 690 migrate_is_not_pcie, 691 0, vmstate_info_pci_config, 692 PCI_CONFIG_SPACE_SIZE), 693 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice, 694 migrate_is_pcie, 695 0, vmstate_info_pci_config, 696 PCIE_CONFIG_SPACE_SIZE), 697 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2, 698 vmstate_info_pci_irq_state, 699 PCI_NUM_PINS * sizeof(int32_t)), 700 VMSTATE_END_OF_LIST() 701 } 702 }; 703 704 705 void pci_device_save(PCIDevice *s, QEMUFile *f) 706 { 707 /* Clear interrupt status bit: it is implicit 708 * in irq_state which we are saving. 709 * This makes us compatible with old devices 710 * which never set or clear this bit. */ 711 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; 712 vmstate_save_state(f, &vmstate_pci_device, s, NULL); 713 /* Restore the interrupt status bit. */ 714 pci_update_irq_status(s); 715 } 716 717 int pci_device_load(PCIDevice *s, QEMUFile *f) 718 { 719 int ret; 720 ret = vmstate_load_state(f, &vmstate_pci_device, s, s->version_id); 721 /* Restore the interrupt status bit. */ 722 pci_update_irq_status(s); 723 return ret; 724 } 725 726 static void pci_set_default_subsystem_id(PCIDevice *pci_dev) 727 { 728 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, 729 pci_default_sub_vendor_id); 730 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 731 pci_default_sub_device_id); 732 } 733 734 /* 735 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL 736 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error 737 */ 738 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, 739 unsigned int *slotp, unsigned int *funcp) 740 { 741 const char *p; 742 char *e; 743 unsigned long val; 744 unsigned long dom = 0, bus = 0; 745 unsigned int slot = 0; 746 unsigned int func = 0; 747 748 p = addr; 749 val = strtoul(p, &e, 16); 750 if (e == p) 751 return -1; 752 if (*e == ':') { 753 bus = val; 754 p = e + 1; 755 val = strtoul(p, &e, 16); 756 if (e == p) 757 return -1; 758 if (*e == ':') { 759 dom = bus; 760 bus = val; 761 p = e + 1; 762 val = strtoul(p, &e, 16); 763 if (e == p) 764 return -1; 765 } 766 } 767 768 slot = val; 769 770 if (funcp != NULL) { 771 if (*e != '.') 772 return -1; 773 774 p = e + 1; 775 val = strtoul(p, &e, 16); 776 if (e == p) 777 return -1; 778 779 func = val; 780 } 781 782 /* if funcp == NULL func is 0 */ 783 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7) 784 return -1; 785 786 if (*e) 787 return -1; 788 789 *domp = dom; 790 *busp = bus; 791 *slotp = slot; 792 if (funcp != NULL) 793 *funcp = func; 794 return 0; 795 } 796 797 static void pci_init_cmask(PCIDevice *dev) 798 { 799 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff); 800 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff); 801 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST; 802 dev->cmask[PCI_REVISION_ID] = 0xff; 803 dev->cmask[PCI_CLASS_PROG] = 0xff; 804 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff); 805 dev->cmask[PCI_HEADER_TYPE] = 0xff; 806 dev->cmask[PCI_CAPABILITY_LIST] = 0xff; 807 } 808 809 static void pci_init_wmask(PCIDevice *dev) 810 { 811 int config_size = pci_config_size(dev); 812 813 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff; 814 dev->wmask[PCI_INTERRUPT_LINE] = 0xff; 815 pci_set_word(dev->wmask + PCI_COMMAND, 816 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | 817 PCI_COMMAND_INTX_DISABLE); 818 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR); 819 820 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff, 821 config_size - PCI_CONFIG_HEADER_SIZE); 822 } 823 824 static void pci_init_w1cmask(PCIDevice *dev) 825 { 826 /* 827 * Note: It's okay to set w1cmask even for readonly bits as 828 * long as their value is hardwired to 0. 829 */ 830 pci_set_word(dev->w1cmask + PCI_STATUS, 831 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT | 832 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT | 833 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY); 834 } 835 836 static void pci_init_mask_bridge(PCIDevice *d) 837 { 838 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and 839 PCI_SEC_LETENCY_TIMER */ 840 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4); 841 842 /* base and limit */ 843 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff; 844 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff; 845 pci_set_word(d->wmask + PCI_MEMORY_BASE, 846 PCI_MEMORY_RANGE_MASK & 0xffff); 847 pci_set_word(d->wmask + PCI_MEMORY_LIMIT, 848 PCI_MEMORY_RANGE_MASK & 0xffff); 849 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE, 850 PCI_PREF_RANGE_MASK & 0xffff); 851 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT, 852 PCI_PREF_RANGE_MASK & 0xffff); 853 854 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */ 855 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8); 856 857 /* Supported memory and i/o types */ 858 d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16; 859 d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16; 860 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE, 861 PCI_PREF_RANGE_TYPE_64); 862 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT, 863 PCI_PREF_RANGE_TYPE_64); 864 865 /* 866 * TODO: Bridges default to 10-bit VGA decoding but we currently only 867 * implement 16-bit decoding (no alias support). 868 */ 869 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 870 PCI_BRIDGE_CTL_PARITY | 871 PCI_BRIDGE_CTL_SERR | 872 PCI_BRIDGE_CTL_ISA | 873 PCI_BRIDGE_CTL_VGA | 874 PCI_BRIDGE_CTL_VGA_16BIT | 875 PCI_BRIDGE_CTL_MASTER_ABORT | 876 PCI_BRIDGE_CTL_BUS_RESET | 877 PCI_BRIDGE_CTL_FAST_BACK | 878 PCI_BRIDGE_CTL_DISCARD | 879 PCI_BRIDGE_CTL_SEC_DISCARD | 880 PCI_BRIDGE_CTL_DISCARD_SERR); 881 /* Below does not do anything as we never set this bit, put here for 882 * completeness. */ 883 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL, 884 PCI_BRIDGE_CTL_DISCARD_STATUS); 885 d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK; 886 d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK; 887 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE, 888 PCI_PREF_RANGE_TYPE_MASK); 889 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT, 890 PCI_PREF_RANGE_TYPE_MASK); 891 } 892 893 static void pci_init_multifunction(PCIBus *bus, PCIDevice *dev, Error **errp) 894 { 895 uint8_t slot = PCI_SLOT(dev->devfn); 896 uint8_t func; 897 898 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 899 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION; 900 } 901 902 /* 903 * With SR/IOV and ARI, a device at function 0 need not be a multifunction 904 * device, as it may just be a VF that ended up with function 0 in 905 * the legacy PCI interpretation. Avoid failing in such cases: 906 */ 907 if (pci_is_vf(dev) && 908 dev->exp.sriov_vf.pf->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 909 return; 910 } 911 912 /* 913 * multifunction bit is interpreted in two ways as follows. 914 * - all functions must set the bit to 1. 915 * Example: Intel X53 916 * - function 0 must set the bit, but the rest function (> 0) 917 * is allowed to leave the bit to 0. 918 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10, 919 * 920 * So OS (at least Linux) checks the bit of only function 0, 921 * and doesn't see the bit of function > 0. 922 * 923 * The below check allows both interpretation. 924 */ 925 if (PCI_FUNC(dev->devfn)) { 926 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)]; 927 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) { 928 /* function 0 should set multifunction bit */ 929 error_setg(errp, "PCI: single function device can't be populated " 930 "in function %x.%x", slot, PCI_FUNC(dev->devfn)); 931 return; 932 } 933 return; 934 } 935 936 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 937 return; 938 } 939 /* function 0 indicates single function, so function > 0 must be NULL */ 940 for (func = 1; func < PCI_FUNC_MAX; ++func) { 941 if (bus->devices[PCI_DEVFN(slot, func)]) { 942 error_setg(errp, "PCI: %x.0 indicates single function, " 943 "but %x.%x is already populated.", 944 slot, slot, func); 945 return; 946 } 947 } 948 } 949 950 static void pci_config_alloc(PCIDevice *pci_dev) 951 { 952 int config_size = pci_config_size(pci_dev); 953 954 pci_dev->config = g_malloc0(config_size); 955 pci_dev->cmask = g_malloc0(config_size); 956 pci_dev->wmask = g_malloc0(config_size); 957 pci_dev->w1cmask = g_malloc0(config_size); 958 pci_dev->used = g_malloc0(config_size); 959 } 960 961 static void pci_config_free(PCIDevice *pci_dev) 962 { 963 g_free(pci_dev->config); 964 g_free(pci_dev->cmask); 965 g_free(pci_dev->wmask); 966 g_free(pci_dev->w1cmask); 967 g_free(pci_dev->used); 968 } 969 970 static void do_pci_unregister_device(PCIDevice *pci_dev) 971 { 972 pci_get_bus(pci_dev)->devices[pci_dev->devfn] = NULL; 973 pci_config_free(pci_dev); 974 975 if (memory_region_is_mapped(&pci_dev->bus_master_enable_region)) { 976 memory_region_del_subregion(&pci_dev->bus_master_container_region, 977 &pci_dev->bus_master_enable_region); 978 } 979 address_space_destroy(&pci_dev->bus_master_as); 980 } 981 982 /* Extract PCIReqIDCache into BDF format */ 983 static uint16_t pci_req_id_cache_extract(PCIReqIDCache *cache) 984 { 985 uint8_t bus_n; 986 uint16_t result; 987 988 switch (cache->type) { 989 case PCI_REQ_ID_BDF: 990 result = pci_get_bdf(cache->dev); 991 break; 992 case PCI_REQ_ID_SECONDARY_BUS: 993 bus_n = pci_dev_bus_num(cache->dev); 994 result = PCI_BUILD_BDF(bus_n, 0); 995 break; 996 default: 997 error_report("Invalid PCI requester ID cache type: %d", 998 cache->type); 999 exit(1); 1000 break; 1001 } 1002 1003 return result; 1004 } 1005 1006 /* Parse bridges up to the root complex and return requester ID 1007 * cache for specific device. For full PCIe topology, the cache 1008 * result would be exactly the same as getting BDF of the device. 1009 * However, several tricks are required when system mixed up with 1010 * legacy PCI devices and PCIe-to-PCI bridges. 1011 * 1012 * Here we cache the proxy device (and type) not requester ID since 1013 * bus number might change from time to time. 1014 */ 1015 static PCIReqIDCache pci_req_id_cache_get(PCIDevice *dev) 1016 { 1017 PCIDevice *parent; 1018 PCIReqIDCache cache = { 1019 .dev = dev, 1020 .type = PCI_REQ_ID_BDF, 1021 }; 1022 1023 while (!pci_bus_is_root(pci_get_bus(dev))) { 1024 /* We are under PCI/PCIe bridges */ 1025 parent = pci_get_bus(dev)->parent_dev; 1026 if (pci_is_express(parent)) { 1027 if (pcie_cap_get_type(parent) == PCI_EXP_TYPE_PCI_BRIDGE) { 1028 /* When we pass through PCIe-to-PCI/PCIX bridges, we 1029 * override the requester ID using secondary bus 1030 * number of parent bridge with zeroed devfn 1031 * (pcie-to-pci bridge spec chap 2.3). */ 1032 cache.type = PCI_REQ_ID_SECONDARY_BUS; 1033 cache.dev = dev; 1034 } 1035 } else { 1036 /* Legacy PCI, override requester ID with the bridge's 1037 * BDF upstream. When the root complex connects to 1038 * legacy PCI devices (including buses), it can only 1039 * obtain requester ID info from directly attached 1040 * devices. If devices are attached under bridges, only 1041 * the requester ID of the bridge that is directly 1042 * attached to the root complex can be recognized. */ 1043 cache.type = PCI_REQ_ID_BDF; 1044 cache.dev = parent; 1045 } 1046 dev = parent; 1047 } 1048 1049 return cache; 1050 } 1051 1052 uint16_t pci_requester_id(PCIDevice *dev) 1053 { 1054 return pci_req_id_cache_extract(&dev->requester_id_cache); 1055 } 1056 1057 static bool pci_bus_devfn_available(PCIBus *bus, int devfn) 1058 { 1059 return !(bus->devices[devfn]); 1060 } 1061 1062 static bool pci_bus_devfn_reserved(PCIBus *bus, int devfn) 1063 { 1064 return bus->slot_reserved_mask & (1UL << PCI_SLOT(devfn)); 1065 } 1066 1067 /* -1 for devfn means auto assign */ 1068 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, 1069 const char *name, int devfn, 1070 Error **errp) 1071 { 1072 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 1073 PCIConfigReadFunc *config_read = pc->config_read; 1074 PCIConfigWriteFunc *config_write = pc->config_write; 1075 Error *local_err = NULL; 1076 DeviceState *dev = DEVICE(pci_dev); 1077 PCIBus *bus = pci_get_bus(pci_dev); 1078 1079 /* Only pci bridges can be attached to extra PCI root buses */ 1080 if (pci_bus_is_root(bus) && bus->parent_dev && !pc->is_bridge) { 1081 error_setg(errp, 1082 "PCI: Only PCI/PCIe bridges can be plugged into %s", 1083 bus->parent_dev->name); 1084 return NULL; 1085 } 1086 1087 if (devfn < 0) { 1088 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices); 1089 devfn += PCI_FUNC_MAX) { 1090 if (pci_bus_devfn_available(bus, devfn) && 1091 !pci_bus_devfn_reserved(bus, devfn)) { 1092 goto found; 1093 } 1094 } 1095 error_setg(errp, "PCI: no slot/function available for %s, all in use " 1096 "or reserved", name); 1097 return NULL; 1098 found: ; 1099 } else if (pci_bus_devfn_reserved(bus, devfn)) { 1100 error_setg(errp, "PCI: slot %d function %d not available for %s," 1101 " reserved", 1102 PCI_SLOT(devfn), PCI_FUNC(devfn), name); 1103 return NULL; 1104 } else if (!pci_bus_devfn_available(bus, devfn)) { 1105 error_setg(errp, "PCI: slot %d function %d not available for %s," 1106 " in use by %s,id=%s", 1107 PCI_SLOT(devfn), PCI_FUNC(devfn), name, 1108 bus->devices[devfn]->name, bus->devices[devfn]->qdev.id); 1109 return NULL; 1110 } else if (dev->hotplugged && 1111 !pci_is_vf(pci_dev) && 1112 pci_get_function_0(pci_dev)) { 1113 error_setg(errp, "PCI: slot %d function 0 already occupied by %s," 1114 " new func %s cannot be exposed to guest.", 1115 PCI_SLOT(pci_get_function_0(pci_dev)->devfn), 1116 pci_get_function_0(pci_dev)->name, 1117 name); 1118 1119 return NULL; 1120 } 1121 1122 pci_dev->devfn = devfn; 1123 pci_dev->requester_id_cache = pci_req_id_cache_get(pci_dev); 1124 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name); 1125 1126 memory_region_init(&pci_dev->bus_master_container_region, OBJECT(pci_dev), 1127 "bus master container", UINT64_MAX); 1128 address_space_init(&pci_dev->bus_master_as, 1129 &pci_dev->bus_master_container_region, pci_dev->name); 1130 1131 if (phase_check(PHASE_MACHINE_READY)) { 1132 pci_init_bus_master(pci_dev); 1133 } 1134 pci_dev->irq_state = 0; 1135 pci_config_alloc(pci_dev); 1136 1137 pci_config_set_vendor_id(pci_dev->config, pc->vendor_id); 1138 pci_config_set_device_id(pci_dev->config, pc->device_id); 1139 pci_config_set_revision(pci_dev->config, pc->revision); 1140 pci_config_set_class(pci_dev->config, pc->class_id); 1141 1142 if (!pc->is_bridge) { 1143 if (pc->subsystem_vendor_id || pc->subsystem_id) { 1144 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, 1145 pc->subsystem_vendor_id); 1146 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 1147 pc->subsystem_id); 1148 } else { 1149 pci_set_default_subsystem_id(pci_dev); 1150 } 1151 } else { 1152 /* subsystem_vendor_id/subsystem_id are only for header type 0 */ 1153 assert(!pc->subsystem_vendor_id); 1154 assert(!pc->subsystem_id); 1155 } 1156 pci_init_cmask(pci_dev); 1157 pci_init_wmask(pci_dev); 1158 pci_init_w1cmask(pci_dev); 1159 if (pc->is_bridge) { 1160 pci_init_mask_bridge(pci_dev); 1161 } 1162 pci_init_multifunction(bus, pci_dev, &local_err); 1163 if (local_err) { 1164 error_propagate(errp, local_err); 1165 do_pci_unregister_device(pci_dev); 1166 return NULL; 1167 } 1168 1169 if (!config_read) 1170 config_read = pci_default_read_config; 1171 if (!config_write) 1172 config_write = pci_default_write_config; 1173 pci_dev->config_read = config_read; 1174 pci_dev->config_write = config_write; 1175 bus->devices[devfn] = pci_dev; 1176 pci_dev->version_id = 2; /* Current pci device vmstate version */ 1177 return pci_dev; 1178 } 1179 1180 static void pci_unregister_io_regions(PCIDevice *pci_dev) 1181 { 1182 PCIIORegion *r; 1183 int i; 1184 1185 for(i = 0; i < PCI_NUM_REGIONS; i++) { 1186 r = &pci_dev->io_regions[i]; 1187 if (!r->size || r->addr == PCI_BAR_UNMAPPED) 1188 continue; 1189 memory_region_del_subregion(r->address_space, r->memory); 1190 } 1191 1192 pci_unregister_vga(pci_dev); 1193 } 1194 1195 static void pci_qdev_unrealize(DeviceState *dev) 1196 { 1197 PCIDevice *pci_dev = PCI_DEVICE(dev); 1198 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 1199 1200 pci_unregister_io_regions(pci_dev); 1201 pci_del_option_rom(pci_dev); 1202 1203 if (pc->exit) { 1204 pc->exit(pci_dev); 1205 } 1206 1207 pci_device_deassert_intx(pci_dev); 1208 do_pci_unregister_device(pci_dev); 1209 } 1210 1211 void pci_register_bar(PCIDevice *pci_dev, int region_num, 1212 uint8_t type, MemoryRegion *memory) 1213 { 1214 PCIIORegion *r; 1215 uint32_t addr; /* offset in pci config space */ 1216 uint64_t wmask; 1217 pcibus_t size = memory_region_size(memory); 1218 uint8_t hdr_type; 1219 1220 assert(!pci_is_vf(pci_dev)); /* VFs must use pcie_sriov_vf_register_bar */ 1221 assert(region_num >= 0); 1222 assert(region_num < PCI_NUM_REGIONS); 1223 assert(is_power_of_2(size)); 1224 1225 /* A PCI bridge device (with Type 1 header) may only have at most 2 BARs */ 1226 hdr_type = 1227 pci_dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 1228 assert(hdr_type != PCI_HEADER_TYPE_BRIDGE || region_num < 2); 1229 1230 r = &pci_dev->io_regions[region_num]; 1231 r->addr = PCI_BAR_UNMAPPED; 1232 r->size = size; 1233 r->type = type; 1234 r->memory = memory; 1235 r->address_space = type & PCI_BASE_ADDRESS_SPACE_IO 1236 ? pci_get_bus(pci_dev)->address_space_io 1237 : pci_get_bus(pci_dev)->address_space_mem; 1238 1239 wmask = ~(size - 1); 1240 if (region_num == PCI_ROM_SLOT) { 1241 /* ROM enable bit is writable */ 1242 wmask |= PCI_ROM_ADDRESS_ENABLE; 1243 } 1244 1245 addr = pci_bar(pci_dev, region_num); 1246 pci_set_long(pci_dev->config + addr, type); 1247 1248 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) && 1249 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 1250 pci_set_quad(pci_dev->wmask + addr, wmask); 1251 pci_set_quad(pci_dev->cmask + addr, ~0ULL); 1252 } else { 1253 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff); 1254 pci_set_long(pci_dev->cmask + addr, 0xffffffff); 1255 } 1256 } 1257 1258 static void pci_update_vga(PCIDevice *pci_dev) 1259 { 1260 uint16_t cmd; 1261 1262 if (!pci_dev->has_vga) { 1263 return; 1264 } 1265 1266 cmd = pci_get_word(pci_dev->config + PCI_COMMAND); 1267 1268 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_MEM], 1269 cmd & PCI_COMMAND_MEMORY); 1270 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO], 1271 cmd & PCI_COMMAND_IO); 1272 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI], 1273 cmd & PCI_COMMAND_IO); 1274 } 1275 1276 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, 1277 MemoryRegion *io_lo, MemoryRegion *io_hi) 1278 { 1279 PCIBus *bus = pci_get_bus(pci_dev); 1280 1281 assert(!pci_dev->has_vga); 1282 1283 assert(memory_region_size(mem) == QEMU_PCI_VGA_MEM_SIZE); 1284 pci_dev->vga_regions[QEMU_PCI_VGA_MEM] = mem; 1285 memory_region_add_subregion_overlap(bus->address_space_mem, 1286 QEMU_PCI_VGA_MEM_BASE, mem, 1); 1287 1288 assert(memory_region_size(io_lo) == QEMU_PCI_VGA_IO_LO_SIZE); 1289 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO] = io_lo; 1290 memory_region_add_subregion_overlap(bus->address_space_io, 1291 QEMU_PCI_VGA_IO_LO_BASE, io_lo, 1); 1292 1293 assert(memory_region_size(io_hi) == QEMU_PCI_VGA_IO_HI_SIZE); 1294 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI] = io_hi; 1295 memory_region_add_subregion_overlap(bus->address_space_io, 1296 QEMU_PCI_VGA_IO_HI_BASE, io_hi, 1); 1297 pci_dev->has_vga = true; 1298 1299 pci_update_vga(pci_dev); 1300 } 1301 1302 void pci_unregister_vga(PCIDevice *pci_dev) 1303 { 1304 PCIBus *bus = pci_get_bus(pci_dev); 1305 1306 if (!pci_dev->has_vga) { 1307 return; 1308 } 1309 1310 memory_region_del_subregion(bus->address_space_mem, 1311 pci_dev->vga_regions[QEMU_PCI_VGA_MEM]); 1312 memory_region_del_subregion(bus->address_space_io, 1313 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO]); 1314 memory_region_del_subregion(bus->address_space_io, 1315 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI]); 1316 pci_dev->has_vga = false; 1317 } 1318 1319 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num) 1320 { 1321 return pci_dev->io_regions[region_num].addr; 1322 } 1323 1324 static pcibus_t pci_config_get_bar_addr(PCIDevice *d, int reg, 1325 uint8_t type, pcibus_t size) 1326 { 1327 pcibus_t new_addr; 1328 if (!pci_is_vf(d)) { 1329 int bar = pci_bar(d, reg); 1330 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 1331 new_addr = pci_get_quad(d->config + bar); 1332 } else { 1333 new_addr = pci_get_long(d->config + bar); 1334 } 1335 } else { 1336 PCIDevice *pf = d->exp.sriov_vf.pf; 1337 uint16_t sriov_cap = pf->exp.sriov_cap; 1338 int bar = sriov_cap + PCI_SRIOV_BAR + reg * 4; 1339 uint16_t vf_offset = 1340 pci_get_word(pf->config + sriov_cap + PCI_SRIOV_VF_OFFSET); 1341 uint16_t vf_stride = 1342 pci_get_word(pf->config + sriov_cap + PCI_SRIOV_VF_STRIDE); 1343 uint32_t vf_num = (d->devfn - (pf->devfn + vf_offset)) / vf_stride; 1344 1345 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 1346 new_addr = pci_get_quad(pf->config + bar); 1347 } else { 1348 new_addr = pci_get_long(pf->config + bar); 1349 } 1350 new_addr += vf_num * size; 1351 } 1352 /* The ROM slot has a specific enable bit, keep it intact */ 1353 if (reg != PCI_ROM_SLOT) { 1354 new_addr &= ~(size - 1); 1355 } 1356 return new_addr; 1357 } 1358 1359 pcibus_t pci_bar_address(PCIDevice *d, 1360 int reg, uint8_t type, pcibus_t size) 1361 { 1362 pcibus_t new_addr, last_addr; 1363 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND); 1364 Object *machine = qdev_get_machine(); 1365 ObjectClass *oc = object_get_class(machine); 1366 MachineClass *mc = MACHINE_CLASS(oc); 1367 bool allow_0_address = mc->pci_allow_0_address; 1368 1369 if (type & PCI_BASE_ADDRESS_SPACE_IO) { 1370 if (!(cmd & PCI_COMMAND_IO)) { 1371 return PCI_BAR_UNMAPPED; 1372 } 1373 new_addr = pci_config_get_bar_addr(d, reg, type, size); 1374 last_addr = new_addr + size - 1; 1375 /* Check if 32 bit BAR wraps around explicitly. 1376 * TODO: make priorities correct and remove this work around. 1377 */ 1378 if (last_addr <= new_addr || last_addr >= UINT32_MAX || 1379 (!allow_0_address && new_addr == 0)) { 1380 return PCI_BAR_UNMAPPED; 1381 } 1382 return new_addr; 1383 } 1384 1385 if (!(cmd & PCI_COMMAND_MEMORY)) { 1386 return PCI_BAR_UNMAPPED; 1387 } 1388 new_addr = pci_config_get_bar_addr(d, reg, type, size); 1389 /* the ROM slot has a specific enable bit */ 1390 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) { 1391 return PCI_BAR_UNMAPPED; 1392 } 1393 new_addr &= ~(size - 1); 1394 last_addr = new_addr + size - 1; 1395 /* NOTE: we do not support wrapping */ 1396 /* XXX: as we cannot support really dynamic 1397 mappings, we handle specific values as invalid 1398 mappings. */ 1399 if (last_addr <= new_addr || last_addr == PCI_BAR_UNMAPPED || 1400 (!allow_0_address && new_addr == 0)) { 1401 return PCI_BAR_UNMAPPED; 1402 } 1403 1404 /* Now pcibus_t is 64bit. 1405 * Check if 32 bit BAR wraps around explicitly. 1406 * Without this, PC ide doesn't work well. 1407 * TODO: remove this work around. 1408 */ 1409 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) { 1410 return PCI_BAR_UNMAPPED; 1411 } 1412 1413 /* 1414 * OS is allowed to set BAR beyond its addressable 1415 * bits. For example, 32 bit OS can set 64bit bar 1416 * to >4G. Check it. TODO: we might need to support 1417 * it in the future for e.g. PAE. 1418 */ 1419 if (last_addr >= HWADDR_MAX) { 1420 return PCI_BAR_UNMAPPED; 1421 } 1422 1423 return new_addr; 1424 } 1425 1426 static void pci_update_mappings(PCIDevice *d) 1427 { 1428 PCIIORegion *r; 1429 int i; 1430 pcibus_t new_addr; 1431 1432 for(i = 0; i < PCI_NUM_REGIONS; i++) { 1433 r = &d->io_regions[i]; 1434 1435 /* this region isn't registered */ 1436 if (!r->size) 1437 continue; 1438 1439 new_addr = pci_bar_address(d, i, r->type, r->size); 1440 if (!d->has_power) { 1441 new_addr = PCI_BAR_UNMAPPED; 1442 } 1443 1444 /* This bar isn't changed */ 1445 if (new_addr == r->addr) 1446 continue; 1447 1448 /* now do the real mapping */ 1449 if (r->addr != PCI_BAR_UNMAPPED) { 1450 trace_pci_update_mappings_del(d->name, pci_dev_bus_num(d), 1451 PCI_SLOT(d->devfn), 1452 PCI_FUNC(d->devfn), 1453 i, r->addr, r->size); 1454 memory_region_del_subregion(r->address_space, r->memory); 1455 } 1456 r->addr = new_addr; 1457 if (r->addr != PCI_BAR_UNMAPPED) { 1458 trace_pci_update_mappings_add(d->name, pci_dev_bus_num(d), 1459 PCI_SLOT(d->devfn), 1460 PCI_FUNC(d->devfn), 1461 i, r->addr, r->size); 1462 memory_region_add_subregion_overlap(r->address_space, 1463 r->addr, r->memory, 1); 1464 } 1465 } 1466 1467 pci_update_vga(d); 1468 } 1469 1470 static inline int pci_irq_disabled(PCIDevice *d) 1471 { 1472 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE; 1473 } 1474 1475 /* Called after interrupt disabled field update in config space, 1476 * assert/deassert interrupts if necessary. 1477 * Gets original interrupt disable bit value (before update). */ 1478 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled) 1479 { 1480 int i, disabled = pci_irq_disabled(d); 1481 if (disabled == was_irq_disabled) 1482 return; 1483 for (i = 0; i < PCI_NUM_PINS; ++i) { 1484 int state = pci_irq_state(d, i); 1485 pci_change_irq_level(d, i, disabled ? -state : state); 1486 } 1487 } 1488 1489 uint32_t pci_default_read_config(PCIDevice *d, 1490 uint32_t address, int len) 1491 { 1492 uint32_t val = 0; 1493 1494 assert(address + len <= pci_config_size(d)); 1495 1496 if (pci_is_express_downstream_port(d) && 1497 ranges_overlap(address, len, d->exp.exp_cap + PCI_EXP_LNKSTA, 2)) { 1498 pcie_sync_bridge_lnk(d); 1499 } 1500 memcpy(&val, d->config + address, len); 1501 return le32_to_cpu(val); 1502 } 1503 1504 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val_in, int l) 1505 { 1506 int i, was_irq_disabled = pci_irq_disabled(d); 1507 uint32_t val = val_in; 1508 1509 assert(addr + l <= pci_config_size(d)); 1510 1511 for (i = 0; i < l; val >>= 8, ++i) { 1512 uint8_t wmask = d->wmask[addr + i]; 1513 uint8_t w1cmask = d->w1cmask[addr + i]; 1514 assert(!(wmask & w1cmask)); 1515 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask); 1516 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */ 1517 } 1518 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) || 1519 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) || 1520 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) || 1521 range_covers_byte(addr, l, PCI_COMMAND)) 1522 pci_update_mappings(d); 1523 1524 if (range_covers_byte(addr, l, PCI_COMMAND)) { 1525 pci_update_irq_disabled(d, was_irq_disabled); 1526 memory_region_set_enabled(&d->bus_master_enable_region, 1527 (pci_get_word(d->config + PCI_COMMAND) 1528 & PCI_COMMAND_MASTER) && d->has_power); 1529 } 1530 1531 msi_write_config(d, addr, val_in, l); 1532 msix_write_config(d, addr, val_in, l); 1533 pcie_sriov_config_write(d, addr, val_in, l); 1534 } 1535 1536 /***********************************************************/ 1537 /* generic PCI irq support */ 1538 1539 /* 0 <= irq_num <= 3. level must be 0 or 1 */ 1540 static void pci_irq_handler(void *opaque, int irq_num, int level) 1541 { 1542 PCIDevice *pci_dev = opaque; 1543 int change; 1544 1545 assert(0 <= irq_num && irq_num < PCI_NUM_PINS); 1546 assert(level == 0 || level == 1); 1547 change = level - pci_irq_state(pci_dev, irq_num); 1548 if (!change) 1549 return; 1550 1551 pci_set_irq_state(pci_dev, irq_num, level); 1552 pci_update_irq_status(pci_dev); 1553 if (pci_irq_disabled(pci_dev)) 1554 return; 1555 pci_change_irq_level(pci_dev, irq_num, change); 1556 } 1557 1558 qemu_irq pci_allocate_irq(PCIDevice *pci_dev) 1559 { 1560 int intx = pci_intx(pci_dev); 1561 assert(0 <= intx && intx < PCI_NUM_PINS); 1562 1563 return qemu_allocate_irq(pci_irq_handler, pci_dev, intx); 1564 } 1565 1566 void pci_set_irq(PCIDevice *pci_dev, int level) 1567 { 1568 int intx = pci_intx(pci_dev); 1569 pci_irq_handler(pci_dev, intx, level); 1570 } 1571 1572 /* Special hooks used by device assignment */ 1573 void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq) 1574 { 1575 assert(pci_bus_is_root(bus)); 1576 bus->route_intx_to_irq = route_intx_to_irq; 1577 } 1578 1579 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin) 1580 { 1581 PCIBus *bus; 1582 1583 do { 1584 bus = pci_get_bus(dev); 1585 pin = bus->map_irq(dev, pin); 1586 dev = bus->parent_dev; 1587 } while (dev); 1588 1589 if (!bus->route_intx_to_irq) { 1590 error_report("PCI: Bug - unimplemented PCI INTx routing (%s)", 1591 object_get_typename(OBJECT(bus->qbus.parent))); 1592 return (PCIINTxRoute) { PCI_INTX_DISABLED, -1 }; 1593 } 1594 1595 return bus->route_intx_to_irq(bus->irq_opaque, pin); 1596 } 1597 1598 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new) 1599 { 1600 return old->mode != new->mode || old->irq != new->irq; 1601 } 1602 1603 void pci_bus_fire_intx_routing_notifier(PCIBus *bus) 1604 { 1605 PCIDevice *dev; 1606 PCIBus *sec; 1607 int i; 1608 1609 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 1610 dev = bus->devices[i]; 1611 if (dev && dev->intx_routing_notifier) { 1612 dev->intx_routing_notifier(dev); 1613 } 1614 } 1615 1616 QLIST_FOREACH(sec, &bus->child, sibling) { 1617 pci_bus_fire_intx_routing_notifier(sec); 1618 } 1619 } 1620 1621 void pci_device_set_intx_routing_notifier(PCIDevice *dev, 1622 PCIINTxRoutingNotifier notifier) 1623 { 1624 dev->intx_routing_notifier = notifier; 1625 } 1626 1627 /* 1628 * PCI-to-PCI bridge specification 1629 * 9.1: Interrupt routing. Table 9-1 1630 * 1631 * the PCI Express Base Specification, Revision 2.1 1632 * 2.2.8.1: INTx interrutp signaling - Rules 1633 * the Implementation Note 1634 * Table 2-20 1635 */ 1636 /* 1637 * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD 1638 * 0-origin unlike PCI interrupt pin register. 1639 */ 1640 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin) 1641 { 1642 return pci_swizzle(PCI_SLOT(pci_dev->devfn), pin); 1643 } 1644 1645 /***********************************************************/ 1646 /* monitor info on PCI */ 1647 1648 typedef struct { 1649 uint16_t class; 1650 const char *desc; 1651 const char *fw_name; 1652 uint16_t fw_ign_bits; 1653 } pci_class_desc; 1654 1655 static const pci_class_desc pci_class_descriptions[] = 1656 { 1657 { 0x0001, "VGA controller", "display"}, 1658 { 0x0100, "SCSI controller", "scsi"}, 1659 { 0x0101, "IDE controller", "ide"}, 1660 { 0x0102, "Floppy controller", "fdc"}, 1661 { 0x0103, "IPI controller", "ipi"}, 1662 { 0x0104, "RAID controller", "raid"}, 1663 { 0x0106, "SATA controller"}, 1664 { 0x0107, "SAS controller"}, 1665 { 0x0180, "Storage controller"}, 1666 { 0x0200, "Ethernet controller", "ethernet"}, 1667 { 0x0201, "Token Ring controller", "token-ring"}, 1668 { 0x0202, "FDDI controller", "fddi"}, 1669 { 0x0203, "ATM controller", "atm"}, 1670 { 0x0280, "Network controller"}, 1671 { 0x0300, "VGA controller", "display", 0x00ff}, 1672 { 0x0301, "XGA controller"}, 1673 { 0x0302, "3D controller"}, 1674 { 0x0380, "Display controller"}, 1675 { 0x0400, "Video controller", "video"}, 1676 { 0x0401, "Audio controller", "sound"}, 1677 { 0x0402, "Phone"}, 1678 { 0x0403, "Audio controller", "sound"}, 1679 { 0x0480, "Multimedia controller"}, 1680 { 0x0500, "RAM controller", "memory"}, 1681 { 0x0501, "Flash controller", "flash"}, 1682 { 0x0580, "Memory controller"}, 1683 { 0x0600, "Host bridge", "host"}, 1684 { 0x0601, "ISA bridge", "isa"}, 1685 { 0x0602, "EISA bridge", "eisa"}, 1686 { 0x0603, "MC bridge", "mca"}, 1687 { 0x0604, "PCI bridge", "pci-bridge"}, 1688 { 0x0605, "PCMCIA bridge", "pcmcia"}, 1689 { 0x0606, "NUBUS bridge", "nubus"}, 1690 { 0x0607, "CARDBUS bridge", "cardbus"}, 1691 { 0x0608, "RACEWAY bridge"}, 1692 { 0x0680, "Bridge"}, 1693 { 0x0700, "Serial port", "serial"}, 1694 { 0x0701, "Parallel port", "parallel"}, 1695 { 0x0800, "Interrupt controller", "interrupt-controller"}, 1696 { 0x0801, "DMA controller", "dma-controller"}, 1697 { 0x0802, "Timer", "timer"}, 1698 { 0x0803, "RTC", "rtc"}, 1699 { 0x0900, "Keyboard", "keyboard"}, 1700 { 0x0901, "Pen", "pen"}, 1701 { 0x0902, "Mouse", "mouse"}, 1702 { 0x0A00, "Dock station", "dock", 0x00ff}, 1703 { 0x0B00, "i386 cpu", "cpu", 0x00ff}, 1704 { 0x0c00, "Firewire controller", "firewire"}, 1705 { 0x0c01, "Access bus controller", "access-bus"}, 1706 { 0x0c02, "SSA controller", "ssa"}, 1707 { 0x0c03, "USB controller", "usb"}, 1708 { 0x0c04, "Fibre channel controller", "fibre-channel"}, 1709 { 0x0c05, "SMBus"}, 1710 { 0, NULL} 1711 }; 1712 1713 void pci_for_each_device_under_bus_reverse(PCIBus *bus, 1714 pci_bus_dev_fn fn, 1715 void *opaque) 1716 { 1717 PCIDevice *d; 1718 int devfn; 1719 1720 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1721 d = bus->devices[ARRAY_SIZE(bus->devices) - 1 - devfn]; 1722 if (d) { 1723 fn(bus, d, opaque); 1724 } 1725 } 1726 } 1727 1728 void pci_for_each_device_reverse(PCIBus *bus, int bus_num, 1729 pci_bus_dev_fn fn, void *opaque) 1730 { 1731 bus = pci_find_bus_nr(bus, bus_num); 1732 1733 if (bus) { 1734 pci_for_each_device_under_bus_reverse(bus, fn, opaque); 1735 } 1736 } 1737 1738 void pci_for_each_device_under_bus(PCIBus *bus, 1739 pci_bus_dev_fn fn, void *opaque) 1740 { 1741 PCIDevice *d; 1742 int devfn; 1743 1744 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1745 d = bus->devices[devfn]; 1746 if (d) { 1747 fn(bus, d, opaque); 1748 } 1749 } 1750 } 1751 1752 void pci_for_each_device(PCIBus *bus, int bus_num, 1753 pci_bus_dev_fn fn, void *opaque) 1754 { 1755 bus = pci_find_bus_nr(bus, bus_num); 1756 1757 if (bus) { 1758 pci_for_each_device_under_bus(bus, fn, opaque); 1759 } 1760 } 1761 1762 static const pci_class_desc *get_class_desc(int class) 1763 { 1764 const pci_class_desc *desc; 1765 1766 desc = pci_class_descriptions; 1767 while (desc->desc && class != desc->class) { 1768 desc++; 1769 } 1770 1771 return desc; 1772 } 1773 1774 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num); 1775 1776 static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev) 1777 { 1778 PciMemoryRegionList *head = NULL, **tail = &head; 1779 int i; 1780 1781 for (i = 0; i < PCI_NUM_REGIONS; i++) { 1782 const PCIIORegion *r = &dev->io_regions[i]; 1783 PciMemoryRegion *region; 1784 1785 if (!r->size) { 1786 continue; 1787 } 1788 1789 region = g_malloc0(sizeof(*region)); 1790 1791 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { 1792 region->type = g_strdup("io"); 1793 } else { 1794 region->type = g_strdup("memory"); 1795 region->has_prefetch = true; 1796 region->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH); 1797 region->has_mem_type_64 = true; 1798 region->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64); 1799 } 1800 1801 region->bar = i; 1802 region->address = r->addr; 1803 region->size = r->size; 1804 1805 QAPI_LIST_APPEND(tail, region); 1806 } 1807 1808 return head; 1809 } 1810 1811 static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus, 1812 int bus_num) 1813 { 1814 PciBridgeInfo *info; 1815 PciMemoryRange *range; 1816 1817 info = g_new0(PciBridgeInfo, 1); 1818 1819 info->bus = g_new0(PciBusInfo, 1); 1820 info->bus->number = dev->config[PCI_PRIMARY_BUS]; 1821 info->bus->secondary = dev->config[PCI_SECONDARY_BUS]; 1822 info->bus->subordinate = dev->config[PCI_SUBORDINATE_BUS]; 1823 1824 range = info->bus->io_range = g_new0(PciMemoryRange, 1); 1825 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO); 1826 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO); 1827 1828 range = info->bus->memory_range = g_new0(PciMemoryRange, 1); 1829 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 1830 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 1831 1832 range = info->bus->prefetchable_range = g_new0(PciMemoryRange, 1); 1833 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 1834 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 1835 1836 if (dev->config[PCI_SECONDARY_BUS] != 0) { 1837 PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]); 1838 if (child_bus) { 1839 info->has_devices = true; 1840 info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]); 1841 } 1842 } 1843 1844 return info; 1845 } 1846 1847 static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus, 1848 int bus_num) 1849 { 1850 const pci_class_desc *desc; 1851 PciDeviceInfo *info; 1852 uint8_t type; 1853 int class; 1854 1855 info = g_new0(PciDeviceInfo, 1); 1856 info->bus = bus_num; 1857 info->slot = PCI_SLOT(dev->devfn); 1858 info->function = PCI_FUNC(dev->devfn); 1859 1860 info->class_info = g_new0(PciDeviceClass, 1); 1861 class = pci_get_word(dev->config + PCI_CLASS_DEVICE); 1862 info->class_info->q_class = class; 1863 desc = get_class_desc(class); 1864 if (desc->desc) { 1865 info->class_info->has_desc = true; 1866 info->class_info->desc = g_strdup(desc->desc); 1867 } 1868 1869 info->id = g_new0(PciDeviceId, 1); 1870 info->id->vendor = pci_get_word(dev->config + PCI_VENDOR_ID); 1871 info->id->device = pci_get_word(dev->config + PCI_DEVICE_ID); 1872 info->regions = qmp_query_pci_regions(dev); 1873 info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : ""); 1874 1875 info->irq_pin = dev->config[PCI_INTERRUPT_PIN]; 1876 if (dev->config[PCI_INTERRUPT_PIN] != 0) { 1877 info->has_irq = true; 1878 info->irq = dev->config[PCI_INTERRUPT_LINE]; 1879 } 1880 1881 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 1882 if (type == PCI_HEADER_TYPE_BRIDGE) { 1883 info->has_pci_bridge = true; 1884 info->pci_bridge = qmp_query_pci_bridge(dev, bus, bus_num); 1885 } else if (type == PCI_HEADER_TYPE_NORMAL) { 1886 info->id->has_subsystem = info->id->has_subsystem_vendor = true; 1887 info->id->subsystem = pci_get_word(dev->config + PCI_SUBSYSTEM_ID); 1888 info->id->subsystem_vendor = 1889 pci_get_word(dev->config + PCI_SUBSYSTEM_VENDOR_ID); 1890 } else if (type == PCI_HEADER_TYPE_CARDBUS) { 1891 info->id->has_subsystem = info->id->has_subsystem_vendor = true; 1892 info->id->subsystem = pci_get_word(dev->config + PCI_CB_SUBSYSTEM_ID); 1893 info->id->subsystem_vendor = 1894 pci_get_word(dev->config + PCI_CB_SUBSYSTEM_VENDOR_ID); 1895 } 1896 1897 return info; 1898 } 1899 1900 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num) 1901 { 1902 PciDeviceInfoList *head = NULL, **tail = &head; 1903 PCIDevice *dev; 1904 int devfn; 1905 1906 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1907 dev = bus->devices[devfn]; 1908 if (dev) { 1909 QAPI_LIST_APPEND(tail, qmp_query_pci_device(dev, bus, bus_num)); 1910 } 1911 } 1912 1913 return head; 1914 } 1915 1916 static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num) 1917 { 1918 PciInfo *info = NULL; 1919 1920 bus = pci_find_bus_nr(bus, bus_num); 1921 if (bus) { 1922 info = g_malloc0(sizeof(*info)); 1923 info->bus = bus_num; 1924 info->devices = qmp_query_pci_devices(bus, bus_num); 1925 } 1926 1927 return info; 1928 } 1929 1930 PciInfoList *qmp_query_pci(Error **errp) 1931 { 1932 PciInfoList *head = NULL, **tail = &head; 1933 PCIHostState *host_bridge; 1934 1935 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { 1936 QAPI_LIST_APPEND(tail, 1937 qmp_query_pci_bus(host_bridge->bus, 1938 pci_bus_num(host_bridge->bus))); 1939 } 1940 1941 return head; 1942 } 1943 1944 /* Initialize a PCI NIC. */ 1945 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus, 1946 const char *default_model, 1947 const char *default_devaddr) 1948 { 1949 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr; 1950 GSList *list; 1951 GPtrArray *pci_nic_models; 1952 PCIBus *bus; 1953 PCIDevice *pci_dev; 1954 DeviceState *dev; 1955 int devfn; 1956 int i; 1957 int dom, busnr; 1958 unsigned slot; 1959 1960 if (nd->model && !strcmp(nd->model, "virtio")) { 1961 g_free(nd->model); 1962 nd->model = g_strdup("virtio-net-pci"); 1963 } 1964 1965 list = object_class_get_list_sorted(TYPE_PCI_DEVICE, false); 1966 pci_nic_models = g_ptr_array_new(); 1967 while (list) { 1968 DeviceClass *dc = OBJECT_CLASS_CHECK(DeviceClass, list->data, 1969 TYPE_DEVICE); 1970 GSList *next; 1971 if (test_bit(DEVICE_CATEGORY_NETWORK, dc->categories) && 1972 dc->user_creatable) { 1973 const char *name = object_class_get_name(list->data); 1974 /* 1975 * A network device might also be something else than a NIC, see 1976 * e.g. the "rocker" device. Thus we have to look for the "netdev" 1977 * property, too. Unfortunately, some devices like virtio-net only 1978 * create this property during instance_init, so we have to create 1979 * a temporary instance here to be able to check it. 1980 */ 1981 Object *obj = object_new_with_class(OBJECT_CLASS(dc)); 1982 if (object_property_find(obj, "netdev")) { 1983 g_ptr_array_add(pci_nic_models, (gpointer)name); 1984 } 1985 object_unref(obj); 1986 } 1987 next = list->next; 1988 g_slist_free_1(list); 1989 list = next; 1990 } 1991 g_ptr_array_add(pci_nic_models, NULL); 1992 1993 if (qemu_show_nic_models(nd->model, (const char **)pci_nic_models->pdata)) { 1994 exit(0); 1995 } 1996 1997 i = qemu_find_nic_model(nd, (const char **)pci_nic_models->pdata, 1998 default_model); 1999 if (i < 0) { 2000 exit(1); 2001 } 2002 2003 if (!rootbus) { 2004 error_report("No primary PCI bus"); 2005 exit(1); 2006 } 2007 2008 assert(!rootbus->parent_dev); 2009 2010 if (!devaddr) { 2011 devfn = -1; 2012 busnr = 0; 2013 } else { 2014 if (pci_parse_devaddr(devaddr, &dom, &busnr, &slot, NULL) < 0) { 2015 error_report("Invalid PCI device address %s for device %s", 2016 devaddr, nd->model); 2017 exit(1); 2018 } 2019 2020 if (dom != 0) { 2021 error_report("No support for non-zero PCI domains"); 2022 exit(1); 2023 } 2024 2025 devfn = PCI_DEVFN(slot, 0); 2026 } 2027 2028 bus = pci_find_bus_nr(rootbus, busnr); 2029 if (!bus) { 2030 error_report("Invalid PCI device address %s for device %s", 2031 devaddr, nd->model); 2032 exit(1); 2033 } 2034 2035 pci_dev = pci_new(devfn, nd->model); 2036 dev = &pci_dev->qdev; 2037 qdev_set_nic_properties(dev, nd); 2038 pci_realize_and_unref(pci_dev, bus, &error_fatal); 2039 g_ptr_array_free(pci_nic_models, true); 2040 return pci_dev; 2041 } 2042 2043 PCIDevice *pci_vga_init(PCIBus *bus) 2044 { 2045 vga_interface_created = true; 2046 switch (vga_interface_type) { 2047 case VGA_CIRRUS: 2048 return pci_create_simple(bus, -1, "cirrus-vga"); 2049 case VGA_QXL: 2050 return pci_create_simple(bus, -1, "qxl-vga"); 2051 case VGA_STD: 2052 return pci_create_simple(bus, -1, "VGA"); 2053 case VGA_VMWARE: 2054 return pci_create_simple(bus, -1, "vmware-svga"); 2055 case VGA_VIRTIO: 2056 return pci_create_simple(bus, -1, "virtio-vga"); 2057 case VGA_NONE: 2058 default: /* Other non-PCI types. Checking for unsupported types is already 2059 done in vl.c. */ 2060 return NULL; 2061 } 2062 } 2063 2064 /* Whether a given bus number is in range of the secondary 2065 * bus of the given bridge device. */ 2066 static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num) 2067 { 2068 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) & 2069 PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ && 2070 dev->config[PCI_SECONDARY_BUS] <= bus_num && 2071 bus_num <= dev->config[PCI_SUBORDINATE_BUS]; 2072 } 2073 2074 /* Whether a given bus number is in a range of a root bus */ 2075 static bool pci_root_bus_in_range(PCIBus *bus, int bus_num) 2076 { 2077 int i; 2078 2079 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 2080 PCIDevice *dev = bus->devices[i]; 2081 2082 if (dev && PCI_DEVICE_GET_CLASS(dev)->is_bridge) { 2083 if (pci_secondary_bus_in_range(dev, bus_num)) { 2084 return true; 2085 } 2086 } 2087 } 2088 2089 return false; 2090 } 2091 2092 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num) 2093 { 2094 PCIBus *sec; 2095 2096 if (!bus) { 2097 return NULL; 2098 } 2099 2100 if (pci_bus_num(bus) == bus_num) { 2101 return bus; 2102 } 2103 2104 /* Consider all bus numbers in range for the host pci bridge. */ 2105 if (!pci_bus_is_root(bus) && 2106 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) { 2107 return NULL; 2108 } 2109 2110 /* try child bus */ 2111 for (; bus; bus = sec) { 2112 QLIST_FOREACH(sec, &bus->child, sibling) { 2113 if (pci_bus_num(sec) == bus_num) { 2114 return sec; 2115 } 2116 /* PXB buses assumed to be children of bus 0 */ 2117 if (pci_bus_is_root(sec)) { 2118 if (pci_root_bus_in_range(sec, bus_num)) { 2119 break; 2120 } 2121 } else { 2122 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) { 2123 break; 2124 } 2125 } 2126 } 2127 } 2128 2129 return NULL; 2130 } 2131 2132 void pci_for_each_bus_depth_first(PCIBus *bus, pci_bus_ret_fn begin, 2133 pci_bus_fn end, void *parent_state) 2134 { 2135 PCIBus *sec; 2136 void *state; 2137 2138 if (!bus) { 2139 return; 2140 } 2141 2142 if (begin) { 2143 state = begin(bus, parent_state); 2144 } else { 2145 state = parent_state; 2146 } 2147 2148 QLIST_FOREACH(sec, &bus->child, sibling) { 2149 pci_for_each_bus_depth_first(sec, begin, end, state); 2150 } 2151 2152 if (end) { 2153 end(bus, state); 2154 } 2155 } 2156 2157 2158 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn) 2159 { 2160 bus = pci_find_bus_nr(bus, bus_num); 2161 2162 if (!bus) 2163 return NULL; 2164 2165 return bus->devices[devfn]; 2166 } 2167 2168 static void pci_qdev_realize(DeviceState *qdev, Error **errp) 2169 { 2170 PCIDevice *pci_dev = (PCIDevice *)qdev; 2171 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 2172 ObjectClass *klass = OBJECT_CLASS(pc); 2173 Error *local_err = NULL; 2174 bool is_default_rom; 2175 uint16_t class_id; 2176 2177 if (pci_dev->romsize != -1 && !is_power_of_2(pci_dev->romsize)) { 2178 error_setg(errp, "ROM size %u is not a power of two", pci_dev->romsize); 2179 return; 2180 } 2181 2182 /* initialize cap_present for pci_is_express() and pci_config_size(), 2183 * Note that hybrid PCIs are not set automatically and need to manage 2184 * QEMU_PCI_CAP_EXPRESS manually */ 2185 if (object_class_dynamic_cast(klass, INTERFACE_PCIE_DEVICE) && 2186 !object_class_dynamic_cast(klass, INTERFACE_CONVENTIONAL_PCI_DEVICE)) { 2187 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; 2188 } 2189 2190 if (object_class_dynamic_cast(klass, INTERFACE_CXL_DEVICE)) { 2191 pci_dev->cap_present |= QEMU_PCIE_CAP_CXL; 2192 } 2193 2194 pci_dev = do_pci_register_device(pci_dev, 2195 object_get_typename(OBJECT(qdev)), 2196 pci_dev->devfn, errp); 2197 if (pci_dev == NULL) 2198 return; 2199 2200 if (pc->realize) { 2201 pc->realize(pci_dev, &local_err); 2202 if (local_err) { 2203 error_propagate(errp, local_err); 2204 do_pci_unregister_device(pci_dev); 2205 return; 2206 } 2207 } 2208 2209 if (pci_dev->failover_pair_id) { 2210 if (!pci_bus_is_express(pci_get_bus(pci_dev))) { 2211 error_setg(errp, "failover primary device must be on " 2212 "PCIExpress bus"); 2213 pci_qdev_unrealize(DEVICE(pci_dev)); 2214 return; 2215 } 2216 class_id = pci_get_word(pci_dev->config + PCI_CLASS_DEVICE); 2217 if (class_id != PCI_CLASS_NETWORK_ETHERNET) { 2218 error_setg(errp, "failover primary device is not an " 2219 "Ethernet device"); 2220 pci_qdev_unrealize(DEVICE(pci_dev)); 2221 return; 2222 } 2223 if ((pci_dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) 2224 || (PCI_FUNC(pci_dev->devfn) != 0)) { 2225 error_setg(errp, "failover: primary device must be in its own " 2226 "PCI slot"); 2227 pci_qdev_unrealize(DEVICE(pci_dev)); 2228 return; 2229 } 2230 qdev->allow_unplug_during_migration = true; 2231 } 2232 2233 /* rom loading */ 2234 is_default_rom = false; 2235 if (pci_dev->romfile == NULL && pc->romfile != NULL) { 2236 pci_dev->romfile = g_strdup(pc->romfile); 2237 is_default_rom = true; 2238 } 2239 2240 pci_add_option_rom(pci_dev, is_default_rom, &local_err); 2241 if (local_err) { 2242 error_propagate(errp, local_err); 2243 pci_qdev_unrealize(DEVICE(pci_dev)); 2244 return; 2245 } 2246 2247 pci_set_power(pci_dev, true); 2248 } 2249 2250 PCIDevice *pci_new_multifunction(int devfn, bool multifunction, 2251 const char *name) 2252 { 2253 DeviceState *dev; 2254 2255 dev = qdev_new(name); 2256 qdev_prop_set_int32(dev, "addr", devfn); 2257 qdev_prop_set_bit(dev, "multifunction", multifunction); 2258 return PCI_DEVICE(dev); 2259 } 2260 2261 PCIDevice *pci_new(int devfn, const char *name) 2262 { 2263 return pci_new_multifunction(devfn, false, name); 2264 } 2265 2266 bool pci_realize_and_unref(PCIDevice *dev, PCIBus *bus, Error **errp) 2267 { 2268 return qdev_realize_and_unref(&dev->qdev, &bus->qbus, errp); 2269 } 2270 2271 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, 2272 bool multifunction, 2273 const char *name) 2274 { 2275 PCIDevice *dev = pci_new_multifunction(devfn, multifunction, name); 2276 pci_realize_and_unref(dev, bus, &error_fatal); 2277 return dev; 2278 } 2279 2280 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name) 2281 { 2282 return pci_create_simple_multifunction(bus, devfn, false, name); 2283 } 2284 2285 static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size) 2286 { 2287 int offset = PCI_CONFIG_HEADER_SIZE; 2288 int i; 2289 for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) { 2290 if (pdev->used[i]) 2291 offset = i + 1; 2292 else if (i - offset + 1 == size) 2293 return offset; 2294 } 2295 return 0; 2296 } 2297 2298 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id, 2299 uint8_t *prev_p) 2300 { 2301 uint8_t next, prev; 2302 2303 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST)) 2304 return 0; 2305 2306 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); 2307 prev = next + PCI_CAP_LIST_NEXT) 2308 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id) 2309 break; 2310 2311 if (prev_p) 2312 *prev_p = prev; 2313 return next; 2314 } 2315 2316 static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset) 2317 { 2318 uint8_t next, prev, found = 0; 2319 2320 if (!(pdev->used[offset])) { 2321 return 0; 2322 } 2323 2324 assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST); 2325 2326 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); 2327 prev = next + PCI_CAP_LIST_NEXT) { 2328 if (next <= offset && next > found) { 2329 found = next; 2330 } 2331 } 2332 return found; 2333 } 2334 2335 /* Patch the PCI vendor and device ids in a PCI rom image if necessary. 2336 This is needed for an option rom which is used for more than one device. */ 2337 static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, uint32_t size) 2338 { 2339 uint16_t vendor_id; 2340 uint16_t device_id; 2341 uint16_t rom_vendor_id; 2342 uint16_t rom_device_id; 2343 uint16_t rom_magic; 2344 uint16_t pcir_offset; 2345 uint8_t checksum; 2346 2347 /* Words in rom data are little endian (like in PCI configuration), 2348 so they can be read / written with pci_get_word / pci_set_word. */ 2349 2350 /* Only a valid rom will be patched. */ 2351 rom_magic = pci_get_word(ptr); 2352 if (rom_magic != 0xaa55) { 2353 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic); 2354 return; 2355 } 2356 pcir_offset = pci_get_word(ptr + 0x18); 2357 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) { 2358 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset); 2359 return; 2360 } 2361 2362 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID); 2363 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID); 2364 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4); 2365 rom_device_id = pci_get_word(ptr + pcir_offset + 6); 2366 2367 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile, 2368 vendor_id, device_id, rom_vendor_id, rom_device_id); 2369 2370 checksum = ptr[6]; 2371 2372 if (vendor_id != rom_vendor_id) { 2373 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */ 2374 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8); 2375 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8); 2376 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); 2377 ptr[6] = checksum; 2378 pci_set_word(ptr + pcir_offset + 4, vendor_id); 2379 } 2380 2381 if (device_id != rom_device_id) { 2382 /* Patch device id and checksum (at offset 6 for etherboot roms). */ 2383 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8); 2384 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8); 2385 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); 2386 ptr[6] = checksum; 2387 pci_set_word(ptr + pcir_offset + 6, device_id); 2388 } 2389 } 2390 2391 /* Add an option rom for the device */ 2392 static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, 2393 Error **errp) 2394 { 2395 int64_t size; 2396 char *path; 2397 void *ptr; 2398 char name[32]; 2399 const VMStateDescription *vmsd; 2400 2401 if (!pdev->romfile) 2402 return; 2403 if (strlen(pdev->romfile) == 0) 2404 return; 2405 2406 if (!pdev->rom_bar) { 2407 /* 2408 * Load rom via fw_cfg instead of creating a rom bar, 2409 * for 0.11 compatibility. 2410 */ 2411 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE); 2412 2413 /* 2414 * Hot-plugged devices can't use the option ROM 2415 * if the rom bar is disabled. 2416 */ 2417 if (DEVICE(pdev)->hotplugged) { 2418 error_setg(errp, "Hot-plugged device without ROM bar" 2419 " can't have an option ROM"); 2420 return; 2421 } 2422 2423 if (class == 0x0300) { 2424 rom_add_vga(pdev->romfile); 2425 } else { 2426 rom_add_option(pdev->romfile, -1); 2427 } 2428 return; 2429 } 2430 2431 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile); 2432 if (path == NULL) { 2433 path = g_strdup(pdev->romfile); 2434 } 2435 2436 size = get_image_size(path); 2437 if (size < 0) { 2438 error_setg(errp, "failed to find romfile \"%s\"", pdev->romfile); 2439 g_free(path); 2440 return; 2441 } else if (size == 0) { 2442 error_setg(errp, "romfile \"%s\" is empty", pdev->romfile); 2443 g_free(path); 2444 return; 2445 } else if (size > 2 * GiB) { 2446 error_setg(errp, "romfile \"%s\" too large (size cannot exceed 2 GiB)", 2447 pdev->romfile); 2448 g_free(path); 2449 return; 2450 } 2451 if (pdev->romsize != -1) { 2452 if (size > pdev->romsize) { 2453 error_setg(errp, "romfile \"%s\" (%u bytes) is too large for ROM size %u", 2454 pdev->romfile, (uint32_t)size, pdev->romsize); 2455 g_free(path); 2456 return; 2457 } 2458 } else { 2459 pdev->romsize = pow2ceil(size); 2460 } 2461 2462 vmsd = qdev_get_vmsd(DEVICE(pdev)); 2463 2464 if (vmsd) { 2465 snprintf(name, sizeof(name), "%s.rom", vmsd->name); 2466 } else { 2467 snprintf(name, sizeof(name), "%s.rom", object_get_typename(OBJECT(pdev))); 2468 } 2469 pdev->has_rom = true; 2470 memory_region_init_rom(&pdev->rom, OBJECT(pdev), name, pdev->romsize, &error_fatal); 2471 ptr = memory_region_get_ram_ptr(&pdev->rom); 2472 if (load_image_size(path, ptr, size) < 0) { 2473 error_setg(errp, "failed to load romfile \"%s\"", pdev->romfile); 2474 g_free(path); 2475 return; 2476 } 2477 g_free(path); 2478 2479 if (is_default_rom) { 2480 /* Only the default rom images will be patched (if needed). */ 2481 pci_patch_ids(pdev, ptr, size); 2482 } 2483 2484 pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom); 2485 } 2486 2487 static void pci_del_option_rom(PCIDevice *pdev) 2488 { 2489 if (!pdev->has_rom) 2490 return; 2491 2492 vmstate_unregister_ram(&pdev->rom, &pdev->qdev); 2493 pdev->has_rom = false; 2494 } 2495 2496 /* 2497 * On success, pci_add_capability() returns a positive value 2498 * that the offset of the pci capability. 2499 * On failure, it sets an error and returns a negative error 2500 * code. 2501 */ 2502 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, 2503 uint8_t offset, uint8_t size, 2504 Error **errp) 2505 { 2506 uint8_t *config; 2507 int i, overlapping_cap; 2508 2509 if (!offset) { 2510 offset = pci_find_space(pdev, size); 2511 /* out of PCI config space is programming error */ 2512 assert(offset); 2513 } else { 2514 /* Verify that capabilities don't overlap. Note: device assignment 2515 * depends on this check to verify that the device is not broken. 2516 * Should never trigger for emulated devices, but it's helpful 2517 * for debugging these. */ 2518 for (i = offset; i < offset + size; i++) { 2519 overlapping_cap = pci_find_capability_at_offset(pdev, i); 2520 if (overlapping_cap) { 2521 error_setg(errp, "%s:%02x:%02x.%x " 2522 "Attempt to add PCI capability %x at offset " 2523 "%x overlaps existing capability %x at offset %x", 2524 pci_root_bus_path(pdev), pci_dev_bus_num(pdev), 2525 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), 2526 cap_id, offset, overlapping_cap, i); 2527 return -EINVAL; 2528 } 2529 } 2530 } 2531 2532 config = pdev->config + offset; 2533 config[PCI_CAP_LIST_ID] = cap_id; 2534 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST]; 2535 pdev->config[PCI_CAPABILITY_LIST] = offset; 2536 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST; 2537 memset(pdev->used + offset, 0xFF, QEMU_ALIGN_UP(size, 4)); 2538 /* Make capability read-only by default */ 2539 memset(pdev->wmask + offset, 0, size); 2540 /* Check capability by default */ 2541 memset(pdev->cmask + offset, 0xFF, size); 2542 return offset; 2543 } 2544 2545 /* Unlink capability from the pci config space. */ 2546 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size) 2547 { 2548 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev); 2549 if (!offset) 2550 return; 2551 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT]; 2552 /* Make capability writable again */ 2553 memset(pdev->wmask + offset, 0xff, size); 2554 memset(pdev->w1cmask + offset, 0, size); 2555 /* Clear cmask as device-specific registers can't be checked */ 2556 memset(pdev->cmask + offset, 0, size); 2557 memset(pdev->used + offset, 0, QEMU_ALIGN_UP(size, 4)); 2558 2559 if (!pdev->config[PCI_CAPABILITY_LIST]) 2560 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST; 2561 } 2562 2563 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id) 2564 { 2565 return pci_find_capability_list(pdev, cap_id, NULL); 2566 } 2567 2568 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent) 2569 { 2570 PCIDevice *d = (PCIDevice *)dev; 2571 const pci_class_desc *desc; 2572 char ctxt[64]; 2573 PCIIORegion *r; 2574 int i, class; 2575 2576 class = pci_get_word(d->config + PCI_CLASS_DEVICE); 2577 desc = pci_class_descriptions; 2578 while (desc->desc && class != desc->class) 2579 desc++; 2580 if (desc->desc) { 2581 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc); 2582 } else { 2583 snprintf(ctxt, sizeof(ctxt), "Class %04x", class); 2584 } 2585 2586 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, " 2587 "pci id %04x:%04x (sub %04x:%04x)\n", 2588 indent, "", ctxt, pci_dev_bus_num(d), 2589 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn), 2590 pci_get_word(d->config + PCI_VENDOR_ID), 2591 pci_get_word(d->config + PCI_DEVICE_ID), 2592 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID), 2593 pci_get_word(d->config + PCI_SUBSYSTEM_ID)); 2594 for (i = 0; i < PCI_NUM_REGIONS; i++) { 2595 r = &d->io_regions[i]; 2596 if (!r->size) 2597 continue; 2598 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS 2599 " [0x%"FMT_PCIBUS"]\n", 2600 indent, "", 2601 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem", 2602 r->addr, r->addr + r->size - 1); 2603 } 2604 } 2605 2606 static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len) 2607 { 2608 PCIDevice *d = (PCIDevice *)dev; 2609 const char *name = NULL; 2610 const pci_class_desc *desc = pci_class_descriptions; 2611 int class = pci_get_word(d->config + PCI_CLASS_DEVICE); 2612 2613 while (desc->desc && 2614 (class & ~desc->fw_ign_bits) != 2615 (desc->class & ~desc->fw_ign_bits)) { 2616 desc++; 2617 } 2618 2619 if (desc->desc) { 2620 name = desc->fw_name; 2621 } 2622 2623 if (name) { 2624 pstrcpy(buf, len, name); 2625 } else { 2626 snprintf(buf, len, "pci%04x,%04x", 2627 pci_get_word(d->config + PCI_VENDOR_ID), 2628 pci_get_word(d->config + PCI_DEVICE_ID)); 2629 } 2630 2631 return buf; 2632 } 2633 2634 static char *pcibus_get_fw_dev_path(DeviceState *dev) 2635 { 2636 PCIDevice *d = (PCIDevice *)dev; 2637 char path[50], name[33]; 2638 int off; 2639 2640 off = snprintf(path, sizeof(path), "%s@%x", 2641 pci_dev_fw_name(dev, name, sizeof name), 2642 PCI_SLOT(d->devfn)); 2643 if (PCI_FUNC(d->devfn)) 2644 snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn)); 2645 return g_strdup(path); 2646 } 2647 2648 static char *pcibus_get_dev_path(DeviceState *dev) 2649 { 2650 PCIDevice *d = container_of(dev, PCIDevice, qdev); 2651 PCIDevice *t; 2652 int slot_depth; 2653 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function. 2654 * 00 is added here to make this format compatible with 2655 * domain:Bus:Slot.Func for systems without nested PCI bridges. 2656 * Slot.Function list specifies the slot and function numbers for all 2657 * devices on the path from root to the specific device. */ 2658 const char *root_bus_path; 2659 int root_bus_len; 2660 char slot[] = ":SS.F"; 2661 int slot_len = sizeof slot - 1 /* For '\0' */; 2662 int path_len; 2663 char *path, *p; 2664 int s; 2665 2666 root_bus_path = pci_root_bus_path(d); 2667 root_bus_len = strlen(root_bus_path); 2668 2669 /* Calculate # of slots on path between device and root. */; 2670 slot_depth = 0; 2671 for (t = d; t; t = pci_get_bus(t)->parent_dev) { 2672 ++slot_depth; 2673 } 2674 2675 path_len = root_bus_len + slot_len * slot_depth; 2676 2677 /* Allocate memory, fill in the terminating null byte. */ 2678 path = g_malloc(path_len + 1 /* For '\0' */); 2679 path[path_len] = '\0'; 2680 2681 memcpy(path, root_bus_path, root_bus_len); 2682 2683 /* Fill in slot numbers. We walk up from device to root, so need to print 2684 * them in the reverse order, last to first. */ 2685 p = path + path_len; 2686 for (t = d; t; t = pci_get_bus(t)->parent_dev) { 2687 p -= slot_len; 2688 s = snprintf(slot, sizeof slot, ":%02x.%x", 2689 PCI_SLOT(t->devfn), PCI_FUNC(t->devfn)); 2690 assert(s == slot_len); 2691 memcpy(p, slot, slot_len); 2692 } 2693 2694 return path; 2695 } 2696 2697 static int pci_qdev_find_recursive(PCIBus *bus, 2698 const char *id, PCIDevice **pdev) 2699 { 2700 DeviceState *qdev = qdev_find_recursive(&bus->qbus, id); 2701 if (!qdev) { 2702 return -ENODEV; 2703 } 2704 2705 /* roughly check if given qdev is pci device */ 2706 if (object_dynamic_cast(OBJECT(qdev), TYPE_PCI_DEVICE)) { 2707 *pdev = PCI_DEVICE(qdev); 2708 return 0; 2709 } 2710 return -EINVAL; 2711 } 2712 2713 int pci_qdev_find_device(const char *id, PCIDevice **pdev) 2714 { 2715 PCIHostState *host_bridge; 2716 int rc = -ENODEV; 2717 2718 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { 2719 int tmp = pci_qdev_find_recursive(host_bridge->bus, id, pdev); 2720 if (!tmp) { 2721 rc = 0; 2722 break; 2723 } 2724 if (tmp != -ENODEV) { 2725 rc = tmp; 2726 } 2727 } 2728 2729 return rc; 2730 } 2731 2732 MemoryRegion *pci_address_space(PCIDevice *dev) 2733 { 2734 return pci_get_bus(dev)->address_space_mem; 2735 } 2736 2737 MemoryRegion *pci_address_space_io(PCIDevice *dev) 2738 { 2739 return pci_get_bus(dev)->address_space_io; 2740 } 2741 2742 static void pci_device_class_init(ObjectClass *klass, void *data) 2743 { 2744 DeviceClass *k = DEVICE_CLASS(klass); 2745 2746 k->realize = pci_qdev_realize; 2747 k->unrealize = pci_qdev_unrealize; 2748 k->bus_type = TYPE_PCI_BUS; 2749 device_class_set_props(k, pci_props); 2750 } 2751 2752 static void pci_device_class_base_init(ObjectClass *klass, void *data) 2753 { 2754 if (!object_class_is_abstract(klass)) { 2755 ObjectClass *conventional = 2756 object_class_dynamic_cast(klass, INTERFACE_CONVENTIONAL_PCI_DEVICE); 2757 ObjectClass *pcie = 2758 object_class_dynamic_cast(klass, INTERFACE_PCIE_DEVICE); 2759 assert(conventional || pcie); 2760 } 2761 } 2762 2763 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev) 2764 { 2765 PCIBus *bus = pci_get_bus(dev); 2766 PCIBus *iommu_bus = bus; 2767 uint8_t devfn = dev->devfn; 2768 2769 while (iommu_bus && !iommu_bus->iommu_fn && iommu_bus->parent_dev) { 2770 PCIBus *parent_bus = pci_get_bus(iommu_bus->parent_dev); 2771 2772 /* 2773 * The requester ID of the provided device may be aliased, as seen from 2774 * the IOMMU, due to topology limitations. The IOMMU relies on a 2775 * requester ID to provide a unique AddressSpace for devices, but 2776 * conventional PCI buses pre-date such concepts. Instead, the PCIe- 2777 * to-PCI bridge creates and accepts transactions on behalf of down- 2778 * stream devices. When doing so, all downstream devices are masked 2779 * (aliased) behind a single requester ID. The requester ID used 2780 * depends on the format of the bridge devices. Proper PCIe-to-PCI 2781 * bridges, with a PCIe capability indicating such, follow the 2782 * guidelines of chapter 2.3 of the PCIe-to-PCI/X bridge specification, 2783 * where the bridge uses the seconary bus as the bridge portion of the 2784 * requester ID and devfn of 00.0. For other bridges, typically those 2785 * found on the root complex such as the dmi-to-pci-bridge, we follow 2786 * the convention of typical bare-metal hardware, which uses the 2787 * requester ID of the bridge itself. There are device specific 2788 * exceptions to these rules, but these are the defaults that the 2789 * Linux kernel uses when determining DMA aliases itself and believed 2790 * to be true for the bare metal equivalents of the devices emulated 2791 * in QEMU. 2792 */ 2793 if (!pci_bus_is_express(iommu_bus)) { 2794 PCIDevice *parent = iommu_bus->parent_dev; 2795 2796 if (pci_is_express(parent) && 2797 pcie_cap_get_type(parent) == PCI_EXP_TYPE_PCI_BRIDGE) { 2798 devfn = PCI_DEVFN(0, 0); 2799 bus = iommu_bus; 2800 } else { 2801 devfn = parent->devfn; 2802 bus = parent_bus; 2803 } 2804 } 2805 2806 iommu_bus = parent_bus; 2807 } 2808 if (!pci_bus_bypass_iommu(bus) && iommu_bus && iommu_bus->iommu_fn) { 2809 return iommu_bus->iommu_fn(bus, iommu_bus->iommu_opaque, devfn); 2810 } 2811 return &address_space_memory; 2812 } 2813 2814 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque) 2815 { 2816 bus->iommu_fn = fn; 2817 bus->iommu_opaque = opaque; 2818 } 2819 2820 static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque) 2821 { 2822 Range *range = opaque; 2823 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 2824 uint16_t cmd = pci_get_word(dev->config + PCI_COMMAND); 2825 int i; 2826 2827 if (!(cmd & PCI_COMMAND_MEMORY)) { 2828 return; 2829 } 2830 2831 if (pc->is_bridge) { 2832 pcibus_t base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 2833 pcibus_t limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 2834 2835 base = MAX(base, 0x1ULL << 32); 2836 2837 if (limit >= base) { 2838 Range pref_range; 2839 range_set_bounds(&pref_range, base, limit); 2840 range_extend(range, &pref_range); 2841 } 2842 } 2843 for (i = 0; i < PCI_NUM_REGIONS; ++i) { 2844 PCIIORegion *r = &dev->io_regions[i]; 2845 pcibus_t lob, upb; 2846 Range region_range; 2847 2848 if (!r->size || 2849 (r->type & PCI_BASE_ADDRESS_SPACE_IO) || 2850 !(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64)) { 2851 continue; 2852 } 2853 2854 lob = pci_bar_address(dev, i, r->type, r->size); 2855 upb = lob + r->size - 1; 2856 if (lob == PCI_BAR_UNMAPPED) { 2857 continue; 2858 } 2859 2860 lob = MAX(lob, 0x1ULL << 32); 2861 2862 if (upb >= lob) { 2863 range_set_bounds(®ion_range, lob, upb); 2864 range_extend(range, ®ion_range); 2865 } 2866 } 2867 } 2868 2869 void pci_bus_get_w64_range(PCIBus *bus, Range *range) 2870 { 2871 range_make_empty(range); 2872 pci_for_each_device_under_bus(bus, pci_dev_get_w64, range); 2873 } 2874 2875 static bool pcie_has_upstream_port(PCIDevice *dev) 2876 { 2877 PCIDevice *parent_dev = pci_bridge_get_device(pci_get_bus(dev)); 2878 2879 /* Device associated with an upstream port. 2880 * As there are several types of these, it's easier to check the 2881 * parent device: upstream ports are always connected to 2882 * root or downstream ports. 2883 */ 2884 return parent_dev && 2885 pci_is_express(parent_dev) && 2886 parent_dev->exp.exp_cap && 2887 (pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_ROOT_PORT || 2888 pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_DOWNSTREAM); 2889 } 2890 2891 PCIDevice *pci_get_function_0(PCIDevice *pci_dev) 2892 { 2893 PCIBus *bus = pci_get_bus(pci_dev); 2894 2895 if(pcie_has_upstream_port(pci_dev)) { 2896 /* With an upstream PCIe port, we only support 1 device at slot 0 */ 2897 return bus->devices[0]; 2898 } else { 2899 /* Other bus types might support multiple devices at slots 0-31 */ 2900 return bus->devices[PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 0)]; 2901 } 2902 } 2903 2904 MSIMessage pci_get_msi_message(PCIDevice *dev, int vector) 2905 { 2906 MSIMessage msg; 2907 if (msix_enabled(dev)) { 2908 msg = msix_get_message(dev, vector); 2909 } else if (msi_enabled(dev)) { 2910 msg = msi_get_message(dev, vector); 2911 } else { 2912 /* Should never happen */ 2913 error_report("%s: unknown interrupt type", __func__); 2914 abort(); 2915 } 2916 return msg; 2917 } 2918 2919 void pci_set_power(PCIDevice *d, bool state) 2920 { 2921 if (d->has_power == state) { 2922 return; 2923 } 2924 2925 d->has_power = state; 2926 pci_update_mappings(d); 2927 memory_region_set_enabled(&d->bus_master_enable_region, 2928 (pci_get_word(d->config + PCI_COMMAND) 2929 & PCI_COMMAND_MASTER) && d->has_power); 2930 if (!d->has_power) { 2931 pci_device_reset(d); 2932 } 2933 } 2934 2935 static const TypeInfo pci_device_type_info = { 2936 .name = TYPE_PCI_DEVICE, 2937 .parent = TYPE_DEVICE, 2938 .instance_size = sizeof(PCIDevice), 2939 .abstract = true, 2940 .class_size = sizeof(PCIDeviceClass), 2941 .class_init = pci_device_class_init, 2942 .class_base_init = pci_device_class_base_init, 2943 }; 2944 2945 static void pci_register_types(void) 2946 { 2947 type_register_static(&pci_bus_info); 2948 type_register_static(&pcie_bus_info); 2949 type_register_static(&conventional_pci_interface_info); 2950 type_register_static(&cxl_interface_info); 2951 type_register_static(&pcie_interface_info); 2952 type_register_static(&pci_device_type_info); 2953 } 2954 2955 type_init(pci_register_types) 2956