1 /* 2 * QEMU PCI bus manager 3 * 4 * Copyright (c) 2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/hw.h" 25 #include "hw/pci/pci.h" 26 #include "hw/pci/pci_bridge.h" 27 #include "hw/pci/pci_bus.h" 28 #include "monitor/monitor.h" 29 #include "net/net.h" 30 #include "sysemu/sysemu.h" 31 #include "hw/loader.h" 32 #include "qemu/range.h" 33 #include "qmp-commands.h" 34 #include "hw/pci/msi.h" 35 #include "hw/pci/msix.h" 36 #include "exec/address-spaces.h" 37 38 //#define DEBUG_PCI 39 #ifdef DEBUG_PCI 40 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) 41 #else 42 # define PCI_DPRINTF(format, ...) do { } while (0) 43 #endif 44 45 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent); 46 static char *pcibus_get_dev_path(DeviceState *dev); 47 static char *pcibus_get_fw_dev_path(DeviceState *dev); 48 static int pcibus_reset(BusState *qbus); 49 50 static Property pci_props[] = { 51 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1), 52 DEFINE_PROP_STRING("romfile", PCIDevice, romfile), 53 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1), 54 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present, 55 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false), 56 DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present, 57 QEMU_PCI_CAP_SERR_BITNR, true), 58 DEFINE_PROP_END_OF_LIST() 59 }; 60 61 static void pci_bus_class_init(ObjectClass *klass, void *data) 62 { 63 BusClass *k = BUS_CLASS(klass); 64 65 k->print_dev = pcibus_dev_print; 66 k->get_dev_path = pcibus_get_dev_path; 67 k->get_fw_dev_path = pcibus_get_fw_dev_path; 68 k->reset = pcibus_reset; 69 } 70 71 static const TypeInfo pci_bus_info = { 72 .name = TYPE_PCI_BUS, 73 .parent = TYPE_BUS, 74 .instance_size = sizeof(PCIBus), 75 .class_init = pci_bus_class_init, 76 }; 77 78 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num); 79 static void pci_update_mappings(PCIDevice *d); 80 static void pci_set_irq(void *opaque, int irq_num, int level); 81 static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom); 82 static void pci_del_option_rom(PCIDevice *pdev); 83 84 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET; 85 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU; 86 87 struct PCIHostBus { 88 int domain; 89 struct PCIBus *bus; 90 QLIST_ENTRY(PCIHostBus) next; 91 }; 92 static QLIST_HEAD(, PCIHostBus) host_buses; 93 94 static const VMStateDescription vmstate_pcibus = { 95 .name = "PCIBUS", 96 .version_id = 1, 97 .minimum_version_id = 1, 98 .minimum_version_id_old = 1, 99 .fields = (VMStateField []) { 100 VMSTATE_INT32_EQUAL(nirq, PCIBus), 101 VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t), 102 VMSTATE_END_OF_LIST() 103 } 104 }; 105 static int pci_bar(PCIDevice *d, int reg) 106 { 107 uint8_t type; 108 109 if (reg != PCI_ROM_SLOT) 110 return PCI_BASE_ADDRESS_0 + reg * 4; 111 112 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 113 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS; 114 } 115 116 static inline int pci_irq_state(PCIDevice *d, int irq_num) 117 { 118 return (d->irq_state >> irq_num) & 0x1; 119 } 120 121 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level) 122 { 123 d->irq_state &= ~(0x1 << irq_num); 124 d->irq_state |= level << irq_num; 125 } 126 127 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change) 128 { 129 PCIBus *bus; 130 for (;;) { 131 bus = pci_dev->bus; 132 irq_num = bus->map_irq(pci_dev, irq_num); 133 if (bus->set_irq) 134 break; 135 pci_dev = bus->parent_dev; 136 } 137 bus->irq_count[irq_num] += change; 138 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0); 139 } 140 141 int pci_bus_get_irq_level(PCIBus *bus, int irq_num) 142 { 143 assert(irq_num >= 0); 144 assert(irq_num < bus->nirq); 145 return !!bus->irq_count[irq_num]; 146 } 147 148 /* Update interrupt status bit in config space on interrupt 149 * state change. */ 150 static void pci_update_irq_status(PCIDevice *dev) 151 { 152 if (dev->irq_state) { 153 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT; 154 } else { 155 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; 156 } 157 } 158 159 void pci_device_deassert_intx(PCIDevice *dev) 160 { 161 int i; 162 for (i = 0; i < PCI_NUM_PINS; ++i) { 163 qemu_set_irq(dev->irq[i], 0); 164 } 165 } 166 167 /* 168 * This function is called on #RST and FLR. 169 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set 170 */ 171 void pci_device_reset(PCIDevice *dev) 172 { 173 int r; 174 175 qdev_reset_all(&dev->qdev); 176 177 dev->irq_state = 0; 178 pci_update_irq_status(dev); 179 pci_device_deassert_intx(dev); 180 /* Clear all writable bits */ 181 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND, 182 pci_get_word(dev->wmask + PCI_COMMAND) | 183 pci_get_word(dev->w1cmask + PCI_COMMAND)); 184 pci_word_test_and_clear_mask(dev->config + PCI_STATUS, 185 pci_get_word(dev->wmask + PCI_STATUS) | 186 pci_get_word(dev->w1cmask + PCI_STATUS)); 187 dev->config[PCI_CACHE_LINE_SIZE] = 0x0; 188 dev->config[PCI_INTERRUPT_LINE] = 0x0; 189 for (r = 0; r < PCI_NUM_REGIONS; ++r) { 190 PCIIORegion *region = &dev->io_regions[r]; 191 if (!region->size) { 192 continue; 193 } 194 195 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) && 196 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 197 pci_set_quad(dev->config + pci_bar(dev, r), region->type); 198 } else { 199 pci_set_long(dev->config + pci_bar(dev, r), region->type); 200 } 201 } 202 pci_update_mappings(dev); 203 204 msi_reset(dev); 205 msix_reset(dev); 206 } 207 208 /* 209 * Trigger pci bus reset under a given bus. 210 * To be called on RST# assert. 211 */ 212 void pci_bus_reset(PCIBus *bus) 213 { 214 int i; 215 216 for (i = 0; i < bus->nirq; i++) { 217 bus->irq_count[i] = 0; 218 } 219 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 220 if (bus->devices[i]) { 221 pci_device_reset(bus->devices[i]); 222 } 223 } 224 } 225 226 static int pcibus_reset(BusState *qbus) 227 { 228 pci_bus_reset(DO_UPCAST(PCIBus, qbus, qbus)); 229 230 /* topology traverse is done by pci_bus_reset(). 231 Tell qbus/qdev walker not to traverse the tree */ 232 return 1; 233 } 234 235 static void pci_host_bus_register(int domain, PCIBus *bus) 236 { 237 struct PCIHostBus *host; 238 host = g_malloc0(sizeof(*host)); 239 host->domain = domain; 240 host->bus = bus; 241 QLIST_INSERT_HEAD(&host_buses, host, next); 242 } 243 244 PCIBus *pci_find_root_bus(int domain) 245 { 246 struct PCIHostBus *host; 247 248 QLIST_FOREACH(host, &host_buses, next) { 249 if (host->domain == domain) { 250 return host->bus; 251 } 252 } 253 254 return NULL; 255 } 256 257 int pci_find_domain(const PCIBus *bus) 258 { 259 PCIDevice *d; 260 struct PCIHostBus *host; 261 262 /* obtain root bus */ 263 while ((d = bus->parent_dev) != NULL) { 264 bus = d->bus; 265 } 266 267 QLIST_FOREACH(host, &host_buses, next) { 268 if (host->bus == bus) { 269 return host->domain; 270 } 271 } 272 273 abort(); /* should not be reached */ 274 return -1; 275 } 276 277 static void pci_bus_init(PCIBus *bus, DeviceState *parent, 278 const char *name, 279 MemoryRegion *address_space_mem, 280 MemoryRegion *address_space_io, 281 uint8_t devfn_min) 282 { 283 assert(PCI_FUNC(devfn_min) == 0); 284 bus->devfn_min = devfn_min; 285 bus->address_space_mem = address_space_mem; 286 bus->address_space_io = address_space_io; 287 288 /* host bridge */ 289 QLIST_INIT(&bus->child); 290 pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */ 291 292 vmstate_register(NULL, -1, &vmstate_pcibus, bus); 293 } 294 295 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent, 296 const char *name, 297 MemoryRegion *address_space_mem, 298 MemoryRegion *address_space_io, 299 uint8_t devfn_min) 300 { 301 qbus_create_inplace(bus, TYPE_PCI_BUS, parent, name); 302 pci_bus_init(bus, parent, name, address_space_mem, 303 address_space_io, devfn_min); 304 } 305 306 PCIBus *pci_bus_new(DeviceState *parent, const char *name, 307 MemoryRegion *address_space_mem, 308 MemoryRegion *address_space_io, 309 uint8_t devfn_min) 310 { 311 PCIBus *bus; 312 313 bus = PCI_BUS(qbus_create(TYPE_PCI_BUS, parent, name)); 314 pci_bus_init(bus, parent, name, address_space_mem, 315 address_space_io, devfn_min); 316 return bus; 317 } 318 319 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 320 void *irq_opaque, int nirq) 321 { 322 bus->set_irq = set_irq; 323 bus->map_irq = map_irq; 324 bus->irq_opaque = irq_opaque; 325 bus->nirq = nirq; 326 bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0])); 327 } 328 329 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *qdev) 330 { 331 bus->qbus.allow_hotplug = 1; 332 bus->hotplug = hotplug; 333 bus->hotplug_qdev = qdev; 334 } 335 336 PCIBus *pci_register_bus(DeviceState *parent, const char *name, 337 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 338 void *irq_opaque, 339 MemoryRegion *address_space_mem, 340 MemoryRegion *address_space_io, 341 uint8_t devfn_min, int nirq) 342 { 343 PCIBus *bus; 344 345 bus = pci_bus_new(parent, name, address_space_mem, 346 address_space_io, devfn_min); 347 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq); 348 return bus; 349 } 350 351 int pci_bus_num(PCIBus *s) 352 { 353 if (!s->parent_dev) 354 return 0; /* pci host bridge */ 355 return s->parent_dev->config[PCI_SECONDARY_BUS]; 356 } 357 358 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size) 359 { 360 PCIDevice *s = container_of(pv, PCIDevice, config); 361 uint8_t *config; 362 int i; 363 364 assert(size == pci_config_size(s)); 365 config = g_malloc(size); 366 367 qemu_get_buffer(f, config, size); 368 for (i = 0; i < size; ++i) { 369 if ((config[i] ^ s->config[i]) & 370 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) { 371 g_free(config); 372 return -EINVAL; 373 } 374 } 375 memcpy(s->config, config, size); 376 377 pci_update_mappings(s); 378 379 memory_region_set_enabled(&s->bus_master_enable_region, 380 pci_get_word(s->config + PCI_COMMAND) 381 & PCI_COMMAND_MASTER); 382 383 g_free(config); 384 return 0; 385 } 386 387 /* just put buffer */ 388 static void put_pci_config_device(QEMUFile *f, void *pv, size_t size) 389 { 390 const uint8_t **v = pv; 391 assert(size == pci_config_size(container_of(pv, PCIDevice, config))); 392 qemu_put_buffer(f, *v, size); 393 } 394 395 static VMStateInfo vmstate_info_pci_config = { 396 .name = "pci config", 397 .get = get_pci_config_device, 398 .put = put_pci_config_device, 399 }; 400 401 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size) 402 { 403 PCIDevice *s = container_of(pv, PCIDevice, irq_state); 404 uint32_t irq_state[PCI_NUM_PINS]; 405 int i; 406 for (i = 0; i < PCI_NUM_PINS; ++i) { 407 irq_state[i] = qemu_get_be32(f); 408 if (irq_state[i] != 0x1 && irq_state[i] != 0) { 409 fprintf(stderr, "irq state %d: must be 0 or 1.\n", 410 irq_state[i]); 411 return -EINVAL; 412 } 413 } 414 415 for (i = 0; i < PCI_NUM_PINS; ++i) { 416 pci_set_irq_state(s, i, irq_state[i]); 417 } 418 419 return 0; 420 } 421 422 static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size) 423 { 424 int i; 425 PCIDevice *s = container_of(pv, PCIDevice, irq_state); 426 427 for (i = 0; i < PCI_NUM_PINS; ++i) { 428 qemu_put_be32(f, pci_irq_state(s, i)); 429 } 430 } 431 432 static VMStateInfo vmstate_info_pci_irq_state = { 433 .name = "pci irq state", 434 .get = get_pci_irq_state, 435 .put = put_pci_irq_state, 436 }; 437 438 const VMStateDescription vmstate_pci_device = { 439 .name = "PCIDevice", 440 .version_id = 2, 441 .minimum_version_id = 1, 442 .minimum_version_id_old = 1, 443 .fields = (VMStateField []) { 444 VMSTATE_INT32_LE(version_id, PCIDevice), 445 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0, 446 vmstate_info_pci_config, 447 PCI_CONFIG_SPACE_SIZE), 448 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2, 449 vmstate_info_pci_irq_state, 450 PCI_NUM_PINS * sizeof(int32_t)), 451 VMSTATE_END_OF_LIST() 452 } 453 }; 454 455 const VMStateDescription vmstate_pcie_device = { 456 .name = "PCIEDevice", 457 .version_id = 2, 458 .minimum_version_id = 1, 459 .minimum_version_id_old = 1, 460 .fields = (VMStateField []) { 461 VMSTATE_INT32_LE(version_id, PCIDevice), 462 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0, 463 vmstate_info_pci_config, 464 PCIE_CONFIG_SPACE_SIZE), 465 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2, 466 vmstate_info_pci_irq_state, 467 PCI_NUM_PINS * sizeof(int32_t)), 468 VMSTATE_END_OF_LIST() 469 } 470 }; 471 472 static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s) 473 { 474 return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device; 475 } 476 477 void pci_device_save(PCIDevice *s, QEMUFile *f) 478 { 479 /* Clear interrupt status bit: it is implicit 480 * in irq_state which we are saving. 481 * This makes us compatible with old devices 482 * which never set or clear this bit. */ 483 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; 484 vmstate_save_state(f, pci_get_vmstate(s), s); 485 /* Restore the interrupt status bit. */ 486 pci_update_irq_status(s); 487 } 488 489 int pci_device_load(PCIDevice *s, QEMUFile *f) 490 { 491 int ret; 492 ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id); 493 /* Restore the interrupt status bit. */ 494 pci_update_irq_status(s); 495 return ret; 496 } 497 498 static void pci_set_default_subsystem_id(PCIDevice *pci_dev) 499 { 500 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, 501 pci_default_sub_vendor_id); 502 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 503 pci_default_sub_device_id); 504 } 505 506 /* 507 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL 508 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error 509 */ 510 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, 511 unsigned int *slotp, unsigned int *funcp) 512 { 513 const char *p; 514 char *e; 515 unsigned long val; 516 unsigned long dom = 0, bus = 0; 517 unsigned int slot = 0; 518 unsigned int func = 0; 519 520 p = addr; 521 val = strtoul(p, &e, 16); 522 if (e == p) 523 return -1; 524 if (*e == ':') { 525 bus = val; 526 p = e + 1; 527 val = strtoul(p, &e, 16); 528 if (e == p) 529 return -1; 530 if (*e == ':') { 531 dom = bus; 532 bus = val; 533 p = e + 1; 534 val = strtoul(p, &e, 16); 535 if (e == p) 536 return -1; 537 } 538 } 539 540 slot = val; 541 542 if (funcp != NULL) { 543 if (*e != '.') 544 return -1; 545 546 p = e + 1; 547 val = strtoul(p, &e, 16); 548 if (e == p) 549 return -1; 550 551 func = val; 552 } 553 554 /* if funcp == NULL func is 0 */ 555 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7) 556 return -1; 557 558 if (*e) 559 return -1; 560 561 *domp = dom; 562 *busp = bus; 563 *slotp = slot; 564 if (funcp != NULL) 565 *funcp = func; 566 return 0; 567 } 568 569 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp, 570 unsigned *slotp) 571 { 572 /* strip legacy tag */ 573 if (!strncmp(addr, "pci_addr=", 9)) { 574 addr += 9; 575 } 576 if (pci_parse_devaddr(addr, domp, busp, slotp, NULL)) { 577 monitor_printf(mon, "Invalid pci address\n"); 578 return -1; 579 } 580 return 0; 581 } 582 583 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr) 584 { 585 int dom, bus; 586 unsigned slot; 587 588 if (!devaddr) { 589 *devfnp = -1; 590 return pci_find_bus_nr(pci_find_root_bus(0), 0); 591 } 592 593 if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) { 594 return NULL; 595 } 596 597 *devfnp = PCI_DEVFN(slot, 0); 598 return pci_find_bus_nr(pci_find_root_bus(dom), bus); 599 } 600 601 static void pci_init_cmask(PCIDevice *dev) 602 { 603 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff); 604 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff); 605 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST; 606 dev->cmask[PCI_REVISION_ID] = 0xff; 607 dev->cmask[PCI_CLASS_PROG] = 0xff; 608 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff); 609 dev->cmask[PCI_HEADER_TYPE] = 0xff; 610 dev->cmask[PCI_CAPABILITY_LIST] = 0xff; 611 } 612 613 static void pci_init_wmask(PCIDevice *dev) 614 { 615 int config_size = pci_config_size(dev); 616 617 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff; 618 dev->wmask[PCI_INTERRUPT_LINE] = 0xff; 619 pci_set_word(dev->wmask + PCI_COMMAND, 620 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | 621 PCI_COMMAND_INTX_DISABLE); 622 if (dev->cap_present & QEMU_PCI_CAP_SERR) { 623 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR); 624 } 625 626 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff, 627 config_size - PCI_CONFIG_HEADER_SIZE); 628 } 629 630 static void pci_init_w1cmask(PCIDevice *dev) 631 { 632 /* 633 * Note: It's okay to set w1cmask even for readonly bits as 634 * long as their value is hardwired to 0. 635 */ 636 pci_set_word(dev->w1cmask + PCI_STATUS, 637 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT | 638 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT | 639 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY); 640 } 641 642 static void pci_init_mask_bridge(PCIDevice *d) 643 { 644 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and 645 PCI_SEC_LETENCY_TIMER */ 646 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4); 647 648 /* base and limit */ 649 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff; 650 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff; 651 pci_set_word(d->wmask + PCI_MEMORY_BASE, 652 PCI_MEMORY_RANGE_MASK & 0xffff); 653 pci_set_word(d->wmask + PCI_MEMORY_LIMIT, 654 PCI_MEMORY_RANGE_MASK & 0xffff); 655 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE, 656 PCI_PREF_RANGE_MASK & 0xffff); 657 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT, 658 PCI_PREF_RANGE_MASK & 0xffff); 659 660 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */ 661 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8); 662 663 /* Supported memory and i/o types */ 664 d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16; 665 d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16; 666 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE, 667 PCI_PREF_RANGE_TYPE_64); 668 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT, 669 PCI_PREF_RANGE_TYPE_64); 670 671 /* TODO: add this define to pci_regs.h in linux and then in qemu. */ 672 #define PCI_BRIDGE_CTL_VGA_16BIT 0x10 /* VGA 16-bit decode */ 673 #define PCI_BRIDGE_CTL_DISCARD 0x100 /* Primary discard timer */ 674 #define PCI_BRIDGE_CTL_SEC_DISCARD 0x200 /* Secondary discard timer */ 675 #define PCI_BRIDGE_CTL_DISCARD_STATUS 0x400 /* Discard timer status */ 676 #define PCI_BRIDGE_CTL_DISCARD_SERR 0x800 /* Discard timer SERR# enable */ 677 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 678 PCI_BRIDGE_CTL_PARITY | 679 PCI_BRIDGE_CTL_SERR | 680 PCI_BRIDGE_CTL_ISA | 681 PCI_BRIDGE_CTL_VGA | 682 PCI_BRIDGE_CTL_VGA_16BIT | 683 PCI_BRIDGE_CTL_MASTER_ABORT | 684 PCI_BRIDGE_CTL_BUS_RESET | 685 PCI_BRIDGE_CTL_FAST_BACK | 686 PCI_BRIDGE_CTL_DISCARD | 687 PCI_BRIDGE_CTL_SEC_DISCARD | 688 PCI_BRIDGE_CTL_DISCARD_SERR); 689 /* Below does not do anything as we never set this bit, put here for 690 * completeness. */ 691 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL, 692 PCI_BRIDGE_CTL_DISCARD_STATUS); 693 d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK; 694 d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK; 695 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE, 696 PCI_PREF_RANGE_TYPE_MASK); 697 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT, 698 PCI_PREF_RANGE_TYPE_MASK); 699 } 700 701 static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev) 702 { 703 uint8_t slot = PCI_SLOT(dev->devfn); 704 uint8_t func; 705 706 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 707 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION; 708 } 709 710 /* 711 * multifunction bit is interpreted in two ways as follows. 712 * - all functions must set the bit to 1. 713 * Example: Intel X53 714 * - function 0 must set the bit, but the rest function (> 0) 715 * is allowed to leave the bit to 0. 716 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10, 717 * 718 * So OS (at least Linux) checks the bit of only function 0, 719 * and doesn't see the bit of function > 0. 720 * 721 * The below check allows both interpretation. 722 */ 723 if (PCI_FUNC(dev->devfn)) { 724 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)]; 725 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) { 726 /* function 0 should set multifunction bit */ 727 error_report("PCI: single function device can't be populated " 728 "in function %x.%x", slot, PCI_FUNC(dev->devfn)); 729 return -1; 730 } 731 return 0; 732 } 733 734 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 735 return 0; 736 } 737 /* function 0 indicates single function, so function > 0 must be NULL */ 738 for (func = 1; func < PCI_FUNC_MAX; ++func) { 739 if (bus->devices[PCI_DEVFN(slot, func)]) { 740 error_report("PCI: %x.0 indicates single function, " 741 "but %x.%x is already populated.", 742 slot, slot, func); 743 return -1; 744 } 745 } 746 return 0; 747 } 748 749 static void pci_config_alloc(PCIDevice *pci_dev) 750 { 751 int config_size = pci_config_size(pci_dev); 752 753 pci_dev->config = g_malloc0(config_size); 754 pci_dev->cmask = g_malloc0(config_size); 755 pci_dev->wmask = g_malloc0(config_size); 756 pci_dev->w1cmask = g_malloc0(config_size); 757 pci_dev->used = g_malloc0(config_size); 758 } 759 760 static void pci_config_free(PCIDevice *pci_dev) 761 { 762 g_free(pci_dev->config); 763 g_free(pci_dev->cmask); 764 g_free(pci_dev->wmask); 765 g_free(pci_dev->w1cmask); 766 g_free(pci_dev->used); 767 } 768 769 /* -1 for devfn means auto assign */ 770 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus, 771 const char *name, int devfn) 772 { 773 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 774 PCIConfigReadFunc *config_read = pc->config_read; 775 PCIConfigWriteFunc *config_write = pc->config_write; 776 777 if (devfn < 0) { 778 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices); 779 devfn += PCI_FUNC_MAX) { 780 if (!bus->devices[devfn]) 781 goto found; 782 } 783 error_report("PCI: no slot/function available for %s, all in use", name); 784 return NULL; 785 found: ; 786 } else if (bus->devices[devfn]) { 787 error_report("PCI: slot %d function %d not available for %s, in use by %s", 788 PCI_SLOT(devfn), PCI_FUNC(devfn), name, bus->devices[devfn]->name); 789 return NULL; 790 } 791 pci_dev->bus = bus; 792 if (bus->dma_context_fn) { 793 pci_dev->dma = bus->dma_context_fn(bus, bus->dma_context_opaque, devfn); 794 } else { 795 /* FIXME: Make dma_context_fn use MemoryRegions instead, so this path is 796 * taken unconditionally */ 797 /* FIXME: inherit memory region from bus creator */ 798 memory_region_init_alias(&pci_dev->bus_master_enable_region, "bus master", 799 get_system_memory(), 0, 800 memory_region_size(get_system_memory())); 801 memory_region_set_enabled(&pci_dev->bus_master_enable_region, false); 802 address_space_init(&pci_dev->bus_master_as, &pci_dev->bus_master_enable_region); 803 pci_dev->dma = g_new(DMAContext, 1); 804 dma_context_init(pci_dev->dma, &pci_dev->bus_master_as, NULL, NULL, NULL); 805 } 806 pci_dev->devfn = devfn; 807 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name); 808 pci_dev->irq_state = 0; 809 pci_config_alloc(pci_dev); 810 811 pci_config_set_vendor_id(pci_dev->config, pc->vendor_id); 812 pci_config_set_device_id(pci_dev->config, pc->device_id); 813 pci_config_set_revision(pci_dev->config, pc->revision); 814 pci_config_set_class(pci_dev->config, pc->class_id); 815 816 if (!pc->is_bridge) { 817 if (pc->subsystem_vendor_id || pc->subsystem_id) { 818 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, 819 pc->subsystem_vendor_id); 820 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 821 pc->subsystem_id); 822 } else { 823 pci_set_default_subsystem_id(pci_dev); 824 } 825 } else { 826 /* subsystem_vendor_id/subsystem_id are only for header type 0 */ 827 assert(!pc->subsystem_vendor_id); 828 assert(!pc->subsystem_id); 829 } 830 pci_init_cmask(pci_dev); 831 pci_init_wmask(pci_dev); 832 pci_init_w1cmask(pci_dev); 833 if (pc->is_bridge) { 834 pci_init_mask_bridge(pci_dev); 835 } 836 if (pci_init_multifunction(bus, pci_dev)) { 837 pci_config_free(pci_dev); 838 return NULL; 839 } 840 841 if (!config_read) 842 config_read = pci_default_read_config; 843 if (!config_write) 844 config_write = pci_default_write_config; 845 pci_dev->config_read = config_read; 846 pci_dev->config_write = config_write; 847 bus->devices[devfn] = pci_dev; 848 pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS); 849 pci_dev->version_id = 2; /* Current pci device vmstate version */ 850 return pci_dev; 851 } 852 853 static void do_pci_unregister_device(PCIDevice *pci_dev) 854 { 855 qemu_free_irqs(pci_dev->irq); 856 pci_dev->bus->devices[pci_dev->devfn] = NULL; 857 pci_config_free(pci_dev); 858 859 if (!pci_dev->bus->dma_context_fn) { 860 address_space_destroy(&pci_dev->bus_master_as); 861 memory_region_destroy(&pci_dev->bus_master_enable_region); 862 g_free(pci_dev->dma); 863 pci_dev->dma = NULL; 864 } 865 } 866 867 static void pci_unregister_io_regions(PCIDevice *pci_dev) 868 { 869 PCIIORegion *r; 870 int i; 871 872 for(i = 0; i < PCI_NUM_REGIONS; i++) { 873 r = &pci_dev->io_regions[i]; 874 if (!r->size || r->addr == PCI_BAR_UNMAPPED) 875 continue; 876 memory_region_del_subregion(r->address_space, r->memory); 877 } 878 } 879 880 static int pci_unregister_device(DeviceState *dev) 881 { 882 PCIDevice *pci_dev = PCI_DEVICE(dev); 883 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 884 885 pci_unregister_io_regions(pci_dev); 886 pci_del_option_rom(pci_dev); 887 888 if (pc->exit) { 889 pc->exit(pci_dev); 890 } 891 892 do_pci_unregister_device(pci_dev); 893 return 0; 894 } 895 896 void pci_register_bar(PCIDevice *pci_dev, int region_num, 897 uint8_t type, MemoryRegion *memory) 898 { 899 PCIIORegion *r; 900 uint32_t addr; 901 uint64_t wmask; 902 pcibus_t size = memory_region_size(memory); 903 904 assert(region_num >= 0); 905 assert(region_num < PCI_NUM_REGIONS); 906 if (size & (size-1)) { 907 fprintf(stderr, "ERROR: PCI region size must be pow2 " 908 "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size); 909 exit(1); 910 } 911 912 r = &pci_dev->io_regions[region_num]; 913 r->addr = PCI_BAR_UNMAPPED; 914 r->size = size; 915 r->type = type; 916 r->memory = NULL; 917 918 wmask = ~(size - 1); 919 addr = pci_bar(pci_dev, region_num); 920 if (region_num == PCI_ROM_SLOT) { 921 /* ROM enable bit is writable */ 922 wmask |= PCI_ROM_ADDRESS_ENABLE; 923 } 924 pci_set_long(pci_dev->config + addr, type); 925 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) && 926 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 927 pci_set_quad(pci_dev->wmask + addr, wmask); 928 pci_set_quad(pci_dev->cmask + addr, ~0ULL); 929 } else { 930 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff); 931 pci_set_long(pci_dev->cmask + addr, 0xffffffff); 932 } 933 pci_dev->io_regions[region_num].memory = memory; 934 pci_dev->io_regions[region_num].address_space 935 = type & PCI_BASE_ADDRESS_SPACE_IO 936 ? pci_dev->bus->address_space_io 937 : pci_dev->bus->address_space_mem; 938 } 939 940 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num) 941 { 942 return pci_dev->io_regions[region_num].addr; 943 } 944 945 static pcibus_t pci_bar_address(PCIDevice *d, 946 int reg, uint8_t type, pcibus_t size) 947 { 948 pcibus_t new_addr, last_addr; 949 int bar = pci_bar(d, reg); 950 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND); 951 952 if (type & PCI_BASE_ADDRESS_SPACE_IO) { 953 if (!(cmd & PCI_COMMAND_IO)) { 954 return PCI_BAR_UNMAPPED; 955 } 956 new_addr = pci_get_long(d->config + bar) & ~(size - 1); 957 last_addr = new_addr + size - 1; 958 /* NOTE: we have only 64K ioports on PC */ 959 if (last_addr <= new_addr || new_addr == 0 || last_addr > UINT16_MAX) { 960 return PCI_BAR_UNMAPPED; 961 } 962 return new_addr; 963 } 964 965 if (!(cmd & PCI_COMMAND_MEMORY)) { 966 return PCI_BAR_UNMAPPED; 967 } 968 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 969 new_addr = pci_get_quad(d->config + bar); 970 } else { 971 new_addr = pci_get_long(d->config + bar); 972 } 973 /* the ROM slot has a specific enable bit */ 974 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) { 975 return PCI_BAR_UNMAPPED; 976 } 977 new_addr &= ~(size - 1); 978 last_addr = new_addr + size - 1; 979 /* NOTE: we do not support wrapping */ 980 /* XXX: as we cannot support really dynamic 981 mappings, we handle specific values as invalid 982 mappings. */ 983 if (last_addr <= new_addr || new_addr == 0 || 984 last_addr == PCI_BAR_UNMAPPED) { 985 return PCI_BAR_UNMAPPED; 986 } 987 988 /* Now pcibus_t is 64bit. 989 * Check if 32 bit BAR wraps around explicitly. 990 * Without this, PC ide doesn't work well. 991 * TODO: remove this work around. 992 */ 993 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) { 994 return PCI_BAR_UNMAPPED; 995 } 996 997 /* 998 * OS is allowed to set BAR beyond its addressable 999 * bits. For example, 32 bit OS can set 64bit bar 1000 * to >4G. Check it. TODO: we might need to support 1001 * it in the future for e.g. PAE. 1002 */ 1003 if (last_addr >= HWADDR_MAX) { 1004 return PCI_BAR_UNMAPPED; 1005 } 1006 1007 return new_addr; 1008 } 1009 1010 static void pci_update_mappings(PCIDevice *d) 1011 { 1012 PCIIORegion *r; 1013 int i; 1014 pcibus_t new_addr; 1015 1016 for(i = 0; i < PCI_NUM_REGIONS; i++) { 1017 r = &d->io_regions[i]; 1018 1019 /* this region isn't registered */ 1020 if (!r->size) 1021 continue; 1022 1023 new_addr = pci_bar_address(d, i, r->type, r->size); 1024 1025 /* This bar isn't changed */ 1026 if (new_addr == r->addr) 1027 continue; 1028 1029 /* now do the real mapping */ 1030 if (r->addr != PCI_BAR_UNMAPPED) { 1031 memory_region_del_subregion(r->address_space, r->memory); 1032 } 1033 r->addr = new_addr; 1034 if (r->addr != PCI_BAR_UNMAPPED) { 1035 memory_region_add_subregion_overlap(r->address_space, 1036 r->addr, r->memory, 1); 1037 } 1038 } 1039 } 1040 1041 static inline int pci_irq_disabled(PCIDevice *d) 1042 { 1043 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE; 1044 } 1045 1046 /* Called after interrupt disabled field update in config space, 1047 * assert/deassert interrupts if necessary. 1048 * Gets original interrupt disable bit value (before update). */ 1049 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled) 1050 { 1051 int i, disabled = pci_irq_disabled(d); 1052 if (disabled == was_irq_disabled) 1053 return; 1054 for (i = 0; i < PCI_NUM_PINS; ++i) { 1055 int state = pci_irq_state(d, i); 1056 pci_change_irq_level(d, i, disabled ? -state : state); 1057 } 1058 } 1059 1060 uint32_t pci_default_read_config(PCIDevice *d, 1061 uint32_t address, int len) 1062 { 1063 uint32_t val = 0; 1064 1065 memcpy(&val, d->config + address, len); 1066 return le32_to_cpu(val); 1067 } 1068 1069 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l) 1070 { 1071 int i, was_irq_disabled = pci_irq_disabled(d); 1072 1073 for (i = 0; i < l; val >>= 8, ++i) { 1074 uint8_t wmask = d->wmask[addr + i]; 1075 uint8_t w1cmask = d->w1cmask[addr + i]; 1076 assert(!(wmask & w1cmask)); 1077 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask); 1078 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */ 1079 } 1080 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) || 1081 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) || 1082 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) || 1083 range_covers_byte(addr, l, PCI_COMMAND)) 1084 pci_update_mappings(d); 1085 1086 if (range_covers_byte(addr, l, PCI_COMMAND)) { 1087 pci_update_irq_disabled(d, was_irq_disabled); 1088 memory_region_set_enabled(&d->bus_master_enable_region, 1089 pci_get_word(d->config + PCI_COMMAND) 1090 & PCI_COMMAND_MASTER); 1091 } 1092 1093 msi_write_config(d, addr, val, l); 1094 msix_write_config(d, addr, val, l); 1095 } 1096 1097 /***********************************************************/ 1098 /* generic PCI irq support */ 1099 1100 /* 0 <= irq_num <= 3. level must be 0 or 1 */ 1101 static void pci_set_irq(void *opaque, int irq_num, int level) 1102 { 1103 PCIDevice *pci_dev = opaque; 1104 int change; 1105 1106 change = level - pci_irq_state(pci_dev, irq_num); 1107 if (!change) 1108 return; 1109 1110 pci_set_irq_state(pci_dev, irq_num, level); 1111 pci_update_irq_status(pci_dev); 1112 if (pci_irq_disabled(pci_dev)) 1113 return; 1114 pci_change_irq_level(pci_dev, irq_num, change); 1115 } 1116 1117 /* Special hooks used by device assignment */ 1118 void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq) 1119 { 1120 assert(!bus->parent_dev); 1121 bus->route_intx_to_irq = route_intx_to_irq; 1122 } 1123 1124 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin) 1125 { 1126 PCIBus *bus; 1127 1128 do { 1129 bus = dev->bus; 1130 pin = bus->map_irq(dev, pin); 1131 dev = bus->parent_dev; 1132 } while (dev); 1133 1134 if (!bus->route_intx_to_irq) { 1135 error_report("PCI: Bug - unimplemented PCI INTx routing (%s)", 1136 object_get_typename(OBJECT(bus->qbus.parent))); 1137 return (PCIINTxRoute) { PCI_INTX_DISABLED, -1 }; 1138 } 1139 1140 return bus->route_intx_to_irq(bus->irq_opaque, pin); 1141 } 1142 1143 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new) 1144 { 1145 return old->mode != new->mode || old->irq != new->irq; 1146 } 1147 1148 void pci_bus_fire_intx_routing_notifier(PCIBus *bus) 1149 { 1150 PCIDevice *dev; 1151 PCIBus *sec; 1152 int i; 1153 1154 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 1155 dev = bus->devices[i]; 1156 if (dev && dev->intx_routing_notifier) { 1157 dev->intx_routing_notifier(dev); 1158 } 1159 QLIST_FOREACH(sec, &bus->child, sibling) { 1160 pci_bus_fire_intx_routing_notifier(sec); 1161 } 1162 } 1163 } 1164 1165 void pci_device_set_intx_routing_notifier(PCIDevice *dev, 1166 PCIINTxRoutingNotifier notifier) 1167 { 1168 dev->intx_routing_notifier = notifier; 1169 } 1170 1171 /* 1172 * PCI-to-PCI bridge specification 1173 * 9.1: Interrupt routing. Table 9-1 1174 * 1175 * the PCI Express Base Specification, Revision 2.1 1176 * 2.2.8.1: INTx interrutp signaling - Rules 1177 * the Implementation Note 1178 * Table 2-20 1179 */ 1180 /* 1181 * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD 1182 * 0-origin unlike PCI interrupt pin register. 1183 */ 1184 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin) 1185 { 1186 return (pin + PCI_SLOT(pci_dev->devfn)) % PCI_NUM_PINS; 1187 } 1188 1189 /***********************************************************/ 1190 /* monitor info on PCI */ 1191 1192 typedef struct { 1193 uint16_t class; 1194 const char *desc; 1195 const char *fw_name; 1196 uint16_t fw_ign_bits; 1197 } pci_class_desc; 1198 1199 static const pci_class_desc pci_class_descriptions[] = 1200 { 1201 { 0x0001, "VGA controller", "display"}, 1202 { 0x0100, "SCSI controller", "scsi"}, 1203 { 0x0101, "IDE controller", "ide"}, 1204 { 0x0102, "Floppy controller", "fdc"}, 1205 { 0x0103, "IPI controller", "ipi"}, 1206 { 0x0104, "RAID controller", "raid"}, 1207 { 0x0106, "SATA controller"}, 1208 { 0x0107, "SAS controller"}, 1209 { 0x0180, "Storage controller"}, 1210 { 0x0200, "Ethernet controller", "ethernet"}, 1211 { 0x0201, "Token Ring controller", "token-ring"}, 1212 { 0x0202, "FDDI controller", "fddi"}, 1213 { 0x0203, "ATM controller", "atm"}, 1214 { 0x0280, "Network controller"}, 1215 { 0x0300, "VGA controller", "display", 0x00ff}, 1216 { 0x0301, "XGA controller"}, 1217 { 0x0302, "3D controller"}, 1218 { 0x0380, "Display controller"}, 1219 { 0x0400, "Video controller", "video"}, 1220 { 0x0401, "Audio controller", "sound"}, 1221 { 0x0402, "Phone"}, 1222 { 0x0403, "Audio controller", "sound"}, 1223 { 0x0480, "Multimedia controller"}, 1224 { 0x0500, "RAM controller", "memory"}, 1225 { 0x0501, "Flash controller", "flash"}, 1226 { 0x0580, "Memory controller"}, 1227 { 0x0600, "Host bridge", "host"}, 1228 { 0x0601, "ISA bridge", "isa"}, 1229 { 0x0602, "EISA bridge", "eisa"}, 1230 { 0x0603, "MC bridge", "mca"}, 1231 { 0x0604, "PCI bridge", "pci"}, 1232 { 0x0605, "PCMCIA bridge", "pcmcia"}, 1233 { 0x0606, "NUBUS bridge", "nubus"}, 1234 { 0x0607, "CARDBUS bridge", "cardbus"}, 1235 { 0x0608, "RACEWAY bridge"}, 1236 { 0x0680, "Bridge"}, 1237 { 0x0700, "Serial port", "serial"}, 1238 { 0x0701, "Parallel port", "parallel"}, 1239 { 0x0800, "Interrupt controller", "interrupt-controller"}, 1240 { 0x0801, "DMA controller", "dma-controller"}, 1241 { 0x0802, "Timer", "timer"}, 1242 { 0x0803, "RTC", "rtc"}, 1243 { 0x0900, "Keyboard", "keyboard"}, 1244 { 0x0901, "Pen", "pen"}, 1245 { 0x0902, "Mouse", "mouse"}, 1246 { 0x0A00, "Dock station", "dock", 0x00ff}, 1247 { 0x0B00, "i386 cpu", "cpu", 0x00ff}, 1248 { 0x0c00, "Fireware contorller", "fireware"}, 1249 { 0x0c01, "Access bus controller", "access-bus"}, 1250 { 0x0c02, "SSA controller", "ssa"}, 1251 { 0x0c03, "USB controller", "usb"}, 1252 { 0x0c04, "Fibre channel controller", "fibre-channel"}, 1253 { 0x0c05, "SMBus"}, 1254 { 0, NULL} 1255 }; 1256 1257 static void pci_for_each_device_under_bus(PCIBus *bus, 1258 void (*fn)(PCIBus *b, PCIDevice *d, 1259 void *opaque), 1260 void *opaque) 1261 { 1262 PCIDevice *d; 1263 int devfn; 1264 1265 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1266 d = bus->devices[devfn]; 1267 if (d) { 1268 fn(bus, d, opaque); 1269 } 1270 } 1271 } 1272 1273 void pci_for_each_device(PCIBus *bus, int bus_num, 1274 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque), 1275 void *opaque) 1276 { 1277 bus = pci_find_bus_nr(bus, bus_num); 1278 1279 if (bus) { 1280 pci_for_each_device_under_bus(bus, fn, opaque); 1281 } 1282 } 1283 1284 static const pci_class_desc *get_class_desc(int class) 1285 { 1286 const pci_class_desc *desc; 1287 1288 desc = pci_class_descriptions; 1289 while (desc->desc && class != desc->class) { 1290 desc++; 1291 } 1292 1293 return desc; 1294 } 1295 1296 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num); 1297 1298 static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev) 1299 { 1300 PciMemoryRegionList *head = NULL, *cur_item = NULL; 1301 int i; 1302 1303 for (i = 0; i < PCI_NUM_REGIONS; i++) { 1304 const PCIIORegion *r = &dev->io_regions[i]; 1305 PciMemoryRegionList *region; 1306 1307 if (!r->size) { 1308 continue; 1309 } 1310 1311 region = g_malloc0(sizeof(*region)); 1312 region->value = g_malloc0(sizeof(*region->value)); 1313 1314 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { 1315 region->value->type = g_strdup("io"); 1316 } else { 1317 region->value->type = g_strdup("memory"); 1318 region->value->has_prefetch = true; 1319 region->value->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH); 1320 region->value->has_mem_type_64 = true; 1321 region->value->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64); 1322 } 1323 1324 region->value->bar = i; 1325 region->value->address = r->addr; 1326 region->value->size = r->size; 1327 1328 /* XXX: waiting for the qapi to support GSList */ 1329 if (!cur_item) { 1330 head = cur_item = region; 1331 } else { 1332 cur_item->next = region; 1333 cur_item = region; 1334 } 1335 } 1336 1337 return head; 1338 } 1339 1340 static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus, 1341 int bus_num) 1342 { 1343 PciBridgeInfo *info; 1344 1345 info = g_malloc0(sizeof(*info)); 1346 1347 info->bus.number = dev->config[PCI_PRIMARY_BUS]; 1348 info->bus.secondary = dev->config[PCI_SECONDARY_BUS]; 1349 info->bus.subordinate = dev->config[PCI_SUBORDINATE_BUS]; 1350 1351 info->bus.io_range = g_malloc0(sizeof(*info->bus.io_range)); 1352 info->bus.io_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO); 1353 info->bus.io_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO); 1354 1355 info->bus.memory_range = g_malloc0(sizeof(*info->bus.memory_range)); 1356 info->bus.memory_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 1357 info->bus.memory_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 1358 1359 info->bus.prefetchable_range = g_malloc0(sizeof(*info->bus.prefetchable_range)); 1360 info->bus.prefetchable_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 1361 info->bus.prefetchable_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 1362 1363 if (dev->config[PCI_SECONDARY_BUS] != 0) { 1364 PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]); 1365 if (child_bus) { 1366 info->has_devices = true; 1367 info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]); 1368 } 1369 } 1370 1371 return info; 1372 } 1373 1374 static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus, 1375 int bus_num) 1376 { 1377 const pci_class_desc *desc; 1378 PciDeviceInfo *info; 1379 uint8_t type; 1380 int class; 1381 1382 info = g_malloc0(sizeof(*info)); 1383 info->bus = bus_num; 1384 info->slot = PCI_SLOT(dev->devfn); 1385 info->function = PCI_FUNC(dev->devfn); 1386 1387 class = pci_get_word(dev->config + PCI_CLASS_DEVICE); 1388 info->class_info.class = class; 1389 desc = get_class_desc(class); 1390 if (desc->desc) { 1391 info->class_info.has_desc = true; 1392 info->class_info.desc = g_strdup(desc->desc); 1393 } 1394 1395 info->id.vendor = pci_get_word(dev->config + PCI_VENDOR_ID); 1396 info->id.device = pci_get_word(dev->config + PCI_DEVICE_ID); 1397 info->regions = qmp_query_pci_regions(dev); 1398 info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : ""); 1399 1400 if (dev->config[PCI_INTERRUPT_PIN] != 0) { 1401 info->has_irq = true; 1402 info->irq = dev->config[PCI_INTERRUPT_LINE]; 1403 } 1404 1405 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 1406 if (type == PCI_HEADER_TYPE_BRIDGE) { 1407 info->has_pci_bridge = true; 1408 info->pci_bridge = qmp_query_pci_bridge(dev, bus, bus_num); 1409 } 1410 1411 return info; 1412 } 1413 1414 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num) 1415 { 1416 PciDeviceInfoList *info, *head = NULL, *cur_item = NULL; 1417 PCIDevice *dev; 1418 int devfn; 1419 1420 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1421 dev = bus->devices[devfn]; 1422 if (dev) { 1423 info = g_malloc0(sizeof(*info)); 1424 info->value = qmp_query_pci_device(dev, bus, bus_num); 1425 1426 /* XXX: waiting for the qapi to support GSList */ 1427 if (!cur_item) { 1428 head = cur_item = info; 1429 } else { 1430 cur_item->next = info; 1431 cur_item = info; 1432 } 1433 } 1434 } 1435 1436 return head; 1437 } 1438 1439 static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num) 1440 { 1441 PciInfo *info = NULL; 1442 1443 bus = pci_find_bus_nr(bus, bus_num); 1444 if (bus) { 1445 info = g_malloc0(sizeof(*info)); 1446 info->bus = bus_num; 1447 info->devices = qmp_query_pci_devices(bus, bus_num); 1448 } 1449 1450 return info; 1451 } 1452 1453 PciInfoList *qmp_query_pci(Error **errp) 1454 { 1455 PciInfoList *info, *head = NULL, *cur_item = NULL; 1456 struct PCIHostBus *host; 1457 1458 QLIST_FOREACH(host, &host_buses, next) { 1459 info = g_malloc0(sizeof(*info)); 1460 info->value = qmp_query_pci_bus(host->bus, 0); 1461 1462 /* XXX: waiting for the qapi to support GSList */ 1463 if (!cur_item) { 1464 head = cur_item = info; 1465 } else { 1466 cur_item->next = info; 1467 cur_item = info; 1468 } 1469 } 1470 1471 return head; 1472 } 1473 1474 static const char * const pci_nic_models[] = { 1475 "ne2k_pci", 1476 "i82551", 1477 "i82557b", 1478 "i82559er", 1479 "rtl8139", 1480 "e1000", 1481 "pcnet", 1482 "virtio", 1483 NULL 1484 }; 1485 1486 static const char * const pci_nic_names[] = { 1487 "ne2k_pci", 1488 "i82551", 1489 "i82557b", 1490 "i82559er", 1491 "rtl8139", 1492 "e1000", 1493 "pcnet", 1494 "virtio-net-pci", 1495 NULL 1496 }; 1497 1498 /* Initialize a PCI NIC. */ 1499 /* FIXME callers should check for failure, but don't */ 1500 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model, 1501 const char *default_devaddr) 1502 { 1503 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr; 1504 PCIBus *bus; 1505 int devfn; 1506 PCIDevice *pci_dev; 1507 DeviceState *dev; 1508 int i; 1509 1510 i = qemu_find_nic_model(nd, pci_nic_models, default_model); 1511 if (i < 0) 1512 return NULL; 1513 1514 bus = pci_get_bus_devfn(&devfn, devaddr); 1515 if (!bus) { 1516 error_report("Invalid PCI device address %s for device %s", 1517 devaddr, pci_nic_names[i]); 1518 return NULL; 1519 } 1520 1521 pci_dev = pci_create(bus, devfn, pci_nic_names[i]); 1522 dev = &pci_dev->qdev; 1523 qdev_set_nic_properties(dev, nd); 1524 if (qdev_init(dev) < 0) 1525 return NULL; 1526 return pci_dev; 1527 } 1528 1529 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model, 1530 const char *default_devaddr) 1531 { 1532 PCIDevice *res; 1533 1534 if (qemu_show_nic_models(nd->model, pci_nic_models)) 1535 exit(0); 1536 1537 res = pci_nic_init(nd, default_model, default_devaddr); 1538 if (!res) 1539 exit(1); 1540 return res; 1541 } 1542 1543 PCIDevice *pci_vga_init(PCIBus *bus) 1544 { 1545 switch (vga_interface_type) { 1546 case VGA_CIRRUS: 1547 return pci_create_simple(bus, -1, "cirrus-vga"); 1548 case VGA_QXL: 1549 return pci_create_simple(bus, -1, "qxl-vga"); 1550 case VGA_STD: 1551 return pci_create_simple(bus, -1, "VGA"); 1552 case VGA_VMWARE: 1553 return pci_create_simple(bus, -1, "vmware-svga"); 1554 case VGA_NONE: 1555 default: /* Other non-PCI types. Checking for unsupported types is already 1556 done in vl.c. */ 1557 return NULL; 1558 } 1559 } 1560 1561 /* Whether a given bus number is in range of the secondary 1562 * bus of the given bridge device. */ 1563 static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num) 1564 { 1565 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) & 1566 PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ && 1567 dev->config[PCI_SECONDARY_BUS] < bus_num && 1568 bus_num <= dev->config[PCI_SUBORDINATE_BUS]; 1569 } 1570 1571 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num) 1572 { 1573 PCIBus *sec; 1574 1575 if (!bus) { 1576 return NULL; 1577 } 1578 1579 if (pci_bus_num(bus) == bus_num) { 1580 return bus; 1581 } 1582 1583 /* Consider all bus numbers in range for the host pci bridge. */ 1584 if (bus->parent_dev && 1585 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) { 1586 return NULL; 1587 } 1588 1589 /* try child bus */ 1590 for (; bus; bus = sec) { 1591 QLIST_FOREACH(sec, &bus->child, sibling) { 1592 assert(sec->parent_dev); 1593 if (sec->parent_dev->config[PCI_SECONDARY_BUS] == bus_num) { 1594 return sec; 1595 } 1596 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) { 1597 break; 1598 } 1599 } 1600 } 1601 1602 return NULL; 1603 } 1604 1605 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn) 1606 { 1607 bus = pci_find_bus_nr(bus, bus_num); 1608 1609 if (!bus) 1610 return NULL; 1611 1612 return bus->devices[devfn]; 1613 } 1614 1615 static int pci_qdev_init(DeviceState *qdev) 1616 { 1617 PCIDevice *pci_dev = (PCIDevice *)qdev; 1618 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 1619 PCIBus *bus; 1620 int rc; 1621 bool is_default_rom; 1622 1623 /* initialize cap_present for pci_is_express() and pci_config_size() */ 1624 if (pc->is_express) { 1625 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; 1626 } 1627 1628 bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev)); 1629 pci_dev = do_pci_register_device(pci_dev, bus, 1630 object_get_typename(OBJECT(qdev)), 1631 pci_dev->devfn); 1632 if (pci_dev == NULL) 1633 return -1; 1634 if (qdev->hotplugged && pc->no_hotplug) { 1635 qerror_report(QERR_DEVICE_NO_HOTPLUG, object_get_typename(OBJECT(pci_dev))); 1636 do_pci_unregister_device(pci_dev); 1637 return -1; 1638 } 1639 if (pc->init) { 1640 rc = pc->init(pci_dev); 1641 if (rc != 0) { 1642 do_pci_unregister_device(pci_dev); 1643 return rc; 1644 } 1645 } 1646 1647 /* rom loading */ 1648 is_default_rom = false; 1649 if (pci_dev->romfile == NULL && pc->romfile != NULL) { 1650 pci_dev->romfile = g_strdup(pc->romfile); 1651 is_default_rom = true; 1652 } 1653 pci_add_option_rom(pci_dev, is_default_rom); 1654 1655 if (bus->hotplug) { 1656 /* Let buses differentiate between hotplug and when device is 1657 * enabled during qemu machine creation. */ 1658 rc = bus->hotplug(bus->hotplug_qdev, pci_dev, 1659 qdev->hotplugged ? PCI_HOTPLUG_ENABLED: 1660 PCI_COLDPLUG_ENABLED); 1661 if (rc != 0) { 1662 int r = pci_unregister_device(&pci_dev->qdev); 1663 assert(!r); 1664 return rc; 1665 } 1666 } 1667 return 0; 1668 } 1669 1670 static int pci_unplug_device(DeviceState *qdev) 1671 { 1672 PCIDevice *dev = PCI_DEVICE(qdev); 1673 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 1674 1675 if (pc->no_hotplug) { 1676 qerror_report(QERR_DEVICE_NO_HOTPLUG, object_get_typename(OBJECT(dev))); 1677 return -1; 1678 } 1679 return dev->bus->hotplug(dev->bus->hotplug_qdev, dev, 1680 PCI_HOTPLUG_DISABLED); 1681 } 1682 1683 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction, 1684 const char *name) 1685 { 1686 DeviceState *dev; 1687 1688 dev = qdev_create(&bus->qbus, name); 1689 qdev_prop_set_int32(dev, "addr", devfn); 1690 qdev_prop_set_bit(dev, "multifunction", multifunction); 1691 return PCI_DEVICE(dev); 1692 } 1693 1694 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, 1695 bool multifunction, 1696 const char *name) 1697 { 1698 PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name); 1699 qdev_init_nofail(&dev->qdev); 1700 return dev; 1701 } 1702 1703 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name) 1704 { 1705 return pci_create_multifunction(bus, devfn, false, name); 1706 } 1707 1708 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name) 1709 { 1710 return pci_create_simple_multifunction(bus, devfn, false, name); 1711 } 1712 1713 static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size) 1714 { 1715 int offset = PCI_CONFIG_HEADER_SIZE; 1716 int i; 1717 for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) { 1718 if (pdev->used[i]) 1719 offset = i + 1; 1720 else if (i - offset + 1 == size) 1721 return offset; 1722 } 1723 return 0; 1724 } 1725 1726 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id, 1727 uint8_t *prev_p) 1728 { 1729 uint8_t next, prev; 1730 1731 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST)) 1732 return 0; 1733 1734 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); 1735 prev = next + PCI_CAP_LIST_NEXT) 1736 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id) 1737 break; 1738 1739 if (prev_p) 1740 *prev_p = prev; 1741 return next; 1742 } 1743 1744 static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset) 1745 { 1746 uint8_t next, prev, found = 0; 1747 1748 if (!(pdev->used[offset])) { 1749 return 0; 1750 } 1751 1752 assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST); 1753 1754 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); 1755 prev = next + PCI_CAP_LIST_NEXT) { 1756 if (next <= offset && next > found) { 1757 found = next; 1758 } 1759 } 1760 return found; 1761 } 1762 1763 /* Patch the PCI vendor and device ids in a PCI rom image if necessary. 1764 This is needed for an option rom which is used for more than one device. */ 1765 static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size) 1766 { 1767 uint16_t vendor_id; 1768 uint16_t device_id; 1769 uint16_t rom_vendor_id; 1770 uint16_t rom_device_id; 1771 uint16_t rom_magic; 1772 uint16_t pcir_offset; 1773 uint8_t checksum; 1774 1775 /* Words in rom data are little endian (like in PCI configuration), 1776 so they can be read / written with pci_get_word / pci_set_word. */ 1777 1778 /* Only a valid rom will be patched. */ 1779 rom_magic = pci_get_word(ptr); 1780 if (rom_magic != 0xaa55) { 1781 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic); 1782 return; 1783 } 1784 pcir_offset = pci_get_word(ptr + 0x18); 1785 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) { 1786 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset); 1787 return; 1788 } 1789 1790 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID); 1791 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID); 1792 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4); 1793 rom_device_id = pci_get_word(ptr + pcir_offset + 6); 1794 1795 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile, 1796 vendor_id, device_id, rom_vendor_id, rom_device_id); 1797 1798 checksum = ptr[6]; 1799 1800 if (vendor_id != rom_vendor_id) { 1801 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */ 1802 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8); 1803 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8); 1804 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); 1805 ptr[6] = checksum; 1806 pci_set_word(ptr + pcir_offset + 4, vendor_id); 1807 } 1808 1809 if (device_id != rom_device_id) { 1810 /* Patch device id and checksum (at offset 6 for etherboot roms). */ 1811 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8); 1812 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8); 1813 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); 1814 ptr[6] = checksum; 1815 pci_set_word(ptr + pcir_offset + 6, device_id); 1816 } 1817 } 1818 1819 /* Add an option rom for the device */ 1820 static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom) 1821 { 1822 int size; 1823 char *path; 1824 void *ptr; 1825 char name[32]; 1826 const VMStateDescription *vmsd; 1827 1828 if (!pdev->romfile) 1829 return 0; 1830 if (strlen(pdev->romfile) == 0) 1831 return 0; 1832 1833 if (!pdev->rom_bar) { 1834 /* 1835 * Load rom via fw_cfg instead of creating a rom bar, 1836 * for 0.11 compatibility. 1837 */ 1838 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE); 1839 if (class == 0x0300) { 1840 rom_add_vga(pdev->romfile); 1841 } else { 1842 rom_add_option(pdev->romfile, -1); 1843 } 1844 return 0; 1845 } 1846 1847 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile); 1848 if (path == NULL) { 1849 path = g_strdup(pdev->romfile); 1850 } 1851 1852 size = get_image_size(path); 1853 if (size < 0) { 1854 error_report("%s: failed to find romfile \"%s\"", 1855 __FUNCTION__, pdev->romfile); 1856 g_free(path); 1857 return -1; 1858 } 1859 if (size & (size - 1)) { 1860 size = 1 << qemu_fls(size); 1861 } 1862 1863 vmsd = qdev_get_vmsd(DEVICE(pdev)); 1864 1865 if (vmsd) { 1866 snprintf(name, sizeof(name), "%s.rom", vmsd->name); 1867 } else { 1868 snprintf(name, sizeof(name), "%s.rom", object_get_typename(OBJECT(pdev))); 1869 } 1870 pdev->has_rom = true; 1871 memory_region_init_ram(&pdev->rom, name, size); 1872 vmstate_register_ram(&pdev->rom, &pdev->qdev); 1873 ptr = memory_region_get_ram_ptr(&pdev->rom); 1874 load_image(path, ptr); 1875 g_free(path); 1876 1877 if (is_default_rom) { 1878 /* Only the default rom images will be patched (if needed). */ 1879 pci_patch_ids(pdev, ptr, size); 1880 } 1881 1882 qemu_put_ram_ptr(ptr); 1883 1884 pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom); 1885 1886 return 0; 1887 } 1888 1889 static void pci_del_option_rom(PCIDevice *pdev) 1890 { 1891 if (!pdev->has_rom) 1892 return; 1893 1894 vmstate_unregister_ram(&pdev->rom, &pdev->qdev); 1895 memory_region_destroy(&pdev->rom); 1896 pdev->has_rom = false; 1897 } 1898 1899 /* 1900 * if !offset 1901 * Reserve space and add capability to the linked list in pci config space 1902 * 1903 * if offset = 0, 1904 * Find and reserve space and add capability to the linked list 1905 * in pci config space */ 1906 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, 1907 uint8_t offset, uint8_t size) 1908 { 1909 uint8_t *config; 1910 int i, overlapping_cap; 1911 1912 if (!offset) { 1913 offset = pci_find_space(pdev, size); 1914 if (!offset) { 1915 return -ENOSPC; 1916 } 1917 } else { 1918 /* Verify that capabilities don't overlap. Note: device assignment 1919 * depends on this check to verify that the device is not broken. 1920 * Should never trigger for emulated devices, but it's helpful 1921 * for debugging these. */ 1922 for (i = offset; i < offset + size; i++) { 1923 overlapping_cap = pci_find_capability_at_offset(pdev, i); 1924 if (overlapping_cap) { 1925 fprintf(stderr, "ERROR: %04x:%02x:%02x.%x " 1926 "Attempt to add PCI capability %x at offset " 1927 "%x overlaps existing capability %x at offset %x\n", 1928 pci_find_domain(pdev->bus), pci_bus_num(pdev->bus), 1929 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), 1930 cap_id, offset, overlapping_cap, i); 1931 return -EINVAL; 1932 } 1933 } 1934 } 1935 1936 config = pdev->config + offset; 1937 config[PCI_CAP_LIST_ID] = cap_id; 1938 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST]; 1939 pdev->config[PCI_CAPABILITY_LIST] = offset; 1940 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST; 1941 memset(pdev->used + offset, 0xFF, QEMU_ALIGN_UP(size, 4)); 1942 /* Make capability read-only by default */ 1943 memset(pdev->wmask + offset, 0, size); 1944 /* Check capability by default */ 1945 memset(pdev->cmask + offset, 0xFF, size); 1946 return offset; 1947 } 1948 1949 /* Unlink capability from the pci config space. */ 1950 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size) 1951 { 1952 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev); 1953 if (!offset) 1954 return; 1955 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT]; 1956 /* Make capability writable again */ 1957 memset(pdev->wmask + offset, 0xff, size); 1958 memset(pdev->w1cmask + offset, 0, size); 1959 /* Clear cmask as device-specific registers can't be checked */ 1960 memset(pdev->cmask + offset, 0, size); 1961 memset(pdev->used + offset, 0, QEMU_ALIGN_UP(size, 4)); 1962 1963 if (!pdev->config[PCI_CAPABILITY_LIST]) 1964 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST; 1965 } 1966 1967 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id) 1968 { 1969 return pci_find_capability_list(pdev, cap_id, NULL); 1970 } 1971 1972 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent) 1973 { 1974 PCIDevice *d = (PCIDevice *)dev; 1975 const pci_class_desc *desc; 1976 char ctxt[64]; 1977 PCIIORegion *r; 1978 int i, class; 1979 1980 class = pci_get_word(d->config + PCI_CLASS_DEVICE); 1981 desc = pci_class_descriptions; 1982 while (desc->desc && class != desc->class) 1983 desc++; 1984 if (desc->desc) { 1985 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc); 1986 } else { 1987 snprintf(ctxt, sizeof(ctxt), "Class %04x", class); 1988 } 1989 1990 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, " 1991 "pci id %04x:%04x (sub %04x:%04x)\n", 1992 indent, "", ctxt, pci_bus_num(d->bus), 1993 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn), 1994 pci_get_word(d->config + PCI_VENDOR_ID), 1995 pci_get_word(d->config + PCI_DEVICE_ID), 1996 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID), 1997 pci_get_word(d->config + PCI_SUBSYSTEM_ID)); 1998 for (i = 0; i < PCI_NUM_REGIONS; i++) { 1999 r = &d->io_regions[i]; 2000 if (!r->size) 2001 continue; 2002 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS 2003 " [0x%"FMT_PCIBUS"]\n", 2004 indent, "", 2005 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem", 2006 r->addr, r->addr + r->size - 1); 2007 } 2008 } 2009 2010 static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len) 2011 { 2012 PCIDevice *d = (PCIDevice *)dev; 2013 const char *name = NULL; 2014 const pci_class_desc *desc = pci_class_descriptions; 2015 int class = pci_get_word(d->config + PCI_CLASS_DEVICE); 2016 2017 while (desc->desc && 2018 (class & ~desc->fw_ign_bits) != 2019 (desc->class & ~desc->fw_ign_bits)) { 2020 desc++; 2021 } 2022 2023 if (desc->desc) { 2024 name = desc->fw_name; 2025 } 2026 2027 if (name) { 2028 pstrcpy(buf, len, name); 2029 } else { 2030 snprintf(buf, len, "pci%04x,%04x", 2031 pci_get_word(d->config + PCI_VENDOR_ID), 2032 pci_get_word(d->config + PCI_DEVICE_ID)); 2033 } 2034 2035 return buf; 2036 } 2037 2038 static char *pcibus_get_fw_dev_path(DeviceState *dev) 2039 { 2040 PCIDevice *d = (PCIDevice *)dev; 2041 char path[50], name[33]; 2042 int off; 2043 2044 off = snprintf(path, sizeof(path), "%s@%x", 2045 pci_dev_fw_name(dev, name, sizeof name), 2046 PCI_SLOT(d->devfn)); 2047 if (PCI_FUNC(d->devfn)) 2048 snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn)); 2049 return g_strdup(path); 2050 } 2051 2052 static char *pcibus_get_dev_path(DeviceState *dev) 2053 { 2054 PCIDevice *d = container_of(dev, PCIDevice, qdev); 2055 PCIDevice *t; 2056 int slot_depth; 2057 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function. 2058 * 00 is added here to make this format compatible with 2059 * domain:Bus:Slot.Func for systems without nested PCI bridges. 2060 * Slot.Function list specifies the slot and function numbers for all 2061 * devices on the path from root to the specific device. */ 2062 char domain[] = "DDDD:00"; 2063 char slot[] = ":SS.F"; 2064 int domain_len = sizeof domain - 1 /* For '\0' */; 2065 int slot_len = sizeof slot - 1 /* For '\0' */; 2066 int path_len; 2067 char *path, *p; 2068 int s; 2069 2070 /* Calculate # of slots on path between device and root. */; 2071 slot_depth = 0; 2072 for (t = d; t; t = t->bus->parent_dev) { 2073 ++slot_depth; 2074 } 2075 2076 path_len = domain_len + slot_len * slot_depth; 2077 2078 /* Allocate memory, fill in the terminating null byte. */ 2079 path = g_malloc(path_len + 1 /* For '\0' */); 2080 path[path_len] = '\0'; 2081 2082 /* First field is the domain. */ 2083 s = snprintf(domain, sizeof domain, "%04x:00", pci_find_domain(d->bus)); 2084 assert(s == domain_len); 2085 memcpy(path, domain, domain_len); 2086 2087 /* Fill in slot numbers. We walk up from device to root, so need to print 2088 * them in the reverse order, last to first. */ 2089 p = path + path_len; 2090 for (t = d; t; t = t->bus->parent_dev) { 2091 p -= slot_len; 2092 s = snprintf(slot, sizeof slot, ":%02x.%x", 2093 PCI_SLOT(t->devfn), PCI_FUNC(t->devfn)); 2094 assert(s == slot_len); 2095 memcpy(p, slot, slot_len); 2096 } 2097 2098 return path; 2099 } 2100 2101 static int pci_qdev_find_recursive(PCIBus *bus, 2102 const char *id, PCIDevice **pdev) 2103 { 2104 DeviceState *qdev = qdev_find_recursive(&bus->qbus, id); 2105 if (!qdev) { 2106 return -ENODEV; 2107 } 2108 2109 /* roughly check if given qdev is pci device */ 2110 if (object_dynamic_cast(OBJECT(qdev), TYPE_PCI_DEVICE)) { 2111 *pdev = PCI_DEVICE(qdev); 2112 return 0; 2113 } 2114 return -EINVAL; 2115 } 2116 2117 int pci_qdev_find_device(const char *id, PCIDevice **pdev) 2118 { 2119 struct PCIHostBus *host; 2120 int rc = -ENODEV; 2121 2122 QLIST_FOREACH(host, &host_buses, next) { 2123 int tmp = pci_qdev_find_recursive(host->bus, id, pdev); 2124 if (!tmp) { 2125 rc = 0; 2126 break; 2127 } 2128 if (tmp != -ENODEV) { 2129 rc = tmp; 2130 } 2131 } 2132 2133 return rc; 2134 } 2135 2136 MemoryRegion *pci_address_space(PCIDevice *dev) 2137 { 2138 return dev->bus->address_space_mem; 2139 } 2140 2141 MemoryRegion *pci_address_space_io(PCIDevice *dev) 2142 { 2143 return dev->bus->address_space_io; 2144 } 2145 2146 static void pci_device_class_init(ObjectClass *klass, void *data) 2147 { 2148 DeviceClass *k = DEVICE_CLASS(klass); 2149 k->init = pci_qdev_init; 2150 k->unplug = pci_unplug_device; 2151 k->exit = pci_unregister_device; 2152 k->bus_type = TYPE_PCI_BUS; 2153 k->props = pci_props; 2154 } 2155 2156 void pci_setup_iommu(PCIBus *bus, PCIDMAContextFunc fn, void *opaque) 2157 { 2158 bus->dma_context_fn = fn; 2159 bus->dma_context_opaque = opaque; 2160 } 2161 2162 static const TypeInfo pci_device_type_info = { 2163 .name = TYPE_PCI_DEVICE, 2164 .parent = TYPE_DEVICE, 2165 .instance_size = sizeof(PCIDevice), 2166 .abstract = true, 2167 .class_size = sizeof(PCIDeviceClass), 2168 .class_init = pci_device_class_init, 2169 }; 2170 2171 static void pci_register_types(void) 2172 { 2173 type_register_static(&pci_bus_info); 2174 type_register_static(&pci_device_type_info); 2175 } 2176 2177 type_init(pci_register_types) 2178