1 /* 2 * QEMU PCI bus manager 3 * 4 * Copyright (c) 2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "qemu/osdep.h" 25 #include "hw/hw.h" 26 #include "hw/pci/pci.h" 27 #include "hw/pci/pci_bridge.h" 28 #include "hw/pci/pci_bus.h" 29 #include "hw/pci/pci_host.h" 30 #include "monitor/monitor.h" 31 #include "net/net.h" 32 #include "sysemu/sysemu.h" 33 #include "hw/loader.h" 34 #include "qemu/error-report.h" 35 #include "qemu/range.h" 36 #include "qmp-commands.h" 37 #include "trace.h" 38 #include "hw/pci/msi.h" 39 #include "hw/pci/msix.h" 40 #include "exec/address-spaces.h" 41 #include "hw/hotplug.h" 42 #include "hw/boards.h" 43 #include "qemu/cutils.h" 44 45 //#define DEBUG_PCI 46 #ifdef DEBUG_PCI 47 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) 48 #else 49 # define PCI_DPRINTF(format, ...) do { } while (0) 50 #endif 51 52 bool pci_available = true; 53 54 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent); 55 static char *pcibus_get_dev_path(DeviceState *dev); 56 static char *pcibus_get_fw_dev_path(DeviceState *dev); 57 static void pcibus_reset(BusState *qbus); 58 59 static Property pci_props[] = { 60 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1), 61 DEFINE_PROP_STRING("romfile", PCIDevice, romfile), 62 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1), 63 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present, 64 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false), 65 DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present, 66 QEMU_PCI_CAP_SERR_BITNR, true), 67 DEFINE_PROP_BIT("x-pcie-lnksta-dllla", PCIDevice, cap_present, 68 QEMU_PCIE_LNKSTA_DLLLA_BITNR, true), 69 DEFINE_PROP_BIT("x-pcie-extcap-init", PCIDevice, cap_present, 70 QEMU_PCIE_EXTCAP_INIT_BITNR, true), 71 DEFINE_PROP_END_OF_LIST() 72 }; 73 74 static const VMStateDescription vmstate_pcibus = { 75 .name = "PCIBUS", 76 .version_id = 1, 77 .minimum_version_id = 1, 78 .fields = (VMStateField[]) { 79 VMSTATE_INT32_EQUAL(nirq, PCIBus, NULL), 80 VMSTATE_VARRAY_INT32(irq_count, PCIBus, 81 nirq, 0, vmstate_info_int32, 82 int32_t), 83 VMSTATE_END_OF_LIST() 84 } 85 }; 86 87 static void pci_init_bus_master(PCIDevice *pci_dev) 88 { 89 AddressSpace *dma_as = pci_device_iommu_address_space(pci_dev); 90 91 memory_region_init_alias(&pci_dev->bus_master_enable_region, 92 OBJECT(pci_dev), "bus master", 93 dma_as->root, 0, memory_region_size(dma_as->root)); 94 memory_region_set_enabled(&pci_dev->bus_master_enable_region, false); 95 memory_region_add_subregion(&pci_dev->bus_master_container_region, 0, 96 &pci_dev->bus_master_enable_region); 97 } 98 99 static void pcibus_machine_done(Notifier *notifier, void *data) 100 { 101 PCIBus *bus = container_of(notifier, PCIBus, machine_done); 102 int i; 103 104 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 105 if (bus->devices[i]) { 106 pci_init_bus_master(bus->devices[i]); 107 } 108 } 109 } 110 111 static void pci_bus_realize(BusState *qbus, Error **errp) 112 { 113 PCIBus *bus = PCI_BUS(qbus); 114 115 bus->machine_done.notify = pcibus_machine_done; 116 qemu_add_machine_init_done_notifier(&bus->machine_done); 117 118 vmstate_register(NULL, -1, &vmstate_pcibus, bus); 119 } 120 121 static void pci_bus_unrealize(BusState *qbus, Error **errp) 122 { 123 PCIBus *bus = PCI_BUS(qbus); 124 125 qemu_remove_machine_init_done_notifier(&bus->machine_done); 126 127 vmstate_unregister(NULL, &vmstate_pcibus, bus); 128 } 129 130 static bool pcibus_is_root(PCIBus *bus) 131 { 132 return !bus->parent_dev; 133 } 134 135 static int pcibus_num(PCIBus *bus) 136 { 137 if (pcibus_is_root(bus)) { 138 return 0; /* pci host bridge */ 139 } 140 return bus->parent_dev->config[PCI_SECONDARY_BUS]; 141 } 142 143 static uint16_t pcibus_numa_node(PCIBus *bus) 144 { 145 return NUMA_NODE_UNASSIGNED; 146 } 147 148 static void pci_bus_class_init(ObjectClass *klass, void *data) 149 { 150 BusClass *k = BUS_CLASS(klass); 151 PCIBusClass *pbc = PCI_BUS_CLASS(klass); 152 153 k->print_dev = pcibus_dev_print; 154 k->get_dev_path = pcibus_get_dev_path; 155 k->get_fw_dev_path = pcibus_get_fw_dev_path; 156 k->realize = pci_bus_realize; 157 k->unrealize = pci_bus_unrealize; 158 k->reset = pcibus_reset; 159 160 pbc->is_root = pcibus_is_root; 161 pbc->bus_num = pcibus_num; 162 pbc->numa_node = pcibus_numa_node; 163 } 164 165 static const TypeInfo pci_bus_info = { 166 .name = TYPE_PCI_BUS, 167 .parent = TYPE_BUS, 168 .instance_size = sizeof(PCIBus), 169 .class_size = sizeof(PCIBusClass), 170 .class_init = pci_bus_class_init, 171 }; 172 173 static const TypeInfo pcie_bus_info = { 174 .name = TYPE_PCIE_BUS, 175 .parent = TYPE_PCI_BUS, 176 }; 177 178 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num); 179 static void pci_update_mappings(PCIDevice *d); 180 static void pci_irq_handler(void *opaque, int irq_num, int level); 181 static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, Error **); 182 static void pci_del_option_rom(PCIDevice *pdev); 183 184 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET; 185 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU; 186 187 static QLIST_HEAD(, PCIHostState) pci_host_bridges; 188 189 int pci_bar(PCIDevice *d, int reg) 190 { 191 uint8_t type; 192 193 if (reg != PCI_ROM_SLOT) 194 return PCI_BASE_ADDRESS_0 + reg * 4; 195 196 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 197 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS; 198 } 199 200 static inline int pci_irq_state(PCIDevice *d, int irq_num) 201 { 202 return (d->irq_state >> irq_num) & 0x1; 203 } 204 205 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level) 206 { 207 d->irq_state &= ~(0x1 << irq_num); 208 d->irq_state |= level << irq_num; 209 } 210 211 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change) 212 { 213 PCIBus *bus; 214 for (;;) { 215 bus = pci_dev->bus; 216 irq_num = bus->map_irq(pci_dev, irq_num); 217 if (bus->set_irq) 218 break; 219 pci_dev = bus->parent_dev; 220 } 221 bus->irq_count[irq_num] += change; 222 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0); 223 } 224 225 int pci_bus_get_irq_level(PCIBus *bus, int irq_num) 226 { 227 assert(irq_num >= 0); 228 assert(irq_num < bus->nirq); 229 return !!bus->irq_count[irq_num]; 230 } 231 232 /* Update interrupt status bit in config space on interrupt 233 * state change. */ 234 static void pci_update_irq_status(PCIDevice *dev) 235 { 236 if (dev->irq_state) { 237 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT; 238 } else { 239 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; 240 } 241 } 242 243 void pci_device_deassert_intx(PCIDevice *dev) 244 { 245 int i; 246 for (i = 0; i < PCI_NUM_PINS; ++i) { 247 pci_irq_handler(dev, i, 0); 248 } 249 } 250 251 static void pci_do_device_reset(PCIDevice *dev) 252 { 253 int r; 254 255 pci_device_deassert_intx(dev); 256 assert(dev->irq_state == 0); 257 258 /* Clear all writable bits */ 259 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND, 260 pci_get_word(dev->wmask + PCI_COMMAND) | 261 pci_get_word(dev->w1cmask + PCI_COMMAND)); 262 pci_word_test_and_clear_mask(dev->config + PCI_STATUS, 263 pci_get_word(dev->wmask + PCI_STATUS) | 264 pci_get_word(dev->w1cmask + PCI_STATUS)); 265 dev->config[PCI_CACHE_LINE_SIZE] = 0x0; 266 dev->config[PCI_INTERRUPT_LINE] = 0x0; 267 for (r = 0; r < PCI_NUM_REGIONS; ++r) { 268 PCIIORegion *region = &dev->io_regions[r]; 269 if (!region->size) { 270 continue; 271 } 272 273 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) && 274 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 275 pci_set_quad(dev->config + pci_bar(dev, r), region->type); 276 } else { 277 pci_set_long(dev->config + pci_bar(dev, r), region->type); 278 } 279 } 280 pci_update_mappings(dev); 281 282 msi_reset(dev); 283 msix_reset(dev); 284 } 285 286 /* 287 * This function is called on #RST and FLR. 288 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set 289 */ 290 void pci_device_reset(PCIDevice *dev) 291 { 292 qdev_reset_all(&dev->qdev); 293 pci_do_device_reset(dev); 294 } 295 296 /* 297 * Trigger pci bus reset under a given bus. 298 * Called via qbus_reset_all on RST# assert, after the devices 299 * have been reset qdev_reset_all-ed already. 300 */ 301 static void pcibus_reset(BusState *qbus) 302 { 303 PCIBus *bus = DO_UPCAST(PCIBus, qbus, qbus); 304 int i; 305 306 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 307 if (bus->devices[i]) { 308 pci_do_device_reset(bus->devices[i]); 309 } 310 } 311 312 for (i = 0; i < bus->nirq; i++) { 313 assert(bus->irq_count[i] == 0); 314 } 315 } 316 317 static void pci_host_bus_register(DeviceState *host) 318 { 319 PCIHostState *host_bridge = PCI_HOST_BRIDGE(host); 320 321 QLIST_INSERT_HEAD(&pci_host_bridges, host_bridge, next); 322 } 323 324 PCIBus *pci_find_primary_bus(void) 325 { 326 PCIBus *primary_bus = NULL; 327 PCIHostState *host; 328 329 QLIST_FOREACH(host, &pci_host_bridges, next) { 330 if (primary_bus) { 331 /* We have multiple root buses, refuse to select a primary */ 332 return NULL; 333 } 334 primary_bus = host->bus; 335 } 336 337 return primary_bus; 338 } 339 340 PCIBus *pci_device_root_bus(const PCIDevice *d) 341 { 342 PCIBus *bus = d->bus; 343 344 while (!pci_bus_is_root(bus)) { 345 d = bus->parent_dev; 346 assert(d != NULL); 347 348 bus = d->bus; 349 } 350 351 return bus; 352 } 353 354 const char *pci_root_bus_path(PCIDevice *dev) 355 { 356 PCIBus *rootbus = pci_device_root_bus(dev); 357 PCIHostState *host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent); 358 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_GET_CLASS(host_bridge); 359 360 assert(host_bridge->bus == rootbus); 361 362 if (hc->root_bus_path) { 363 return (*hc->root_bus_path)(host_bridge, rootbus); 364 } 365 366 return rootbus->qbus.name; 367 } 368 369 static void pci_bus_init(PCIBus *bus, DeviceState *parent, 370 MemoryRegion *address_space_mem, 371 MemoryRegion *address_space_io, 372 uint8_t devfn_min) 373 { 374 assert(PCI_FUNC(devfn_min) == 0); 375 bus->devfn_min = devfn_min; 376 bus->address_space_mem = address_space_mem; 377 bus->address_space_io = address_space_io; 378 379 /* host bridge */ 380 QLIST_INIT(&bus->child); 381 382 pci_host_bus_register(parent); 383 } 384 385 bool pci_bus_is_express(PCIBus *bus) 386 { 387 return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS); 388 } 389 390 bool pci_bus_is_root(PCIBus *bus) 391 { 392 return PCI_BUS_GET_CLASS(bus)->is_root(bus); 393 } 394 395 void pci_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent, 396 const char *name, 397 MemoryRegion *address_space_mem, 398 MemoryRegion *address_space_io, 399 uint8_t devfn_min, const char *typename) 400 { 401 qbus_create_inplace(bus, bus_size, typename, parent, name); 402 pci_bus_init(bus, parent, address_space_mem, address_space_io, devfn_min); 403 } 404 405 PCIBus *pci_bus_new(DeviceState *parent, const char *name, 406 MemoryRegion *address_space_mem, 407 MemoryRegion *address_space_io, 408 uint8_t devfn_min, const char *typename) 409 { 410 PCIBus *bus; 411 412 bus = PCI_BUS(qbus_create(typename, parent, name)); 413 pci_bus_init(bus, parent, address_space_mem, address_space_io, devfn_min); 414 return bus; 415 } 416 417 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 418 void *irq_opaque, int nirq) 419 { 420 bus->set_irq = set_irq; 421 bus->map_irq = map_irq; 422 bus->irq_opaque = irq_opaque; 423 bus->nirq = nirq; 424 bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0])); 425 } 426 427 PCIBus *pci_register_bus(DeviceState *parent, const char *name, 428 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 429 void *irq_opaque, 430 MemoryRegion *address_space_mem, 431 MemoryRegion *address_space_io, 432 uint8_t devfn_min, int nirq, const char *typename) 433 { 434 PCIBus *bus; 435 436 bus = pci_bus_new(parent, name, address_space_mem, 437 address_space_io, devfn_min, typename); 438 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq); 439 return bus; 440 } 441 442 int pci_bus_num(PCIBus *s) 443 { 444 return PCI_BUS_GET_CLASS(s)->bus_num(s); 445 } 446 447 int pci_bus_numa_node(PCIBus *bus) 448 { 449 return PCI_BUS_GET_CLASS(bus)->numa_node(bus); 450 } 451 452 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size, 453 VMStateField *field) 454 { 455 PCIDevice *s = container_of(pv, PCIDevice, config); 456 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(s); 457 uint8_t *config; 458 int i; 459 460 assert(size == pci_config_size(s)); 461 config = g_malloc(size); 462 463 qemu_get_buffer(f, config, size); 464 for (i = 0; i < size; ++i) { 465 if ((config[i] ^ s->config[i]) & 466 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) { 467 error_report("%s: Bad config data: i=0x%x read: %x device: %x " 468 "cmask: %x wmask: %x w1cmask:%x", __func__, 469 i, config[i], s->config[i], 470 s->cmask[i], s->wmask[i], s->w1cmask[i]); 471 g_free(config); 472 return -EINVAL; 473 } 474 } 475 memcpy(s->config, config, size); 476 477 pci_update_mappings(s); 478 if (pc->is_bridge) { 479 PCIBridge *b = PCI_BRIDGE(s); 480 pci_bridge_update_mappings(b); 481 } 482 483 memory_region_set_enabled(&s->bus_master_enable_region, 484 pci_get_word(s->config + PCI_COMMAND) 485 & PCI_COMMAND_MASTER); 486 487 g_free(config); 488 return 0; 489 } 490 491 /* just put buffer */ 492 static int put_pci_config_device(QEMUFile *f, void *pv, size_t size, 493 VMStateField *field, QJSON *vmdesc) 494 { 495 const uint8_t **v = pv; 496 assert(size == pci_config_size(container_of(pv, PCIDevice, config))); 497 qemu_put_buffer(f, *v, size); 498 499 return 0; 500 } 501 502 static VMStateInfo vmstate_info_pci_config = { 503 .name = "pci config", 504 .get = get_pci_config_device, 505 .put = put_pci_config_device, 506 }; 507 508 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size, 509 VMStateField *field) 510 { 511 PCIDevice *s = container_of(pv, PCIDevice, irq_state); 512 uint32_t irq_state[PCI_NUM_PINS]; 513 int i; 514 for (i = 0; i < PCI_NUM_PINS; ++i) { 515 irq_state[i] = qemu_get_be32(f); 516 if (irq_state[i] != 0x1 && irq_state[i] != 0) { 517 fprintf(stderr, "irq state %d: must be 0 or 1.\n", 518 irq_state[i]); 519 return -EINVAL; 520 } 521 } 522 523 for (i = 0; i < PCI_NUM_PINS; ++i) { 524 pci_set_irq_state(s, i, irq_state[i]); 525 } 526 527 return 0; 528 } 529 530 static int put_pci_irq_state(QEMUFile *f, void *pv, size_t size, 531 VMStateField *field, QJSON *vmdesc) 532 { 533 int i; 534 PCIDevice *s = container_of(pv, PCIDevice, irq_state); 535 536 for (i = 0; i < PCI_NUM_PINS; ++i) { 537 qemu_put_be32(f, pci_irq_state(s, i)); 538 } 539 540 return 0; 541 } 542 543 static VMStateInfo vmstate_info_pci_irq_state = { 544 .name = "pci irq state", 545 .get = get_pci_irq_state, 546 .put = put_pci_irq_state, 547 }; 548 549 static bool migrate_is_pcie(void *opaque, int version_id) 550 { 551 return pci_is_express((PCIDevice *)opaque); 552 } 553 554 static bool migrate_is_not_pcie(void *opaque, int version_id) 555 { 556 return !pci_is_express((PCIDevice *)opaque); 557 } 558 559 const VMStateDescription vmstate_pci_device = { 560 .name = "PCIDevice", 561 .version_id = 2, 562 .minimum_version_id = 1, 563 .fields = (VMStateField[]) { 564 VMSTATE_INT32_POSITIVE_LE(version_id, PCIDevice), 565 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice, 566 migrate_is_not_pcie, 567 0, vmstate_info_pci_config, 568 PCI_CONFIG_SPACE_SIZE), 569 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice, 570 migrate_is_pcie, 571 0, vmstate_info_pci_config, 572 PCIE_CONFIG_SPACE_SIZE), 573 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2, 574 vmstate_info_pci_irq_state, 575 PCI_NUM_PINS * sizeof(int32_t)), 576 VMSTATE_END_OF_LIST() 577 } 578 }; 579 580 581 void pci_device_save(PCIDevice *s, QEMUFile *f) 582 { 583 /* Clear interrupt status bit: it is implicit 584 * in irq_state which we are saving. 585 * This makes us compatible with old devices 586 * which never set or clear this bit. */ 587 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; 588 vmstate_save_state(f, &vmstate_pci_device, s, NULL); 589 /* Restore the interrupt status bit. */ 590 pci_update_irq_status(s); 591 } 592 593 int pci_device_load(PCIDevice *s, QEMUFile *f) 594 { 595 int ret; 596 ret = vmstate_load_state(f, &vmstate_pci_device, s, s->version_id); 597 /* Restore the interrupt status bit. */ 598 pci_update_irq_status(s); 599 return ret; 600 } 601 602 static void pci_set_default_subsystem_id(PCIDevice *pci_dev) 603 { 604 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, 605 pci_default_sub_vendor_id); 606 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 607 pci_default_sub_device_id); 608 } 609 610 /* 611 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL 612 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error 613 */ 614 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, 615 unsigned int *slotp, unsigned int *funcp) 616 { 617 const char *p; 618 char *e; 619 unsigned long val; 620 unsigned long dom = 0, bus = 0; 621 unsigned int slot = 0; 622 unsigned int func = 0; 623 624 p = addr; 625 val = strtoul(p, &e, 16); 626 if (e == p) 627 return -1; 628 if (*e == ':') { 629 bus = val; 630 p = e + 1; 631 val = strtoul(p, &e, 16); 632 if (e == p) 633 return -1; 634 if (*e == ':') { 635 dom = bus; 636 bus = val; 637 p = e + 1; 638 val = strtoul(p, &e, 16); 639 if (e == p) 640 return -1; 641 } 642 } 643 644 slot = val; 645 646 if (funcp != NULL) { 647 if (*e != '.') 648 return -1; 649 650 p = e + 1; 651 val = strtoul(p, &e, 16); 652 if (e == p) 653 return -1; 654 655 func = val; 656 } 657 658 /* if funcp == NULL func is 0 */ 659 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7) 660 return -1; 661 662 if (*e) 663 return -1; 664 665 *domp = dom; 666 *busp = bus; 667 *slotp = slot; 668 if (funcp != NULL) 669 *funcp = func; 670 return 0; 671 } 672 673 static PCIBus *pci_get_bus_devfn(int *devfnp, PCIBus *root, 674 const char *devaddr) 675 { 676 int dom, bus; 677 unsigned slot; 678 679 if (!root) { 680 fprintf(stderr, "No primary PCI bus\n"); 681 return NULL; 682 } 683 684 assert(!root->parent_dev); 685 686 if (!devaddr) { 687 *devfnp = -1; 688 return pci_find_bus_nr(root, 0); 689 } 690 691 if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) { 692 return NULL; 693 } 694 695 if (dom != 0) { 696 fprintf(stderr, "No support for non-zero PCI domains\n"); 697 return NULL; 698 } 699 700 *devfnp = PCI_DEVFN(slot, 0); 701 return pci_find_bus_nr(root, bus); 702 } 703 704 static void pci_init_cmask(PCIDevice *dev) 705 { 706 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff); 707 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff); 708 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST; 709 dev->cmask[PCI_REVISION_ID] = 0xff; 710 dev->cmask[PCI_CLASS_PROG] = 0xff; 711 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff); 712 dev->cmask[PCI_HEADER_TYPE] = 0xff; 713 dev->cmask[PCI_CAPABILITY_LIST] = 0xff; 714 } 715 716 static void pci_init_wmask(PCIDevice *dev) 717 { 718 int config_size = pci_config_size(dev); 719 720 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff; 721 dev->wmask[PCI_INTERRUPT_LINE] = 0xff; 722 pci_set_word(dev->wmask + PCI_COMMAND, 723 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | 724 PCI_COMMAND_INTX_DISABLE); 725 if (dev->cap_present & QEMU_PCI_CAP_SERR) { 726 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR); 727 } 728 729 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff, 730 config_size - PCI_CONFIG_HEADER_SIZE); 731 } 732 733 static void pci_init_w1cmask(PCIDevice *dev) 734 { 735 /* 736 * Note: It's okay to set w1cmask even for readonly bits as 737 * long as their value is hardwired to 0. 738 */ 739 pci_set_word(dev->w1cmask + PCI_STATUS, 740 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT | 741 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT | 742 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY); 743 } 744 745 static void pci_init_mask_bridge(PCIDevice *d) 746 { 747 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and 748 PCI_SEC_LETENCY_TIMER */ 749 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4); 750 751 /* base and limit */ 752 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff; 753 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff; 754 pci_set_word(d->wmask + PCI_MEMORY_BASE, 755 PCI_MEMORY_RANGE_MASK & 0xffff); 756 pci_set_word(d->wmask + PCI_MEMORY_LIMIT, 757 PCI_MEMORY_RANGE_MASK & 0xffff); 758 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE, 759 PCI_PREF_RANGE_MASK & 0xffff); 760 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT, 761 PCI_PREF_RANGE_MASK & 0xffff); 762 763 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */ 764 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8); 765 766 /* Supported memory and i/o types */ 767 d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16; 768 d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16; 769 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE, 770 PCI_PREF_RANGE_TYPE_64); 771 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT, 772 PCI_PREF_RANGE_TYPE_64); 773 774 /* 775 * TODO: Bridges default to 10-bit VGA decoding but we currently only 776 * implement 16-bit decoding (no alias support). 777 */ 778 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 779 PCI_BRIDGE_CTL_PARITY | 780 PCI_BRIDGE_CTL_SERR | 781 PCI_BRIDGE_CTL_ISA | 782 PCI_BRIDGE_CTL_VGA | 783 PCI_BRIDGE_CTL_VGA_16BIT | 784 PCI_BRIDGE_CTL_MASTER_ABORT | 785 PCI_BRIDGE_CTL_BUS_RESET | 786 PCI_BRIDGE_CTL_FAST_BACK | 787 PCI_BRIDGE_CTL_DISCARD | 788 PCI_BRIDGE_CTL_SEC_DISCARD | 789 PCI_BRIDGE_CTL_DISCARD_SERR); 790 /* Below does not do anything as we never set this bit, put here for 791 * completeness. */ 792 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL, 793 PCI_BRIDGE_CTL_DISCARD_STATUS); 794 d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK; 795 d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK; 796 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE, 797 PCI_PREF_RANGE_TYPE_MASK); 798 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT, 799 PCI_PREF_RANGE_TYPE_MASK); 800 } 801 802 static void pci_init_multifunction(PCIBus *bus, PCIDevice *dev, Error **errp) 803 { 804 uint8_t slot = PCI_SLOT(dev->devfn); 805 uint8_t func; 806 807 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 808 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION; 809 } 810 811 /* 812 * multifunction bit is interpreted in two ways as follows. 813 * - all functions must set the bit to 1. 814 * Example: Intel X53 815 * - function 0 must set the bit, but the rest function (> 0) 816 * is allowed to leave the bit to 0. 817 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10, 818 * 819 * So OS (at least Linux) checks the bit of only function 0, 820 * and doesn't see the bit of function > 0. 821 * 822 * The below check allows both interpretation. 823 */ 824 if (PCI_FUNC(dev->devfn)) { 825 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)]; 826 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) { 827 /* function 0 should set multifunction bit */ 828 error_setg(errp, "PCI: single function device can't be populated " 829 "in function %x.%x", slot, PCI_FUNC(dev->devfn)); 830 return; 831 } 832 return; 833 } 834 835 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 836 return; 837 } 838 /* function 0 indicates single function, so function > 0 must be NULL */ 839 for (func = 1; func < PCI_FUNC_MAX; ++func) { 840 if (bus->devices[PCI_DEVFN(slot, func)]) { 841 error_setg(errp, "PCI: %x.0 indicates single function, " 842 "but %x.%x is already populated.", 843 slot, slot, func); 844 return; 845 } 846 } 847 } 848 849 static void pci_config_alloc(PCIDevice *pci_dev) 850 { 851 int config_size = pci_config_size(pci_dev); 852 853 pci_dev->config = g_malloc0(config_size); 854 pci_dev->cmask = g_malloc0(config_size); 855 pci_dev->wmask = g_malloc0(config_size); 856 pci_dev->w1cmask = g_malloc0(config_size); 857 pci_dev->used = g_malloc0(config_size); 858 } 859 860 static void pci_config_free(PCIDevice *pci_dev) 861 { 862 g_free(pci_dev->config); 863 g_free(pci_dev->cmask); 864 g_free(pci_dev->wmask); 865 g_free(pci_dev->w1cmask); 866 g_free(pci_dev->used); 867 } 868 869 static void do_pci_unregister_device(PCIDevice *pci_dev) 870 { 871 pci_dev->bus->devices[pci_dev->devfn] = NULL; 872 pci_config_free(pci_dev); 873 874 if (memory_region_is_mapped(&pci_dev->bus_master_enable_region)) { 875 memory_region_del_subregion(&pci_dev->bus_master_container_region, 876 &pci_dev->bus_master_enable_region); 877 } 878 address_space_destroy(&pci_dev->bus_master_as); 879 } 880 881 /* Extract PCIReqIDCache into BDF format */ 882 static uint16_t pci_req_id_cache_extract(PCIReqIDCache *cache) 883 { 884 uint8_t bus_n; 885 uint16_t result; 886 887 switch (cache->type) { 888 case PCI_REQ_ID_BDF: 889 result = pci_get_bdf(cache->dev); 890 break; 891 case PCI_REQ_ID_SECONDARY_BUS: 892 bus_n = pci_bus_num(cache->dev->bus); 893 result = PCI_BUILD_BDF(bus_n, 0); 894 break; 895 default: 896 error_printf("Invalid PCI requester ID cache type: %d\n", 897 cache->type); 898 exit(1); 899 break; 900 } 901 902 return result; 903 } 904 905 /* Parse bridges up to the root complex and return requester ID 906 * cache for specific device. For full PCIe topology, the cache 907 * result would be exactly the same as getting BDF of the device. 908 * However, several tricks are required when system mixed up with 909 * legacy PCI devices and PCIe-to-PCI bridges. 910 * 911 * Here we cache the proxy device (and type) not requester ID since 912 * bus number might change from time to time. 913 */ 914 static PCIReqIDCache pci_req_id_cache_get(PCIDevice *dev) 915 { 916 PCIDevice *parent; 917 PCIReqIDCache cache = { 918 .dev = dev, 919 .type = PCI_REQ_ID_BDF, 920 }; 921 922 while (!pci_bus_is_root(dev->bus)) { 923 /* We are under PCI/PCIe bridges */ 924 parent = dev->bus->parent_dev; 925 if (pci_is_express(parent)) { 926 if (pcie_cap_get_type(parent) == PCI_EXP_TYPE_PCI_BRIDGE) { 927 /* When we pass through PCIe-to-PCI/PCIX bridges, we 928 * override the requester ID using secondary bus 929 * number of parent bridge with zeroed devfn 930 * (pcie-to-pci bridge spec chap 2.3). */ 931 cache.type = PCI_REQ_ID_SECONDARY_BUS; 932 cache.dev = dev; 933 } 934 } else { 935 /* Legacy PCI, override requester ID with the bridge's 936 * BDF upstream. When the root complex connects to 937 * legacy PCI devices (including buses), it can only 938 * obtain requester ID info from directly attached 939 * devices. If devices are attached under bridges, only 940 * the requester ID of the bridge that is directly 941 * attached to the root complex can be recognized. */ 942 cache.type = PCI_REQ_ID_BDF; 943 cache.dev = parent; 944 } 945 dev = parent; 946 } 947 948 return cache; 949 } 950 951 uint16_t pci_requester_id(PCIDevice *dev) 952 { 953 return pci_req_id_cache_extract(&dev->requester_id_cache); 954 } 955 956 /* -1 for devfn means auto assign */ 957 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus, 958 const char *name, int devfn, 959 Error **errp) 960 { 961 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 962 PCIConfigReadFunc *config_read = pc->config_read; 963 PCIConfigWriteFunc *config_write = pc->config_write; 964 Error *local_err = NULL; 965 DeviceState *dev = DEVICE(pci_dev); 966 967 pci_dev->bus = bus; 968 /* Only pci bridges can be attached to extra PCI root buses */ 969 if (pci_bus_is_root(bus) && bus->parent_dev && !pc->is_bridge) { 970 error_setg(errp, 971 "PCI: Only PCI/PCIe bridges can be plugged into %s", 972 bus->parent_dev->name); 973 return NULL; 974 } 975 976 if (devfn < 0) { 977 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices); 978 devfn += PCI_FUNC_MAX) { 979 if (!bus->devices[devfn]) 980 goto found; 981 } 982 error_setg(errp, "PCI: no slot/function available for %s, all in use", 983 name); 984 return NULL; 985 found: ; 986 } else if (bus->devices[devfn]) { 987 error_setg(errp, "PCI: slot %d function %d not available for %s," 988 " in use by %s", 989 PCI_SLOT(devfn), PCI_FUNC(devfn), name, 990 bus->devices[devfn]->name); 991 return NULL; 992 } else if (dev->hotplugged && 993 pci_get_function_0(pci_dev)) { 994 error_setg(errp, "PCI: slot %d function 0 already ocuppied by %s," 995 " new func %s cannot be exposed to guest.", 996 PCI_SLOT(pci_get_function_0(pci_dev)->devfn), 997 pci_get_function_0(pci_dev)->name, 998 name); 999 1000 return NULL; 1001 } 1002 1003 pci_dev->devfn = devfn; 1004 pci_dev->requester_id_cache = pci_req_id_cache_get(pci_dev); 1005 1006 memory_region_init(&pci_dev->bus_master_container_region, OBJECT(pci_dev), 1007 "bus master container", UINT64_MAX); 1008 address_space_init(&pci_dev->bus_master_as, 1009 &pci_dev->bus_master_container_region, pci_dev->name); 1010 1011 if (qdev_hotplug) { 1012 pci_init_bus_master(pci_dev); 1013 } 1014 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name); 1015 pci_dev->irq_state = 0; 1016 pci_config_alloc(pci_dev); 1017 1018 pci_config_set_vendor_id(pci_dev->config, pc->vendor_id); 1019 pci_config_set_device_id(pci_dev->config, pc->device_id); 1020 pci_config_set_revision(pci_dev->config, pc->revision); 1021 pci_config_set_class(pci_dev->config, pc->class_id); 1022 1023 if (!pc->is_bridge) { 1024 if (pc->subsystem_vendor_id || pc->subsystem_id) { 1025 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, 1026 pc->subsystem_vendor_id); 1027 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 1028 pc->subsystem_id); 1029 } else { 1030 pci_set_default_subsystem_id(pci_dev); 1031 } 1032 } else { 1033 /* subsystem_vendor_id/subsystem_id are only for header type 0 */ 1034 assert(!pc->subsystem_vendor_id); 1035 assert(!pc->subsystem_id); 1036 } 1037 pci_init_cmask(pci_dev); 1038 pci_init_wmask(pci_dev); 1039 pci_init_w1cmask(pci_dev); 1040 if (pc->is_bridge) { 1041 pci_init_mask_bridge(pci_dev); 1042 } 1043 pci_init_multifunction(bus, pci_dev, &local_err); 1044 if (local_err) { 1045 error_propagate(errp, local_err); 1046 do_pci_unregister_device(pci_dev); 1047 return NULL; 1048 } 1049 1050 if (!config_read) 1051 config_read = pci_default_read_config; 1052 if (!config_write) 1053 config_write = pci_default_write_config; 1054 pci_dev->config_read = config_read; 1055 pci_dev->config_write = config_write; 1056 bus->devices[devfn] = pci_dev; 1057 pci_dev->version_id = 2; /* Current pci device vmstate version */ 1058 return pci_dev; 1059 } 1060 1061 static void pci_unregister_io_regions(PCIDevice *pci_dev) 1062 { 1063 PCIIORegion *r; 1064 int i; 1065 1066 for(i = 0; i < PCI_NUM_REGIONS; i++) { 1067 r = &pci_dev->io_regions[i]; 1068 if (!r->size || r->addr == PCI_BAR_UNMAPPED) 1069 continue; 1070 memory_region_del_subregion(r->address_space, r->memory); 1071 } 1072 1073 pci_unregister_vga(pci_dev); 1074 } 1075 1076 static void pci_qdev_unrealize(DeviceState *dev, Error **errp) 1077 { 1078 PCIDevice *pci_dev = PCI_DEVICE(dev); 1079 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 1080 1081 pci_unregister_io_regions(pci_dev); 1082 pci_del_option_rom(pci_dev); 1083 1084 if (pc->exit) { 1085 pc->exit(pci_dev); 1086 } 1087 1088 pci_device_deassert_intx(pci_dev); 1089 do_pci_unregister_device(pci_dev); 1090 } 1091 1092 void pci_register_bar(PCIDevice *pci_dev, int region_num, 1093 uint8_t type, MemoryRegion *memory) 1094 { 1095 PCIIORegion *r; 1096 uint32_t addr; /* offset in pci config space */ 1097 uint64_t wmask; 1098 pcibus_t size = memory_region_size(memory); 1099 1100 assert(region_num >= 0); 1101 assert(region_num < PCI_NUM_REGIONS); 1102 if (size & (size-1)) { 1103 fprintf(stderr, "ERROR: PCI region size must be pow2 " 1104 "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size); 1105 exit(1); 1106 } 1107 1108 r = &pci_dev->io_regions[region_num]; 1109 r->addr = PCI_BAR_UNMAPPED; 1110 r->size = size; 1111 r->type = type; 1112 r->memory = memory; 1113 r->address_space = type & PCI_BASE_ADDRESS_SPACE_IO 1114 ? pci_dev->bus->address_space_io 1115 : pci_dev->bus->address_space_mem; 1116 1117 wmask = ~(size - 1); 1118 if (region_num == PCI_ROM_SLOT) { 1119 /* ROM enable bit is writable */ 1120 wmask |= PCI_ROM_ADDRESS_ENABLE; 1121 } 1122 1123 addr = pci_bar(pci_dev, region_num); 1124 pci_set_long(pci_dev->config + addr, type); 1125 1126 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) && 1127 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 1128 pci_set_quad(pci_dev->wmask + addr, wmask); 1129 pci_set_quad(pci_dev->cmask + addr, ~0ULL); 1130 } else { 1131 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff); 1132 pci_set_long(pci_dev->cmask + addr, 0xffffffff); 1133 } 1134 } 1135 1136 static void pci_update_vga(PCIDevice *pci_dev) 1137 { 1138 uint16_t cmd; 1139 1140 if (!pci_dev->has_vga) { 1141 return; 1142 } 1143 1144 cmd = pci_get_word(pci_dev->config + PCI_COMMAND); 1145 1146 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_MEM], 1147 cmd & PCI_COMMAND_MEMORY); 1148 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO], 1149 cmd & PCI_COMMAND_IO); 1150 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI], 1151 cmd & PCI_COMMAND_IO); 1152 } 1153 1154 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, 1155 MemoryRegion *io_lo, MemoryRegion *io_hi) 1156 { 1157 assert(!pci_dev->has_vga); 1158 1159 assert(memory_region_size(mem) == QEMU_PCI_VGA_MEM_SIZE); 1160 pci_dev->vga_regions[QEMU_PCI_VGA_MEM] = mem; 1161 memory_region_add_subregion_overlap(pci_dev->bus->address_space_mem, 1162 QEMU_PCI_VGA_MEM_BASE, mem, 1); 1163 1164 assert(memory_region_size(io_lo) == QEMU_PCI_VGA_IO_LO_SIZE); 1165 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO] = io_lo; 1166 memory_region_add_subregion_overlap(pci_dev->bus->address_space_io, 1167 QEMU_PCI_VGA_IO_LO_BASE, io_lo, 1); 1168 1169 assert(memory_region_size(io_hi) == QEMU_PCI_VGA_IO_HI_SIZE); 1170 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI] = io_hi; 1171 memory_region_add_subregion_overlap(pci_dev->bus->address_space_io, 1172 QEMU_PCI_VGA_IO_HI_BASE, io_hi, 1); 1173 pci_dev->has_vga = true; 1174 1175 pci_update_vga(pci_dev); 1176 } 1177 1178 void pci_unregister_vga(PCIDevice *pci_dev) 1179 { 1180 if (!pci_dev->has_vga) { 1181 return; 1182 } 1183 1184 memory_region_del_subregion(pci_dev->bus->address_space_mem, 1185 pci_dev->vga_regions[QEMU_PCI_VGA_MEM]); 1186 memory_region_del_subregion(pci_dev->bus->address_space_io, 1187 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO]); 1188 memory_region_del_subregion(pci_dev->bus->address_space_io, 1189 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI]); 1190 pci_dev->has_vga = false; 1191 } 1192 1193 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num) 1194 { 1195 return pci_dev->io_regions[region_num].addr; 1196 } 1197 1198 static pcibus_t pci_bar_address(PCIDevice *d, 1199 int reg, uint8_t type, pcibus_t size) 1200 { 1201 pcibus_t new_addr, last_addr; 1202 int bar = pci_bar(d, reg); 1203 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND); 1204 Object *machine = qdev_get_machine(); 1205 ObjectClass *oc = object_get_class(machine); 1206 MachineClass *mc = MACHINE_CLASS(oc); 1207 bool allow_0_address = mc->pci_allow_0_address; 1208 1209 if (type & PCI_BASE_ADDRESS_SPACE_IO) { 1210 if (!(cmd & PCI_COMMAND_IO)) { 1211 return PCI_BAR_UNMAPPED; 1212 } 1213 new_addr = pci_get_long(d->config + bar) & ~(size - 1); 1214 last_addr = new_addr + size - 1; 1215 /* Check if 32 bit BAR wraps around explicitly. 1216 * TODO: make priorities correct and remove this work around. 1217 */ 1218 if (last_addr <= new_addr || last_addr >= UINT32_MAX || 1219 (!allow_0_address && new_addr == 0)) { 1220 return PCI_BAR_UNMAPPED; 1221 } 1222 return new_addr; 1223 } 1224 1225 if (!(cmd & PCI_COMMAND_MEMORY)) { 1226 return PCI_BAR_UNMAPPED; 1227 } 1228 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 1229 new_addr = pci_get_quad(d->config + bar); 1230 } else { 1231 new_addr = pci_get_long(d->config + bar); 1232 } 1233 /* the ROM slot has a specific enable bit */ 1234 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) { 1235 return PCI_BAR_UNMAPPED; 1236 } 1237 new_addr &= ~(size - 1); 1238 last_addr = new_addr + size - 1; 1239 /* NOTE: we do not support wrapping */ 1240 /* XXX: as we cannot support really dynamic 1241 mappings, we handle specific values as invalid 1242 mappings. */ 1243 if (last_addr <= new_addr || last_addr == PCI_BAR_UNMAPPED || 1244 (!allow_0_address && new_addr == 0)) { 1245 return PCI_BAR_UNMAPPED; 1246 } 1247 1248 /* Now pcibus_t is 64bit. 1249 * Check if 32 bit BAR wraps around explicitly. 1250 * Without this, PC ide doesn't work well. 1251 * TODO: remove this work around. 1252 */ 1253 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) { 1254 return PCI_BAR_UNMAPPED; 1255 } 1256 1257 /* 1258 * OS is allowed to set BAR beyond its addressable 1259 * bits. For example, 32 bit OS can set 64bit bar 1260 * to >4G. Check it. TODO: we might need to support 1261 * it in the future for e.g. PAE. 1262 */ 1263 if (last_addr >= HWADDR_MAX) { 1264 return PCI_BAR_UNMAPPED; 1265 } 1266 1267 return new_addr; 1268 } 1269 1270 static void pci_update_mappings(PCIDevice *d) 1271 { 1272 PCIIORegion *r; 1273 int i; 1274 pcibus_t new_addr; 1275 1276 for(i = 0; i < PCI_NUM_REGIONS; i++) { 1277 r = &d->io_regions[i]; 1278 1279 /* this region isn't registered */ 1280 if (!r->size) 1281 continue; 1282 1283 new_addr = pci_bar_address(d, i, r->type, r->size); 1284 1285 /* This bar isn't changed */ 1286 if (new_addr == r->addr) 1287 continue; 1288 1289 /* now do the real mapping */ 1290 if (r->addr != PCI_BAR_UNMAPPED) { 1291 trace_pci_update_mappings_del(d, pci_bus_num(d->bus), 1292 PCI_SLOT(d->devfn), 1293 PCI_FUNC(d->devfn), 1294 i, r->addr, r->size); 1295 memory_region_del_subregion(r->address_space, r->memory); 1296 } 1297 r->addr = new_addr; 1298 if (r->addr != PCI_BAR_UNMAPPED) { 1299 trace_pci_update_mappings_add(d, pci_bus_num(d->bus), 1300 PCI_SLOT(d->devfn), 1301 PCI_FUNC(d->devfn), 1302 i, r->addr, r->size); 1303 memory_region_add_subregion_overlap(r->address_space, 1304 r->addr, r->memory, 1); 1305 } 1306 } 1307 1308 pci_update_vga(d); 1309 } 1310 1311 static inline int pci_irq_disabled(PCIDevice *d) 1312 { 1313 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE; 1314 } 1315 1316 /* Called after interrupt disabled field update in config space, 1317 * assert/deassert interrupts if necessary. 1318 * Gets original interrupt disable bit value (before update). */ 1319 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled) 1320 { 1321 int i, disabled = pci_irq_disabled(d); 1322 if (disabled == was_irq_disabled) 1323 return; 1324 for (i = 0; i < PCI_NUM_PINS; ++i) { 1325 int state = pci_irq_state(d, i); 1326 pci_change_irq_level(d, i, disabled ? -state : state); 1327 } 1328 } 1329 1330 uint32_t pci_default_read_config(PCIDevice *d, 1331 uint32_t address, int len) 1332 { 1333 uint32_t val = 0; 1334 1335 memcpy(&val, d->config + address, len); 1336 return le32_to_cpu(val); 1337 } 1338 1339 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val_in, int l) 1340 { 1341 int i, was_irq_disabled = pci_irq_disabled(d); 1342 uint32_t val = val_in; 1343 1344 for (i = 0; i < l; val >>= 8, ++i) { 1345 uint8_t wmask = d->wmask[addr + i]; 1346 uint8_t w1cmask = d->w1cmask[addr + i]; 1347 assert(!(wmask & w1cmask)); 1348 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask); 1349 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */ 1350 } 1351 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) || 1352 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) || 1353 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) || 1354 range_covers_byte(addr, l, PCI_COMMAND)) 1355 pci_update_mappings(d); 1356 1357 if (range_covers_byte(addr, l, PCI_COMMAND)) { 1358 pci_update_irq_disabled(d, was_irq_disabled); 1359 memory_region_set_enabled(&d->bus_master_enable_region, 1360 pci_get_word(d->config + PCI_COMMAND) 1361 & PCI_COMMAND_MASTER); 1362 } 1363 1364 msi_write_config(d, addr, val_in, l); 1365 msix_write_config(d, addr, val_in, l); 1366 } 1367 1368 /***********************************************************/ 1369 /* generic PCI irq support */ 1370 1371 /* 0 <= irq_num <= 3. level must be 0 or 1 */ 1372 static void pci_irq_handler(void *opaque, int irq_num, int level) 1373 { 1374 PCIDevice *pci_dev = opaque; 1375 int change; 1376 1377 change = level - pci_irq_state(pci_dev, irq_num); 1378 if (!change) 1379 return; 1380 1381 pci_set_irq_state(pci_dev, irq_num, level); 1382 pci_update_irq_status(pci_dev); 1383 if (pci_irq_disabled(pci_dev)) 1384 return; 1385 pci_change_irq_level(pci_dev, irq_num, change); 1386 } 1387 1388 static inline int pci_intx(PCIDevice *pci_dev) 1389 { 1390 return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1; 1391 } 1392 1393 qemu_irq pci_allocate_irq(PCIDevice *pci_dev) 1394 { 1395 int intx = pci_intx(pci_dev); 1396 1397 return qemu_allocate_irq(pci_irq_handler, pci_dev, intx); 1398 } 1399 1400 void pci_set_irq(PCIDevice *pci_dev, int level) 1401 { 1402 int intx = pci_intx(pci_dev); 1403 pci_irq_handler(pci_dev, intx, level); 1404 } 1405 1406 /* Special hooks used by device assignment */ 1407 void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq) 1408 { 1409 assert(pci_bus_is_root(bus)); 1410 bus->route_intx_to_irq = route_intx_to_irq; 1411 } 1412 1413 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin) 1414 { 1415 PCIBus *bus; 1416 1417 do { 1418 bus = dev->bus; 1419 pin = bus->map_irq(dev, pin); 1420 dev = bus->parent_dev; 1421 } while (dev); 1422 1423 if (!bus->route_intx_to_irq) { 1424 error_report("PCI: Bug - unimplemented PCI INTx routing (%s)", 1425 object_get_typename(OBJECT(bus->qbus.parent))); 1426 return (PCIINTxRoute) { PCI_INTX_DISABLED, -1 }; 1427 } 1428 1429 return bus->route_intx_to_irq(bus->irq_opaque, pin); 1430 } 1431 1432 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new) 1433 { 1434 return old->mode != new->mode || old->irq != new->irq; 1435 } 1436 1437 void pci_bus_fire_intx_routing_notifier(PCIBus *bus) 1438 { 1439 PCIDevice *dev; 1440 PCIBus *sec; 1441 int i; 1442 1443 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 1444 dev = bus->devices[i]; 1445 if (dev && dev->intx_routing_notifier) { 1446 dev->intx_routing_notifier(dev); 1447 } 1448 } 1449 1450 QLIST_FOREACH(sec, &bus->child, sibling) { 1451 pci_bus_fire_intx_routing_notifier(sec); 1452 } 1453 } 1454 1455 void pci_device_set_intx_routing_notifier(PCIDevice *dev, 1456 PCIINTxRoutingNotifier notifier) 1457 { 1458 dev->intx_routing_notifier = notifier; 1459 } 1460 1461 /* 1462 * PCI-to-PCI bridge specification 1463 * 9.1: Interrupt routing. Table 9-1 1464 * 1465 * the PCI Express Base Specification, Revision 2.1 1466 * 2.2.8.1: INTx interrutp signaling - Rules 1467 * the Implementation Note 1468 * Table 2-20 1469 */ 1470 /* 1471 * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD 1472 * 0-origin unlike PCI interrupt pin register. 1473 */ 1474 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin) 1475 { 1476 return (pin + PCI_SLOT(pci_dev->devfn)) % PCI_NUM_PINS; 1477 } 1478 1479 /***********************************************************/ 1480 /* monitor info on PCI */ 1481 1482 typedef struct { 1483 uint16_t class; 1484 const char *desc; 1485 const char *fw_name; 1486 uint16_t fw_ign_bits; 1487 } pci_class_desc; 1488 1489 static const pci_class_desc pci_class_descriptions[] = 1490 { 1491 { 0x0001, "VGA controller", "display"}, 1492 { 0x0100, "SCSI controller", "scsi"}, 1493 { 0x0101, "IDE controller", "ide"}, 1494 { 0x0102, "Floppy controller", "fdc"}, 1495 { 0x0103, "IPI controller", "ipi"}, 1496 { 0x0104, "RAID controller", "raid"}, 1497 { 0x0106, "SATA controller"}, 1498 { 0x0107, "SAS controller"}, 1499 { 0x0180, "Storage controller"}, 1500 { 0x0200, "Ethernet controller", "ethernet"}, 1501 { 0x0201, "Token Ring controller", "token-ring"}, 1502 { 0x0202, "FDDI controller", "fddi"}, 1503 { 0x0203, "ATM controller", "atm"}, 1504 { 0x0280, "Network controller"}, 1505 { 0x0300, "VGA controller", "display", 0x00ff}, 1506 { 0x0301, "XGA controller"}, 1507 { 0x0302, "3D controller"}, 1508 { 0x0380, "Display controller"}, 1509 { 0x0400, "Video controller", "video"}, 1510 { 0x0401, "Audio controller", "sound"}, 1511 { 0x0402, "Phone"}, 1512 { 0x0403, "Audio controller", "sound"}, 1513 { 0x0480, "Multimedia controller"}, 1514 { 0x0500, "RAM controller", "memory"}, 1515 { 0x0501, "Flash controller", "flash"}, 1516 { 0x0580, "Memory controller"}, 1517 { 0x0600, "Host bridge", "host"}, 1518 { 0x0601, "ISA bridge", "isa"}, 1519 { 0x0602, "EISA bridge", "eisa"}, 1520 { 0x0603, "MC bridge", "mca"}, 1521 { 0x0604, "PCI bridge", "pci-bridge"}, 1522 { 0x0605, "PCMCIA bridge", "pcmcia"}, 1523 { 0x0606, "NUBUS bridge", "nubus"}, 1524 { 0x0607, "CARDBUS bridge", "cardbus"}, 1525 { 0x0608, "RACEWAY bridge"}, 1526 { 0x0680, "Bridge"}, 1527 { 0x0700, "Serial port", "serial"}, 1528 { 0x0701, "Parallel port", "parallel"}, 1529 { 0x0800, "Interrupt controller", "interrupt-controller"}, 1530 { 0x0801, "DMA controller", "dma-controller"}, 1531 { 0x0802, "Timer", "timer"}, 1532 { 0x0803, "RTC", "rtc"}, 1533 { 0x0900, "Keyboard", "keyboard"}, 1534 { 0x0901, "Pen", "pen"}, 1535 { 0x0902, "Mouse", "mouse"}, 1536 { 0x0A00, "Dock station", "dock", 0x00ff}, 1537 { 0x0B00, "i386 cpu", "cpu", 0x00ff}, 1538 { 0x0c00, "Fireware contorller", "fireware"}, 1539 { 0x0c01, "Access bus controller", "access-bus"}, 1540 { 0x0c02, "SSA controller", "ssa"}, 1541 { 0x0c03, "USB controller", "usb"}, 1542 { 0x0c04, "Fibre channel controller", "fibre-channel"}, 1543 { 0x0c05, "SMBus"}, 1544 { 0, NULL} 1545 }; 1546 1547 static void pci_for_each_device_under_bus_reverse(PCIBus *bus, 1548 void (*fn)(PCIBus *b, 1549 PCIDevice *d, 1550 void *opaque), 1551 void *opaque) 1552 { 1553 PCIDevice *d; 1554 int devfn; 1555 1556 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1557 d = bus->devices[ARRAY_SIZE(bus->devices) - 1 - devfn]; 1558 if (d) { 1559 fn(bus, d, opaque); 1560 } 1561 } 1562 } 1563 1564 void pci_for_each_device_reverse(PCIBus *bus, int bus_num, 1565 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque), 1566 void *opaque) 1567 { 1568 bus = pci_find_bus_nr(bus, bus_num); 1569 1570 if (bus) { 1571 pci_for_each_device_under_bus_reverse(bus, fn, opaque); 1572 } 1573 } 1574 1575 static void pci_for_each_device_under_bus(PCIBus *bus, 1576 void (*fn)(PCIBus *b, PCIDevice *d, 1577 void *opaque), 1578 void *opaque) 1579 { 1580 PCIDevice *d; 1581 int devfn; 1582 1583 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1584 d = bus->devices[devfn]; 1585 if (d) { 1586 fn(bus, d, opaque); 1587 } 1588 } 1589 } 1590 1591 void pci_for_each_device(PCIBus *bus, int bus_num, 1592 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque), 1593 void *opaque) 1594 { 1595 bus = pci_find_bus_nr(bus, bus_num); 1596 1597 if (bus) { 1598 pci_for_each_device_under_bus(bus, fn, opaque); 1599 } 1600 } 1601 1602 static const pci_class_desc *get_class_desc(int class) 1603 { 1604 const pci_class_desc *desc; 1605 1606 desc = pci_class_descriptions; 1607 while (desc->desc && class != desc->class) { 1608 desc++; 1609 } 1610 1611 return desc; 1612 } 1613 1614 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num); 1615 1616 static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev) 1617 { 1618 PciMemoryRegionList *head = NULL, *cur_item = NULL; 1619 int i; 1620 1621 for (i = 0; i < PCI_NUM_REGIONS; i++) { 1622 const PCIIORegion *r = &dev->io_regions[i]; 1623 PciMemoryRegionList *region; 1624 1625 if (!r->size) { 1626 continue; 1627 } 1628 1629 region = g_malloc0(sizeof(*region)); 1630 region->value = g_malloc0(sizeof(*region->value)); 1631 1632 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { 1633 region->value->type = g_strdup("io"); 1634 } else { 1635 region->value->type = g_strdup("memory"); 1636 region->value->has_prefetch = true; 1637 region->value->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH); 1638 region->value->has_mem_type_64 = true; 1639 region->value->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64); 1640 } 1641 1642 region->value->bar = i; 1643 region->value->address = r->addr; 1644 region->value->size = r->size; 1645 1646 /* XXX: waiting for the qapi to support GSList */ 1647 if (!cur_item) { 1648 head = cur_item = region; 1649 } else { 1650 cur_item->next = region; 1651 cur_item = region; 1652 } 1653 } 1654 1655 return head; 1656 } 1657 1658 static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus, 1659 int bus_num) 1660 { 1661 PciBridgeInfo *info; 1662 PciMemoryRange *range; 1663 1664 info = g_new0(PciBridgeInfo, 1); 1665 1666 info->bus = g_new0(PciBusInfo, 1); 1667 info->bus->number = dev->config[PCI_PRIMARY_BUS]; 1668 info->bus->secondary = dev->config[PCI_SECONDARY_BUS]; 1669 info->bus->subordinate = dev->config[PCI_SUBORDINATE_BUS]; 1670 1671 range = info->bus->io_range = g_new0(PciMemoryRange, 1); 1672 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO); 1673 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO); 1674 1675 range = info->bus->memory_range = g_new0(PciMemoryRange, 1); 1676 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 1677 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 1678 1679 range = info->bus->prefetchable_range = g_new0(PciMemoryRange, 1); 1680 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 1681 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 1682 1683 if (dev->config[PCI_SECONDARY_BUS] != 0) { 1684 PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]); 1685 if (child_bus) { 1686 info->has_devices = true; 1687 info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]); 1688 } 1689 } 1690 1691 return info; 1692 } 1693 1694 static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus, 1695 int bus_num) 1696 { 1697 const pci_class_desc *desc; 1698 PciDeviceInfo *info; 1699 uint8_t type; 1700 int class; 1701 1702 info = g_new0(PciDeviceInfo, 1); 1703 info->bus = bus_num; 1704 info->slot = PCI_SLOT(dev->devfn); 1705 info->function = PCI_FUNC(dev->devfn); 1706 1707 info->class_info = g_new0(PciDeviceClass, 1); 1708 class = pci_get_word(dev->config + PCI_CLASS_DEVICE); 1709 info->class_info->q_class = class; 1710 desc = get_class_desc(class); 1711 if (desc->desc) { 1712 info->class_info->has_desc = true; 1713 info->class_info->desc = g_strdup(desc->desc); 1714 } 1715 1716 info->id = g_new0(PciDeviceId, 1); 1717 info->id->vendor = pci_get_word(dev->config + PCI_VENDOR_ID); 1718 info->id->device = pci_get_word(dev->config + PCI_DEVICE_ID); 1719 info->regions = qmp_query_pci_regions(dev); 1720 info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : ""); 1721 1722 if (dev->config[PCI_INTERRUPT_PIN] != 0) { 1723 info->has_irq = true; 1724 info->irq = dev->config[PCI_INTERRUPT_LINE]; 1725 } 1726 1727 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 1728 if (type == PCI_HEADER_TYPE_BRIDGE) { 1729 info->has_pci_bridge = true; 1730 info->pci_bridge = qmp_query_pci_bridge(dev, bus, bus_num); 1731 } 1732 1733 return info; 1734 } 1735 1736 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num) 1737 { 1738 PciDeviceInfoList *info, *head = NULL, *cur_item = NULL; 1739 PCIDevice *dev; 1740 int devfn; 1741 1742 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1743 dev = bus->devices[devfn]; 1744 if (dev) { 1745 info = g_malloc0(sizeof(*info)); 1746 info->value = qmp_query_pci_device(dev, bus, bus_num); 1747 1748 /* XXX: waiting for the qapi to support GSList */ 1749 if (!cur_item) { 1750 head = cur_item = info; 1751 } else { 1752 cur_item->next = info; 1753 cur_item = info; 1754 } 1755 } 1756 } 1757 1758 return head; 1759 } 1760 1761 static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num) 1762 { 1763 PciInfo *info = NULL; 1764 1765 bus = pci_find_bus_nr(bus, bus_num); 1766 if (bus) { 1767 info = g_malloc0(sizeof(*info)); 1768 info->bus = bus_num; 1769 info->devices = qmp_query_pci_devices(bus, bus_num); 1770 } 1771 1772 return info; 1773 } 1774 1775 PciInfoList *qmp_query_pci(Error **errp) 1776 { 1777 PciInfoList *info, *head = NULL, *cur_item = NULL; 1778 PCIHostState *host_bridge; 1779 1780 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { 1781 info = g_malloc0(sizeof(*info)); 1782 info->value = qmp_query_pci_bus(host_bridge->bus, 1783 pci_bus_num(host_bridge->bus)); 1784 1785 /* XXX: waiting for the qapi to support GSList */ 1786 if (!cur_item) { 1787 head = cur_item = info; 1788 } else { 1789 cur_item->next = info; 1790 cur_item = info; 1791 } 1792 } 1793 1794 return head; 1795 } 1796 1797 static const char * const pci_nic_models[] = { 1798 "ne2k_pci", 1799 "i82551", 1800 "i82557b", 1801 "i82559er", 1802 "rtl8139", 1803 "e1000", 1804 "pcnet", 1805 "virtio", 1806 NULL 1807 }; 1808 1809 static const char * const pci_nic_names[] = { 1810 "ne2k_pci", 1811 "i82551", 1812 "i82557b", 1813 "i82559er", 1814 "rtl8139", 1815 "e1000", 1816 "pcnet", 1817 "virtio-net-pci", 1818 NULL 1819 }; 1820 1821 /* Initialize a PCI NIC. */ 1822 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus, 1823 const char *default_model, 1824 const char *default_devaddr) 1825 { 1826 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr; 1827 PCIBus *bus; 1828 PCIDevice *pci_dev; 1829 DeviceState *dev; 1830 int devfn; 1831 int i; 1832 1833 if (qemu_show_nic_models(nd->model, pci_nic_models)) { 1834 exit(0); 1835 } 1836 1837 i = qemu_find_nic_model(nd, pci_nic_models, default_model); 1838 if (i < 0) { 1839 exit(1); 1840 } 1841 1842 bus = pci_get_bus_devfn(&devfn, rootbus, devaddr); 1843 if (!bus) { 1844 error_report("Invalid PCI device address %s for device %s", 1845 devaddr, pci_nic_names[i]); 1846 exit(1); 1847 } 1848 1849 pci_dev = pci_create(bus, devfn, pci_nic_names[i]); 1850 dev = &pci_dev->qdev; 1851 qdev_set_nic_properties(dev, nd); 1852 qdev_init_nofail(dev); 1853 1854 return pci_dev; 1855 } 1856 1857 PCIDevice *pci_vga_init(PCIBus *bus) 1858 { 1859 switch (vga_interface_type) { 1860 case VGA_CIRRUS: 1861 return pci_create_simple(bus, -1, "cirrus-vga"); 1862 case VGA_QXL: 1863 return pci_create_simple(bus, -1, "qxl-vga"); 1864 case VGA_STD: 1865 return pci_create_simple(bus, -1, "VGA"); 1866 case VGA_VMWARE: 1867 return pci_create_simple(bus, -1, "vmware-svga"); 1868 case VGA_VIRTIO: 1869 return pci_create_simple(bus, -1, "virtio-vga"); 1870 case VGA_NONE: 1871 default: /* Other non-PCI types. Checking for unsupported types is already 1872 done in vl.c. */ 1873 return NULL; 1874 } 1875 } 1876 1877 /* Whether a given bus number is in range of the secondary 1878 * bus of the given bridge device. */ 1879 static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num) 1880 { 1881 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) & 1882 PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ && 1883 dev->config[PCI_SECONDARY_BUS] <= bus_num && 1884 bus_num <= dev->config[PCI_SUBORDINATE_BUS]; 1885 } 1886 1887 /* Whether a given bus number is in a range of a root bus */ 1888 static bool pci_root_bus_in_range(PCIBus *bus, int bus_num) 1889 { 1890 int i; 1891 1892 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 1893 PCIDevice *dev = bus->devices[i]; 1894 1895 if (dev && PCI_DEVICE_GET_CLASS(dev)->is_bridge) { 1896 if (pci_secondary_bus_in_range(dev, bus_num)) { 1897 return true; 1898 } 1899 } 1900 } 1901 1902 return false; 1903 } 1904 1905 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num) 1906 { 1907 PCIBus *sec; 1908 1909 if (!bus) { 1910 return NULL; 1911 } 1912 1913 if (pci_bus_num(bus) == bus_num) { 1914 return bus; 1915 } 1916 1917 /* Consider all bus numbers in range for the host pci bridge. */ 1918 if (!pci_bus_is_root(bus) && 1919 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) { 1920 return NULL; 1921 } 1922 1923 /* try child bus */ 1924 for (; bus; bus = sec) { 1925 QLIST_FOREACH(sec, &bus->child, sibling) { 1926 if (pci_bus_num(sec) == bus_num) { 1927 return sec; 1928 } 1929 /* PXB buses assumed to be children of bus 0 */ 1930 if (pci_bus_is_root(sec)) { 1931 if (pci_root_bus_in_range(sec, bus_num)) { 1932 break; 1933 } 1934 } else { 1935 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) { 1936 break; 1937 } 1938 } 1939 } 1940 } 1941 1942 return NULL; 1943 } 1944 1945 void pci_for_each_bus_depth_first(PCIBus *bus, 1946 void *(*begin)(PCIBus *bus, void *parent_state), 1947 void (*end)(PCIBus *bus, void *state), 1948 void *parent_state) 1949 { 1950 PCIBus *sec; 1951 void *state; 1952 1953 if (!bus) { 1954 return; 1955 } 1956 1957 if (begin) { 1958 state = begin(bus, parent_state); 1959 } else { 1960 state = parent_state; 1961 } 1962 1963 QLIST_FOREACH(sec, &bus->child, sibling) { 1964 pci_for_each_bus_depth_first(sec, begin, end, state); 1965 } 1966 1967 if (end) { 1968 end(bus, state); 1969 } 1970 } 1971 1972 1973 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn) 1974 { 1975 bus = pci_find_bus_nr(bus, bus_num); 1976 1977 if (!bus) 1978 return NULL; 1979 1980 return bus->devices[devfn]; 1981 } 1982 1983 static void pci_qdev_realize(DeviceState *qdev, Error **errp) 1984 { 1985 PCIDevice *pci_dev = (PCIDevice *)qdev; 1986 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 1987 Error *local_err = NULL; 1988 PCIBus *bus; 1989 bool is_default_rom; 1990 1991 /* initialize cap_present for pci_is_express() and pci_config_size() */ 1992 if (pc->is_express) { 1993 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; 1994 } 1995 1996 bus = PCI_BUS(qdev_get_parent_bus(qdev)); 1997 pci_dev = do_pci_register_device(pci_dev, bus, 1998 object_get_typename(OBJECT(qdev)), 1999 pci_dev->devfn, errp); 2000 if (pci_dev == NULL) 2001 return; 2002 2003 if (pc->realize) { 2004 pc->realize(pci_dev, &local_err); 2005 if (local_err) { 2006 error_propagate(errp, local_err); 2007 do_pci_unregister_device(pci_dev); 2008 return; 2009 } 2010 } 2011 2012 /* rom loading */ 2013 is_default_rom = false; 2014 if (pci_dev->romfile == NULL && pc->romfile != NULL) { 2015 pci_dev->romfile = g_strdup(pc->romfile); 2016 is_default_rom = true; 2017 } 2018 2019 pci_add_option_rom(pci_dev, is_default_rom, &local_err); 2020 if (local_err) { 2021 error_propagate(errp, local_err); 2022 pci_qdev_unrealize(DEVICE(pci_dev), NULL); 2023 return; 2024 } 2025 } 2026 2027 static void pci_default_realize(PCIDevice *dev, Error **errp) 2028 { 2029 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 2030 2031 if (pc->init) { 2032 if (pc->init(dev) < 0) { 2033 error_setg(errp, "Device initialization failed"); 2034 return; 2035 } 2036 } 2037 } 2038 2039 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction, 2040 const char *name) 2041 { 2042 DeviceState *dev; 2043 2044 dev = qdev_create(&bus->qbus, name); 2045 qdev_prop_set_int32(dev, "addr", devfn); 2046 qdev_prop_set_bit(dev, "multifunction", multifunction); 2047 return PCI_DEVICE(dev); 2048 } 2049 2050 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, 2051 bool multifunction, 2052 const char *name) 2053 { 2054 PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name); 2055 qdev_init_nofail(&dev->qdev); 2056 return dev; 2057 } 2058 2059 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name) 2060 { 2061 return pci_create_multifunction(bus, devfn, false, name); 2062 } 2063 2064 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name) 2065 { 2066 return pci_create_simple_multifunction(bus, devfn, false, name); 2067 } 2068 2069 static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size) 2070 { 2071 int offset = PCI_CONFIG_HEADER_SIZE; 2072 int i; 2073 for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) { 2074 if (pdev->used[i]) 2075 offset = i + 1; 2076 else if (i - offset + 1 == size) 2077 return offset; 2078 } 2079 return 0; 2080 } 2081 2082 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id, 2083 uint8_t *prev_p) 2084 { 2085 uint8_t next, prev; 2086 2087 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST)) 2088 return 0; 2089 2090 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); 2091 prev = next + PCI_CAP_LIST_NEXT) 2092 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id) 2093 break; 2094 2095 if (prev_p) 2096 *prev_p = prev; 2097 return next; 2098 } 2099 2100 static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset) 2101 { 2102 uint8_t next, prev, found = 0; 2103 2104 if (!(pdev->used[offset])) { 2105 return 0; 2106 } 2107 2108 assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST); 2109 2110 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); 2111 prev = next + PCI_CAP_LIST_NEXT) { 2112 if (next <= offset && next > found) { 2113 found = next; 2114 } 2115 } 2116 return found; 2117 } 2118 2119 /* Patch the PCI vendor and device ids in a PCI rom image if necessary. 2120 This is needed for an option rom which is used for more than one device. */ 2121 static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size) 2122 { 2123 uint16_t vendor_id; 2124 uint16_t device_id; 2125 uint16_t rom_vendor_id; 2126 uint16_t rom_device_id; 2127 uint16_t rom_magic; 2128 uint16_t pcir_offset; 2129 uint8_t checksum; 2130 2131 /* Words in rom data are little endian (like in PCI configuration), 2132 so they can be read / written with pci_get_word / pci_set_word. */ 2133 2134 /* Only a valid rom will be patched. */ 2135 rom_magic = pci_get_word(ptr); 2136 if (rom_magic != 0xaa55) { 2137 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic); 2138 return; 2139 } 2140 pcir_offset = pci_get_word(ptr + 0x18); 2141 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) { 2142 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset); 2143 return; 2144 } 2145 2146 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID); 2147 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID); 2148 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4); 2149 rom_device_id = pci_get_word(ptr + pcir_offset + 6); 2150 2151 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile, 2152 vendor_id, device_id, rom_vendor_id, rom_device_id); 2153 2154 checksum = ptr[6]; 2155 2156 if (vendor_id != rom_vendor_id) { 2157 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */ 2158 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8); 2159 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8); 2160 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); 2161 ptr[6] = checksum; 2162 pci_set_word(ptr + pcir_offset + 4, vendor_id); 2163 } 2164 2165 if (device_id != rom_device_id) { 2166 /* Patch device id and checksum (at offset 6 for etherboot roms). */ 2167 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8); 2168 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8); 2169 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); 2170 ptr[6] = checksum; 2171 pci_set_word(ptr + pcir_offset + 6, device_id); 2172 } 2173 } 2174 2175 /* Add an option rom for the device */ 2176 static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, 2177 Error **errp) 2178 { 2179 int size; 2180 char *path; 2181 void *ptr; 2182 char name[32]; 2183 const VMStateDescription *vmsd; 2184 2185 if (!pdev->romfile) 2186 return; 2187 if (strlen(pdev->romfile) == 0) 2188 return; 2189 2190 if (!pdev->rom_bar) { 2191 /* 2192 * Load rom via fw_cfg instead of creating a rom bar, 2193 * for 0.11 compatibility. 2194 */ 2195 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE); 2196 2197 /* 2198 * Hot-plugged devices can't use the option ROM 2199 * if the rom bar is disabled. 2200 */ 2201 if (DEVICE(pdev)->hotplugged) { 2202 error_setg(errp, "Hot-plugged device without ROM bar" 2203 " can't have an option ROM"); 2204 return; 2205 } 2206 2207 if (class == 0x0300) { 2208 rom_add_vga(pdev->romfile); 2209 } else { 2210 rom_add_option(pdev->romfile, -1); 2211 } 2212 return; 2213 } 2214 2215 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile); 2216 if (path == NULL) { 2217 path = g_strdup(pdev->romfile); 2218 } 2219 2220 size = get_image_size(path); 2221 if (size < 0) { 2222 error_setg(errp, "failed to find romfile \"%s\"", pdev->romfile); 2223 g_free(path); 2224 return; 2225 } else if (size == 0) { 2226 error_setg(errp, "romfile \"%s\" is empty", pdev->romfile); 2227 g_free(path); 2228 return; 2229 } 2230 size = pow2ceil(size); 2231 2232 vmsd = qdev_get_vmsd(DEVICE(pdev)); 2233 2234 if (vmsd) { 2235 snprintf(name, sizeof(name), "%s.rom", vmsd->name); 2236 } else { 2237 snprintf(name, sizeof(name), "%s.rom", object_get_typename(OBJECT(pdev))); 2238 } 2239 pdev->has_rom = true; 2240 memory_region_init_rom(&pdev->rom, OBJECT(pdev), name, size, &error_fatal); 2241 ptr = memory_region_get_ram_ptr(&pdev->rom); 2242 load_image(path, ptr); 2243 g_free(path); 2244 2245 if (is_default_rom) { 2246 /* Only the default rom images will be patched (if needed). */ 2247 pci_patch_ids(pdev, ptr, size); 2248 } 2249 2250 pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom); 2251 } 2252 2253 static void pci_del_option_rom(PCIDevice *pdev) 2254 { 2255 if (!pdev->has_rom) 2256 return; 2257 2258 vmstate_unregister_ram(&pdev->rom, &pdev->qdev); 2259 pdev->has_rom = false; 2260 } 2261 2262 /* 2263 * On success, pci_add_capability() returns a positive value 2264 * that the offset of the pci capability. 2265 * On failure, it sets an error and returns a negative error 2266 * code. 2267 */ 2268 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, 2269 uint8_t offset, uint8_t size, 2270 Error **errp) 2271 { 2272 uint8_t *config; 2273 int i, overlapping_cap; 2274 2275 if (!offset) { 2276 offset = pci_find_space(pdev, size); 2277 /* out of PCI config space is programming error */ 2278 assert(offset); 2279 } else { 2280 /* Verify that capabilities don't overlap. Note: device assignment 2281 * depends on this check to verify that the device is not broken. 2282 * Should never trigger for emulated devices, but it's helpful 2283 * for debugging these. */ 2284 for (i = offset; i < offset + size; i++) { 2285 overlapping_cap = pci_find_capability_at_offset(pdev, i); 2286 if (overlapping_cap) { 2287 error_setg(errp, "%s:%02x:%02x.%x " 2288 "Attempt to add PCI capability %x at offset " 2289 "%x overlaps existing capability %x at offset %x", 2290 pci_root_bus_path(pdev), pci_bus_num(pdev->bus), 2291 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), 2292 cap_id, offset, overlapping_cap, i); 2293 return -EINVAL; 2294 } 2295 } 2296 } 2297 2298 config = pdev->config + offset; 2299 config[PCI_CAP_LIST_ID] = cap_id; 2300 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST]; 2301 pdev->config[PCI_CAPABILITY_LIST] = offset; 2302 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST; 2303 memset(pdev->used + offset, 0xFF, QEMU_ALIGN_UP(size, 4)); 2304 /* Make capability read-only by default */ 2305 memset(pdev->wmask + offset, 0, size); 2306 /* Check capability by default */ 2307 memset(pdev->cmask + offset, 0xFF, size); 2308 return offset; 2309 } 2310 2311 /* Unlink capability from the pci config space. */ 2312 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size) 2313 { 2314 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev); 2315 if (!offset) 2316 return; 2317 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT]; 2318 /* Make capability writable again */ 2319 memset(pdev->wmask + offset, 0xff, size); 2320 memset(pdev->w1cmask + offset, 0, size); 2321 /* Clear cmask as device-specific registers can't be checked */ 2322 memset(pdev->cmask + offset, 0, size); 2323 memset(pdev->used + offset, 0, QEMU_ALIGN_UP(size, 4)); 2324 2325 if (!pdev->config[PCI_CAPABILITY_LIST]) 2326 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST; 2327 } 2328 2329 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id) 2330 { 2331 return pci_find_capability_list(pdev, cap_id, NULL); 2332 } 2333 2334 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent) 2335 { 2336 PCIDevice *d = (PCIDevice *)dev; 2337 const pci_class_desc *desc; 2338 char ctxt[64]; 2339 PCIIORegion *r; 2340 int i, class; 2341 2342 class = pci_get_word(d->config + PCI_CLASS_DEVICE); 2343 desc = pci_class_descriptions; 2344 while (desc->desc && class != desc->class) 2345 desc++; 2346 if (desc->desc) { 2347 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc); 2348 } else { 2349 snprintf(ctxt, sizeof(ctxt), "Class %04x", class); 2350 } 2351 2352 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, " 2353 "pci id %04x:%04x (sub %04x:%04x)\n", 2354 indent, "", ctxt, pci_bus_num(d->bus), 2355 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn), 2356 pci_get_word(d->config + PCI_VENDOR_ID), 2357 pci_get_word(d->config + PCI_DEVICE_ID), 2358 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID), 2359 pci_get_word(d->config + PCI_SUBSYSTEM_ID)); 2360 for (i = 0; i < PCI_NUM_REGIONS; i++) { 2361 r = &d->io_regions[i]; 2362 if (!r->size) 2363 continue; 2364 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS 2365 " [0x%"FMT_PCIBUS"]\n", 2366 indent, "", 2367 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem", 2368 r->addr, r->addr + r->size - 1); 2369 } 2370 } 2371 2372 static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len) 2373 { 2374 PCIDevice *d = (PCIDevice *)dev; 2375 const char *name = NULL; 2376 const pci_class_desc *desc = pci_class_descriptions; 2377 int class = pci_get_word(d->config + PCI_CLASS_DEVICE); 2378 2379 while (desc->desc && 2380 (class & ~desc->fw_ign_bits) != 2381 (desc->class & ~desc->fw_ign_bits)) { 2382 desc++; 2383 } 2384 2385 if (desc->desc) { 2386 name = desc->fw_name; 2387 } 2388 2389 if (name) { 2390 pstrcpy(buf, len, name); 2391 } else { 2392 snprintf(buf, len, "pci%04x,%04x", 2393 pci_get_word(d->config + PCI_VENDOR_ID), 2394 pci_get_word(d->config + PCI_DEVICE_ID)); 2395 } 2396 2397 return buf; 2398 } 2399 2400 static char *pcibus_get_fw_dev_path(DeviceState *dev) 2401 { 2402 PCIDevice *d = (PCIDevice *)dev; 2403 char path[50], name[33]; 2404 int off; 2405 2406 off = snprintf(path, sizeof(path), "%s@%x", 2407 pci_dev_fw_name(dev, name, sizeof name), 2408 PCI_SLOT(d->devfn)); 2409 if (PCI_FUNC(d->devfn)) 2410 snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn)); 2411 return g_strdup(path); 2412 } 2413 2414 static char *pcibus_get_dev_path(DeviceState *dev) 2415 { 2416 PCIDevice *d = container_of(dev, PCIDevice, qdev); 2417 PCIDevice *t; 2418 int slot_depth; 2419 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function. 2420 * 00 is added here to make this format compatible with 2421 * domain:Bus:Slot.Func for systems without nested PCI bridges. 2422 * Slot.Function list specifies the slot and function numbers for all 2423 * devices on the path from root to the specific device. */ 2424 const char *root_bus_path; 2425 int root_bus_len; 2426 char slot[] = ":SS.F"; 2427 int slot_len = sizeof slot - 1 /* For '\0' */; 2428 int path_len; 2429 char *path, *p; 2430 int s; 2431 2432 root_bus_path = pci_root_bus_path(d); 2433 root_bus_len = strlen(root_bus_path); 2434 2435 /* Calculate # of slots on path between device and root. */; 2436 slot_depth = 0; 2437 for (t = d; t; t = t->bus->parent_dev) { 2438 ++slot_depth; 2439 } 2440 2441 path_len = root_bus_len + slot_len * slot_depth; 2442 2443 /* Allocate memory, fill in the terminating null byte. */ 2444 path = g_malloc(path_len + 1 /* For '\0' */); 2445 path[path_len] = '\0'; 2446 2447 memcpy(path, root_bus_path, root_bus_len); 2448 2449 /* Fill in slot numbers. We walk up from device to root, so need to print 2450 * them in the reverse order, last to first. */ 2451 p = path + path_len; 2452 for (t = d; t; t = t->bus->parent_dev) { 2453 p -= slot_len; 2454 s = snprintf(slot, sizeof slot, ":%02x.%x", 2455 PCI_SLOT(t->devfn), PCI_FUNC(t->devfn)); 2456 assert(s == slot_len); 2457 memcpy(p, slot, slot_len); 2458 } 2459 2460 return path; 2461 } 2462 2463 static int pci_qdev_find_recursive(PCIBus *bus, 2464 const char *id, PCIDevice **pdev) 2465 { 2466 DeviceState *qdev = qdev_find_recursive(&bus->qbus, id); 2467 if (!qdev) { 2468 return -ENODEV; 2469 } 2470 2471 /* roughly check if given qdev is pci device */ 2472 if (object_dynamic_cast(OBJECT(qdev), TYPE_PCI_DEVICE)) { 2473 *pdev = PCI_DEVICE(qdev); 2474 return 0; 2475 } 2476 return -EINVAL; 2477 } 2478 2479 int pci_qdev_find_device(const char *id, PCIDevice **pdev) 2480 { 2481 PCIHostState *host_bridge; 2482 int rc = -ENODEV; 2483 2484 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { 2485 int tmp = pci_qdev_find_recursive(host_bridge->bus, id, pdev); 2486 if (!tmp) { 2487 rc = 0; 2488 break; 2489 } 2490 if (tmp != -ENODEV) { 2491 rc = tmp; 2492 } 2493 } 2494 2495 return rc; 2496 } 2497 2498 MemoryRegion *pci_address_space(PCIDevice *dev) 2499 { 2500 return dev->bus->address_space_mem; 2501 } 2502 2503 MemoryRegion *pci_address_space_io(PCIDevice *dev) 2504 { 2505 return dev->bus->address_space_io; 2506 } 2507 2508 static void pci_device_class_init(ObjectClass *klass, void *data) 2509 { 2510 DeviceClass *k = DEVICE_CLASS(klass); 2511 PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass); 2512 2513 k->realize = pci_qdev_realize; 2514 k->unrealize = pci_qdev_unrealize; 2515 k->bus_type = TYPE_PCI_BUS; 2516 k->props = pci_props; 2517 pc->realize = pci_default_realize; 2518 } 2519 2520 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev) 2521 { 2522 PCIBus *bus = PCI_BUS(dev->bus); 2523 PCIBus *iommu_bus = bus; 2524 2525 while(iommu_bus && !iommu_bus->iommu_fn && iommu_bus->parent_dev) { 2526 iommu_bus = PCI_BUS(iommu_bus->parent_dev->bus); 2527 } 2528 if (iommu_bus && iommu_bus->iommu_fn) { 2529 return iommu_bus->iommu_fn(bus, iommu_bus->iommu_opaque, dev->devfn); 2530 } 2531 return &address_space_memory; 2532 } 2533 2534 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque) 2535 { 2536 bus->iommu_fn = fn; 2537 bus->iommu_opaque = opaque; 2538 } 2539 2540 static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque) 2541 { 2542 Range *range = opaque; 2543 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 2544 uint16_t cmd = pci_get_word(dev->config + PCI_COMMAND); 2545 int i; 2546 2547 if (!(cmd & PCI_COMMAND_MEMORY)) { 2548 return; 2549 } 2550 2551 if (pc->is_bridge) { 2552 pcibus_t base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 2553 pcibus_t limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 2554 2555 base = MAX(base, 0x1ULL << 32); 2556 2557 if (limit >= base) { 2558 Range pref_range; 2559 range_set_bounds(&pref_range, base, limit); 2560 range_extend(range, &pref_range); 2561 } 2562 } 2563 for (i = 0; i < PCI_NUM_REGIONS; ++i) { 2564 PCIIORegion *r = &dev->io_regions[i]; 2565 pcibus_t lob, upb; 2566 Range region_range; 2567 2568 if (!r->size || 2569 (r->type & PCI_BASE_ADDRESS_SPACE_IO) || 2570 !(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64)) { 2571 continue; 2572 } 2573 2574 lob = pci_bar_address(dev, i, r->type, r->size); 2575 upb = lob + r->size - 1; 2576 if (lob == PCI_BAR_UNMAPPED) { 2577 continue; 2578 } 2579 2580 lob = MAX(lob, 0x1ULL << 32); 2581 2582 if (upb >= lob) { 2583 range_set_bounds(®ion_range, lob, upb); 2584 range_extend(range, ®ion_range); 2585 } 2586 } 2587 } 2588 2589 void pci_bus_get_w64_range(PCIBus *bus, Range *range) 2590 { 2591 range_make_empty(range); 2592 pci_for_each_device_under_bus(bus, pci_dev_get_w64, range); 2593 } 2594 2595 static bool pcie_has_upstream_port(PCIDevice *dev) 2596 { 2597 PCIDevice *parent_dev = pci_bridge_get_device(dev->bus); 2598 2599 /* Device associated with an upstream port. 2600 * As there are several types of these, it's easier to check the 2601 * parent device: upstream ports are always connected to 2602 * root or downstream ports. 2603 */ 2604 return parent_dev && 2605 pci_is_express(parent_dev) && 2606 parent_dev->exp.exp_cap && 2607 (pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_ROOT_PORT || 2608 pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_DOWNSTREAM); 2609 } 2610 2611 PCIDevice *pci_get_function_0(PCIDevice *pci_dev) 2612 { 2613 if(pcie_has_upstream_port(pci_dev)) { 2614 /* With an upstream PCIe port, we only support 1 device at slot 0 */ 2615 return pci_dev->bus->devices[0]; 2616 } else { 2617 /* Other bus types might support multiple devices at slots 0-31 */ 2618 return pci_dev->bus->devices[PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 0)]; 2619 } 2620 } 2621 2622 MSIMessage pci_get_msi_message(PCIDevice *dev, int vector) 2623 { 2624 MSIMessage msg; 2625 if (msix_enabled(dev)) { 2626 msg = msix_get_message(dev, vector); 2627 } else if (msi_enabled(dev)) { 2628 msg = msi_get_message(dev, vector); 2629 } else { 2630 /* Should never happen */ 2631 error_report("%s: unknown interrupt type", __func__); 2632 abort(); 2633 } 2634 return msg; 2635 } 2636 2637 static const TypeInfo pci_device_type_info = { 2638 .name = TYPE_PCI_DEVICE, 2639 .parent = TYPE_DEVICE, 2640 .instance_size = sizeof(PCIDevice), 2641 .abstract = true, 2642 .class_size = sizeof(PCIDeviceClass), 2643 .class_init = pci_device_class_init, 2644 }; 2645 2646 static void pci_register_types(void) 2647 { 2648 type_register_static(&pci_bus_info); 2649 type_register_static(&pcie_bus_info); 2650 type_register_static(&pci_device_type_info); 2651 } 2652 2653 type_init(pci_register_types) 2654