1 /* 2 * QEMU PCI bus manager 3 * 4 * Copyright (c) 2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/hw.h" 25 #include "hw/pci/pci.h" 26 #include "hw/pci/pci_bridge.h" 27 #include "hw/pci/pci_bus.h" 28 #include "monitor/monitor.h" 29 #include "net/net.h" 30 #include "sysemu/sysemu.h" 31 #include "hw/loader.h" 32 #include "qemu/range.h" 33 #include "qmp-commands.h" 34 #include "hw/pci/msi.h" 35 #include "hw/pci/msix.h" 36 #include "exec/address-spaces.h" 37 38 //#define DEBUG_PCI 39 #ifdef DEBUG_PCI 40 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) 41 #else 42 # define PCI_DPRINTF(format, ...) do { } while (0) 43 #endif 44 45 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent); 46 static char *pcibus_get_dev_path(DeviceState *dev); 47 static char *pcibus_get_fw_dev_path(DeviceState *dev); 48 static int pcibus_reset(BusState *qbus); 49 50 static Property pci_props[] = { 51 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1), 52 DEFINE_PROP_STRING("romfile", PCIDevice, romfile), 53 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1), 54 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present, 55 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false), 56 DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present, 57 QEMU_PCI_CAP_SERR_BITNR, true), 58 DEFINE_PROP_END_OF_LIST() 59 }; 60 61 static void pci_bus_class_init(ObjectClass *klass, void *data) 62 { 63 BusClass *k = BUS_CLASS(klass); 64 65 k->print_dev = pcibus_dev_print; 66 k->get_dev_path = pcibus_get_dev_path; 67 k->get_fw_dev_path = pcibus_get_fw_dev_path; 68 k->reset = pcibus_reset; 69 } 70 71 static const TypeInfo pci_bus_info = { 72 .name = TYPE_PCI_BUS, 73 .parent = TYPE_BUS, 74 .instance_size = sizeof(PCIBus), 75 .class_init = pci_bus_class_init, 76 }; 77 78 static const TypeInfo pcie_bus_info = { 79 .name = TYPE_PCIE_BUS, 80 .parent = TYPE_PCI_BUS, 81 }; 82 83 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num); 84 static void pci_update_mappings(PCIDevice *d); 85 static void pci_set_irq(void *opaque, int irq_num, int level); 86 static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom); 87 static void pci_del_option_rom(PCIDevice *pdev); 88 89 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET; 90 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU; 91 92 struct PCIHostBus { 93 int domain; 94 struct PCIBus *bus; 95 QLIST_ENTRY(PCIHostBus) next; 96 }; 97 static QLIST_HEAD(, PCIHostBus) host_buses; 98 99 static const VMStateDescription vmstate_pcibus = { 100 .name = "PCIBUS", 101 .version_id = 1, 102 .minimum_version_id = 1, 103 .minimum_version_id_old = 1, 104 .fields = (VMStateField []) { 105 VMSTATE_INT32_EQUAL(nirq, PCIBus), 106 VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t), 107 VMSTATE_END_OF_LIST() 108 } 109 }; 110 static int pci_bar(PCIDevice *d, int reg) 111 { 112 uint8_t type; 113 114 if (reg != PCI_ROM_SLOT) 115 return PCI_BASE_ADDRESS_0 + reg * 4; 116 117 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 118 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS; 119 } 120 121 static inline int pci_irq_state(PCIDevice *d, int irq_num) 122 { 123 return (d->irq_state >> irq_num) & 0x1; 124 } 125 126 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level) 127 { 128 d->irq_state &= ~(0x1 << irq_num); 129 d->irq_state |= level << irq_num; 130 } 131 132 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change) 133 { 134 PCIBus *bus; 135 for (;;) { 136 bus = pci_dev->bus; 137 irq_num = bus->map_irq(pci_dev, irq_num); 138 if (bus->set_irq) 139 break; 140 pci_dev = bus->parent_dev; 141 } 142 bus->irq_count[irq_num] += change; 143 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0); 144 } 145 146 int pci_bus_get_irq_level(PCIBus *bus, int irq_num) 147 { 148 assert(irq_num >= 0); 149 assert(irq_num < bus->nirq); 150 return !!bus->irq_count[irq_num]; 151 } 152 153 /* Update interrupt status bit in config space on interrupt 154 * state change. */ 155 static void pci_update_irq_status(PCIDevice *dev) 156 { 157 if (dev->irq_state) { 158 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT; 159 } else { 160 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; 161 } 162 } 163 164 void pci_device_deassert_intx(PCIDevice *dev) 165 { 166 int i; 167 for (i = 0; i < PCI_NUM_PINS; ++i) { 168 qemu_set_irq(dev->irq[i], 0); 169 } 170 } 171 172 /* 173 * This function is called on #RST and FLR. 174 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set 175 */ 176 void pci_device_reset(PCIDevice *dev) 177 { 178 int r; 179 180 qdev_reset_all(&dev->qdev); 181 182 dev->irq_state = 0; 183 pci_update_irq_status(dev); 184 pci_device_deassert_intx(dev); 185 /* Clear all writable bits */ 186 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND, 187 pci_get_word(dev->wmask + PCI_COMMAND) | 188 pci_get_word(dev->w1cmask + PCI_COMMAND)); 189 pci_word_test_and_clear_mask(dev->config + PCI_STATUS, 190 pci_get_word(dev->wmask + PCI_STATUS) | 191 pci_get_word(dev->w1cmask + PCI_STATUS)); 192 dev->config[PCI_CACHE_LINE_SIZE] = 0x0; 193 dev->config[PCI_INTERRUPT_LINE] = 0x0; 194 for (r = 0; r < PCI_NUM_REGIONS; ++r) { 195 PCIIORegion *region = &dev->io_regions[r]; 196 if (!region->size) { 197 continue; 198 } 199 200 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) && 201 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 202 pci_set_quad(dev->config + pci_bar(dev, r), region->type); 203 } else { 204 pci_set_long(dev->config + pci_bar(dev, r), region->type); 205 } 206 } 207 pci_update_mappings(dev); 208 209 msi_reset(dev); 210 msix_reset(dev); 211 } 212 213 /* 214 * Trigger pci bus reset under a given bus. 215 * To be called on RST# assert. 216 */ 217 void pci_bus_reset(PCIBus *bus) 218 { 219 int i; 220 221 for (i = 0; i < bus->nirq; i++) { 222 bus->irq_count[i] = 0; 223 } 224 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 225 if (bus->devices[i]) { 226 pci_device_reset(bus->devices[i]); 227 } 228 } 229 } 230 231 static int pcibus_reset(BusState *qbus) 232 { 233 pci_bus_reset(DO_UPCAST(PCIBus, qbus, qbus)); 234 235 /* topology traverse is done by pci_bus_reset(). 236 Tell qbus/qdev walker not to traverse the tree */ 237 return 1; 238 } 239 240 static void pci_host_bus_register(int domain, PCIBus *bus) 241 { 242 struct PCIHostBus *host; 243 host = g_malloc0(sizeof(*host)); 244 host->domain = domain; 245 host->bus = bus; 246 QLIST_INSERT_HEAD(&host_buses, host, next); 247 } 248 249 PCIBus *pci_find_root_bus(int domain) 250 { 251 struct PCIHostBus *host; 252 253 QLIST_FOREACH(host, &host_buses, next) { 254 if (host->domain == domain) { 255 return host->bus; 256 } 257 } 258 259 return NULL; 260 } 261 262 int pci_find_domain(const PCIBus *bus) 263 { 264 PCIDevice *d; 265 struct PCIHostBus *host; 266 267 /* obtain root bus */ 268 while ((d = bus->parent_dev) != NULL) { 269 bus = d->bus; 270 } 271 272 QLIST_FOREACH(host, &host_buses, next) { 273 if (host->bus == bus) { 274 return host->domain; 275 } 276 } 277 278 abort(); /* should not be reached */ 279 return -1; 280 } 281 282 static void pci_bus_init(PCIBus *bus, DeviceState *parent, 283 const char *name, 284 MemoryRegion *address_space_mem, 285 MemoryRegion *address_space_io, 286 uint8_t devfn_min) 287 { 288 assert(PCI_FUNC(devfn_min) == 0); 289 bus->devfn_min = devfn_min; 290 bus->address_space_mem = address_space_mem; 291 bus->address_space_io = address_space_io; 292 293 /* host bridge */ 294 QLIST_INIT(&bus->child); 295 pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */ 296 297 vmstate_register(NULL, -1, &vmstate_pcibus, bus); 298 } 299 300 bool pci_bus_is_express(PCIBus *bus) 301 { 302 return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS); 303 } 304 305 bool pci_bus_is_root(PCIBus *bus) 306 { 307 return !bus->parent_dev; 308 } 309 310 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent, 311 const char *name, 312 MemoryRegion *address_space_mem, 313 MemoryRegion *address_space_io, 314 uint8_t devfn_min, const char *typename) 315 { 316 qbus_create_inplace(bus, typename, parent, name); 317 pci_bus_init(bus, parent, name, address_space_mem, 318 address_space_io, devfn_min); 319 } 320 321 PCIBus *pci_bus_new(DeviceState *parent, const char *name, 322 MemoryRegion *address_space_mem, 323 MemoryRegion *address_space_io, 324 uint8_t devfn_min, const char *typename) 325 { 326 PCIBus *bus; 327 328 bus = PCI_BUS(qbus_create(typename, parent, name)); 329 pci_bus_init(bus, parent, name, address_space_mem, 330 address_space_io, devfn_min); 331 return bus; 332 } 333 334 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 335 void *irq_opaque, int nirq) 336 { 337 bus->set_irq = set_irq; 338 bus->map_irq = map_irq; 339 bus->irq_opaque = irq_opaque; 340 bus->nirq = nirq; 341 bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0])); 342 } 343 344 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *qdev) 345 { 346 bus->qbus.allow_hotplug = 1; 347 bus->hotplug = hotplug; 348 bus->hotplug_qdev = qdev; 349 } 350 351 PCIBus *pci_register_bus(DeviceState *parent, const char *name, 352 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 353 void *irq_opaque, 354 MemoryRegion *address_space_mem, 355 MemoryRegion *address_space_io, 356 uint8_t devfn_min, int nirq, const char *typename) 357 { 358 PCIBus *bus; 359 360 bus = pci_bus_new(parent, name, address_space_mem, 361 address_space_io, devfn_min, typename); 362 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq); 363 return bus; 364 } 365 366 int pci_bus_num(PCIBus *s) 367 { 368 if (pci_bus_is_root(s)) 369 return 0; /* pci host bridge */ 370 return s->parent_dev->config[PCI_SECONDARY_BUS]; 371 } 372 373 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size) 374 { 375 PCIDevice *s = container_of(pv, PCIDevice, config); 376 uint8_t *config; 377 int i; 378 379 assert(size == pci_config_size(s)); 380 config = g_malloc(size); 381 382 qemu_get_buffer(f, config, size); 383 for (i = 0; i < size; ++i) { 384 if ((config[i] ^ s->config[i]) & 385 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) { 386 g_free(config); 387 return -EINVAL; 388 } 389 } 390 memcpy(s->config, config, size); 391 392 pci_update_mappings(s); 393 394 memory_region_set_enabled(&s->bus_master_enable_region, 395 pci_get_word(s->config + PCI_COMMAND) 396 & PCI_COMMAND_MASTER); 397 398 g_free(config); 399 return 0; 400 } 401 402 /* just put buffer */ 403 static void put_pci_config_device(QEMUFile *f, void *pv, size_t size) 404 { 405 const uint8_t **v = pv; 406 assert(size == pci_config_size(container_of(pv, PCIDevice, config))); 407 qemu_put_buffer(f, *v, size); 408 } 409 410 static VMStateInfo vmstate_info_pci_config = { 411 .name = "pci config", 412 .get = get_pci_config_device, 413 .put = put_pci_config_device, 414 }; 415 416 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size) 417 { 418 PCIDevice *s = container_of(pv, PCIDevice, irq_state); 419 uint32_t irq_state[PCI_NUM_PINS]; 420 int i; 421 for (i = 0; i < PCI_NUM_PINS; ++i) { 422 irq_state[i] = qemu_get_be32(f); 423 if (irq_state[i] != 0x1 && irq_state[i] != 0) { 424 fprintf(stderr, "irq state %d: must be 0 or 1.\n", 425 irq_state[i]); 426 return -EINVAL; 427 } 428 } 429 430 for (i = 0; i < PCI_NUM_PINS; ++i) { 431 pci_set_irq_state(s, i, irq_state[i]); 432 } 433 434 return 0; 435 } 436 437 static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size) 438 { 439 int i; 440 PCIDevice *s = container_of(pv, PCIDevice, irq_state); 441 442 for (i = 0; i < PCI_NUM_PINS; ++i) { 443 qemu_put_be32(f, pci_irq_state(s, i)); 444 } 445 } 446 447 static VMStateInfo vmstate_info_pci_irq_state = { 448 .name = "pci irq state", 449 .get = get_pci_irq_state, 450 .put = put_pci_irq_state, 451 }; 452 453 const VMStateDescription vmstate_pci_device = { 454 .name = "PCIDevice", 455 .version_id = 2, 456 .minimum_version_id = 1, 457 .minimum_version_id_old = 1, 458 .fields = (VMStateField []) { 459 VMSTATE_INT32_LE(version_id, PCIDevice), 460 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0, 461 vmstate_info_pci_config, 462 PCI_CONFIG_SPACE_SIZE), 463 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2, 464 vmstate_info_pci_irq_state, 465 PCI_NUM_PINS * sizeof(int32_t)), 466 VMSTATE_END_OF_LIST() 467 } 468 }; 469 470 const VMStateDescription vmstate_pcie_device = { 471 .name = "PCIEDevice", 472 .version_id = 2, 473 .minimum_version_id = 1, 474 .minimum_version_id_old = 1, 475 .fields = (VMStateField []) { 476 VMSTATE_INT32_LE(version_id, PCIDevice), 477 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0, 478 vmstate_info_pci_config, 479 PCIE_CONFIG_SPACE_SIZE), 480 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2, 481 vmstate_info_pci_irq_state, 482 PCI_NUM_PINS * sizeof(int32_t)), 483 VMSTATE_END_OF_LIST() 484 } 485 }; 486 487 static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s) 488 { 489 return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device; 490 } 491 492 void pci_device_save(PCIDevice *s, QEMUFile *f) 493 { 494 /* Clear interrupt status bit: it is implicit 495 * in irq_state which we are saving. 496 * This makes us compatible with old devices 497 * which never set or clear this bit. */ 498 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; 499 vmstate_save_state(f, pci_get_vmstate(s), s); 500 /* Restore the interrupt status bit. */ 501 pci_update_irq_status(s); 502 } 503 504 int pci_device_load(PCIDevice *s, QEMUFile *f) 505 { 506 int ret; 507 ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id); 508 /* Restore the interrupt status bit. */ 509 pci_update_irq_status(s); 510 return ret; 511 } 512 513 static void pci_set_default_subsystem_id(PCIDevice *pci_dev) 514 { 515 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, 516 pci_default_sub_vendor_id); 517 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 518 pci_default_sub_device_id); 519 } 520 521 /* 522 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL 523 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error 524 */ 525 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, 526 unsigned int *slotp, unsigned int *funcp) 527 { 528 const char *p; 529 char *e; 530 unsigned long val; 531 unsigned long dom = 0, bus = 0; 532 unsigned int slot = 0; 533 unsigned int func = 0; 534 535 p = addr; 536 val = strtoul(p, &e, 16); 537 if (e == p) 538 return -1; 539 if (*e == ':') { 540 bus = val; 541 p = e + 1; 542 val = strtoul(p, &e, 16); 543 if (e == p) 544 return -1; 545 if (*e == ':') { 546 dom = bus; 547 bus = val; 548 p = e + 1; 549 val = strtoul(p, &e, 16); 550 if (e == p) 551 return -1; 552 } 553 } 554 555 slot = val; 556 557 if (funcp != NULL) { 558 if (*e != '.') 559 return -1; 560 561 p = e + 1; 562 val = strtoul(p, &e, 16); 563 if (e == p) 564 return -1; 565 566 func = val; 567 } 568 569 /* if funcp == NULL func is 0 */ 570 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7) 571 return -1; 572 573 if (*e) 574 return -1; 575 576 *domp = dom; 577 *busp = bus; 578 *slotp = slot; 579 if (funcp != NULL) 580 *funcp = func; 581 return 0; 582 } 583 584 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp, 585 unsigned *slotp) 586 { 587 /* strip legacy tag */ 588 if (!strncmp(addr, "pci_addr=", 9)) { 589 addr += 9; 590 } 591 if (pci_parse_devaddr(addr, domp, busp, slotp, NULL)) { 592 monitor_printf(mon, "Invalid pci address\n"); 593 return -1; 594 } 595 return 0; 596 } 597 598 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr) 599 { 600 int dom, bus; 601 unsigned slot; 602 603 if (!devaddr) { 604 *devfnp = -1; 605 return pci_find_bus_nr(pci_find_root_bus(0), 0); 606 } 607 608 if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) { 609 return NULL; 610 } 611 612 *devfnp = PCI_DEVFN(slot, 0); 613 return pci_find_bus_nr(pci_find_root_bus(dom), bus); 614 } 615 616 static void pci_init_cmask(PCIDevice *dev) 617 { 618 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff); 619 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff); 620 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST; 621 dev->cmask[PCI_REVISION_ID] = 0xff; 622 dev->cmask[PCI_CLASS_PROG] = 0xff; 623 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff); 624 dev->cmask[PCI_HEADER_TYPE] = 0xff; 625 dev->cmask[PCI_CAPABILITY_LIST] = 0xff; 626 } 627 628 static void pci_init_wmask(PCIDevice *dev) 629 { 630 int config_size = pci_config_size(dev); 631 632 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff; 633 dev->wmask[PCI_INTERRUPT_LINE] = 0xff; 634 pci_set_word(dev->wmask + PCI_COMMAND, 635 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | 636 PCI_COMMAND_INTX_DISABLE); 637 if (dev->cap_present & QEMU_PCI_CAP_SERR) { 638 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR); 639 } 640 641 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff, 642 config_size - PCI_CONFIG_HEADER_SIZE); 643 } 644 645 static void pci_init_w1cmask(PCIDevice *dev) 646 { 647 /* 648 * Note: It's okay to set w1cmask even for readonly bits as 649 * long as their value is hardwired to 0. 650 */ 651 pci_set_word(dev->w1cmask + PCI_STATUS, 652 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT | 653 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT | 654 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY); 655 } 656 657 static void pci_init_mask_bridge(PCIDevice *d) 658 { 659 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and 660 PCI_SEC_LETENCY_TIMER */ 661 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4); 662 663 /* base and limit */ 664 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff; 665 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff; 666 pci_set_word(d->wmask + PCI_MEMORY_BASE, 667 PCI_MEMORY_RANGE_MASK & 0xffff); 668 pci_set_word(d->wmask + PCI_MEMORY_LIMIT, 669 PCI_MEMORY_RANGE_MASK & 0xffff); 670 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE, 671 PCI_PREF_RANGE_MASK & 0xffff); 672 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT, 673 PCI_PREF_RANGE_MASK & 0xffff); 674 675 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */ 676 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8); 677 678 /* Supported memory and i/o types */ 679 d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16; 680 d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16; 681 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE, 682 PCI_PREF_RANGE_TYPE_64); 683 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT, 684 PCI_PREF_RANGE_TYPE_64); 685 686 /* 687 * TODO: Bridges default to 10-bit VGA decoding but we currently only 688 * implement 16-bit decoding (no alias support). 689 */ 690 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 691 PCI_BRIDGE_CTL_PARITY | 692 PCI_BRIDGE_CTL_SERR | 693 PCI_BRIDGE_CTL_ISA | 694 PCI_BRIDGE_CTL_VGA | 695 PCI_BRIDGE_CTL_VGA_16BIT | 696 PCI_BRIDGE_CTL_MASTER_ABORT | 697 PCI_BRIDGE_CTL_BUS_RESET | 698 PCI_BRIDGE_CTL_FAST_BACK | 699 PCI_BRIDGE_CTL_DISCARD | 700 PCI_BRIDGE_CTL_SEC_DISCARD | 701 PCI_BRIDGE_CTL_DISCARD_SERR); 702 /* Below does not do anything as we never set this bit, put here for 703 * completeness. */ 704 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL, 705 PCI_BRIDGE_CTL_DISCARD_STATUS); 706 d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK; 707 d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK; 708 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE, 709 PCI_PREF_RANGE_TYPE_MASK); 710 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT, 711 PCI_PREF_RANGE_TYPE_MASK); 712 } 713 714 static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev) 715 { 716 uint8_t slot = PCI_SLOT(dev->devfn); 717 uint8_t func; 718 719 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 720 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION; 721 } 722 723 /* 724 * multifunction bit is interpreted in two ways as follows. 725 * - all functions must set the bit to 1. 726 * Example: Intel X53 727 * - function 0 must set the bit, but the rest function (> 0) 728 * is allowed to leave the bit to 0. 729 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10, 730 * 731 * So OS (at least Linux) checks the bit of only function 0, 732 * and doesn't see the bit of function > 0. 733 * 734 * The below check allows both interpretation. 735 */ 736 if (PCI_FUNC(dev->devfn)) { 737 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)]; 738 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) { 739 /* function 0 should set multifunction bit */ 740 error_report("PCI: single function device can't be populated " 741 "in function %x.%x", slot, PCI_FUNC(dev->devfn)); 742 return -1; 743 } 744 return 0; 745 } 746 747 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 748 return 0; 749 } 750 /* function 0 indicates single function, so function > 0 must be NULL */ 751 for (func = 1; func < PCI_FUNC_MAX; ++func) { 752 if (bus->devices[PCI_DEVFN(slot, func)]) { 753 error_report("PCI: %x.0 indicates single function, " 754 "but %x.%x is already populated.", 755 slot, slot, func); 756 return -1; 757 } 758 } 759 return 0; 760 } 761 762 static void pci_config_alloc(PCIDevice *pci_dev) 763 { 764 int config_size = pci_config_size(pci_dev); 765 766 pci_dev->config = g_malloc0(config_size); 767 pci_dev->cmask = g_malloc0(config_size); 768 pci_dev->wmask = g_malloc0(config_size); 769 pci_dev->w1cmask = g_malloc0(config_size); 770 pci_dev->used = g_malloc0(config_size); 771 } 772 773 static void pci_config_free(PCIDevice *pci_dev) 774 { 775 g_free(pci_dev->config); 776 g_free(pci_dev->cmask); 777 g_free(pci_dev->wmask); 778 g_free(pci_dev->w1cmask); 779 g_free(pci_dev->used); 780 } 781 782 /* -1 for devfn means auto assign */ 783 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus, 784 const char *name, int devfn) 785 { 786 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 787 PCIConfigReadFunc *config_read = pc->config_read; 788 PCIConfigWriteFunc *config_write = pc->config_write; 789 AddressSpace *dma_as; 790 791 if (devfn < 0) { 792 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices); 793 devfn += PCI_FUNC_MAX) { 794 if (!bus->devices[devfn]) 795 goto found; 796 } 797 error_report("PCI: no slot/function available for %s, all in use", name); 798 return NULL; 799 found: ; 800 } else if (bus->devices[devfn]) { 801 error_report("PCI: slot %d function %d not available for %s, in use by %s", 802 PCI_SLOT(devfn), PCI_FUNC(devfn), name, bus->devices[devfn]->name); 803 return NULL; 804 } 805 806 pci_dev->bus = bus; 807 if (bus->iommu_fn) { 808 dma_as = bus->iommu_fn(bus, bus->iommu_opaque, devfn); 809 } else { 810 /* FIXME: inherit memory region from bus creator */ 811 dma_as = &address_space_memory; 812 } 813 814 memory_region_init_alias(&pci_dev->bus_master_enable_region, 815 OBJECT(pci_dev), "bus master", 816 dma_as->root, 0, memory_region_size(dma_as->root)); 817 memory_region_set_enabled(&pci_dev->bus_master_enable_region, false); 818 address_space_init(&pci_dev->bus_master_as, &pci_dev->bus_master_enable_region, 819 name); 820 821 pci_dev->devfn = devfn; 822 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name); 823 pci_dev->irq_state = 0; 824 pci_config_alloc(pci_dev); 825 826 pci_config_set_vendor_id(pci_dev->config, pc->vendor_id); 827 pci_config_set_device_id(pci_dev->config, pc->device_id); 828 pci_config_set_revision(pci_dev->config, pc->revision); 829 pci_config_set_class(pci_dev->config, pc->class_id); 830 831 if (!pc->is_bridge) { 832 if (pc->subsystem_vendor_id || pc->subsystem_id) { 833 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, 834 pc->subsystem_vendor_id); 835 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 836 pc->subsystem_id); 837 } else { 838 pci_set_default_subsystem_id(pci_dev); 839 } 840 } else { 841 /* subsystem_vendor_id/subsystem_id are only for header type 0 */ 842 assert(!pc->subsystem_vendor_id); 843 assert(!pc->subsystem_id); 844 } 845 pci_init_cmask(pci_dev); 846 pci_init_wmask(pci_dev); 847 pci_init_w1cmask(pci_dev); 848 if (pc->is_bridge) { 849 pci_init_mask_bridge(pci_dev); 850 } 851 if (pci_init_multifunction(bus, pci_dev)) { 852 pci_config_free(pci_dev); 853 return NULL; 854 } 855 856 if (!config_read) 857 config_read = pci_default_read_config; 858 if (!config_write) 859 config_write = pci_default_write_config; 860 pci_dev->config_read = config_read; 861 pci_dev->config_write = config_write; 862 bus->devices[devfn] = pci_dev; 863 pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS); 864 pci_dev->version_id = 2; /* Current pci device vmstate version */ 865 return pci_dev; 866 } 867 868 static void do_pci_unregister_device(PCIDevice *pci_dev) 869 { 870 qemu_free_irqs(pci_dev->irq); 871 pci_dev->bus->devices[pci_dev->devfn] = NULL; 872 pci_config_free(pci_dev); 873 874 address_space_destroy(&pci_dev->bus_master_as); 875 memory_region_destroy(&pci_dev->bus_master_enable_region); 876 } 877 878 static void pci_unregister_io_regions(PCIDevice *pci_dev) 879 { 880 PCIIORegion *r; 881 int i; 882 883 for(i = 0; i < PCI_NUM_REGIONS; i++) { 884 r = &pci_dev->io_regions[i]; 885 if (!r->size || r->addr == PCI_BAR_UNMAPPED) 886 continue; 887 memory_region_del_subregion(r->address_space, r->memory); 888 } 889 890 pci_unregister_vga(pci_dev); 891 } 892 893 static int pci_unregister_device(DeviceState *dev) 894 { 895 PCIDevice *pci_dev = PCI_DEVICE(dev); 896 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 897 898 pci_unregister_io_regions(pci_dev); 899 pci_del_option_rom(pci_dev); 900 901 if (pc->exit) { 902 pc->exit(pci_dev); 903 } 904 905 do_pci_unregister_device(pci_dev); 906 return 0; 907 } 908 909 void pci_register_bar(PCIDevice *pci_dev, int region_num, 910 uint8_t type, MemoryRegion *memory) 911 { 912 PCIIORegion *r; 913 uint32_t addr; 914 uint64_t wmask; 915 pcibus_t size = memory_region_size(memory); 916 917 assert(region_num >= 0); 918 assert(region_num < PCI_NUM_REGIONS); 919 if (size & (size-1)) { 920 fprintf(stderr, "ERROR: PCI region size must be pow2 " 921 "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size); 922 exit(1); 923 } 924 925 r = &pci_dev->io_regions[region_num]; 926 r->addr = PCI_BAR_UNMAPPED; 927 r->size = size; 928 r->type = type; 929 r->memory = NULL; 930 931 wmask = ~(size - 1); 932 addr = pci_bar(pci_dev, region_num); 933 if (region_num == PCI_ROM_SLOT) { 934 /* ROM enable bit is writable */ 935 wmask |= PCI_ROM_ADDRESS_ENABLE; 936 } 937 pci_set_long(pci_dev->config + addr, type); 938 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) && 939 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 940 pci_set_quad(pci_dev->wmask + addr, wmask); 941 pci_set_quad(pci_dev->cmask + addr, ~0ULL); 942 } else { 943 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff); 944 pci_set_long(pci_dev->cmask + addr, 0xffffffff); 945 } 946 pci_dev->io_regions[region_num].memory = memory; 947 pci_dev->io_regions[region_num].address_space 948 = type & PCI_BASE_ADDRESS_SPACE_IO 949 ? pci_dev->bus->address_space_io 950 : pci_dev->bus->address_space_mem; 951 } 952 953 static void pci_update_vga(PCIDevice *pci_dev) 954 { 955 uint16_t cmd; 956 957 if (!pci_dev->has_vga) { 958 return; 959 } 960 961 cmd = pci_get_word(pci_dev->config + PCI_COMMAND); 962 963 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_MEM], 964 cmd & PCI_COMMAND_MEMORY); 965 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO], 966 cmd & PCI_COMMAND_IO); 967 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI], 968 cmd & PCI_COMMAND_IO); 969 } 970 971 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, 972 MemoryRegion *io_lo, MemoryRegion *io_hi) 973 { 974 assert(!pci_dev->has_vga); 975 976 assert(memory_region_size(mem) == QEMU_PCI_VGA_MEM_SIZE); 977 pci_dev->vga_regions[QEMU_PCI_VGA_MEM] = mem; 978 memory_region_add_subregion_overlap(pci_dev->bus->address_space_mem, 979 QEMU_PCI_VGA_MEM_BASE, mem, 1); 980 981 assert(memory_region_size(io_lo) == QEMU_PCI_VGA_IO_LO_SIZE); 982 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO] = io_lo; 983 memory_region_add_subregion_overlap(pci_dev->bus->address_space_io, 984 QEMU_PCI_VGA_IO_LO_BASE, io_lo, 1); 985 986 assert(memory_region_size(io_hi) == QEMU_PCI_VGA_IO_HI_SIZE); 987 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI] = io_hi; 988 memory_region_add_subregion_overlap(pci_dev->bus->address_space_io, 989 QEMU_PCI_VGA_IO_HI_BASE, io_hi, 1); 990 pci_dev->has_vga = true; 991 992 pci_update_vga(pci_dev); 993 } 994 995 void pci_unregister_vga(PCIDevice *pci_dev) 996 { 997 if (!pci_dev->has_vga) { 998 return; 999 } 1000 1001 memory_region_del_subregion(pci_dev->bus->address_space_mem, 1002 pci_dev->vga_regions[QEMU_PCI_VGA_MEM]); 1003 memory_region_del_subregion(pci_dev->bus->address_space_io, 1004 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO]); 1005 memory_region_del_subregion(pci_dev->bus->address_space_io, 1006 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI]); 1007 pci_dev->has_vga = false; 1008 } 1009 1010 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num) 1011 { 1012 return pci_dev->io_regions[region_num].addr; 1013 } 1014 1015 static pcibus_t pci_bar_address(PCIDevice *d, 1016 int reg, uint8_t type, pcibus_t size) 1017 { 1018 pcibus_t new_addr, last_addr; 1019 int bar = pci_bar(d, reg); 1020 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND); 1021 1022 if (type & PCI_BASE_ADDRESS_SPACE_IO) { 1023 if (!(cmd & PCI_COMMAND_IO)) { 1024 return PCI_BAR_UNMAPPED; 1025 } 1026 new_addr = pci_get_long(d->config + bar) & ~(size - 1); 1027 last_addr = new_addr + size - 1; 1028 /* NOTE: we have only 64K ioports on PC */ 1029 if (last_addr <= new_addr || new_addr == 0 || last_addr > UINT16_MAX) { 1030 return PCI_BAR_UNMAPPED; 1031 } 1032 return new_addr; 1033 } 1034 1035 if (!(cmd & PCI_COMMAND_MEMORY)) { 1036 return PCI_BAR_UNMAPPED; 1037 } 1038 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 1039 new_addr = pci_get_quad(d->config + bar); 1040 } else { 1041 new_addr = pci_get_long(d->config + bar); 1042 } 1043 /* the ROM slot has a specific enable bit */ 1044 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) { 1045 return PCI_BAR_UNMAPPED; 1046 } 1047 new_addr &= ~(size - 1); 1048 last_addr = new_addr + size - 1; 1049 /* NOTE: we do not support wrapping */ 1050 /* XXX: as we cannot support really dynamic 1051 mappings, we handle specific values as invalid 1052 mappings. */ 1053 if (last_addr <= new_addr || new_addr == 0 || 1054 last_addr == PCI_BAR_UNMAPPED) { 1055 return PCI_BAR_UNMAPPED; 1056 } 1057 1058 /* Now pcibus_t is 64bit. 1059 * Check if 32 bit BAR wraps around explicitly. 1060 * Without this, PC ide doesn't work well. 1061 * TODO: remove this work around. 1062 */ 1063 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) { 1064 return PCI_BAR_UNMAPPED; 1065 } 1066 1067 /* 1068 * OS is allowed to set BAR beyond its addressable 1069 * bits. For example, 32 bit OS can set 64bit bar 1070 * to >4G. Check it. TODO: we might need to support 1071 * it in the future for e.g. PAE. 1072 */ 1073 if (last_addr >= HWADDR_MAX) { 1074 return PCI_BAR_UNMAPPED; 1075 } 1076 1077 return new_addr; 1078 } 1079 1080 static void pci_update_mappings(PCIDevice *d) 1081 { 1082 PCIIORegion *r; 1083 int i; 1084 pcibus_t new_addr; 1085 1086 for(i = 0; i < PCI_NUM_REGIONS; i++) { 1087 r = &d->io_regions[i]; 1088 1089 /* this region isn't registered */ 1090 if (!r->size) 1091 continue; 1092 1093 new_addr = pci_bar_address(d, i, r->type, r->size); 1094 1095 /* This bar isn't changed */ 1096 if (new_addr == r->addr) 1097 continue; 1098 1099 /* now do the real mapping */ 1100 if (r->addr != PCI_BAR_UNMAPPED) { 1101 memory_region_del_subregion(r->address_space, r->memory); 1102 } 1103 r->addr = new_addr; 1104 if (r->addr != PCI_BAR_UNMAPPED) { 1105 memory_region_add_subregion_overlap(r->address_space, 1106 r->addr, r->memory, 1); 1107 } 1108 } 1109 1110 pci_update_vga(d); 1111 } 1112 1113 static inline int pci_irq_disabled(PCIDevice *d) 1114 { 1115 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE; 1116 } 1117 1118 /* Called after interrupt disabled field update in config space, 1119 * assert/deassert interrupts if necessary. 1120 * Gets original interrupt disable bit value (before update). */ 1121 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled) 1122 { 1123 int i, disabled = pci_irq_disabled(d); 1124 if (disabled == was_irq_disabled) 1125 return; 1126 for (i = 0; i < PCI_NUM_PINS; ++i) { 1127 int state = pci_irq_state(d, i); 1128 pci_change_irq_level(d, i, disabled ? -state : state); 1129 } 1130 } 1131 1132 uint32_t pci_default_read_config(PCIDevice *d, 1133 uint32_t address, int len) 1134 { 1135 uint32_t val = 0; 1136 1137 memcpy(&val, d->config + address, len); 1138 return le32_to_cpu(val); 1139 } 1140 1141 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l) 1142 { 1143 int i, was_irq_disabled = pci_irq_disabled(d); 1144 1145 for (i = 0; i < l; val >>= 8, ++i) { 1146 uint8_t wmask = d->wmask[addr + i]; 1147 uint8_t w1cmask = d->w1cmask[addr + i]; 1148 assert(!(wmask & w1cmask)); 1149 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask); 1150 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */ 1151 } 1152 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) || 1153 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) || 1154 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) || 1155 range_covers_byte(addr, l, PCI_COMMAND)) 1156 pci_update_mappings(d); 1157 1158 if (range_covers_byte(addr, l, PCI_COMMAND)) { 1159 pci_update_irq_disabled(d, was_irq_disabled); 1160 memory_region_set_enabled(&d->bus_master_enable_region, 1161 pci_get_word(d->config + PCI_COMMAND) 1162 & PCI_COMMAND_MASTER); 1163 } 1164 1165 msi_write_config(d, addr, val, l); 1166 msix_write_config(d, addr, val, l); 1167 } 1168 1169 /***********************************************************/ 1170 /* generic PCI irq support */ 1171 1172 /* 0 <= irq_num <= 3. level must be 0 or 1 */ 1173 static void pci_set_irq(void *opaque, int irq_num, int level) 1174 { 1175 PCIDevice *pci_dev = opaque; 1176 int change; 1177 1178 change = level - pci_irq_state(pci_dev, irq_num); 1179 if (!change) 1180 return; 1181 1182 pci_set_irq_state(pci_dev, irq_num, level); 1183 pci_update_irq_status(pci_dev); 1184 if (pci_irq_disabled(pci_dev)) 1185 return; 1186 pci_change_irq_level(pci_dev, irq_num, change); 1187 } 1188 1189 /* Special hooks used by device assignment */ 1190 void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq) 1191 { 1192 assert(pci_bus_is_root(bus)); 1193 bus->route_intx_to_irq = route_intx_to_irq; 1194 } 1195 1196 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin) 1197 { 1198 PCIBus *bus; 1199 1200 do { 1201 bus = dev->bus; 1202 pin = bus->map_irq(dev, pin); 1203 dev = bus->parent_dev; 1204 } while (dev); 1205 1206 if (!bus->route_intx_to_irq) { 1207 error_report("PCI: Bug - unimplemented PCI INTx routing (%s)", 1208 object_get_typename(OBJECT(bus->qbus.parent))); 1209 return (PCIINTxRoute) { PCI_INTX_DISABLED, -1 }; 1210 } 1211 1212 return bus->route_intx_to_irq(bus->irq_opaque, pin); 1213 } 1214 1215 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new) 1216 { 1217 return old->mode != new->mode || old->irq != new->irq; 1218 } 1219 1220 void pci_bus_fire_intx_routing_notifier(PCIBus *bus) 1221 { 1222 PCIDevice *dev; 1223 PCIBus *sec; 1224 int i; 1225 1226 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 1227 dev = bus->devices[i]; 1228 if (dev && dev->intx_routing_notifier) { 1229 dev->intx_routing_notifier(dev); 1230 } 1231 } 1232 1233 QLIST_FOREACH(sec, &bus->child, sibling) { 1234 pci_bus_fire_intx_routing_notifier(sec); 1235 } 1236 } 1237 1238 void pci_device_set_intx_routing_notifier(PCIDevice *dev, 1239 PCIINTxRoutingNotifier notifier) 1240 { 1241 dev->intx_routing_notifier = notifier; 1242 } 1243 1244 /* 1245 * PCI-to-PCI bridge specification 1246 * 9.1: Interrupt routing. Table 9-1 1247 * 1248 * the PCI Express Base Specification, Revision 2.1 1249 * 2.2.8.1: INTx interrutp signaling - Rules 1250 * the Implementation Note 1251 * Table 2-20 1252 */ 1253 /* 1254 * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD 1255 * 0-origin unlike PCI interrupt pin register. 1256 */ 1257 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin) 1258 { 1259 return (pin + PCI_SLOT(pci_dev->devfn)) % PCI_NUM_PINS; 1260 } 1261 1262 /***********************************************************/ 1263 /* monitor info on PCI */ 1264 1265 typedef struct { 1266 uint16_t class; 1267 const char *desc; 1268 const char *fw_name; 1269 uint16_t fw_ign_bits; 1270 } pci_class_desc; 1271 1272 static const pci_class_desc pci_class_descriptions[] = 1273 { 1274 { 0x0001, "VGA controller", "display"}, 1275 { 0x0100, "SCSI controller", "scsi"}, 1276 { 0x0101, "IDE controller", "ide"}, 1277 { 0x0102, "Floppy controller", "fdc"}, 1278 { 0x0103, "IPI controller", "ipi"}, 1279 { 0x0104, "RAID controller", "raid"}, 1280 { 0x0106, "SATA controller"}, 1281 { 0x0107, "SAS controller"}, 1282 { 0x0180, "Storage controller"}, 1283 { 0x0200, "Ethernet controller", "ethernet"}, 1284 { 0x0201, "Token Ring controller", "token-ring"}, 1285 { 0x0202, "FDDI controller", "fddi"}, 1286 { 0x0203, "ATM controller", "atm"}, 1287 { 0x0280, "Network controller"}, 1288 { 0x0300, "VGA controller", "display", 0x00ff}, 1289 { 0x0301, "XGA controller"}, 1290 { 0x0302, "3D controller"}, 1291 { 0x0380, "Display controller"}, 1292 { 0x0400, "Video controller", "video"}, 1293 { 0x0401, "Audio controller", "sound"}, 1294 { 0x0402, "Phone"}, 1295 { 0x0403, "Audio controller", "sound"}, 1296 { 0x0480, "Multimedia controller"}, 1297 { 0x0500, "RAM controller", "memory"}, 1298 { 0x0501, "Flash controller", "flash"}, 1299 { 0x0580, "Memory controller"}, 1300 { 0x0600, "Host bridge", "host"}, 1301 { 0x0601, "ISA bridge", "isa"}, 1302 { 0x0602, "EISA bridge", "eisa"}, 1303 { 0x0603, "MC bridge", "mca"}, 1304 { 0x0604, "PCI bridge", "pci"}, 1305 { 0x0605, "PCMCIA bridge", "pcmcia"}, 1306 { 0x0606, "NUBUS bridge", "nubus"}, 1307 { 0x0607, "CARDBUS bridge", "cardbus"}, 1308 { 0x0608, "RACEWAY bridge"}, 1309 { 0x0680, "Bridge"}, 1310 { 0x0700, "Serial port", "serial"}, 1311 { 0x0701, "Parallel port", "parallel"}, 1312 { 0x0800, "Interrupt controller", "interrupt-controller"}, 1313 { 0x0801, "DMA controller", "dma-controller"}, 1314 { 0x0802, "Timer", "timer"}, 1315 { 0x0803, "RTC", "rtc"}, 1316 { 0x0900, "Keyboard", "keyboard"}, 1317 { 0x0901, "Pen", "pen"}, 1318 { 0x0902, "Mouse", "mouse"}, 1319 { 0x0A00, "Dock station", "dock", 0x00ff}, 1320 { 0x0B00, "i386 cpu", "cpu", 0x00ff}, 1321 { 0x0c00, "Fireware contorller", "fireware"}, 1322 { 0x0c01, "Access bus controller", "access-bus"}, 1323 { 0x0c02, "SSA controller", "ssa"}, 1324 { 0x0c03, "USB controller", "usb"}, 1325 { 0x0c04, "Fibre channel controller", "fibre-channel"}, 1326 { 0x0c05, "SMBus"}, 1327 { 0, NULL} 1328 }; 1329 1330 static void pci_for_each_device_under_bus(PCIBus *bus, 1331 void (*fn)(PCIBus *b, PCIDevice *d, 1332 void *opaque), 1333 void *opaque) 1334 { 1335 PCIDevice *d; 1336 int devfn; 1337 1338 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1339 d = bus->devices[devfn]; 1340 if (d) { 1341 fn(bus, d, opaque); 1342 } 1343 } 1344 } 1345 1346 void pci_for_each_device(PCIBus *bus, int bus_num, 1347 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque), 1348 void *opaque) 1349 { 1350 bus = pci_find_bus_nr(bus, bus_num); 1351 1352 if (bus) { 1353 pci_for_each_device_under_bus(bus, fn, opaque); 1354 } 1355 } 1356 1357 static const pci_class_desc *get_class_desc(int class) 1358 { 1359 const pci_class_desc *desc; 1360 1361 desc = pci_class_descriptions; 1362 while (desc->desc && class != desc->class) { 1363 desc++; 1364 } 1365 1366 return desc; 1367 } 1368 1369 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num); 1370 1371 static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev) 1372 { 1373 PciMemoryRegionList *head = NULL, *cur_item = NULL; 1374 int i; 1375 1376 for (i = 0; i < PCI_NUM_REGIONS; i++) { 1377 const PCIIORegion *r = &dev->io_regions[i]; 1378 PciMemoryRegionList *region; 1379 1380 if (!r->size) { 1381 continue; 1382 } 1383 1384 region = g_malloc0(sizeof(*region)); 1385 region->value = g_malloc0(sizeof(*region->value)); 1386 1387 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { 1388 region->value->type = g_strdup("io"); 1389 } else { 1390 region->value->type = g_strdup("memory"); 1391 region->value->has_prefetch = true; 1392 region->value->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH); 1393 region->value->has_mem_type_64 = true; 1394 region->value->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64); 1395 } 1396 1397 region->value->bar = i; 1398 region->value->address = r->addr; 1399 region->value->size = r->size; 1400 1401 /* XXX: waiting for the qapi to support GSList */ 1402 if (!cur_item) { 1403 head = cur_item = region; 1404 } else { 1405 cur_item->next = region; 1406 cur_item = region; 1407 } 1408 } 1409 1410 return head; 1411 } 1412 1413 static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus, 1414 int bus_num) 1415 { 1416 PciBridgeInfo *info; 1417 1418 info = g_malloc0(sizeof(*info)); 1419 1420 info->bus.number = dev->config[PCI_PRIMARY_BUS]; 1421 info->bus.secondary = dev->config[PCI_SECONDARY_BUS]; 1422 info->bus.subordinate = dev->config[PCI_SUBORDINATE_BUS]; 1423 1424 info->bus.io_range = g_malloc0(sizeof(*info->bus.io_range)); 1425 info->bus.io_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO); 1426 info->bus.io_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO); 1427 1428 info->bus.memory_range = g_malloc0(sizeof(*info->bus.memory_range)); 1429 info->bus.memory_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 1430 info->bus.memory_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 1431 1432 info->bus.prefetchable_range = g_malloc0(sizeof(*info->bus.prefetchable_range)); 1433 info->bus.prefetchable_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 1434 info->bus.prefetchable_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 1435 1436 if (dev->config[PCI_SECONDARY_BUS] != 0) { 1437 PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]); 1438 if (child_bus) { 1439 info->has_devices = true; 1440 info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]); 1441 } 1442 } 1443 1444 return info; 1445 } 1446 1447 static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus, 1448 int bus_num) 1449 { 1450 const pci_class_desc *desc; 1451 PciDeviceInfo *info; 1452 uint8_t type; 1453 int class; 1454 1455 info = g_malloc0(sizeof(*info)); 1456 info->bus = bus_num; 1457 info->slot = PCI_SLOT(dev->devfn); 1458 info->function = PCI_FUNC(dev->devfn); 1459 1460 class = pci_get_word(dev->config + PCI_CLASS_DEVICE); 1461 info->class_info.class = class; 1462 desc = get_class_desc(class); 1463 if (desc->desc) { 1464 info->class_info.has_desc = true; 1465 info->class_info.desc = g_strdup(desc->desc); 1466 } 1467 1468 info->id.vendor = pci_get_word(dev->config + PCI_VENDOR_ID); 1469 info->id.device = pci_get_word(dev->config + PCI_DEVICE_ID); 1470 info->regions = qmp_query_pci_regions(dev); 1471 info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : ""); 1472 1473 if (dev->config[PCI_INTERRUPT_PIN] != 0) { 1474 info->has_irq = true; 1475 info->irq = dev->config[PCI_INTERRUPT_LINE]; 1476 } 1477 1478 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 1479 if (type == PCI_HEADER_TYPE_BRIDGE) { 1480 info->has_pci_bridge = true; 1481 info->pci_bridge = qmp_query_pci_bridge(dev, bus, bus_num); 1482 } 1483 1484 return info; 1485 } 1486 1487 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num) 1488 { 1489 PciDeviceInfoList *info, *head = NULL, *cur_item = NULL; 1490 PCIDevice *dev; 1491 int devfn; 1492 1493 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1494 dev = bus->devices[devfn]; 1495 if (dev) { 1496 info = g_malloc0(sizeof(*info)); 1497 info->value = qmp_query_pci_device(dev, bus, bus_num); 1498 1499 /* XXX: waiting for the qapi to support GSList */ 1500 if (!cur_item) { 1501 head = cur_item = info; 1502 } else { 1503 cur_item->next = info; 1504 cur_item = info; 1505 } 1506 } 1507 } 1508 1509 return head; 1510 } 1511 1512 static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num) 1513 { 1514 PciInfo *info = NULL; 1515 1516 bus = pci_find_bus_nr(bus, bus_num); 1517 if (bus) { 1518 info = g_malloc0(sizeof(*info)); 1519 info->bus = bus_num; 1520 info->devices = qmp_query_pci_devices(bus, bus_num); 1521 } 1522 1523 return info; 1524 } 1525 1526 PciInfoList *qmp_query_pci(Error **errp) 1527 { 1528 PciInfoList *info, *head = NULL, *cur_item = NULL; 1529 struct PCIHostBus *host; 1530 1531 QLIST_FOREACH(host, &host_buses, next) { 1532 info = g_malloc0(sizeof(*info)); 1533 info->value = qmp_query_pci_bus(host->bus, 0); 1534 1535 /* XXX: waiting for the qapi to support GSList */ 1536 if (!cur_item) { 1537 head = cur_item = info; 1538 } else { 1539 cur_item->next = info; 1540 cur_item = info; 1541 } 1542 } 1543 1544 return head; 1545 } 1546 1547 static const char * const pci_nic_models[] = { 1548 "ne2k_pci", 1549 "i82551", 1550 "i82557b", 1551 "i82559er", 1552 "rtl8139", 1553 "e1000", 1554 "pcnet", 1555 "virtio", 1556 NULL 1557 }; 1558 1559 static const char * const pci_nic_names[] = { 1560 "ne2k_pci", 1561 "i82551", 1562 "i82557b", 1563 "i82559er", 1564 "rtl8139", 1565 "e1000", 1566 "pcnet", 1567 "virtio-net-pci", 1568 NULL 1569 }; 1570 1571 /* Initialize a PCI NIC. */ 1572 /* FIXME callers should check for failure, but don't */ 1573 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model, 1574 const char *default_devaddr) 1575 { 1576 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr; 1577 PCIBus *bus; 1578 int devfn; 1579 PCIDevice *pci_dev; 1580 DeviceState *dev; 1581 int i; 1582 1583 i = qemu_find_nic_model(nd, pci_nic_models, default_model); 1584 if (i < 0) 1585 return NULL; 1586 1587 bus = pci_get_bus_devfn(&devfn, devaddr); 1588 if (!bus) { 1589 error_report("Invalid PCI device address %s for device %s", 1590 devaddr, pci_nic_names[i]); 1591 return NULL; 1592 } 1593 1594 pci_dev = pci_create(bus, devfn, pci_nic_names[i]); 1595 dev = &pci_dev->qdev; 1596 qdev_set_nic_properties(dev, nd); 1597 if (qdev_init(dev) < 0) 1598 return NULL; 1599 return pci_dev; 1600 } 1601 1602 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model, 1603 const char *default_devaddr) 1604 { 1605 PCIDevice *res; 1606 1607 if (qemu_show_nic_models(nd->model, pci_nic_models)) 1608 exit(0); 1609 1610 res = pci_nic_init(nd, default_model, default_devaddr); 1611 if (!res) 1612 exit(1); 1613 return res; 1614 } 1615 1616 PCIDevice *pci_vga_init(PCIBus *bus) 1617 { 1618 switch (vga_interface_type) { 1619 case VGA_CIRRUS: 1620 return pci_create_simple(bus, -1, "cirrus-vga"); 1621 case VGA_QXL: 1622 return pci_create_simple(bus, -1, "qxl-vga"); 1623 case VGA_STD: 1624 return pci_create_simple(bus, -1, "VGA"); 1625 case VGA_VMWARE: 1626 return pci_create_simple(bus, -1, "vmware-svga"); 1627 case VGA_NONE: 1628 default: /* Other non-PCI types. Checking for unsupported types is already 1629 done in vl.c. */ 1630 return NULL; 1631 } 1632 } 1633 1634 /* Whether a given bus number is in range of the secondary 1635 * bus of the given bridge device. */ 1636 static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num) 1637 { 1638 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) & 1639 PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ && 1640 dev->config[PCI_SECONDARY_BUS] < bus_num && 1641 bus_num <= dev->config[PCI_SUBORDINATE_BUS]; 1642 } 1643 1644 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num) 1645 { 1646 PCIBus *sec; 1647 1648 if (!bus) { 1649 return NULL; 1650 } 1651 1652 if (pci_bus_num(bus) == bus_num) { 1653 return bus; 1654 } 1655 1656 /* Consider all bus numbers in range for the host pci bridge. */ 1657 if (!pci_bus_is_root(bus) && 1658 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) { 1659 return NULL; 1660 } 1661 1662 /* try child bus */ 1663 for (; bus; bus = sec) { 1664 QLIST_FOREACH(sec, &bus->child, sibling) { 1665 assert(!pci_bus_is_root(sec)); 1666 if (sec->parent_dev->config[PCI_SECONDARY_BUS] == bus_num) { 1667 return sec; 1668 } 1669 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) { 1670 break; 1671 } 1672 } 1673 } 1674 1675 return NULL; 1676 } 1677 1678 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn) 1679 { 1680 bus = pci_find_bus_nr(bus, bus_num); 1681 1682 if (!bus) 1683 return NULL; 1684 1685 return bus->devices[devfn]; 1686 } 1687 1688 static int pci_qdev_init(DeviceState *qdev) 1689 { 1690 PCIDevice *pci_dev = (PCIDevice *)qdev; 1691 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 1692 PCIBus *bus; 1693 int rc; 1694 bool is_default_rom; 1695 1696 /* initialize cap_present for pci_is_express() and pci_config_size() */ 1697 if (pc->is_express) { 1698 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; 1699 } 1700 1701 bus = PCI_BUS(qdev_get_parent_bus(qdev)); 1702 pci_dev = do_pci_register_device(pci_dev, bus, 1703 object_get_typename(OBJECT(qdev)), 1704 pci_dev->devfn); 1705 if (pci_dev == NULL) 1706 return -1; 1707 if (qdev->hotplugged && pc->no_hotplug) { 1708 qerror_report(QERR_DEVICE_NO_HOTPLUG, object_get_typename(OBJECT(pci_dev))); 1709 do_pci_unregister_device(pci_dev); 1710 return -1; 1711 } 1712 if (pc->init) { 1713 rc = pc->init(pci_dev); 1714 if (rc != 0) { 1715 do_pci_unregister_device(pci_dev); 1716 return rc; 1717 } 1718 } 1719 1720 /* rom loading */ 1721 is_default_rom = false; 1722 if (pci_dev->romfile == NULL && pc->romfile != NULL) { 1723 pci_dev->romfile = g_strdup(pc->romfile); 1724 is_default_rom = true; 1725 } 1726 pci_add_option_rom(pci_dev, is_default_rom); 1727 1728 if (bus->hotplug) { 1729 /* Let buses differentiate between hotplug and when device is 1730 * enabled during qemu machine creation. */ 1731 rc = bus->hotplug(bus->hotplug_qdev, pci_dev, 1732 qdev->hotplugged ? PCI_HOTPLUG_ENABLED: 1733 PCI_COLDPLUG_ENABLED); 1734 if (rc != 0) { 1735 int r = pci_unregister_device(&pci_dev->qdev); 1736 assert(!r); 1737 return rc; 1738 } 1739 } 1740 return 0; 1741 } 1742 1743 static int pci_unplug_device(DeviceState *qdev) 1744 { 1745 PCIDevice *dev = PCI_DEVICE(qdev); 1746 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 1747 1748 if (pc->no_hotplug) { 1749 qerror_report(QERR_DEVICE_NO_HOTPLUG, object_get_typename(OBJECT(dev))); 1750 return -1; 1751 } 1752 return dev->bus->hotplug(dev->bus->hotplug_qdev, dev, 1753 PCI_HOTPLUG_DISABLED); 1754 } 1755 1756 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction, 1757 const char *name) 1758 { 1759 DeviceState *dev; 1760 1761 dev = qdev_create(&bus->qbus, name); 1762 qdev_prop_set_int32(dev, "addr", devfn); 1763 qdev_prop_set_bit(dev, "multifunction", multifunction); 1764 return PCI_DEVICE(dev); 1765 } 1766 1767 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, 1768 bool multifunction, 1769 const char *name) 1770 { 1771 PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name); 1772 qdev_init_nofail(&dev->qdev); 1773 return dev; 1774 } 1775 1776 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name) 1777 { 1778 return pci_create_multifunction(bus, devfn, false, name); 1779 } 1780 1781 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name) 1782 { 1783 return pci_create_simple_multifunction(bus, devfn, false, name); 1784 } 1785 1786 static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size) 1787 { 1788 int offset = PCI_CONFIG_HEADER_SIZE; 1789 int i; 1790 for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) { 1791 if (pdev->used[i]) 1792 offset = i + 1; 1793 else if (i - offset + 1 == size) 1794 return offset; 1795 } 1796 return 0; 1797 } 1798 1799 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id, 1800 uint8_t *prev_p) 1801 { 1802 uint8_t next, prev; 1803 1804 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST)) 1805 return 0; 1806 1807 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); 1808 prev = next + PCI_CAP_LIST_NEXT) 1809 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id) 1810 break; 1811 1812 if (prev_p) 1813 *prev_p = prev; 1814 return next; 1815 } 1816 1817 static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset) 1818 { 1819 uint8_t next, prev, found = 0; 1820 1821 if (!(pdev->used[offset])) { 1822 return 0; 1823 } 1824 1825 assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST); 1826 1827 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); 1828 prev = next + PCI_CAP_LIST_NEXT) { 1829 if (next <= offset && next > found) { 1830 found = next; 1831 } 1832 } 1833 return found; 1834 } 1835 1836 /* Patch the PCI vendor and device ids in a PCI rom image if necessary. 1837 This is needed for an option rom which is used for more than one device. */ 1838 static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size) 1839 { 1840 uint16_t vendor_id; 1841 uint16_t device_id; 1842 uint16_t rom_vendor_id; 1843 uint16_t rom_device_id; 1844 uint16_t rom_magic; 1845 uint16_t pcir_offset; 1846 uint8_t checksum; 1847 1848 /* Words in rom data are little endian (like in PCI configuration), 1849 so they can be read / written with pci_get_word / pci_set_word. */ 1850 1851 /* Only a valid rom will be patched. */ 1852 rom_magic = pci_get_word(ptr); 1853 if (rom_magic != 0xaa55) { 1854 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic); 1855 return; 1856 } 1857 pcir_offset = pci_get_word(ptr + 0x18); 1858 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) { 1859 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset); 1860 return; 1861 } 1862 1863 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID); 1864 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID); 1865 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4); 1866 rom_device_id = pci_get_word(ptr + pcir_offset + 6); 1867 1868 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile, 1869 vendor_id, device_id, rom_vendor_id, rom_device_id); 1870 1871 checksum = ptr[6]; 1872 1873 if (vendor_id != rom_vendor_id) { 1874 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */ 1875 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8); 1876 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8); 1877 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); 1878 ptr[6] = checksum; 1879 pci_set_word(ptr + pcir_offset + 4, vendor_id); 1880 } 1881 1882 if (device_id != rom_device_id) { 1883 /* Patch device id and checksum (at offset 6 for etherboot roms). */ 1884 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8); 1885 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8); 1886 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); 1887 ptr[6] = checksum; 1888 pci_set_word(ptr + pcir_offset + 6, device_id); 1889 } 1890 } 1891 1892 /* Add an option rom for the device */ 1893 static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom) 1894 { 1895 int size; 1896 char *path; 1897 void *ptr; 1898 char name[32]; 1899 const VMStateDescription *vmsd; 1900 1901 if (!pdev->romfile) 1902 return 0; 1903 if (strlen(pdev->romfile) == 0) 1904 return 0; 1905 1906 if (!pdev->rom_bar) { 1907 /* 1908 * Load rom via fw_cfg instead of creating a rom bar, 1909 * for 0.11 compatibility. 1910 */ 1911 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE); 1912 if (class == 0x0300) { 1913 rom_add_vga(pdev->romfile); 1914 } else { 1915 rom_add_option(pdev->romfile, -1); 1916 } 1917 return 0; 1918 } 1919 1920 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile); 1921 if (path == NULL) { 1922 path = g_strdup(pdev->romfile); 1923 } 1924 1925 size = get_image_size(path); 1926 if (size < 0) { 1927 error_report("%s: failed to find romfile \"%s\"", 1928 __func__, pdev->romfile); 1929 g_free(path); 1930 return -1; 1931 } else if (size == 0) { 1932 error_report("%s: ignoring empty romfile \"%s\"", 1933 __func__, pdev->romfile); 1934 g_free(path); 1935 return -1; 1936 } 1937 if (size & (size - 1)) { 1938 size = 1 << qemu_fls(size); 1939 } 1940 1941 vmsd = qdev_get_vmsd(DEVICE(pdev)); 1942 1943 if (vmsd) { 1944 snprintf(name, sizeof(name), "%s.rom", vmsd->name); 1945 } else { 1946 snprintf(name, sizeof(name), "%s.rom", object_get_typename(OBJECT(pdev))); 1947 } 1948 pdev->has_rom = true; 1949 memory_region_init_ram(&pdev->rom, OBJECT(pdev), name, size); 1950 vmstate_register_ram(&pdev->rom, &pdev->qdev); 1951 ptr = memory_region_get_ram_ptr(&pdev->rom); 1952 load_image(path, ptr); 1953 g_free(path); 1954 1955 if (is_default_rom) { 1956 /* Only the default rom images will be patched (if needed). */ 1957 pci_patch_ids(pdev, ptr, size); 1958 } 1959 1960 pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom); 1961 1962 return 0; 1963 } 1964 1965 static void pci_del_option_rom(PCIDevice *pdev) 1966 { 1967 if (!pdev->has_rom) 1968 return; 1969 1970 vmstate_unregister_ram(&pdev->rom, &pdev->qdev); 1971 memory_region_destroy(&pdev->rom); 1972 pdev->has_rom = false; 1973 } 1974 1975 /* 1976 * if !offset 1977 * Reserve space and add capability to the linked list in pci config space 1978 * 1979 * if offset = 0, 1980 * Find and reserve space and add capability to the linked list 1981 * in pci config space */ 1982 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, 1983 uint8_t offset, uint8_t size) 1984 { 1985 uint8_t *config; 1986 int i, overlapping_cap; 1987 1988 if (!offset) { 1989 offset = pci_find_space(pdev, size); 1990 if (!offset) { 1991 return -ENOSPC; 1992 } 1993 } else { 1994 /* Verify that capabilities don't overlap. Note: device assignment 1995 * depends on this check to verify that the device is not broken. 1996 * Should never trigger for emulated devices, but it's helpful 1997 * for debugging these. */ 1998 for (i = offset; i < offset + size; i++) { 1999 overlapping_cap = pci_find_capability_at_offset(pdev, i); 2000 if (overlapping_cap) { 2001 fprintf(stderr, "ERROR: %04x:%02x:%02x.%x " 2002 "Attempt to add PCI capability %x at offset " 2003 "%x overlaps existing capability %x at offset %x\n", 2004 pci_find_domain(pdev->bus), pci_bus_num(pdev->bus), 2005 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), 2006 cap_id, offset, overlapping_cap, i); 2007 return -EINVAL; 2008 } 2009 } 2010 } 2011 2012 config = pdev->config + offset; 2013 config[PCI_CAP_LIST_ID] = cap_id; 2014 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST]; 2015 pdev->config[PCI_CAPABILITY_LIST] = offset; 2016 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST; 2017 memset(pdev->used + offset, 0xFF, QEMU_ALIGN_UP(size, 4)); 2018 /* Make capability read-only by default */ 2019 memset(pdev->wmask + offset, 0, size); 2020 /* Check capability by default */ 2021 memset(pdev->cmask + offset, 0xFF, size); 2022 return offset; 2023 } 2024 2025 /* Unlink capability from the pci config space. */ 2026 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size) 2027 { 2028 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev); 2029 if (!offset) 2030 return; 2031 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT]; 2032 /* Make capability writable again */ 2033 memset(pdev->wmask + offset, 0xff, size); 2034 memset(pdev->w1cmask + offset, 0, size); 2035 /* Clear cmask as device-specific registers can't be checked */ 2036 memset(pdev->cmask + offset, 0, size); 2037 memset(pdev->used + offset, 0, QEMU_ALIGN_UP(size, 4)); 2038 2039 if (!pdev->config[PCI_CAPABILITY_LIST]) 2040 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST; 2041 } 2042 2043 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id) 2044 { 2045 return pci_find_capability_list(pdev, cap_id, NULL); 2046 } 2047 2048 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent) 2049 { 2050 PCIDevice *d = (PCIDevice *)dev; 2051 const pci_class_desc *desc; 2052 char ctxt[64]; 2053 PCIIORegion *r; 2054 int i, class; 2055 2056 class = pci_get_word(d->config + PCI_CLASS_DEVICE); 2057 desc = pci_class_descriptions; 2058 while (desc->desc && class != desc->class) 2059 desc++; 2060 if (desc->desc) { 2061 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc); 2062 } else { 2063 snprintf(ctxt, sizeof(ctxt), "Class %04x", class); 2064 } 2065 2066 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, " 2067 "pci id %04x:%04x (sub %04x:%04x)\n", 2068 indent, "", ctxt, pci_bus_num(d->bus), 2069 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn), 2070 pci_get_word(d->config + PCI_VENDOR_ID), 2071 pci_get_word(d->config + PCI_DEVICE_ID), 2072 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID), 2073 pci_get_word(d->config + PCI_SUBSYSTEM_ID)); 2074 for (i = 0; i < PCI_NUM_REGIONS; i++) { 2075 r = &d->io_regions[i]; 2076 if (!r->size) 2077 continue; 2078 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS 2079 " [0x%"FMT_PCIBUS"]\n", 2080 indent, "", 2081 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem", 2082 r->addr, r->addr + r->size - 1); 2083 } 2084 } 2085 2086 static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len) 2087 { 2088 PCIDevice *d = (PCIDevice *)dev; 2089 const char *name = NULL; 2090 const pci_class_desc *desc = pci_class_descriptions; 2091 int class = pci_get_word(d->config + PCI_CLASS_DEVICE); 2092 2093 while (desc->desc && 2094 (class & ~desc->fw_ign_bits) != 2095 (desc->class & ~desc->fw_ign_bits)) { 2096 desc++; 2097 } 2098 2099 if (desc->desc) { 2100 name = desc->fw_name; 2101 } 2102 2103 if (name) { 2104 pstrcpy(buf, len, name); 2105 } else { 2106 snprintf(buf, len, "pci%04x,%04x", 2107 pci_get_word(d->config + PCI_VENDOR_ID), 2108 pci_get_word(d->config + PCI_DEVICE_ID)); 2109 } 2110 2111 return buf; 2112 } 2113 2114 static char *pcibus_get_fw_dev_path(DeviceState *dev) 2115 { 2116 PCIDevice *d = (PCIDevice *)dev; 2117 char path[50], name[33]; 2118 int off; 2119 2120 off = snprintf(path, sizeof(path), "%s@%x", 2121 pci_dev_fw_name(dev, name, sizeof name), 2122 PCI_SLOT(d->devfn)); 2123 if (PCI_FUNC(d->devfn)) 2124 snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn)); 2125 return g_strdup(path); 2126 } 2127 2128 static char *pcibus_get_dev_path(DeviceState *dev) 2129 { 2130 PCIDevice *d = container_of(dev, PCIDevice, qdev); 2131 PCIDevice *t; 2132 int slot_depth; 2133 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function. 2134 * 00 is added here to make this format compatible with 2135 * domain:Bus:Slot.Func for systems without nested PCI bridges. 2136 * Slot.Function list specifies the slot and function numbers for all 2137 * devices on the path from root to the specific device. */ 2138 char domain[] = "DDDD:00"; 2139 char slot[] = ":SS.F"; 2140 int domain_len = sizeof domain - 1 /* For '\0' */; 2141 int slot_len = sizeof slot - 1 /* For '\0' */; 2142 int path_len; 2143 char *path, *p; 2144 int s; 2145 2146 /* Calculate # of slots on path between device and root. */; 2147 slot_depth = 0; 2148 for (t = d; t; t = t->bus->parent_dev) { 2149 ++slot_depth; 2150 } 2151 2152 path_len = domain_len + slot_len * slot_depth; 2153 2154 /* Allocate memory, fill in the terminating null byte. */ 2155 path = g_malloc(path_len + 1 /* For '\0' */); 2156 path[path_len] = '\0'; 2157 2158 /* First field is the domain. */ 2159 s = snprintf(domain, sizeof domain, "%04x:00", pci_find_domain(d->bus)); 2160 assert(s == domain_len); 2161 memcpy(path, domain, domain_len); 2162 2163 /* Fill in slot numbers. We walk up from device to root, so need to print 2164 * them in the reverse order, last to first. */ 2165 p = path + path_len; 2166 for (t = d; t; t = t->bus->parent_dev) { 2167 p -= slot_len; 2168 s = snprintf(slot, sizeof slot, ":%02x.%x", 2169 PCI_SLOT(t->devfn), PCI_FUNC(t->devfn)); 2170 assert(s == slot_len); 2171 memcpy(p, slot, slot_len); 2172 } 2173 2174 return path; 2175 } 2176 2177 static int pci_qdev_find_recursive(PCIBus *bus, 2178 const char *id, PCIDevice **pdev) 2179 { 2180 DeviceState *qdev = qdev_find_recursive(&bus->qbus, id); 2181 if (!qdev) { 2182 return -ENODEV; 2183 } 2184 2185 /* roughly check if given qdev is pci device */ 2186 if (object_dynamic_cast(OBJECT(qdev), TYPE_PCI_DEVICE)) { 2187 *pdev = PCI_DEVICE(qdev); 2188 return 0; 2189 } 2190 return -EINVAL; 2191 } 2192 2193 int pci_qdev_find_device(const char *id, PCIDevice **pdev) 2194 { 2195 struct PCIHostBus *host; 2196 int rc = -ENODEV; 2197 2198 QLIST_FOREACH(host, &host_buses, next) { 2199 int tmp = pci_qdev_find_recursive(host->bus, id, pdev); 2200 if (!tmp) { 2201 rc = 0; 2202 break; 2203 } 2204 if (tmp != -ENODEV) { 2205 rc = tmp; 2206 } 2207 } 2208 2209 return rc; 2210 } 2211 2212 MemoryRegion *pci_address_space(PCIDevice *dev) 2213 { 2214 return dev->bus->address_space_mem; 2215 } 2216 2217 MemoryRegion *pci_address_space_io(PCIDevice *dev) 2218 { 2219 return dev->bus->address_space_io; 2220 } 2221 2222 static void pci_device_class_init(ObjectClass *klass, void *data) 2223 { 2224 DeviceClass *k = DEVICE_CLASS(klass); 2225 k->init = pci_qdev_init; 2226 k->unplug = pci_unplug_device; 2227 k->exit = pci_unregister_device; 2228 k->bus_type = TYPE_PCI_BUS; 2229 k->props = pci_props; 2230 } 2231 2232 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque) 2233 { 2234 bus->iommu_fn = fn; 2235 bus->iommu_opaque = opaque; 2236 } 2237 2238 static const TypeInfo pci_device_type_info = { 2239 .name = TYPE_PCI_DEVICE, 2240 .parent = TYPE_DEVICE, 2241 .instance_size = sizeof(PCIDevice), 2242 .abstract = true, 2243 .class_size = sizeof(PCIDeviceClass), 2244 .class_init = pci_device_class_init, 2245 }; 2246 2247 static void pci_register_types(void) 2248 { 2249 type_register_static(&pci_bus_info); 2250 type_register_static(&pcie_bus_info); 2251 type_register_static(&pci_device_type_info); 2252 } 2253 2254 type_init(pci_register_types) 2255