1 /* 2 * QEMU PCI bus manager 3 * 4 * Copyright (c) 2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "qemu/osdep.h" 25 #include "hw/hw.h" 26 #include "hw/pci/pci.h" 27 #include "hw/pci/pci_bridge.h" 28 #include "hw/pci/pci_bus.h" 29 #include "hw/pci/pci_host.h" 30 #include "monitor/monitor.h" 31 #include "net/net.h" 32 #include "sysemu/sysemu.h" 33 #include "hw/loader.h" 34 #include "qemu/error-report.h" 35 #include "qemu/range.h" 36 #include "qmp-commands.h" 37 #include "trace.h" 38 #include "hw/pci/msi.h" 39 #include "hw/pci/msix.h" 40 #include "exec/address-spaces.h" 41 #include "hw/hotplug.h" 42 #include "hw/boards.h" 43 #include "qemu/cutils.h" 44 45 //#define DEBUG_PCI 46 #ifdef DEBUG_PCI 47 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) 48 #else 49 # define PCI_DPRINTF(format, ...) do { } while (0) 50 #endif 51 52 bool pci_available = true; 53 54 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent); 55 static char *pcibus_get_dev_path(DeviceState *dev); 56 static char *pcibus_get_fw_dev_path(DeviceState *dev); 57 static void pcibus_reset(BusState *qbus); 58 59 static Property pci_props[] = { 60 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1), 61 DEFINE_PROP_STRING("romfile", PCIDevice, romfile), 62 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1), 63 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present, 64 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false), 65 DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present, 66 QEMU_PCI_CAP_SERR_BITNR, true), 67 DEFINE_PROP_BIT("x-pcie-lnksta-dllla", PCIDevice, cap_present, 68 QEMU_PCIE_LNKSTA_DLLLA_BITNR, true), 69 DEFINE_PROP_BIT("x-pcie-extcap-init", PCIDevice, cap_present, 70 QEMU_PCIE_EXTCAP_INIT_BITNR, true), 71 DEFINE_PROP_END_OF_LIST() 72 }; 73 74 static const VMStateDescription vmstate_pcibus = { 75 .name = "PCIBUS", 76 .version_id = 1, 77 .minimum_version_id = 1, 78 .fields = (VMStateField[]) { 79 VMSTATE_INT32_EQUAL(nirq, PCIBus, NULL), 80 VMSTATE_VARRAY_INT32(irq_count, PCIBus, 81 nirq, 0, vmstate_info_int32, 82 int32_t), 83 VMSTATE_END_OF_LIST() 84 } 85 }; 86 87 static void pci_init_bus_master(PCIDevice *pci_dev) 88 { 89 AddressSpace *dma_as = pci_device_iommu_address_space(pci_dev); 90 91 memory_region_init_alias(&pci_dev->bus_master_enable_region, 92 OBJECT(pci_dev), "bus master", 93 dma_as->root, 0, memory_region_size(dma_as->root)); 94 memory_region_set_enabled(&pci_dev->bus_master_enable_region, false); 95 memory_region_add_subregion(&pci_dev->bus_master_container_region, 0, 96 &pci_dev->bus_master_enable_region); 97 } 98 99 static void pcibus_machine_done(Notifier *notifier, void *data) 100 { 101 PCIBus *bus = container_of(notifier, PCIBus, machine_done); 102 int i; 103 104 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 105 if (bus->devices[i]) { 106 pci_init_bus_master(bus->devices[i]); 107 } 108 } 109 } 110 111 static void pci_bus_realize(BusState *qbus, Error **errp) 112 { 113 PCIBus *bus = PCI_BUS(qbus); 114 115 bus->machine_done.notify = pcibus_machine_done; 116 qemu_add_machine_init_done_notifier(&bus->machine_done); 117 118 vmstate_register(NULL, -1, &vmstate_pcibus, bus); 119 } 120 121 static void pci_bus_unrealize(BusState *qbus, Error **errp) 122 { 123 PCIBus *bus = PCI_BUS(qbus); 124 125 qemu_remove_machine_init_done_notifier(&bus->machine_done); 126 127 vmstate_unregister(NULL, &vmstate_pcibus, bus); 128 } 129 130 static bool pcibus_is_root(PCIBus *bus) 131 { 132 return !bus->parent_dev; 133 } 134 135 static int pcibus_num(PCIBus *bus) 136 { 137 if (pcibus_is_root(bus)) { 138 return 0; /* pci host bridge */ 139 } 140 return bus->parent_dev->config[PCI_SECONDARY_BUS]; 141 } 142 143 static uint16_t pcibus_numa_node(PCIBus *bus) 144 { 145 return NUMA_NODE_UNASSIGNED; 146 } 147 148 static void pci_bus_class_init(ObjectClass *klass, void *data) 149 { 150 BusClass *k = BUS_CLASS(klass); 151 PCIBusClass *pbc = PCI_BUS_CLASS(klass); 152 153 k->print_dev = pcibus_dev_print; 154 k->get_dev_path = pcibus_get_dev_path; 155 k->get_fw_dev_path = pcibus_get_fw_dev_path; 156 k->realize = pci_bus_realize; 157 k->unrealize = pci_bus_unrealize; 158 k->reset = pcibus_reset; 159 160 pbc->is_root = pcibus_is_root; 161 pbc->bus_num = pcibus_num; 162 pbc->numa_node = pcibus_numa_node; 163 } 164 165 static const TypeInfo pci_bus_info = { 166 .name = TYPE_PCI_BUS, 167 .parent = TYPE_BUS, 168 .instance_size = sizeof(PCIBus), 169 .class_size = sizeof(PCIBusClass), 170 .class_init = pci_bus_class_init, 171 }; 172 173 static const TypeInfo pcie_interface_info = { 174 .name = INTERFACE_PCIE_DEVICE, 175 .parent = TYPE_INTERFACE, 176 }; 177 178 static const TypeInfo conventional_pci_interface_info = { 179 .name = INTERFACE_CONVENTIONAL_PCI_DEVICE, 180 .parent = TYPE_INTERFACE, 181 }; 182 183 static const TypeInfo pcie_bus_info = { 184 .name = TYPE_PCIE_BUS, 185 .parent = TYPE_PCI_BUS, 186 }; 187 188 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num); 189 static void pci_update_mappings(PCIDevice *d); 190 static void pci_irq_handler(void *opaque, int irq_num, int level); 191 static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, Error **); 192 static void pci_del_option_rom(PCIDevice *pdev); 193 194 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET; 195 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU; 196 197 static QLIST_HEAD(, PCIHostState) pci_host_bridges; 198 199 int pci_bar(PCIDevice *d, int reg) 200 { 201 uint8_t type; 202 203 if (reg != PCI_ROM_SLOT) 204 return PCI_BASE_ADDRESS_0 + reg * 4; 205 206 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 207 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS; 208 } 209 210 static inline int pci_irq_state(PCIDevice *d, int irq_num) 211 { 212 return (d->irq_state >> irq_num) & 0x1; 213 } 214 215 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level) 216 { 217 d->irq_state &= ~(0x1 << irq_num); 218 d->irq_state |= level << irq_num; 219 } 220 221 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change) 222 { 223 PCIBus *bus; 224 for (;;) { 225 bus = pci_dev->bus; 226 irq_num = bus->map_irq(pci_dev, irq_num); 227 if (bus->set_irq) 228 break; 229 pci_dev = bus->parent_dev; 230 } 231 bus->irq_count[irq_num] += change; 232 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0); 233 } 234 235 int pci_bus_get_irq_level(PCIBus *bus, int irq_num) 236 { 237 assert(irq_num >= 0); 238 assert(irq_num < bus->nirq); 239 return !!bus->irq_count[irq_num]; 240 } 241 242 /* Update interrupt status bit in config space on interrupt 243 * state change. */ 244 static void pci_update_irq_status(PCIDevice *dev) 245 { 246 if (dev->irq_state) { 247 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT; 248 } else { 249 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; 250 } 251 } 252 253 void pci_device_deassert_intx(PCIDevice *dev) 254 { 255 int i; 256 for (i = 0; i < PCI_NUM_PINS; ++i) { 257 pci_irq_handler(dev, i, 0); 258 } 259 } 260 261 static void pci_do_device_reset(PCIDevice *dev) 262 { 263 int r; 264 265 pci_device_deassert_intx(dev); 266 assert(dev->irq_state == 0); 267 268 /* Clear all writable bits */ 269 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND, 270 pci_get_word(dev->wmask + PCI_COMMAND) | 271 pci_get_word(dev->w1cmask + PCI_COMMAND)); 272 pci_word_test_and_clear_mask(dev->config + PCI_STATUS, 273 pci_get_word(dev->wmask + PCI_STATUS) | 274 pci_get_word(dev->w1cmask + PCI_STATUS)); 275 dev->config[PCI_CACHE_LINE_SIZE] = 0x0; 276 dev->config[PCI_INTERRUPT_LINE] = 0x0; 277 for (r = 0; r < PCI_NUM_REGIONS; ++r) { 278 PCIIORegion *region = &dev->io_regions[r]; 279 if (!region->size) { 280 continue; 281 } 282 283 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) && 284 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 285 pci_set_quad(dev->config + pci_bar(dev, r), region->type); 286 } else { 287 pci_set_long(dev->config + pci_bar(dev, r), region->type); 288 } 289 } 290 pci_update_mappings(dev); 291 292 msi_reset(dev); 293 msix_reset(dev); 294 } 295 296 /* 297 * This function is called on #RST and FLR. 298 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set 299 */ 300 void pci_device_reset(PCIDevice *dev) 301 { 302 qdev_reset_all(&dev->qdev); 303 pci_do_device_reset(dev); 304 } 305 306 /* 307 * Trigger pci bus reset under a given bus. 308 * Called via qbus_reset_all on RST# assert, after the devices 309 * have been reset qdev_reset_all-ed already. 310 */ 311 static void pcibus_reset(BusState *qbus) 312 { 313 PCIBus *bus = DO_UPCAST(PCIBus, qbus, qbus); 314 int i; 315 316 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 317 if (bus->devices[i]) { 318 pci_do_device_reset(bus->devices[i]); 319 } 320 } 321 322 for (i = 0; i < bus->nirq; i++) { 323 assert(bus->irq_count[i] == 0); 324 } 325 } 326 327 static void pci_host_bus_register(DeviceState *host) 328 { 329 PCIHostState *host_bridge = PCI_HOST_BRIDGE(host); 330 331 QLIST_INSERT_HEAD(&pci_host_bridges, host_bridge, next); 332 } 333 334 PCIBus *pci_find_primary_bus(void) 335 { 336 PCIBus *primary_bus = NULL; 337 PCIHostState *host; 338 339 QLIST_FOREACH(host, &pci_host_bridges, next) { 340 if (primary_bus) { 341 /* We have multiple root buses, refuse to select a primary */ 342 return NULL; 343 } 344 primary_bus = host->bus; 345 } 346 347 return primary_bus; 348 } 349 350 PCIBus *pci_device_root_bus(const PCIDevice *d) 351 { 352 PCIBus *bus = d->bus; 353 354 while (!pci_bus_is_root(bus)) { 355 d = bus->parent_dev; 356 assert(d != NULL); 357 358 bus = d->bus; 359 } 360 361 return bus; 362 } 363 364 const char *pci_root_bus_path(PCIDevice *dev) 365 { 366 PCIBus *rootbus = pci_device_root_bus(dev); 367 PCIHostState *host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent); 368 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_GET_CLASS(host_bridge); 369 370 assert(host_bridge->bus == rootbus); 371 372 if (hc->root_bus_path) { 373 return (*hc->root_bus_path)(host_bridge, rootbus); 374 } 375 376 return rootbus->qbus.name; 377 } 378 379 static void pci_root_bus_init(PCIBus *bus, DeviceState *parent, 380 MemoryRegion *address_space_mem, 381 MemoryRegion *address_space_io, 382 uint8_t devfn_min) 383 { 384 assert(PCI_FUNC(devfn_min) == 0); 385 bus->devfn_min = devfn_min; 386 bus->slot_reserved_mask = 0x0; 387 bus->address_space_mem = address_space_mem; 388 bus->address_space_io = address_space_io; 389 390 /* host bridge */ 391 QLIST_INIT(&bus->child); 392 393 pci_host_bus_register(parent); 394 } 395 396 bool pci_bus_is_express(PCIBus *bus) 397 { 398 return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS); 399 } 400 401 bool pci_bus_is_root(PCIBus *bus) 402 { 403 return PCI_BUS_GET_CLASS(bus)->is_root(bus); 404 } 405 406 void pci_root_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent, 407 const char *name, 408 MemoryRegion *address_space_mem, 409 MemoryRegion *address_space_io, 410 uint8_t devfn_min, const char *typename) 411 { 412 qbus_create_inplace(bus, bus_size, typename, parent, name); 413 pci_root_bus_init(bus, parent, address_space_mem, address_space_io, 414 devfn_min); 415 } 416 417 PCIBus *pci_root_bus_new(DeviceState *parent, const char *name, 418 MemoryRegion *address_space_mem, 419 MemoryRegion *address_space_io, 420 uint8_t devfn_min, const char *typename) 421 { 422 PCIBus *bus; 423 424 bus = PCI_BUS(qbus_create(typename, parent, name)); 425 pci_root_bus_init(bus, parent, address_space_mem, address_space_io, 426 devfn_min); 427 return bus; 428 } 429 430 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 431 void *irq_opaque, int nirq) 432 { 433 bus->set_irq = set_irq; 434 bus->map_irq = map_irq; 435 bus->irq_opaque = irq_opaque; 436 bus->nirq = nirq; 437 bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0])); 438 } 439 440 PCIBus *pci_register_root_bus(DeviceState *parent, const char *name, 441 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 442 void *irq_opaque, 443 MemoryRegion *address_space_mem, 444 MemoryRegion *address_space_io, 445 uint8_t devfn_min, int nirq, 446 const char *typename) 447 { 448 PCIBus *bus; 449 450 bus = pci_root_bus_new(parent, name, address_space_mem, 451 address_space_io, devfn_min, typename); 452 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq); 453 return bus; 454 } 455 456 int pci_bus_num(PCIBus *s) 457 { 458 return PCI_BUS_GET_CLASS(s)->bus_num(s); 459 } 460 461 int pci_bus_numa_node(PCIBus *bus) 462 { 463 return PCI_BUS_GET_CLASS(bus)->numa_node(bus); 464 } 465 466 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size, 467 VMStateField *field) 468 { 469 PCIDevice *s = container_of(pv, PCIDevice, config); 470 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(s); 471 uint8_t *config; 472 int i; 473 474 assert(size == pci_config_size(s)); 475 config = g_malloc(size); 476 477 qemu_get_buffer(f, config, size); 478 for (i = 0; i < size; ++i) { 479 if ((config[i] ^ s->config[i]) & 480 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) { 481 error_report("%s: Bad config data: i=0x%x read: %x device: %x " 482 "cmask: %x wmask: %x w1cmask:%x", __func__, 483 i, config[i], s->config[i], 484 s->cmask[i], s->wmask[i], s->w1cmask[i]); 485 g_free(config); 486 return -EINVAL; 487 } 488 } 489 memcpy(s->config, config, size); 490 491 pci_update_mappings(s); 492 if (pc->is_bridge) { 493 PCIBridge *b = PCI_BRIDGE(s); 494 pci_bridge_update_mappings(b); 495 } 496 497 memory_region_set_enabled(&s->bus_master_enable_region, 498 pci_get_word(s->config + PCI_COMMAND) 499 & PCI_COMMAND_MASTER); 500 501 g_free(config); 502 return 0; 503 } 504 505 /* just put buffer */ 506 static int put_pci_config_device(QEMUFile *f, void *pv, size_t size, 507 VMStateField *field, QJSON *vmdesc) 508 { 509 const uint8_t **v = pv; 510 assert(size == pci_config_size(container_of(pv, PCIDevice, config))); 511 qemu_put_buffer(f, *v, size); 512 513 return 0; 514 } 515 516 static VMStateInfo vmstate_info_pci_config = { 517 .name = "pci config", 518 .get = get_pci_config_device, 519 .put = put_pci_config_device, 520 }; 521 522 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size, 523 VMStateField *field) 524 { 525 PCIDevice *s = container_of(pv, PCIDevice, irq_state); 526 uint32_t irq_state[PCI_NUM_PINS]; 527 int i; 528 for (i = 0; i < PCI_NUM_PINS; ++i) { 529 irq_state[i] = qemu_get_be32(f); 530 if (irq_state[i] != 0x1 && irq_state[i] != 0) { 531 fprintf(stderr, "irq state %d: must be 0 or 1.\n", 532 irq_state[i]); 533 return -EINVAL; 534 } 535 } 536 537 for (i = 0; i < PCI_NUM_PINS; ++i) { 538 pci_set_irq_state(s, i, irq_state[i]); 539 } 540 541 return 0; 542 } 543 544 static int put_pci_irq_state(QEMUFile *f, void *pv, size_t size, 545 VMStateField *field, QJSON *vmdesc) 546 { 547 int i; 548 PCIDevice *s = container_of(pv, PCIDevice, irq_state); 549 550 for (i = 0; i < PCI_NUM_PINS; ++i) { 551 qemu_put_be32(f, pci_irq_state(s, i)); 552 } 553 554 return 0; 555 } 556 557 static VMStateInfo vmstate_info_pci_irq_state = { 558 .name = "pci irq state", 559 .get = get_pci_irq_state, 560 .put = put_pci_irq_state, 561 }; 562 563 static bool migrate_is_pcie(void *opaque, int version_id) 564 { 565 return pci_is_express((PCIDevice *)opaque); 566 } 567 568 static bool migrate_is_not_pcie(void *opaque, int version_id) 569 { 570 return !pci_is_express((PCIDevice *)opaque); 571 } 572 573 const VMStateDescription vmstate_pci_device = { 574 .name = "PCIDevice", 575 .version_id = 2, 576 .minimum_version_id = 1, 577 .fields = (VMStateField[]) { 578 VMSTATE_INT32_POSITIVE_LE(version_id, PCIDevice), 579 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice, 580 migrate_is_not_pcie, 581 0, vmstate_info_pci_config, 582 PCI_CONFIG_SPACE_SIZE), 583 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice, 584 migrate_is_pcie, 585 0, vmstate_info_pci_config, 586 PCIE_CONFIG_SPACE_SIZE), 587 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2, 588 vmstate_info_pci_irq_state, 589 PCI_NUM_PINS * sizeof(int32_t)), 590 VMSTATE_END_OF_LIST() 591 } 592 }; 593 594 595 void pci_device_save(PCIDevice *s, QEMUFile *f) 596 { 597 /* Clear interrupt status bit: it is implicit 598 * in irq_state which we are saving. 599 * This makes us compatible with old devices 600 * which never set or clear this bit. */ 601 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; 602 vmstate_save_state(f, &vmstate_pci_device, s, NULL); 603 /* Restore the interrupt status bit. */ 604 pci_update_irq_status(s); 605 } 606 607 int pci_device_load(PCIDevice *s, QEMUFile *f) 608 { 609 int ret; 610 ret = vmstate_load_state(f, &vmstate_pci_device, s, s->version_id); 611 /* Restore the interrupt status bit. */ 612 pci_update_irq_status(s); 613 return ret; 614 } 615 616 static void pci_set_default_subsystem_id(PCIDevice *pci_dev) 617 { 618 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, 619 pci_default_sub_vendor_id); 620 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 621 pci_default_sub_device_id); 622 } 623 624 /* 625 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL 626 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error 627 */ 628 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, 629 unsigned int *slotp, unsigned int *funcp) 630 { 631 const char *p; 632 char *e; 633 unsigned long val; 634 unsigned long dom = 0, bus = 0; 635 unsigned int slot = 0; 636 unsigned int func = 0; 637 638 p = addr; 639 val = strtoul(p, &e, 16); 640 if (e == p) 641 return -1; 642 if (*e == ':') { 643 bus = val; 644 p = e + 1; 645 val = strtoul(p, &e, 16); 646 if (e == p) 647 return -1; 648 if (*e == ':') { 649 dom = bus; 650 bus = val; 651 p = e + 1; 652 val = strtoul(p, &e, 16); 653 if (e == p) 654 return -1; 655 } 656 } 657 658 slot = val; 659 660 if (funcp != NULL) { 661 if (*e != '.') 662 return -1; 663 664 p = e + 1; 665 val = strtoul(p, &e, 16); 666 if (e == p) 667 return -1; 668 669 func = val; 670 } 671 672 /* if funcp == NULL func is 0 */ 673 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7) 674 return -1; 675 676 if (*e) 677 return -1; 678 679 *domp = dom; 680 *busp = bus; 681 *slotp = slot; 682 if (funcp != NULL) 683 *funcp = func; 684 return 0; 685 } 686 687 static PCIBus *pci_get_bus_devfn(int *devfnp, PCIBus *root, 688 const char *devaddr) 689 { 690 int dom, bus; 691 unsigned slot; 692 693 if (!root) { 694 fprintf(stderr, "No primary PCI bus\n"); 695 return NULL; 696 } 697 698 assert(!root->parent_dev); 699 700 if (!devaddr) { 701 *devfnp = -1; 702 return pci_find_bus_nr(root, 0); 703 } 704 705 if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) { 706 return NULL; 707 } 708 709 if (dom != 0) { 710 fprintf(stderr, "No support for non-zero PCI domains\n"); 711 return NULL; 712 } 713 714 *devfnp = PCI_DEVFN(slot, 0); 715 return pci_find_bus_nr(root, bus); 716 } 717 718 static void pci_init_cmask(PCIDevice *dev) 719 { 720 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff); 721 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff); 722 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST; 723 dev->cmask[PCI_REVISION_ID] = 0xff; 724 dev->cmask[PCI_CLASS_PROG] = 0xff; 725 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff); 726 dev->cmask[PCI_HEADER_TYPE] = 0xff; 727 dev->cmask[PCI_CAPABILITY_LIST] = 0xff; 728 } 729 730 static void pci_init_wmask(PCIDevice *dev) 731 { 732 int config_size = pci_config_size(dev); 733 734 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff; 735 dev->wmask[PCI_INTERRUPT_LINE] = 0xff; 736 pci_set_word(dev->wmask + PCI_COMMAND, 737 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | 738 PCI_COMMAND_INTX_DISABLE); 739 if (dev->cap_present & QEMU_PCI_CAP_SERR) { 740 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR); 741 } 742 743 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff, 744 config_size - PCI_CONFIG_HEADER_SIZE); 745 } 746 747 static void pci_init_w1cmask(PCIDevice *dev) 748 { 749 /* 750 * Note: It's okay to set w1cmask even for readonly bits as 751 * long as their value is hardwired to 0. 752 */ 753 pci_set_word(dev->w1cmask + PCI_STATUS, 754 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT | 755 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT | 756 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY); 757 } 758 759 static void pci_init_mask_bridge(PCIDevice *d) 760 { 761 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and 762 PCI_SEC_LETENCY_TIMER */ 763 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4); 764 765 /* base and limit */ 766 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff; 767 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff; 768 pci_set_word(d->wmask + PCI_MEMORY_BASE, 769 PCI_MEMORY_RANGE_MASK & 0xffff); 770 pci_set_word(d->wmask + PCI_MEMORY_LIMIT, 771 PCI_MEMORY_RANGE_MASK & 0xffff); 772 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE, 773 PCI_PREF_RANGE_MASK & 0xffff); 774 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT, 775 PCI_PREF_RANGE_MASK & 0xffff); 776 777 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */ 778 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8); 779 780 /* Supported memory and i/o types */ 781 d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16; 782 d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16; 783 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE, 784 PCI_PREF_RANGE_TYPE_64); 785 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT, 786 PCI_PREF_RANGE_TYPE_64); 787 788 /* 789 * TODO: Bridges default to 10-bit VGA decoding but we currently only 790 * implement 16-bit decoding (no alias support). 791 */ 792 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 793 PCI_BRIDGE_CTL_PARITY | 794 PCI_BRIDGE_CTL_SERR | 795 PCI_BRIDGE_CTL_ISA | 796 PCI_BRIDGE_CTL_VGA | 797 PCI_BRIDGE_CTL_VGA_16BIT | 798 PCI_BRIDGE_CTL_MASTER_ABORT | 799 PCI_BRIDGE_CTL_BUS_RESET | 800 PCI_BRIDGE_CTL_FAST_BACK | 801 PCI_BRIDGE_CTL_DISCARD | 802 PCI_BRIDGE_CTL_SEC_DISCARD | 803 PCI_BRIDGE_CTL_DISCARD_SERR); 804 /* Below does not do anything as we never set this bit, put here for 805 * completeness. */ 806 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL, 807 PCI_BRIDGE_CTL_DISCARD_STATUS); 808 d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK; 809 d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK; 810 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE, 811 PCI_PREF_RANGE_TYPE_MASK); 812 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT, 813 PCI_PREF_RANGE_TYPE_MASK); 814 } 815 816 static void pci_init_multifunction(PCIBus *bus, PCIDevice *dev, Error **errp) 817 { 818 uint8_t slot = PCI_SLOT(dev->devfn); 819 uint8_t func; 820 821 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 822 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION; 823 } 824 825 /* 826 * multifunction bit is interpreted in two ways as follows. 827 * - all functions must set the bit to 1. 828 * Example: Intel X53 829 * - function 0 must set the bit, but the rest function (> 0) 830 * is allowed to leave the bit to 0. 831 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10, 832 * 833 * So OS (at least Linux) checks the bit of only function 0, 834 * and doesn't see the bit of function > 0. 835 * 836 * The below check allows both interpretation. 837 */ 838 if (PCI_FUNC(dev->devfn)) { 839 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)]; 840 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) { 841 /* function 0 should set multifunction bit */ 842 error_setg(errp, "PCI: single function device can't be populated " 843 "in function %x.%x", slot, PCI_FUNC(dev->devfn)); 844 return; 845 } 846 return; 847 } 848 849 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 850 return; 851 } 852 /* function 0 indicates single function, so function > 0 must be NULL */ 853 for (func = 1; func < PCI_FUNC_MAX; ++func) { 854 if (bus->devices[PCI_DEVFN(slot, func)]) { 855 error_setg(errp, "PCI: %x.0 indicates single function, " 856 "but %x.%x is already populated.", 857 slot, slot, func); 858 return; 859 } 860 } 861 } 862 863 static void pci_config_alloc(PCIDevice *pci_dev) 864 { 865 int config_size = pci_config_size(pci_dev); 866 867 pci_dev->config = g_malloc0(config_size); 868 pci_dev->cmask = g_malloc0(config_size); 869 pci_dev->wmask = g_malloc0(config_size); 870 pci_dev->w1cmask = g_malloc0(config_size); 871 pci_dev->used = g_malloc0(config_size); 872 } 873 874 static void pci_config_free(PCIDevice *pci_dev) 875 { 876 g_free(pci_dev->config); 877 g_free(pci_dev->cmask); 878 g_free(pci_dev->wmask); 879 g_free(pci_dev->w1cmask); 880 g_free(pci_dev->used); 881 } 882 883 static void do_pci_unregister_device(PCIDevice *pci_dev) 884 { 885 pci_dev->bus->devices[pci_dev->devfn] = NULL; 886 pci_config_free(pci_dev); 887 888 if (memory_region_is_mapped(&pci_dev->bus_master_enable_region)) { 889 memory_region_del_subregion(&pci_dev->bus_master_container_region, 890 &pci_dev->bus_master_enable_region); 891 } 892 address_space_destroy(&pci_dev->bus_master_as); 893 } 894 895 /* Extract PCIReqIDCache into BDF format */ 896 static uint16_t pci_req_id_cache_extract(PCIReqIDCache *cache) 897 { 898 uint8_t bus_n; 899 uint16_t result; 900 901 switch (cache->type) { 902 case PCI_REQ_ID_BDF: 903 result = pci_get_bdf(cache->dev); 904 break; 905 case PCI_REQ_ID_SECONDARY_BUS: 906 bus_n = pci_bus_num(cache->dev->bus); 907 result = PCI_BUILD_BDF(bus_n, 0); 908 break; 909 default: 910 error_printf("Invalid PCI requester ID cache type: %d\n", 911 cache->type); 912 exit(1); 913 break; 914 } 915 916 return result; 917 } 918 919 /* Parse bridges up to the root complex and return requester ID 920 * cache for specific device. For full PCIe topology, the cache 921 * result would be exactly the same as getting BDF of the device. 922 * However, several tricks are required when system mixed up with 923 * legacy PCI devices and PCIe-to-PCI bridges. 924 * 925 * Here we cache the proxy device (and type) not requester ID since 926 * bus number might change from time to time. 927 */ 928 static PCIReqIDCache pci_req_id_cache_get(PCIDevice *dev) 929 { 930 PCIDevice *parent; 931 PCIReqIDCache cache = { 932 .dev = dev, 933 .type = PCI_REQ_ID_BDF, 934 }; 935 936 while (!pci_bus_is_root(dev->bus)) { 937 /* We are under PCI/PCIe bridges */ 938 parent = dev->bus->parent_dev; 939 if (pci_is_express(parent)) { 940 if (pcie_cap_get_type(parent) == PCI_EXP_TYPE_PCI_BRIDGE) { 941 /* When we pass through PCIe-to-PCI/PCIX bridges, we 942 * override the requester ID using secondary bus 943 * number of parent bridge with zeroed devfn 944 * (pcie-to-pci bridge spec chap 2.3). */ 945 cache.type = PCI_REQ_ID_SECONDARY_BUS; 946 cache.dev = dev; 947 } 948 } else { 949 /* Legacy PCI, override requester ID with the bridge's 950 * BDF upstream. When the root complex connects to 951 * legacy PCI devices (including buses), it can only 952 * obtain requester ID info from directly attached 953 * devices. If devices are attached under bridges, only 954 * the requester ID of the bridge that is directly 955 * attached to the root complex can be recognized. */ 956 cache.type = PCI_REQ_ID_BDF; 957 cache.dev = parent; 958 } 959 dev = parent; 960 } 961 962 return cache; 963 } 964 965 uint16_t pci_requester_id(PCIDevice *dev) 966 { 967 return pci_req_id_cache_extract(&dev->requester_id_cache); 968 } 969 970 static bool pci_bus_devfn_available(PCIBus *bus, int devfn) 971 { 972 return !(bus->devices[devfn]); 973 } 974 975 static bool pci_bus_devfn_reserved(PCIBus *bus, int devfn) 976 { 977 return bus->slot_reserved_mask & (1UL << PCI_SLOT(devfn)); 978 } 979 980 /* -1 for devfn means auto assign */ 981 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus, 982 const char *name, int devfn, 983 Error **errp) 984 { 985 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 986 PCIConfigReadFunc *config_read = pc->config_read; 987 PCIConfigWriteFunc *config_write = pc->config_write; 988 Error *local_err = NULL; 989 DeviceState *dev = DEVICE(pci_dev); 990 991 pci_dev->bus = bus; 992 /* Only pci bridges can be attached to extra PCI root buses */ 993 if (pci_bus_is_root(bus) && bus->parent_dev && !pc->is_bridge) { 994 error_setg(errp, 995 "PCI: Only PCI/PCIe bridges can be plugged into %s", 996 bus->parent_dev->name); 997 return NULL; 998 } 999 1000 if (devfn < 0) { 1001 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices); 1002 devfn += PCI_FUNC_MAX) { 1003 if (pci_bus_devfn_available(bus, devfn) && 1004 !pci_bus_devfn_reserved(bus, devfn)) { 1005 goto found; 1006 } 1007 } 1008 error_setg(errp, "PCI: no slot/function available for %s, all in use " 1009 "or reserved", name); 1010 return NULL; 1011 found: ; 1012 } else if (pci_bus_devfn_reserved(bus, devfn)) { 1013 error_setg(errp, "PCI: slot %d function %d not available for %s," 1014 " reserved", 1015 PCI_SLOT(devfn), PCI_FUNC(devfn), name); 1016 return NULL; 1017 } else if (!pci_bus_devfn_available(bus, devfn)) { 1018 error_setg(errp, "PCI: slot %d function %d not available for %s," 1019 " in use by %s", 1020 PCI_SLOT(devfn), PCI_FUNC(devfn), name, 1021 bus->devices[devfn]->name); 1022 return NULL; 1023 } else if (dev->hotplugged && 1024 pci_get_function_0(pci_dev)) { 1025 error_setg(errp, "PCI: slot %d function 0 already ocuppied by %s," 1026 " new func %s cannot be exposed to guest.", 1027 PCI_SLOT(pci_get_function_0(pci_dev)->devfn), 1028 pci_get_function_0(pci_dev)->name, 1029 name); 1030 1031 return NULL; 1032 } 1033 1034 pci_dev->devfn = devfn; 1035 pci_dev->requester_id_cache = pci_req_id_cache_get(pci_dev); 1036 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name); 1037 1038 memory_region_init(&pci_dev->bus_master_container_region, OBJECT(pci_dev), 1039 "bus master container", UINT64_MAX); 1040 address_space_init(&pci_dev->bus_master_as, 1041 &pci_dev->bus_master_container_region, pci_dev->name); 1042 1043 if (qdev_hotplug) { 1044 pci_init_bus_master(pci_dev); 1045 } 1046 pci_dev->irq_state = 0; 1047 pci_config_alloc(pci_dev); 1048 1049 pci_config_set_vendor_id(pci_dev->config, pc->vendor_id); 1050 pci_config_set_device_id(pci_dev->config, pc->device_id); 1051 pci_config_set_revision(pci_dev->config, pc->revision); 1052 pci_config_set_class(pci_dev->config, pc->class_id); 1053 1054 if (!pc->is_bridge) { 1055 if (pc->subsystem_vendor_id || pc->subsystem_id) { 1056 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, 1057 pc->subsystem_vendor_id); 1058 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 1059 pc->subsystem_id); 1060 } else { 1061 pci_set_default_subsystem_id(pci_dev); 1062 } 1063 } else { 1064 /* subsystem_vendor_id/subsystem_id are only for header type 0 */ 1065 assert(!pc->subsystem_vendor_id); 1066 assert(!pc->subsystem_id); 1067 } 1068 pci_init_cmask(pci_dev); 1069 pci_init_wmask(pci_dev); 1070 pci_init_w1cmask(pci_dev); 1071 if (pc->is_bridge) { 1072 pci_init_mask_bridge(pci_dev); 1073 } 1074 pci_init_multifunction(bus, pci_dev, &local_err); 1075 if (local_err) { 1076 error_propagate(errp, local_err); 1077 do_pci_unregister_device(pci_dev); 1078 return NULL; 1079 } 1080 1081 if (!config_read) 1082 config_read = pci_default_read_config; 1083 if (!config_write) 1084 config_write = pci_default_write_config; 1085 pci_dev->config_read = config_read; 1086 pci_dev->config_write = config_write; 1087 bus->devices[devfn] = pci_dev; 1088 pci_dev->version_id = 2; /* Current pci device vmstate version */ 1089 return pci_dev; 1090 } 1091 1092 static void pci_unregister_io_regions(PCIDevice *pci_dev) 1093 { 1094 PCIIORegion *r; 1095 int i; 1096 1097 for(i = 0; i < PCI_NUM_REGIONS; i++) { 1098 r = &pci_dev->io_regions[i]; 1099 if (!r->size || r->addr == PCI_BAR_UNMAPPED) 1100 continue; 1101 memory_region_del_subregion(r->address_space, r->memory); 1102 } 1103 1104 pci_unregister_vga(pci_dev); 1105 } 1106 1107 static void pci_qdev_unrealize(DeviceState *dev, Error **errp) 1108 { 1109 PCIDevice *pci_dev = PCI_DEVICE(dev); 1110 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 1111 1112 pci_unregister_io_regions(pci_dev); 1113 pci_del_option_rom(pci_dev); 1114 1115 if (pc->exit) { 1116 pc->exit(pci_dev); 1117 } 1118 1119 pci_device_deassert_intx(pci_dev); 1120 do_pci_unregister_device(pci_dev); 1121 } 1122 1123 void pci_register_bar(PCIDevice *pci_dev, int region_num, 1124 uint8_t type, MemoryRegion *memory) 1125 { 1126 PCIIORegion *r; 1127 uint32_t addr; /* offset in pci config space */ 1128 uint64_t wmask; 1129 pcibus_t size = memory_region_size(memory); 1130 1131 assert(region_num >= 0); 1132 assert(region_num < PCI_NUM_REGIONS); 1133 if (size & (size-1)) { 1134 fprintf(stderr, "ERROR: PCI region size must be pow2 " 1135 "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size); 1136 exit(1); 1137 } 1138 1139 r = &pci_dev->io_regions[region_num]; 1140 r->addr = PCI_BAR_UNMAPPED; 1141 r->size = size; 1142 r->type = type; 1143 r->memory = memory; 1144 r->address_space = type & PCI_BASE_ADDRESS_SPACE_IO 1145 ? pci_dev->bus->address_space_io 1146 : pci_dev->bus->address_space_mem; 1147 1148 wmask = ~(size - 1); 1149 if (region_num == PCI_ROM_SLOT) { 1150 /* ROM enable bit is writable */ 1151 wmask |= PCI_ROM_ADDRESS_ENABLE; 1152 } 1153 1154 addr = pci_bar(pci_dev, region_num); 1155 pci_set_long(pci_dev->config + addr, type); 1156 1157 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) && 1158 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 1159 pci_set_quad(pci_dev->wmask + addr, wmask); 1160 pci_set_quad(pci_dev->cmask + addr, ~0ULL); 1161 } else { 1162 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff); 1163 pci_set_long(pci_dev->cmask + addr, 0xffffffff); 1164 } 1165 } 1166 1167 static void pci_update_vga(PCIDevice *pci_dev) 1168 { 1169 uint16_t cmd; 1170 1171 if (!pci_dev->has_vga) { 1172 return; 1173 } 1174 1175 cmd = pci_get_word(pci_dev->config + PCI_COMMAND); 1176 1177 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_MEM], 1178 cmd & PCI_COMMAND_MEMORY); 1179 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO], 1180 cmd & PCI_COMMAND_IO); 1181 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI], 1182 cmd & PCI_COMMAND_IO); 1183 } 1184 1185 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, 1186 MemoryRegion *io_lo, MemoryRegion *io_hi) 1187 { 1188 assert(!pci_dev->has_vga); 1189 1190 assert(memory_region_size(mem) == QEMU_PCI_VGA_MEM_SIZE); 1191 pci_dev->vga_regions[QEMU_PCI_VGA_MEM] = mem; 1192 memory_region_add_subregion_overlap(pci_dev->bus->address_space_mem, 1193 QEMU_PCI_VGA_MEM_BASE, mem, 1); 1194 1195 assert(memory_region_size(io_lo) == QEMU_PCI_VGA_IO_LO_SIZE); 1196 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO] = io_lo; 1197 memory_region_add_subregion_overlap(pci_dev->bus->address_space_io, 1198 QEMU_PCI_VGA_IO_LO_BASE, io_lo, 1); 1199 1200 assert(memory_region_size(io_hi) == QEMU_PCI_VGA_IO_HI_SIZE); 1201 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI] = io_hi; 1202 memory_region_add_subregion_overlap(pci_dev->bus->address_space_io, 1203 QEMU_PCI_VGA_IO_HI_BASE, io_hi, 1); 1204 pci_dev->has_vga = true; 1205 1206 pci_update_vga(pci_dev); 1207 } 1208 1209 void pci_unregister_vga(PCIDevice *pci_dev) 1210 { 1211 if (!pci_dev->has_vga) { 1212 return; 1213 } 1214 1215 memory_region_del_subregion(pci_dev->bus->address_space_mem, 1216 pci_dev->vga_regions[QEMU_PCI_VGA_MEM]); 1217 memory_region_del_subregion(pci_dev->bus->address_space_io, 1218 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO]); 1219 memory_region_del_subregion(pci_dev->bus->address_space_io, 1220 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI]); 1221 pci_dev->has_vga = false; 1222 } 1223 1224 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num) 1225 { 1226 return pci_dev->io_regions[region_num].addr; 1227 } 1228 1229 static pcibus_t pci_bar_address(PCIDevice *d, 1230 int reg, uint8_t type, pcibus_t size) 1231 { 1232 pcibus_t new_addr, last_addr; 1233 int bar = pci_bar(d, reg); 1234 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND); 1235 Object *machine = qdev_get_machine(); 1236 ObjectClass *oc = object_get_class(machine); 1237 MachineClass *mc = MACHINE_CLASS(oc); 1238 bool allow_0_address = mc->pci_allow_0_address; 1239 1240 if (type & PCI_BASE_ADDRESS_SPACE_IO) { 1241 if (!(cmd & PCI_COMMAND_IO)) { 1242 return PCI_BAR_UNMAPPED; 1243 } 1244 new_addr = pci_get_long(d->config + bar) & ~(size - 1); 1245 last_addr = new_addr + size - 1; 1246 /* Check if 32 bit BAR wraps around explicitly. 1247 * TODO: make priorities correct and remove this work around. 1248 */ 1249 if (last_addr <= new_addr || last_addr >= UINT32_MAX || 1250 (!allow_0_address && new_addr == 0)) { 1251 return PCI_BAR_UNMAPPED; 1252 } 1253 return new_addr; 1254 } 1255 1256 if (!(cmd & PCI_COMMAND_MEMORY)) { 1257 return PCI_BAR_UNMAPPED; 1258 } 1259 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 1260 new_addr = pci_get_quad(d->config + bar); 1261 } else { 1262 new_addr = pci_get_long(d->config + bar); 1263 } 1264 /* the ROM slot has a specific enable bit */ 1265 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) { 1266 return PCI_BAR_UNMAPPED; 1267 } 1268 new_addr &= ~(size - 1); 1269 last_addr = new_addr + size - 1; 1270 /* NOTE: we do not support wrapping */ 1271 /* XXX: as we cannot support really dynamic 1272 mappings, we handle specific values as invalid 1273 mappings. */ 1274 if (last_addr <= new_addr || last_addr == PCI_BAR_UNMAPPED || 1275 (!allow_0_address && new_addr == 0)) { 1276 return PCI_BAR_UNMAPPED; 1277 } 1278 1279 /* Now pcibus_t is 64bit. 1280 * Check if 32 bit BAR wraps around explicitly. 1281 * Without this, PC ide doesn't work well. 1282 * TODO: remove this work around. 1283 */ 1284 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) { 1285 return PCI_BAR_UNMAPPED; 1286 } 1287 1288 /* 1289 * OS is allowed to set BAR beyond its addressable 1290 * bits. For example, 32 bit OS can set 64bit bar 1291 * to >4G. Check it. TODO: we might need to support 1292 * it in the future for e.g. PAE. 1293 */ 1294 if (last_addr >= HWADDR_MAX) { 1295 return PCI_BAR_UNMAPPED; 1296 } 1297 1298 return new_addr; 1299 } 1300 1301 static void pci_update_mappings(PCIDevice *d) 1302 { 1303 PCIIORegion *r; 1304 int i; 1305 pcibus_t new_addr; 1306 1307 for(i = 0; i < PCI_NUM_REGIONS; i++) { 1308 r = &d->io_regions[i]; 1309 1310 /* this region isn't registered */ 1311 if (!r->size) 1312 continue; 1313 1314 new_addr = pci_bar_address(d, i, r->type, r->size); 1315 1316 /* This bar isn't changed */ 1317 if (new_addr == r->addr) 1318 continue; 1319 1320 /* now do the real mapping */ 1321 if (r->addr != PCI_BAR_UNMAPPED) { 1322 trace_pci_update_mappings_del(d, pci_bus_num(d->bus), 1323 PCI_SLOT(d->devfn), 1324 PCI_FUNC(d->devfn), 1325 i, r->addr, r->size); 1326 memory_region_del_subregion(r->address_space, r->memory); 1327 } 1328 r->addr = new_addr; 1329 if (r->addr != PCI_BAR_UNMAPPED) { 1330 trace_pci_update_mappings_add(d, pci_bus_num(d->bus), 1331 PCI_SLOT(d->devfn), 1332 PCI_FUNC(d->devfn), 1333 i, r->addr, r->size); 1334 memory_region_add_subregion_overlap(r->address_space, 1335 r->addr, r->memory, 1); 1336 } 1337 } 1338 1339 pci_update_vga(d); 1340 } 1341 1342 static inline int pci_irq_disabled(PCIDevice *d) 1343 { 1344 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE; 1345 } 1346 1347 /* Called after interrupt disabled field update in config space, 1348 * assert/deassert interrupts if necessary. 1349 * Gets original interrupt disable bit value (before update). */ 1350 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled) 1351 { 1352 int i, disabled = pci_irq_disabled(d); 1353 if (disabled == was_irq_disabled) 1354 return; 1355 for (i = 0; i < PCI_NUM_PINS; ++i) { 1356 int state = pci_irq_state(d, i); 1357 pci_change_irq_level(d, i, disabled ? -state : state); 1358 } 1359 } 1360 1361 uint32_t pci_default_read_config(PCIDevice *d, 1362 uint32_t address, int len) 1363 { 1364 uint32_t val = 0; 1365 1366 memcpy(&val, d->config + address, len); 1367 return le32_to_cpu(val); 1368 } 1369 1370 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val_in, int l) 1371 { 1372 int i, was_irq_disabled = pci_irq_disabled(d); 1373 uint32_t val = val_in; 1374 1375 for (i = 0; i < l; val >>= 8, ++i) { 1376 uint8_t wmask = d->wmask[addr + i]; 1377 uint8_t w1cmask = d->w1cmask[addr + i]; 1378 assert(!(wmask & w1cmask)); 1379 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask); 1380 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */ 1381 } 1382 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) || 1383 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) || 1384 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) || 1385 range_covers_byte(addr, l, PCI_COMMAND)) 1386 pci_update_mappings(d); 1387 1388 if (range_covers_byte(addr, l, PCI_COMMAND)) { 1389 pci_update_irq_disabled(d, was_irq_disabled); 1390 memory_region_set_enabled(&d->bus_master_enable_region, 1391 pci_get_word(d->config + PCI_COMMAND) 1392 & PCI_COMMAND_MASTER); 1393 } 1394 1395 msi_write_config(d, addr, val_in, l); 1396 msix_write_config(d, addr, val_in, l); 1397 } 1398 1399 /***********************************************************/ 1400 /* generic PCI irq support */ 1401 1402 /* 0 <= irq_num <= 3. level must be 0 or 1 */ 1403 static void pci_irq_handler(void *opaque, int irq_num, int level) 1404 { 1405 PCIDevice *pci_dev = opaque; 1406 int change; 1407 1408 change = level - pci_irq_state(pci_dev, irq_num); 1409 if (!change) 1410 return; 1411 1412 pci_set_irq_state(pci_dev, irq_num, level); 1413 pci_update_irq_status(pci_dev); 1414 if (pci_irq_disabled(pci_dev)) 1415 return; 1416 pci_change_irq_level(pci_dev, irq_num, change); 1417 } 1418 1419 static inline int pci_intx(PCIDevice *pci_dev) 1420 { 1421 return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1; 1422 } 1423 1424 qemu_irq pci_allocate_irq(PCIDevice *pci_dev) 1425 { 1426 int intx = pci_intx(pci_dev); 1427 1428 return qemu_allocate_irq(pci_irq_handler, pci_dev, intx); 1429 } 1430 1431 void pci_set_irq(PCIDevice *pci_dev, int level) 1432 { 1433 int intx = pci_intx(pci_dev); 1434 pci_irq_handler(pci_dev, intx, level); 1435 } 1436 1437 /* Special hooks used by device assignment */ 1438 void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq) 1439 { 1440 assert(pci_bus_is_root(bus)); 1441 bus->route_intx_to_irq = route_intx_to_irq; 1442 } 1443 1444 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin) 1445 { 1446 PCIBus *bus; 1447 1448 do { 1449 bus = dev->bus; 1450 pin = bus->map_irq(dev, pin); 1451 dev = bus->parent_dev; 1452 } while (dev); 1453 1454 if (!bus->route_intx_to_irq) { 1455 error_report("PCI: Bug - unimplemented PCI INTx routing (%s)", 1456 object_get_typename(OBJECT(bus->qbus.parent))); 1457 return (PCIINTxRoute) { PCI_INTX_DISABLED, -1 }; 1458 } 1459 1460 return bus->route_intx_to_irq(bus->irq_opaque, pin); 1461 } 1462 1463 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new) 1464 { 1465 return old->mode != new->mode || old->irq != new->irq; 1466 } 1467 1468 void pci_bus_fire_intx_routing_notifier(PCIBus *bus) 1469 { 1470 PCIDevice *dev; 1471 PCIBus *sec; 1472 int i; 1473 1474 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 1475 dev = bus->devices[i]; 1476 if (dev && dev->intx_routing_notifier) { 1477 dev->intx_routing_notifier(dev); 1478 } 1479 } 1480 1481 QLIST_FOREACH(sec, &bus->child, sibling) { 1482 pci_bus_fire_intx_routing_notifier(sec); 1483 } 1484 } 1485 1486 void pci_device_set_intx_routing_notifier(PCIDevice *dev, 1487 PCIINTxRoutingNotifier notifier) 1488 { 1489 dev->intx_routing_notifier = notifier; 1490 } 1491 1492 /* 1493 * PCI-to-PCI bridge specification 1494 * 9.1: Interrupt routing. Table 9-1 1495 * 1496 * the PCI Express Base Specification, Revision 2.1 1497 * 2.2.8.1: INTx interrutp signaling - Rules 1498 * the Implementation Note 1499 * Table 2-20 1500 */ 1501 /* 1502 * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD 1503 * 0-origin unlike PCI interrupt pin register. 1504 */ 1505 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin) 1506 { 1507 return (pin + PCI_SLOT(pci_dev->devfn)) % PCI_NUM_PINS; 1508 } 1509 1510 /***********************************************************/ 1511 /* monitor info on PCI */ 1512 1513 typedef struct { 1514 uint16_t class; 1515 const char *desc; 1516 const char *fw_name; 1517 uint16_t fw_ign_bits; 1518 } pci_class_desc; 1519 1520 static const pci_class_desc pci_class_descriptions[] = 1521 { 1522 { 0x0001, "VGA controller", "display"}, 1523 { 0x0100, "SCSI controller", "scsi"}, 1524 { 0x0101, "IDE controller", "ide"}, 1525 { 0x0102, "Floppy controller", "fdc"}, 1526 { 0x0103, "IPI controller", "ipi"}, 1527 { 0x0104, "RAID controller", "raid"}, 1528 { 0x0106, "SATA controller"}, 1529 { 0x0107, "SAS controller"}, 1530 { 0x0180, "Storage controller"}, 1531 { 0x0200, "Ethernet controller", "ethernet"}, 1532 { 0x0201, "Token Ring controller", "token-ring"}, 1533 { 0x0202, "FDDI controller", "fddi"}, 1534 { 0x0203, "ATM controller", "atm"}, 1535 { 0x0280, "Network controller"}, 1536 { 0x0300, "VGA controller", "display", 0x00ff}, 1537 { 0x0301, "XGA controller"}, 1538 { 0x0302, "3D controller"}, 1539 { 0x0380, "Display controller"}, 1540 { 0x0400, "Video controller", "video"}, 1541 { 0x0401, "Audio controller", "sound"}, 1542 { 0x0402, "Phone"}, 1543 { 0x0403, "Audio controller", "sound"}, 1544 { 0x0480, "Multimedia controller"}, 1545 { 0x0500, "RAM controller", "memory"}, 1546 { 0x0501, "Flash controller", "flash"}, 1547 { 0x0580, "Memory controller"}, 1548 { 0x0600, "Host bridge", "host"}, 1549 { 0x0601, "ISA bridge", "isa"}, 1550 { 0x0602, "EISA bridge", "eisa"}, 1551 { 0x0603, "MC bridge", "mca"}, 1552 { 0x0604, "PCI bridge", "pci-bridge"}, 1553 { 0x0605, "PCMCIA bridge", "pcmcia"}, 1554 { 0x0606, "NUBUS bridge", "nubus"}, 1555 { 0x0607, "CARDBUS bridge", "cardbus"}, 1556 { 0x0608, "RACEWAY bridge"}, 1557 { 0x0680, "Bridge"}, 1558 { 0x0700, "Serial port", "serial"}, 1559 { 0x0701, "Parallel port", "parallel"}, 1560 { 0x0800, "Interrupt controller", "interrupt-controller"}, 1561 { 0x0801, "DMA controller", "dma-controller"}, 1562 { 0x0802, "Timer", "timer"}, 1563 { 0x0803, "RTC", "rtc"}, 1564 { 0x0900, "Keyboard", "keyboard"}, 1565 { 0x0901, "Pen", "pen"}, 1566 { 0x0902, "Mouse", "mouse"}, 1567 { 0x0A00, "Dock station", "dock", 0x00ff}, 1568 { 0x0B00, "i386 cpu", "cpu", 0x00ff}, 1569 { 0x0c00, "Fireware contorller", "fireware"}, 1570 { 0x0c01, "Access bus controller", "access-bus"}, 1571 { 0x0c02, "SSA controller", "ssa"}, 1572 { 0x0c03, "USB controller", "usb"}, 1573 { 0x0c04, "Fibre channel controller", "fibre-channel"}, 1574 { 0x0c05, "SMBus"}, 1575 { 0, NULL} 1576 }; 1577 1578 static void pci_for_each_device_under_bus_reverse(PCIBus *bus, 1579 void (*fn)(PCIBus *b, 1580 PCIDevice *d, 1581 void *opaque), 1582 void *opaque) 1583 { 1584 PCIDevice *d; 1585 int devfn; 1586 1587 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1588 d = bus->devices[ARRAY_SIZE(bus->devices) - 1 - devfn]; 1589 if (d) { 1590 fn(bus, d, opaque); 1591 } 1592 } 1593 } 1594 1595 void pci_for_each_device_reverse(PCIBus *bus, int bus_num, 1596 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque), 1597 void *opaque) 1598 { 1599 bus = pci_find_bus_nr(bus, bus_num); 1600 1601 if (bus) { 1602 pci_for_each_device_under_bus_reverse(bus, fn, opaque); 1603 } 1604 } 1605 1606 static void pci_for_each_device_under_bus(PCIBus *bus, 1607 void (*fn)(PCIBus *b, PCIDevice *d, 1608 void *opaque), 1609 void *opaque) 1610 { 1611 PCIDevice *d; 1612 int devfn; 1613 1614 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1615 d = bus->devices[devfn]; 1616 if (d) { 1617 fn(bus, d, opaque); 1618 } 1619 } 1620 } 1621 1622 void pci_for_each_device(PCIBus *bus, int bus_num, 1623 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque), 1624 void *opaque) 1625 { 1626 bus = pci_find_bus_nr(bus, bus_num); 1627 1628 if (bus) { 1629 pci_for_each_device_under_bus(bus, fn, opaque); 1630 } 1631 } 1632 1633 static const pci_class_desc *get_class_desc(int class) 1634 { 1635 const pci_class_desc *desc; 1636 1637 desc = pci_class_descriptions; 1638 while (desc->desc && class != desc->class) { 1639 desc++; 1640 } 1641 1642 return desc; 1643 } 1644 1645 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num); 1646 1647 static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev) 1648 { 1649 PciMemoryRegionList *head = NULL, *cur_item = NULL; 1650 int i; 1651 1652 for (i = 0; i < PCI_NUM_REGIONS; i++) { 1653 const PCIIORegion *r = &dev->io_regions[i]; 1654 PciMemoryRegionList *region; 1655 1656 if (!r->size) { 1657 continue; 1658 } 1659 1660 region = g_malloc0(sizeof(*region)); 1661 region->value = g_malloc0(sizeof(*region->value)); 1662 1663 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { 1664 region->value->type = g_strdup("io"); 1665 } else { 1666 region->value->type = g_strdup("memory"); 1667 region->value->has_prefetch = true; 1668 region->value->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH); 1669 region->value->has_mem_type_64 = true; 1670 region->value->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64); 1671 } 1672 1673 region->value->bar = i; 1674 region->value->address = r->addr; 1675 region->value->size = r->size; 1676 1677 /* XXX: waiting for the qapi to support GSList */ 1678 if (!cur_item) { 1679 head = cur_item = region; 1680 } else { 1681 cur_item->next = region; 1682 cur_item = region; 1683 } 1684 } 1685 1686 return head; 1687 } 1688 1689 static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus, 1690 int bus_num) 1691 { 1692 PciBridgeInfo *info; 1693 PciMemoryRange *range; 1694 1695 info = g_new0(PciBridgeInfo, 1); 1696 1697 info->bus = g_new0(PciBusInfo, 1); 1698 info->bus->number = dev->config[PCI_PRIMARY_BUS]; 1699 info->bus->secondary = dev->config[PCI_SECONDARY_BUS]; 1700 info->bus->subordinate = dev->config[PCI_SUBORDINATE_BUS]; 1701 1702 range = info->bus->io_range = g_new0(PciMemoryRange, 1); 1703 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO); 1704 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO); 1705 1706 range = info->bus->memory_range = g_new0(PciMemoryRange, 1); 1707 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 1708 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 1709 1710 range = info->bus->prefetchable_range = g_new0(PciMemoryRange, 1); 1711 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 1712 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 1713 1714 if (dev->config[PCI_SECONDARY_BUS] != 0) { 1715 PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]); 1716 if (child_bus) { 1717 info->has_devices = true; 1718 info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]); 1719 } 1720 } 1721 1722 return info; 1723 } 1724 1725 static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus, 1726 int bus_num) 1727 { 1728 const pci_class_desc *desc; 1729 PciDeviceInfo *info; 1730 uint8_t type; 1731 int class; 1732 1733 info = g_new0(PciDeviceInfo, 1); 1734 info->bus = bus_num; 1735 info->slot = PCI_SLOT(dev->devfn); 1736 info->function = PCI_FUNC(dev->devfn); 1737 1738 info->class_info = g_new0(PciDeviceClass, 1); 1739 class = pci_get_word(dev->config + PCI_CLASS_DEVICE); 1740 info->class_info->q_class = class; 1741 desc = get_class_desc(class); 1742 if (desc->desc) { 1743 info->class_info->has_desc = true; 1744 info->class_info->desc = g_strdup(desc->desc); 1745 } 1746 1747 info->id = g_new0(PciDeviceId, 1); 1748 info->id->vendor = pci_get_word(dev->config + PCI_VENDOR_ID); 1749 info->id->device = pci_get_word(dev->config + PCI_DEVICE_ID); 1750 info->regions = qmp_query_pci_regions(dev); 1751 info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : ""); 1752 1753 if (dev->config[PCI_INTERRUPT_PIN] != 0) { 1754 info->has_irq = true; 1755 info->irq = dev->config[PCI_INTERRUPT_LINE]; 1756 } 1757 1758 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 1759 if (type == PCI_HEADER_TYPE_BRIDGE) { 1760 info->has_pci_bridge = true; 1761 info->pci_bridge = qmp_query_pci_bridge(dev, bus, bus_num); 1762 } 1763 1764 return info; 1765 } 1766 1767 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num) 1768 { 1769 PciDeviceInfoList *info, *head = NULL, *cur_item = NULL; 1770 PCIDevice *dev; 1771 int devfn; 1772 1773 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1774 dev = bus->devices[devfn]; 1775 if (dev) { 1776 info = g_malloc0(sizeof(*info)); 1777 info->value = qmp_query_pci_device(dev, bus, bus_num); 1778 1779 /* XXX: waiting for the qapi to support GSList */ 1780 if (!cur_item) { 1781 head = cur_item = info; 1782 } else { 1783 cur_item->next = info; 1784 cur_item = info; 1785 } 1786 } 1787 } 1788 1789 return head; 1790 } 1791 1792 static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num) 1793 { 1794 PciInfo *info = NULL; 1795 1796 bus = pci_find_bus_nr(bus, bus_num); 1797 if (bus) { 1798 info = g_malloc0(sizeof(*info)); 1799 info->bus = bus_num; 1800 info->devices = qmp_query_pci_devices(bus, bus_num); 1801 } 1802 1803 return info; 1804 } 1805 1806 PciInfoList *qmp_query_pci(Error **errp) 1807 { 1808 PciInfoList *info, *head = NULL, *cur_item = NULL; 1809 PCIHostState *host_bridge; 1810 1811 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { 1812 info = g_malloc0(sizeof(*info)); 1813 info->value = qmp_query_pci_bus(host_bridge->bus, 1814 pci_bus_num(host_bridge->bus)); 1815 1816 /* XXX: waiting for the qapi to support GSList */ 1817 if (!cur_item) { 1818 head = cur_item = info; 1819 } else { 1820 cur_item->next = info; 1821 cur_item = info; 1822 } 1823 } 1824 1825 return head; 1826 } 1827 1828 static const char * const pci_nic_models[] = { 1829 "ne2k_pci", 1830 "i82551", 1831 "i82557b", 1832 "i82559er", 1833 "rtl8139", 1834 "e1000", 1835 "pcnet", 1836 "virtio", 1837 "sungem", 1838 NULL 1839 }; 1840 1841 static const char * const pci_nic_names[] = { 1842 "ne2k_pci", 1843 "i82551", 1844 "i82557b", 1845 "i82559er", 1846 "rtl8139", 1847 "e1000", 1848 "pcnet", 1849 "virtio-net-pci", 1850 "sungem", 1851 NULL 1852 }; 1853 1854 /* Initialize a PCI NIC. */ 1855 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus, 1856 const char *default_model, 1857 const char *default_devaddr) 1858 { 1859 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr; 1860 PCIBus *bus; 1861 PCIDevice *pci_dev; 1862 DeviceState *dev; 1863 int devfn; 1864 int i; 1865 1866 if (qemu_show_nic_models(nd->model, pci_nic_models)) { 1867 exit(0); 1868 } 1869 1870 i = qemu_find_nic_model(nd, pci_nic_models, default_model); 1871 if (i < 0) { 1872 exit(1); 1873 } 1874 1875 bus = pci_get_bus_devfn(&devfn, rootbus, devaddr); 1876 if (!bus) { 1877 error_report("Invalid PCI device address %s for device %s", 1878 devaddr, pci_nic_names[i]); 1879 exit(1); 1880 } 1881 1882 pci_dev = pci_create(bus, devfn, pci_nic_names[i]); 1883 dev = &pci_dev->qdev; 1884 qdev_set_nic_properties(dev, nd); 1885 qdev_init_nofail(dev); 1886 1887 return pci_dev; 1888 } 1889 1890 PCIDevice *pci_vga_init(PCIBus *bus) 1891 { 1892 switch (vga_interface_type) { 1893 case VGA_CIRRUS: 1894 return pci_create_simple(bus, -1, "cirrus-vga"); 1895 case VGA_QXL: 1896 return pci_create_simple(bus, -1, "qxl-vga"); 1897 case VGA_STD: 1898 return pci_create_simple(bus, -1, "VGA"); 1899 case VGA_VMWARE: 1900 return pci_create_simple(bus, -1, "vmware-svga"); 1901 case VGA_VIRTIO: 1902 return pci_create_simple(bus, -1, "virtio-vga"); 1903 case VGA_NONE: 1904 default: /* Other non-PCI types. Checking for unsupported types is already 1905 done in vl.c. */ 1906 return NULL; 1907 } 1908 } 1909 1910 /* Whether a given bus number is in range of the secondary 1911 * bus of the given bridge device. */ 1912 static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num) 1913 { 1914 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) & 1915 PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ && 1916 dev->config[PCI_SECONDARY_BUS] <= bus_num && 1917 bus_num <= dev->config[PCI_SUBORDINATE_BUS]; 1918 } 1919 1920 /* Whether a given bus number is in a range of a root bus */ 1921 static bool pci_root_bus_in_range(PCIBus *bus, int bus_num) 1922 { 1923 int i; 1924 1925 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 1926 PCIDevice *dev = bus->devices[i]; 1927 1928 if (dev && PCI_DEVICE_GET_CLASS(dev)->is_bridge) { 1929 if (pci_secondary_bus_in_range(dev, bus_num)) { 1930 return true; 1931 } 1932 } 1933 } 1934 1935 return false; 1936 } 1937 1938 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num) 1939 { 1940 PCIBus *sec; 1941 1942 if (!bus) { 1943 return NULL; 1944 } 1945 1946 if (pci_bus_num(bus) == bus_num) { 1947 return bus; 1948 } 1949 1950 /* Consider all bus numbers in range for the host pci bridge. */ 1951 if (!pci_bus_is_root(bus) && 1952 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) { 1953 return NULL; 1954 } 1955 1956 /* try child bus */ 1957 for (; bus; bus = sec) { 1958 QLIST_FOREACH(sec, &bus->child, sibling) { 1959 if (pci_bus_num(sec) == bus_num) { 1960 return sec; 1961 } 1962 /* PXB buses assumed to be children of bus 0 */ 1963 if (pci_bus_is_root(sec)) { 1964 if (pci_root_bus_in_range(sec, bus_num)) { 1965 break; 1966 } 1967 } else { 1968 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) { 1969 break; 1970 } 1971 } 1972 } 1973 } 1974 1975 return NULL; 1976 } 1977 1978 void pci_for_each_bus_depth_first(PCIBus *bus, 1979 void *(*begin)(PCIBus *bus, void *parent_state), 1980 void (*end)(PCIBus *bus, void *state), 1981 void *parent_state) 1982 { 1983 PCIBus *sec; 1984 void *state; 1985 1986 if (!bus) { 1987 return; 1988 } 1989 1990 if (begin) { 1991 state = begin(bus, parent_state); 1992 } else { 1993 state = parent_state; 1994 } 1995 1996 QLIST_FOREACH(sec, &bus->child, sibling) { 1997 pci_for_each_bus_depth_first(sec, begin, end, state); 1998 } 1999 2000 if (end) { 2001 end(bus, state); 2002 } 2003 } 2004 2005 2006 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn) 2007 { 2008 bus = pci_find_bus_nr(bus, bus_num); 2009 2010 if (!bus) 2011 return NULL; 2012 2013 return bus->devices[devfn]; 2014 } 2015 2016 static void pci_qdev_realize(DeviceState *qdev, Error **errp) 2017 { 2018 PCIDevice *pci_dev = (PCIDevice *)qdev; 2019 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 2020 Error *local_err = NULL; 2021 PCIBus *bus; 2022 bool is_default_rom; 2023 2024 /* initialize cap_present for pci_is_express() and pci_config_size() */ 2025 if (pc->is_express) { 2026 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; 2027 } 2028 2029 bus = PCI_BUS(qdev_get_parent_bus(qdev)); 2030 pci_dev = do_pci_register_device(pci_dev, bus, 2031 object_get_typename(OBJECT(qdev)), 2032 pci_dev->devfn, errp); 2033 if (pci_dev == NULL) 2034 return; 2035 2036 if (pc->realize) { 2037 pc->realize(pci_dev, &local_err); 2038 if (local_err) { 2039 error_propagate(errp, local_err); 2040 do_pci_unregister_device(pci_dev); 2041 return; 2042 } 2043 } 2044 2045 /* rom loading */ 2046 is_default_rom = false; 2047 if (pci_dev->romfile == NULL && pc->romfile != NULL) { 2048 pci_dev->romfile = g_strdup(pc->romfile); 2049 is_default_rom = true; 2050 } 2051 2052 pci_add_option_rom(pci_dev, is_default_rom, &local_err); 2053 if (local_err) { 2054 error_propagate(errp, local_err); 2055 pci_qdev_unrealize(DEVICE(pci_dev), NULL); 2056 return; 2057 } 2058 } 2059 2060 static void pci_default_realize(PCIDevice *dev, Error **errp) 2061 { 2062 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 2063 2064 if (pc->init) { 2065 if (pc->init(dev) < 0) { 2066 error_setg(errp, "Device initialization failed"); 2067 return; 2068 } 2069 } 2070 } 2071 2072 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction, 2073 const char *name) 2074 { 2075 DeviceState *dev; 2076 2077 dev = qdev_create(&bus->qbus, name); 2078 qdev_prop_set_int32(dev, "addr", devfn); 2079 qdev_prop_set_bit(dev, "multifunction", multifunction); 2080 return PCI_DEVICE(dev); 2081 } 2082 2083 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, 2084 bool multifunction, 2085 const char *name) 2086 { 2087 PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name); 2088 qdev_init_nofail(&dev->qdev); 2089 return dev; 2090 } 2091 2092 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name) 2093 { 2094 return pci_create_multifunction(bus, devfn, false, name); 2095 } 2096 2097 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name) 2098 { 2099 return pci_create_simple_multifunction(bus, devfn, false, name); 2100 } 2101 2102 static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size) 2103 { 2104 int offset = PCI_CONFIG_HEADER_SIZE; 2105 int i; 2106 for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) { 2107 if (pdev->used[i]) 2108 offset = i + 1; 2109 else if (i - offset + 1 == size) 2110 return offset; 2111 } 2112 return 0; 2113 } 2114 2115 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id, 2116 uint8_t *prev_p) 2117 { 2118 uint8_t next, prev; 2119 2120 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST)) 2121 return 0; 2122 2123 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); 2124 prev = next + PCI_CAP_LIST_NEXT) 2125 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id) 2126 break; 2127 2128 if (prev_p) 2129 *prev_p = prev; 2130 return next; 2131 } 2132 2133 static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset) 2134 { 2135 uint8_t next, prev, found = 0; 2136 2137 if (!(pdev->used[offset])) { 2138 return 0; 2139 } 2140 2141 assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST); 2142 2143 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); 2144 prev = next + PCI_CAP_LIST_NEXT) { 2145 if (next <= offset && next > found) { 2146 found = next; 2147 } 2148 } 2149 return found; 2150 } 2151 2152 /* Patch the PCI vendor and device ids in a PCI rom image if necessary. 2153 This is needed for an option rom which is used for more than one device. */ 2154 static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size) 2155 { 2156 uint16_t vendor_id; 2157 uint16_t device_id; 2158 uint16_t rom_vendor_id; 2159 uint16_t rom_device_id; 2160 uint16_t rom_magic; 2161 uint16_t pcir_offset; 2162 uint8_t checksum; 2163 2164 /* Words in rom data are little endian (like in PCI configuration), 2165 so they can be read / written with pci_get_word / pci_set_word. */ 2166 2167 /* Only a valid rom will be patched. */ 2168 rom_magic = pci_get_word(ptr); 2169 if (rom_magic != 0xaa55) { 2170 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic); 2171 return; 2172 } 2173 pcir_offset = pci_get_word(ptr + 0x18); 2174 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) { 2175 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset); 2176 return; 2177 } 2178 2179 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID); 2180 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID); 2181 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4); 2182 rom_device_id = pci_get_word(ptr + pcir_offset + 6); 2183 2184 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile, 2185 vendor_id, device_id, rom_vendor_id, rom_device_id); 2186 2187 checksum = ptr[6]; 2188 2189 if (vendor_id != rom_vendor_id) { 2190 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */ 2191 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8); 2192 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8); 2193 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); 2194 ptr[6] = checksum; 2195 pci_set_word(ptr + pcir_offset + 4, vendor_id); 2196 } 2197 2198 if (device_id != rom_device_id) { 2199 /* Patch device id and checksum (at offset 6 for etherboot roms). */ 2200 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8); 2201 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8); 2202 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); 2203 ptr[6] = checksum; 2204 pci_set_word(ptr + pcir_offset + 6, device_id); 2205 } 2206 } 2207 2208 /* Add an option rom for the device */ 2209 static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, 2210 Error **errp) 2211 { 2212 int size; 2213 char *path; 2214 void *ptr; 2215 char name[32]; 2216 const VMStateDescription *vmsd; 2217 2218 if (!pdev->romfile) 2219 return; 2220 if (strlen(pdev->romfile) == 0) 2221 return; 2222 2223 if (!pdev->rom_bar) { 2224 /* 2225 * Load rom via fw_cfg instead of creating a rom bar, 2226 * for 0.11 compatibility. 2227 */ 2228 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE); 2229 2230 /* 2231 * Hot-plugged devices can't use the option ROM 2232 * if the rom bar is disabled. 2233 */ 2234 if (DEVICE(pdev)->hotplugged) { 2235 error_setg(errp, "Hot-plugged device without ROM bar" 2236 " can't have an option ROM"); 2237 return; 2238 } 2239 2240 if (class == 0x0300) { 2241 rom_add_vga(pdev->romfile); 2242 } else { 2243 rom_add_option(pdev->romfile, -1); 2244 } 2245 return; 2246 } 2247 2248 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile); 2249 if (path == NULL) { 2250 path = g_strdup(pdev->romfile); 2251 } 2252 2253 size = get_image_size(path); 2254 if (size < 0) { 2255 error_setg(errp, "failed to find romfile \"%s\"", pdev->romfile); 2256 g_free(path); 2257 return; 2258 } else if (size == 0) { 2259 error_setg(errp, "romfile \"%s\" is empty", pdev->romfile); 2260 g_free(path); 2261 return; 2262 } 2263 size = pow2ceil(size); 2264 2265 vmsd = qdev_get_vmsd(DEVICE(pdev)); 2266 2267 if (vmsd) { 2268 snprintf(name, sizeof(name), "%s.rom", vmsd->name); 2269 } else { 2270 snprintf(name, sizeof(name), "%s.rom", object_get_typename(OBJECT(pdev))); 2271 } 2272 pdev->has_rom = true; 2273 memory_region_init_rom(&pdev->rom, OBJECT(pdev), name, size, &error_fatal); 2274 ptr = memory_region_get_ram_ptr(&pdev->rom); 2275 load_image(path, ptr); 2276 g_free(path); 2277 2278 if (is_default_rom) { 2279 /* Only the default rom images will be patched (if needed). */ 2280 pci_patch_ids(pdev, ptr, size); 2281 } 2282 2283 pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom); 2284 } 2285 2286 static void pci_del_option_rom(PCIDevice *pdev) 2287 { 2288 if (!pdev->has_rom) 2289 return; 2290 2291 vmstate_unregister_ram(&pdev->rom, &pdev->qdev); 2292 pdev->has_rom = false; 2293 } 2294 2295 /* 2296 * On success, pci_add_capability() returns a positive value 2297 * that the offset of the pci capability. 2298 * On failure, it sets an error and returns a negative error 2299 * code. 2300 */ 2301 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, 2302 uint8_t offset, uint8_t size, 2303 Error **errp) 2304 { 2305 uint8_t *config; 2306 int i, overlapping_cap; 2307 2308 if (!offset) { 2309 offset = pci_find_space(pdev, size); 2310 /* out of PCI config space is programming error */ 2311 assert(offset); 2312 } else { 2313 /* Verify that capabilities don't overlap. Note: device assignment 2314 * depends on this check to verify that the device is not broken. 2315 * Should never trigger for emulated devices, but it's helpful 2316 * for debugging these. */ 2317 for (i = offset; i < offset + size; i++) { 2318 overlapping_cap = pci_find_capability_at_offset(pdev, i); 2319 if (overlapping_cap) { 2320 error_setg(errp, "%s:%02x:%02x.%x " 2321 "Attempt to add PCI capability %x at offset " 2322 "%x overlaps existing capability %x at offset %x", 2323 pci_root_bus_path(pdev), pci_bus_num(pdev->bus), 2324 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), 2325 cap_id, offset, overlapping_cap, i); 2326 return -EINVAL; 2327 } 2328 } 2329 } 2330 2331 config = pdev->config + offset; 2332 config[PCI_CAP_LIST_ID] = cap_id; 2333 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST]; 2334 pdev->config[PCI_CAPABILITY_LIST] = offset; 2335 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST; 2336 memset(pdev->used + offset, 0xFF, QEMU_ALIGN_UP(size, 4)); 2337 /* Make capability read-only by default */ 2338 memset(pdev->wmask + offset, 0, size); 2339 /* Check capability by default */ 2340 memset(pdev->cmask + offset, 0xFF, size); 2341 return offset; 2342 } 2343 2344 /* Unlink capability from the pci config space. */ 2345 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size) 2346 { 2347 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev); 2348 if (!offset) 2349 return; 2350 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT]; 2351 /* Make capability writable again */ 2352 memset(pdev->wmask + offset, 0xff, size); 2353 memset(pdev->w1cmask + offset, 0, size); 2354 /* Clear cmask as device-specific registers can't be checked */ 2355 memset(pdev->cmask + offset, 0, size); 2356 memset(pdev->used + offset, 0, QEMU_ALIGN_UP(size, 4)); 2357 2358 if (!pdev->config[PCI_CAPABILITY_LIST]) 2359 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST; 2360 } 2361 2362 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id) 2363 { 2364 return pci_find_capability_list(pdev, cap_id, NULL); 2365 } 2366 2367 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent) 2368 { 2369 PCIDevice *d = (PCIDevice *)dev; 2370 const pci_class_desc *desc; 2371 char ctxt[64]; 2372 PCIIORegion *r; 2373 int i, class; 2374 2375 class = pci_get_word(d->config + PCI_CLASS_DEVICE); 2376 desc = pci_class_descriptions; 2377 while (desc->desc && class != desc->class) 2378 desc++; 2379 if (desc->desc) { 2380 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc); 2381 } else { 2382 snprintf(ctxt, sizeof(ctxt), "Class %04x", class); 2383 } 2384 2385 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, " 2386 "pci id %04x:%04x (sub %04x:%04x)\n", 2387 indent, "", ctxt, pci_bus_num(d->bus), 2388 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn), 2389 pci_get_word(d->config + PCI_VENDOR_ID), 2390 pci_get_word(d->config + PCI_DEVICE_ID), 2391 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID), 2392 pci_get_word(d->config + PCI_SUBSYSTEM_ID)); 2393 for (i = 0; i < PCI_NUM_REGIONS; i++) { 2394 r = &d->io_regions[i]; 2395 if (!r->size) 2396 continue; 2397 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS 2398 " [0x%"FMT_PCIBUS"]\n", 2399 indent, "", 2400 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem", 2401 r->addr, r->addr + r->size - 1); 2402 } 2403 } 2404 2405 static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len) 2406 { 2407 PCIDevice *d = (PCIDevice *)dev; 2408 const char *name = NULL; 2409 const pci_class_desc *desc = pci_class_descriptions; 2410 int class = pci_get_word(d->config + PCI_CLASS_DEVICE); 2411 2412 while (desc->desc && 2413 (class & ~desc->fw_ign_bits) != 2414 (desc->class & ~desc->fw_ign_bits)) { 2415 desc++; 2416 } 2417 2418 if (desc->desc) { 2419 name = desc->fw_name; 2420 } 2421 2422 if (name) { 2423 pstrcpy(buf, len, name); 2424 } else { 2425 snprintf(buf, len, "pci%04x,%04x", 2426 pci_get_word(d->config + PCI_VENDOR_ID), 2427 pci_get_word(d->config + PCI_DEVICE_ID)); 2428 } 2429 2430 return buf; 2431 } 2432 2433 static char *pcibus_get_fw_dev_path(DeviceState *dev) 2434 { 2435 PCIDevice *d = (PCIDevice *)dev; 2436 char path[50], name[33]; 2437 int off; 2438 2439 off = snprintf(path, sizeof(path), "%s@%x", 2440 pci_dev_fw_name(dev, name, sizeof name), 2441 PCI_SLOT(d->devfn)); 2442 if (PCI_FUNC(d->devfn)) 2443 snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn)); 2444 return g_strdup(path); 2445 } 2446 2447 static char *pcibus_get_dev_path(DeviceState *dev) 2448 { 2449 PCIDevice *d = container_of(dev, PCIDevice, qdev); 2450 PCIDevice *t; 2451 int slot_depth; 2452 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function. 2453 * 00 is added here to make this format compatible with 2454 * domain:Bus:Slot.Func for systems without nested PCI bridges. 2455 * Slot.Function list specifies the slot and function numbers for all 2456 * devices on the path from root to the specific device. */ 2457 const char *root_bus_path; 2458 int root_bus_len; 2459 char slot[] = ":SS.F"; 2460 int slot_len = sizeof slot - 1 /* For '\0' */; 2461 int path_len; 2462 char *path, *p; 2463 int s; 2464 2465 root_bus_path = pci_root_bus_path(d); 2466 root_bus_len = strlen(root_bus_path); 2467 2468 /* Calculate # of slots on path between device and root. */; 2469 slot_depth = 0; 2470 for (t = d; t; t = t->bus->parent_dev) { 2471 ++slot_depth; 2472 } 2473 2474 path_len = root_bus_len + slot_len * slot_depth; 2475 2476 /* Allocate memory, fill in the terminating null byte. */ 2477 path = g_malloc(path_len + 1 /* For '\0' */); 2478 path[path_len] = '\0'; 2479 2480 memcpy(path, root_bus_path, root_bus_len); 2481 2482 /* Fill in slot numbers. We walk up from device to root, so need to print 2483 * them in the reverse order, last to first. */ 2484 p = path + path_len; 2485 for (t = d; t; t = t->bus->parent_dev) { 2486 p -= slot_len; 2487 s = snprintf(slot, sizeof slot, ":%02x.%x", 2488 PCI_SLOT(t->devfn), PCI_FUNC(t->devfn)); 2489 assert(s == slot_len); 2490 memcpy(p, slot, slot_len); 2491 } 2492 2493 return path; 2494 } 2495 2496 static int pci_qdev_find_recursive(PCIBus *bus, 2497 const char *id, PCIDevice **pdev) 2498 { 2499 DeviceState *qdev = qdev_find_recursive(&bus->qbus, id); 2500 if (!qdev) { 2501 return -ENODEV; 2502 } 2503 2504 /* roughly check if given qdev is pci device */ 2505 if (object_dynamic_cast(OBJECT(qdev), TYPE_PCI_DEVICE)) { 2506 *pdev = PCI_DEVICE(qdev); 2507 return 0; 2508 } 2509 return -EINVAL; 2510 } 2511 2512 int pci_qdev_find_device(const char *id, PCIDevice **pdev) 2513 { 2514 PCIHostState *host_bridge; 2515 int rc = -ENODEV; 2516 2517 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { 2518 int tmp = pci_qdev_find_recursive(host_bridge->bus, id, pdev); 2519 if (!tmp) { 2520 rc = 0; 2521 break; 2522 } 2523 if (tmp != -ENODEV) { 2524 rc = tmp; 2525 } 2526 } 2527 2528 return rc; 2529 } 2530 2531 MemoryRegion *pci_address_space(PCIDevice *dev) 2532 { 2533 return dev->bus->address_space_mem; 2534 } 2535 2536 MemoryRegion *pci_address_space_io(PCIDevice *dev) 2537 { 2538 return dev->bus->address_space_io; 2539 } 2540 2541 static void pci_device_class_init(ObjectClass *klass, void *data) 2542 { 2543 DeviceClass *k = DEVICE_CLASS(klass); 2544 PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass); 2545 2546 k->realize = pci_qdev_realize; 2547 k->unrealize = pci_qdev_unrealize; 2548 k->bus_type = TYPE_PCI_BUS; 2549 k->props = pci_props; 2550 pc->realize = pci_default_realize; 2551 } 2552 2553 static void pci_device_class_base_init(ObjectClass *klass, void *data) 2554 { 2555 if (!object_class_is_abstract(klass)) { 2556 ObjectClass *conventional = 2557 object_class_dynamic_cast(klass, INTERFACE_CONVENTIONAL_PCI_DEVICE); 2558 ObjectClass *pcie = 2559 object_class_dynamic_cast(klass, INTERFACE_PCIE_DEVICE); 2560 assert(conventional || pcie); 2561 } 2562 } 2563 2564 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev) 2565 { 2566 PCIBus *bus = PCI_BUS(dev->bus); 2567 PCIBus *iommu_bus = bus; 2568 2569 while(iommu_bus && !iommu_bus->iommu_fn && iommu_bus->parent_dev) { 2570 iommu_bus = PCI_BUS(iommu_bus->parent_dev->bus); 2571 } 2572 if (iommu_bus && iommu_bus->iommu_fn) { 2573 return iommu_bus->iommu_fn(bus, iommu_bus->iommu_opaque, dev->devfn); 2574 } 2575 return &address_space_memory; 2576 } 2577 2578 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque) 2579 { 2580 bus->iommu_fn = fn; 2581 bus->iommu_opaque = opaque; 2582 } 2583 2584 static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque) 2585 { 2586 Range *range = opaque; 2587 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 2588 uint16_t cmd = pci_get_word(dev->config + PCI_COMMAND); 2589 int i; 2590 2591 if (!(cmd & PCI_COMMAND_MEMORY)) { 2592 return; 2593 } 2594 2595 if (pc->is_bridge) { 2596 pcibus_t base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 2597 pcibus_t limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 2598 2599 base = MAX(base, 0x1ULL << 32); 2600 2601 if (limit >= base) { 2602 Range pref_range; 2603 range_set_bounds(&pref_range, base, limit); 2604 range_extend(range, &pref_range); 2605 } 2606 } 2607 for (i = 0; i < PCI_NUM_REGIONS; ++i) { 2608 PCIIORegion *r = &dev->io_regions[i]; 2609 pcibus_t lob, upb; 2610 Range region_range; 2611 2612 if (!r->size || 2613 (r->type & PCI_BASE_ADDRESS_SPACE_IO) || 2614 !(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64)) { 2615 continue; 2616 } 2617 2618 lob = pci_bar_address(dev, i, r->type, r->size); 2619 upb = lob + r->size - 1; 2620 if (lob == PCI_BAR_UNMAPPED) { 2621 continue; 2622 } 2623 2624 lob = MAX(lob, 0x1ULL << 32); 2625 2626 if (upb >= lob) { 2627 range_set_bounds(®ion_range, lob, upb); 2628 range_extend(range, ®ion_range); 2629 } 2630 } 2631 } 2632 2633 void pci_bus_get_w64_range(PCIBus *bus, Range *range) 2634 { 2635 range_make_empty(range); 2636 pci_for_each_device_under_bus(bus, pci_dev_get_w64, range); 2637 } 2638 2639 static bool pcie_has_upstream_port(PCIDevice *dev) 2640 { 2641 PCIDevice *parent_dev = pci_bridge_get_device(dev->bus); 2642 2643 /* Device associated with an upstream port. 2644 * As there are several types of these, it's easier to check the 2645 * parent device: upstream ports are always connected to 2646 * root or downstream ports. 2647 */ 2648 return parent_dev && 2649 pci_is_express(parent_dev) && 2650 parent_dev->exp.exp_cap && 2651 (pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_ROOT_PORT || 2652 pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_DOWNSTREAM); 2653 } 2654 2655 PCIDevice *pci_get_function_0(PCIDevice *pci_dev) 2656 { 2657 if(pcie_has_upstream_port(pci_dev)) { 2658 /* With an upstream PCIe port, we only support 1 device at slot 0 */ 2659 return pci_dev->bus->devices[0]; 2660 } else { 2661 /* Other bus types might support multiple devices at slots 0-31 */ 2662 return pci_dev->bus->devices[PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 0)]; 2663 } 2664 } 2665 2666 MSIMessage pci_get_msi_message(PCIDevice *dev, int vector) 2667 { 2668 MSIMessage msg; 2669 if (msix_enabled(dev)) { 2670 msg = msix_get_message(dev, vector); 2671 } else if (msi_enabled(dev)) { 2672 msg = msi_get_message(dev, vector); 2673 } else { 2674 /* Should never happen */ 2675 error_report("%s: unknown interrupt type", __func__); 2676 abort(); 2677 } 2678 return msg; 2679 } 2680 2681 static const TypeInfo pci_device_type_info = { 2682 .name = TYPE_PCI_DEVICE, 2683 .parent = TYPE_DEVICE, 2684 .instance_size = sizeof(PCIDevice), 2685 .abstract = true, 2686 .class_size = sizeof(PCIDeviceClass), 2687 .class_init = pci_device_class_init, 2688 .class_base_init = pci_device_class_base_init, 2689 }; 2690 2691 static void pci_register_types(void) 2692 { 2693 type_register_static(&pci_bus_info); 2694 type_register_static(&pcie_bus_info); 2695 type_register_static(&conventional_pci_interface_info); 2696 type_register_static(&pcie_interface_info); 2697 type_register_static(&pci_device_type_info); 2698 } 2699 2700 type_init(pci_register_types) 2701