xref: /openbmc/qemu/hw/pci/pci.c (revision 64552b6b)
1 /*
2  * QEMU PCI bus manager
3  *
4  * Copyright (c) 2004 Fabrice Bellard
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a copy
7  * of this software and associated documentation files (the "Software"), to deal
8  * in the Software without restriction, including without limitation the rights
9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10  * copies of the Software, and to permit persons to whom the Software is
11  * furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22  * THE SOFTWARE.
23  */
24 
25 #include "qemu/osdep.h"
26 #include "qemu-common.h"
27 #include "hw/hw.h"
28 #include "hw/irq.h"
29 #include "hw/pci/pci.h"
30 #include "hw/pci/pci_bridge.h"
31 #include "hw/pci/pci_bus.h"
32 #include "hw/pci/pci_host.h"
33 #include "migration/qemu-file-types.h"
34 #include "monitor/monitor.h"
35 #include "net/net.h"
36 #include "sysemu/sysemu.h"
37 #include "hw/loader.h"
38 #include "qemu/error-report.h"
39 #include "qemu/range.h"
40 #include "trace.h"
41 #include "hw/pci/msi.h"
42 #include "hw/pci/msix.h"
43 #include "exec/address-spaces.h"
44 #include "hw/hotplug.h"
45 #include "hw/boards.h"
46 #include "qapi/error.h"
47 #include "qapi/qapi-commands-misc.h"
48 #include "qemu/cutils.h"
49 
50 //#define DEBUG_PCI
51 #ifdef DEBUG_PCI
52 # define PCI_DPRINTF(format, ...)       printf(format, ## __VA_ARGS__)
53 #else
54 # define PCI_DPRINTF(format, ...)       do { } while (0)
55 #endif
56 
57 bool pci_available = true;
58 
59 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
60 static char *pcibus_get_dev_path(DeviceState *dev);
61 static char *pcibus_get_fw_dev_path(DeviceState *dev);
62 static void pcibus_reset(BusState *qbus);
63 
64 static Property pci_props[] = {
65     DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
66     DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
67     DEFINE_PROP_UINT32("rombar",  PCIDevice, rom_bar, 1),
68     DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present,
69                     QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
70     DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present,
71                     QEMU_PCI_CAP_SERR_BITNR, true),
72     DEFINE_PROP_BIT("x-pcie-lnksta-dllla", PCIDevice, cap_present,
73                     QEMU_PCIE_LNKSTA_DLLLA_BITNR, true),
74     DEFINE_PROP_BIT("x-pcie-extcap-init", PCIDevice, cap_present,
75                     QEMU_PCIE_EXTCAP_INIT_BITNR, true),
76     DEFINE_PROP_END_OF_LIST()
77 };
78 
79 static const VMStateDescription vmstate_pcibus = {
80     .name = "PCIBUS",
81     .version_id = 1,
82     .minimum_version_id = 1,
83     .fields = (VMStateField[]) {
84         VMSTATE_INT32_EQUAL(nirq, PCIBus, NULL),
85         VMSTATE_VARRAY_INT32(irq_count, PCIBus,
86                              nirq, 0, vmstate_info_int32,
87                              int32_t),
88         VMSTATE_END_OF_LIST()
89     }
90 };
91 
92 static void pci_init_bus_master(PCIDevice *pci_dev)
93 {
94     AddressSpace *dma_as = pci_device_iommu_address_space(pci_dev);
95 
96     memory_region_init_alias(&pci_dev->bus_master_enable_region,
97                              OBJECT(pci_dev), "bus master",
98                              dma_as->root, 0, memory_region_size(dma_as->root));
99     memory_region_set_enabled(&pci_dev->bus_master_enable_region, false);
100     memory_region_add_subregion(&pci_dev->bus_master_container_region, 0,
101                                 &pci_dev->bus_master_enable_region);
102 }
103 
104 static void pcibus_machine_done(Notifier *notifier, void *data)
105 {
106     PCIBus *bus = container_of(notifier, PCIBus, machine_done);
107     int i;
108 
109     for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
110         if (bus->devices[i]) {
111             pci_init_bus_master(bus->devices[i]);
112         }
113     }
114 }
115 
116 static void pci_bus_realize(BusState *qbus, Error **errp)
117 {
118     PCIBus *bus = PCI_BUS(qbus);
119 
120     bus->machine_done.notify = pcibus_machine_done;
121     qemu_add_machine_init_done_notifier(&bus->machine_done);
122 
123     vmstate_register(NULL, -1, &vmstate_pcibus, bus);
124 }
125 
126 static void pcie_bus_realize(BusState *qbus, Error **errp)
127 {
128     PCIBus *bus = PCI_BUS(qbus);
129 
130     pci_bus_realize(qbus, errp);
131 
132     /*
133      * A PCI-E bus can support extended config space if it's the root
134      * bus, or if the bus/bridge above it does as well
135      */
136     if (pci_bus_is_root(bus)) {
137         bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE;
138     } else {
139         PCIBus *parent_bus = pci_get_bus(bus->parent_dev);
140 
141         if (pci_bus_allows_extended_config_space(parent_bus)) {
142             bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE;
143         }
144     }
145 }
146 
147 static void pci_bus_unrealize(BusState *qbus, Error **errp)
148 {
149     PCIBus *bus = PCI_BUS(qbus);
150 
151     qemu_remove_machine_init_done_notifier(&bus->machine_done);
152 
153     vmstate_unregister(NULL, &vmstate_pcibus, bus);
154 }
155 
156 static int pcibus_num(PCIBus *bus)
157 {
158     if (pci_bus_is_root(bus)) {
159         return 0; /* pci host bridge */
160     }
161     return bus->parent_dev->config[PCI_SECONDARY_BUS];
162 }
163 
164 static uint16_t pcibus_numa_node(PCIBus *bus)
165 {
166     return NUMA_NODE_UNASSIGNED;
167 }
168 
169 static void pci_bus_class_init(ObjectClass *klass, void *data)
170 {
171     BusClass *k = BUS_CLASS(klass);
172     PCIBusClass *pbc = PCI_BUS_CLASS(klass);
173 
174     k->print_dev = pcibus_dev_print;
175     k->get_dev_path = pcibus_get_dev_path;
176     k->get_fw_dev_path = pcibus_get_fw_dev_path;
177     k->realize = pci_bus_realize;
178     k->unrealize = pci_bus_unrealize;
179     k->reset = pcibus_reset;
180 
181     pbc->bus_num = pcibus_num;
182     pbc->numa_node = pcibus_numa_node;
183 }
184 
185 static const TypeInfo pci_bus_info = {
186     .name = TYPE_PCI_BUS,
187     .parent = TYPE_BUS,
188     .instance_size = sizeof(PCIBus),
189     .class_size = sizeof(PCIBusClass),
190     .class_init = pci_bus_class_init,
191 };
192 
193 static const TypeInfo pcie_interface_info = {
194     .name          = INTERFACE_PCIE_DEVICE,
195     .parent        = TYPE_INTERFACE,
196 };
197 
198 static const TypeInfo conventional_pci_interface_info = {
199     .name          = INTERFACE_CONVENTIONAL_PCI_DEVICE,
200     .parent        = TYPE_INTERFACE,
201 };
202 
203 static void pcie_bus_class_init(ObjectClass *klass, void *data)
204 {
205     BusClass *k = BUS_CLASS(klass);
206 
207     k->realize = pcie_bus_realize;
208 }
209 
210 static const TypeInfo pcie_bus_info = {
211     .name = TYPE_PCIE_BUS,
212     .parent = TYPE_PCI_BUS,
213     .class_init = pcie_bus_class_init,
214 };
215 
216 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num);
217 static void pci_update_mappings(PCIDevice *d);
218 static void pci_irq_handler(void *opaque, int irq_num, int level);
219 static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, Error **);
220 static void pci_del_option_rom(PCIDevice *pdev);
221 
222 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
223 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
224 
225 static QLIST_HEAD(, PCIHostState) pci_host_bridges;
226 
227 int pci_bar(PCIDevice *d, int reg)
228 {
229     uint8_t type;
230 
231     if (reg != PCI_ROM_SLOT)
232         return PCI_BASE_ADDRESS_0 + reg * 4;
233 
234     type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
235     return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
236 }
237 
238 static inline int pci_irq_state(PCIDevice *d, int irq_num)
239 {
240         return (d->irq_state >> irq_num) & 0x1;
241 }
242 
243 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
244 {
245         d->irq_state &= ~(0x1 << irq_num);
246         d->irq_state |= level << irq_num;
247 }
248 
249 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
250 {
251     PCIBus *bus;
252     for (;;) {
253         bus = pci_get_bus(pci_dev);
254         irq_num = bus->map_irq(pci_dev, irq_num);
255         if (bus->set_irq)
256             break;
257         pci_dev = bus->parent_dev;
258     }
259     bus->irq_count[irq_num] += change;
260     bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
261 }
262 
263 int pci_bus_get_irq_level(PCIBus *bus, int irq_num)
264 {
265     assert(irq_num >= 0);
266     assert(irq_num < bus->nirq);
267     return !!bus->irq_count[irq_num];
268 }
269 
270 /* Update interrupt status bit in config space on interrupt
271  * state change. */
272 static void pci_update_irq_status(PCIDevice *dev)
273 {
274     if (dev->irq_state) {
275         dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;
276     } else {
277         dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
278     }
279 }
280 
281 void pci_device_deassert_intx(PCIDevice *dev)
282 {
283     int i;
284     for (i = 0; i < PCI_NUM_PINS; ++i) {
285         pci_irq_handler(dev, i, 0);
286     }
287 }
288 
289 static void pci_do_device_reset(PCIDevice *dev)
290 {
291     int r;
292 
293     pci_device_deassert_intx(dev);
294     assert(dev->irq_state == 0);
295 
296     /* Clear all writable bits */
297     pci_word_test_and_clear_mask(dev->config + PCI_COMMAND,
298                                  pci_get_word(dev->wmask + PCI_COMMAND) |
299                                  pci_get_word(dev->w1cmask + PCI_COMMAND));
300     pci_word_test_and_clear_mask(dev->config + PCI_STATUS,
301                                  pci_get_word(dev->wmask + PCI_STATUS) |
302                                  pci_get_word(dev->w1cmask + PCI_STATUS));
303     dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
304     dev->config[PCI_INTERRUPT_LINE] = 0x0;
305     for (r = 0; r < PCI_NUM_REGIONS; ++r) {
306         PCIIORegion *region = &dev->io_regions[r];
307         if (!region->size) {
308             continue;
309         }
310 
311         if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) &&
312             region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
313             pci_set_quad(dev->config + pci_bar(dev, r), region->type);
314         } else {
315             pci_set_long(dev->config + pci_bar(dev, r), region->type);
316         }
317     }
318     pci_update_mappings(dev);
319 
320     msi_reset(dev);
321     msix_reset(dev);
322 }
323 
324 /*
325  * This function is called on #RST and FLR.
326  * FLR if PCI_EXP_DEVCTL_BCR_FLR is set
327  */
328 void pci_device_reset(PCIDevice *dev)
329 {
330     qdev_reset_all(&dev->qdev);
331     pci_do_device_reset(dev);
332 }
333 
334 /*
335  * Trigger pci bus reset under a given bus.
336  * Called via qbus_reset_all on RST# assert, after the devices
337  * have been reset qdev_reset_all-ed already.
338  */
339 static void pcibus_reset(BusState *qbus)
340 {
341     PCIBus *bus = DO_UPCAST(PCIBus, qbus, qbus);
342     int i;
343 
344     for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
345         if (bus->devices[i]) {
346             pci_do_device_reset(bus->devices[i]);
347         }
348     }
349 
350     for (i = 0; i < bus->nirq; i++) {
351         assert(bus->irq_count[i] == 0);
352     }
353 }
354 
355 static void pci_host_bus_register(DeviceState *host)
356 {
357     PCIHostState *host_bridge = PCI_HOST_BRIDGE(host);
358 
359     QLIST_INSERT_HEAD(&pci_host_bridges, host_bridge, next);
360 }
361 
362 static void pci_host_bus_unregister(DeviceState *host)
363 {
364     PCIHostState *host_bridge = PCI_HOST_BRIDGE(host);
365 
366     QLIST_REMOVE(host_bridge, next);
367 }
368 
369 PCIBus *pci_device_root_bus(const PCIDevice *d)
370 {
371     PCIBus *bus = pci_get_bus(d);
372 
373     while (!pci_bus_is_root(bus)) {
374         d = bus->parent_dev;
375         assert(d != NULL);
376 
377         bus = pci_get_bus(d);
378     }
379 
380     return bus;
381 }
382 
383 const char *pci_root_bus_path(PCIDevice *dev)
384 {
385     PCIBus *rootbus = pci_device_root_bus(dev);
386     PCIHostState *host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent);
387     PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_GET_CLASS(host_bridge);
388 
389     assert(host_bridge->bus == rootbus);
390 
391     if (hc->root_bus_path) {
392         return (*hc->root_bus_path)(host_bridge, rootbus);
393     }
394 
395     return rootbus->qbus.name;
396 }
397 
398 static void pci_root_bus_init(PCIBus *bus, DeviceState *parent,
399                               MemoryRegion *address_space_mem,
400                               MemoryRegion *address_space_io,
401                               uint8_t devfn_min)
402 {
403     assert(PCI_FUNC(devfn_min) == 0);
404     bus->devfn_min = devfn_min;
405     bus->slot_reserved_mask = 0x0;
406     bus->address_space_mem = address_space_mem;
407     bus->address_space_io = address_space_io;
408     bus->flags |= PCI_BUS_IS_ROOT;
409 
410     /* host bridge */
411     QLIST_INIT(&bus->child);
412 
413     pci_host_bus_register(parent);
414 }
415 
416 static void pci_bus_uninit(PCIBus *bus)
417 {
418     pci_host_bus_unregister(BUS(bus)->parent);
419 }
420 
421 bool pci_bus_is_express(PCIBus *bus)
422 {
423     return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS);
424 }
425 
426 void pci_root_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent,
427                               const char *name,
428                               MemoryRegion *address_space_mem,
429                               MemoryRegion *address_space_io,
430                               uint8_t devfn_min, const char *typename)
431 {
432     qbus_create_inplace(bus, bus_size, typename, parent, name);
433     pci_root_bus_init(bus, parent, address_space_mem, address_space_io,
434                       devfn_min);
435 }
436 
437 PCIBus *pci_root_bus_new(DeviceState *parent, const char *name,
438                          MemoryRegion *address_space_mem,
439                          MemoryRegion *address_space_io,
440                          uint8_t devfn_min, const char *typename)
441 {
442     PCIBus *bus;
443 
444     bus = PCI_BUS(qbus_create(typename, parent, name));
445     pci_root_bus_init(bus, parent, address_space_mem, address_space_io,
446                       devfn_min);
447     return bus;
448 }
449 
450 void pci_root_bus_cleanup(PCIBus *bus)
451 {
452     pci_bus_uninit(bus);
453     /* the caller of the unplug hotplug handler will delete this device */
454     object_property_set_bool(OBJECT(bus), false, "realized", NULL);
455 }
456 
457 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
458                   void *irq_opaque, int nirq)
459 {
460     bus->set_irq = set_irq;
461     bus->map_irq = map_irq;
462     bus->irq_opaque = irq_opaque;
463     bus->nirq = nirq;
464     bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0]));
465 }
466 
467 void pci_bus_irqs_cleanup(PCIBus *bus)
468 {
469     bus->set_irq = NULL;
470     bus->map_irq = NULL;
471     bus->irq_opaque = NULL;
472     bus->nirq = 0;
473     g_free(bus->irq_count);
474 }
475 
476 PCIBus *pci_register_root_bus(DeviceState *parent, const char *name,
477                               pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
478                               void *irq_opaque,
479                               MemoryRegion *address_space_mem,
480                               MemoryRegion *address_space_io,
481                               uint8_t devfn_min, int nirq,
482                               const char *typename)
483 {
484     PCIBus *bus;
485 
486     bus = pci_root_bus_new(parent, name, address_space_mem,
487                            address_space_io, devfn_min, typename);
488     pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
489     return bus;
490 }
491 
492 void pci_unregister_root_bus(PCIBus *bus)
493 {
494     pci_bus_irqs_cleanup(bus);
495     pci_root_bus_cleanup(bus);
496 }
497 
498 int pci_bus_num(PCIBus *s)
499 {
500     return PCI_BUS_GET_CLASS(s)->bus_num(s);
501 }
502 
503 int pci_bus_numa_node(PCIBus *bus)
504 {
505     return PCI_BUS_GET_CLASS(bus)->numa_node(bus);
506 }
507 
508 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size,
509                                  const VMStateField *field)
510 {
511     PCIDevice *s = container_of(pv, PCIDevice, config);
512     PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(s);
513     uint8_t *config;
514     int i;
515 
516     assert(size == pci_config_size(s));
517     config = g_malloc(size);
518 
519     qemu_get_buffer(f, config, size);
520     for (i = 0; i < size; ++i) {
521         if ((config[i] ^ s->config[i]) &
522             s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) {
523             error_report("%s: Bad config data: i=0x%x read: %x device: %x "
524                          "cmask: %x wmask: %x w1cmask:%x", __func__,
525                          i, config[i], s->config[i],
526                          s->cmask[i], s->wmask[i], s->w1cmask[i]);
527             g_free(config);
528             return -EINVAL;
529         }
530     }
531     memcpy(s->config, config, size);
532 
533     pci_update_mappings(s);
534     if (pc->is_bridge) {
535         PCIBridge *b = PCI_BRIDGE(s);
536         pci_bridge_update_mappings(b);
537     }
538 
539     memory_region_set_enabled(&s->bus_master_enable_region,
540                               pci_get_word(s->config + PCI_COMMAND)
541                               & PCI_COMMAND_MASTER);
542 
543     g_free(config);
544     return 0;
545 }
546 
547 /* just put buffer */
548 static int put_pci_config_device(QEMUFile *f, void *pv, size_t size,
549                                  const VMStateField *field, QJSON *vmdesc)
550 {
551     const uint8_t **v = pv;
552     assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
553     qemu_put_buffer(f, *v, size);
554 
555     return 0;
556 }
557 
558 static VMStateInfo vmstate_info_pci_config = {
559     .name = "pci config",
560     .get  = get_pci_config_device,
561     .put  = put_pci_config_device,
562 };
563 
564 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size,
565                              const VMStateField *field)
566 {
567     PCIDevice *s = container_of(pv, PCIDevice, irq_state);
568     uint32_t irq_state[PCI_NUM_PINS];
569     int i;
570     for (i = 0; i < PCI_NUM_PINS; ++i) {
571         irq_state[i] = qemu_get_be32(f);
572         if (irq_state[i] != 0x1 && irq_state[i] != 0) {
573             fprintf(stderr, "irq state %d: must be 0 or 1.\n",
574                     irq_state[i]);
575             return -EINVAL;
576         }
577     }
578 
579     for (i = 0; i < PCI_NUM_PINS; ++i) {
580         pci_set_irq_state(s, i, irq_state[i]);
581     }
582 
583     return 0;
584 }
585 
586 static int put_pci_irq_state(QEMUFile *f, void *pv, size_t size,
587                              const VMStateField *field, QJSON *vmdesc)
588 {
589     int i;
590     PCIDevice *s = container_of(pv, PCIDevice, irq_state);
591 
592     for (i = 0; i < PCI_NUM_PINS; ++i) {
593         qemu_put_be32(f, pci_irq_state(s, i));
594     }
595 
596     return 0;
597 }
598 
599 static VMStateInfo vmstate_info_pci_irq_state = {
600     .name = "pci irq state",
601     .get  = get_pci_irq_state,
602     .put  = put_pci_irq_state,
603 };
604 
605 static bool migrate_is_pcie(void *opaque, int version_id)
606 {
607     return pci_is_express((PCIDevice *)opaque);
608 }
609 
610 static bool migrate_is_not_pcie(void *opaque, int version_id)
611 {
612     return !pci_is_express((PCIDevice *)opaque);
613 }
614 
615 const VMStateDescription vmstate_pci_device = {
616     .name = "PCIDevice",
617     .version_id = 2,
618     .minimum_version_id = 1,
619     .fields = (VMStateField[]) {
620         VMSTATE_INT32_POSITIVE_LE(version_id, PCIDevice),
621         VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice,
622                                    migrate_is_not_pcie,
623                                    0, vmstate_info_pci_config,
624                                    PCI_CONFIG_SPACE_SIZE),
625         VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice,
626                                    migrate_is_pcie,
627                                    0, vmstate_info_pci_config,
628                                    PCIE_CONFIG_SPACE_SIZE),
629         VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
630                                    vmstate_info_pci_irq_state,
631                                    PCI_NUM_PINS * sizeof(int32_t)),
632         VMSTATE_END_OF_LIST()
633     }
634 };
635 
636 
637 void pci_device_save(PCIDevice *s, QEMUFile *f)
638 {
639     /* Clear interrupt status bit: it is implicit
640      * in irq_state which we are saving.
641      * This makes us compatible with old devices
642      * which never set or clear this bit. */
643     s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
644     vmstate_save_state(f, &vmstate_pci_device, s, NULL);
645     /* Restore the interrupt status bit. */
646     pci_update_irq_status(s);
647 }
648 
649 int pci_device_load(PCIDevice *s, QEMUFile *f)
650 {
651     int ret;
652     ret = vmstate_load_state(f, &vmstate_pci_device, s, s->version_id);
653     /* Restore the interrupt status bit. */
654     pci_update_irq_status(s);
655     return ret;
656 }
657 
658 static void pci_set_default_subsystem_id(PCIDevice *pci_dev)
659 {
660     pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
661                  pci_default_sub_vendor_id);
662     pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
663                  pci_default_sub_device_id);
664 }
665 
666 /*
667  * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
668  *       [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
669  */
670 static int pci_parse_devaddr(const char *addr, int *domp, int *busp,
671                              unsigned int *slotp, unsigned int *funcp)
672 {
673     const char *p;
674     char *e;
675     unsigned long val;
676     unsigned long dom = 0, bus = 0;
677     unsigned int slot = 0;
678     unsigned int func = 0;
679 
680     p = addr;
681     val = strtoul(p, &e, 16);
682     if (e == p)
683         return -1;
684     if (*e == ':') {
685         bus = val;
686         p = e + 1;
687         val = strtoul(p, &e, 16);
688         if (e == p)
689             return -1;
690         if (*e == ':') {
691             dom = bus;
692             bus = val;
693             p = e + 1;
694             val = strtoul(p, &e, 16);
695             if (e == p)
696                 return -1;
697         }
698     }
699 
700     slot = val;
701 
702     if (funcp != NULL) {
703         if (*e != '.')
704             return -1;
705 
706         p = e + 1;
707         val = strtoul(p, &e, 16);
708         if (e == p)
709             return -1;
710 
711         func = val;
712     }
713 
714     /* if funcp == NULL func is 0 */
715     if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7)
716         return -1;
717 
718     if (*e)
719         return -1;
720 
721     *domp = dom;
722     *busp = bus;
723     *slotp = slot;
724     if (funcp != NULL)
725         *funcp = func;
726     return 0;
727 }
728 
729 static void pci_init_cmask(PCIDevice *dev)
730 {
731     pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
732     pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
733     dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
734     dev->cmask[PCI_REVISION_ID] = 0xff;
735     dev->cmask[PCI_CLASS_PROG] = 0xff;
736     pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
737     dev->cmask[PCI_HEADER_TYPE] = 0xff;
738     dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
739 }
740 
741 static void pci_init_wmask(PCIDevice *dev)
742 {
743     int config_size = pci_config_size(dev);
744 
745     dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
746     dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
747     pci_set_word(dev->wmask + PCI_COMMAND,
748                  PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
749                  PCI_COMMAND_INTX_DISABLE);
750     if (dev->cap_present & QEMU_PCI_CAP_SERR) {
751         pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR);
752     }
753 
754     memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
755            config_size - PCI_CONFIG_HEADER_SIZE);
756 }
757 
758 static void pci_init_w1cmask(PCIDevice *dev)
759 {
760     /*
761      * Note: It's okay to set w1cmask even for readonly bits as
762      * long as their value is hardwired to 0.
763      */
764     pci_set_word(dev->w1cmask + PCI_STATUS,
765                  PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT |
766                  PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT |
767                  PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
768 }
769 
770 static void pci_init_mask_bridge(PCIDevice *d)
771 {
772     /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
773        PCI_SEC_LETENCY_TIMER */
774     memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
775 
776     /* base and limit */
777     d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
778     d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
779     pci_set_word(d->wmask + PCI_MEMORY_BASE,
780                  PCI_MEMORY_RANGE_MASK & 0xffff);
781     pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
782                  PCI_MEMORY_RANGE_MASK & 0xffff);
783     pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
784                  PCI_PREF_RANGE_MASK & 0xffff);
785     pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
786                  PCI_PREF_RANGE_MASK & 0xffff);
787 
788     /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
789     memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
790 
791     /* Supported memory and i/o types */
792     d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16;
793     d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16;
794     pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE,
795                                PCI_PREF_RANGE_TYPE_64);
796     pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT,
797                                PCI_PREF_RANGE_TYPE_64);
798 
799     /*
800      * TODO: Bridges default to 10-bit VGA decoding but we currently only
801      * implement 16-bit decoding (no alias support).
802      */
803     pci_set_word(d->wmask + PCI_BRIDGE_CONTROL,
804                  PCI_BRIDGE_CTL_PARITY |
805                  PCI_BRIDGE_CTL_SERR |
806                  PCI_BRIDGE_CTL_ISA |
807                  PCI_BRIDGE_CTL_VGA |
808                  PCI_BRIDGE_CTL_VGA_16BIT |
809                  PCI_BRIDGE_CTL_MASTER_ABORT |
810                  PCI_BRIDGE_CTL_BUS_RESET |
811                  PCI_BRIDGE_CTL_FAST_BACK |
812                  PCI_BRIDGE_CTL_DISCARD |
813                  PCI_BRIDGE_CTL_SEC_DISCARD |
814                  PCI_BRIDGE_CTL_DISCARD_SERR);
815     /* Below does not do anything as we never set this bit, put here for
816      * completeness. */
817     pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL,
818                  PCI_BRIDGE_CTL_DISCARD_STATUS);
819     d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK;
820     d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK;
821     pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE,
822                                PCI_PREF_RANGE_TYPE_MASK);
823     pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT,
824                                PCI_PREF_RANGE_TYPE_MASK);
825 }
826 
827 static void pci_init_multifunction(PCIBus *bus, PCIDevice *dev, Error **errp)
828 {
829     uint8_t slot = PCI_SLOT(dev->devfn);
830     uint8_t func;
831 
832     if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
833         dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
834     }
835 
836     /*
837      * multifunction bit is interpreted in two ways as follows.
838      *   - all functions must set the bit to 1.
839      *     Example: Intel X53
840      *   - function 0 must set the bit, but the rest function (> 0)
841      *     is allowed to leave the bit to 0.
842      *     Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
843      *
844      * So OS (at least Linux) checks the bit of only function 0,
845      * and doesn't see the bit of function > 0.
846      *
847      * The below check allows both interpretation.
848      */
849     if (PCI_FUNC(dev->devfn)) {
850         PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)];
851         if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) {
852             /* function 0 should set multifunction bit */
853             error_setg(errp, "PCI: single function device can't be populated "
854                        "in function %x.%x", slot, PCI_FUNC(dev->devfn));
855             return;
856         }
857         return;
858     }
859 
860     if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
861         return;
862     }
863     /* function 0 indicates single function, so function > 0 must be NULL */
864     for (func = 1; func < PCI_FUNC_MAX; ++func) {
865         if (bus->devices[PCI_DEVFN(slot, func)]) {
866             error_setg(errp, "PCI: %x.0 indicates single function, "
867                        "but %x.%x is already populated.",
868                        slot, slot, func);
869             return;
870         }
871     }
872 }
873 
874 static void pci_config_alloc(PCIDevice *pci_dev)
875 {
876     int config_size = pci_config_size(pci_dev);
877 
878     pci_dev->config = g_malloc0(config_size);
879     pci_dev->cmask = g_malloc0(config_size);
880     pci_dev->wmask = g_malloc0(config_size);
881     pci_dev->w1cmask = g_malloc0(config_size);
882     pci_dev->used = g_malloc0(config_size);
883 }
884 
885 static void pci_config_free(PCIDevice *pci_dev)
886 {
887     g_free(pci_dev->config);
888     g_free(pci_dev->cmask);
889     g_free(pci_dev->wmask);
890     g_free(pci_dev->w1cmask);
891     g_free(pci_dev->used);
892 }
893 
894 static void do_pci_unregister_device(PCIDevice *pci_dev)
895 {
896     pci_get_bus(pci_dev)->devices[pci_dev->devfn] = NULL;
897     pci_config_free(pci_dev);
898 
899     if (memory_region_is_mapped(&pci_dev->bus_master_enable_region)) {
900         memory_region_del_subregion(&pci_dev->bus_master_container_region,
901                                     &pci_dev->bus_master_enable_region);
902     }
903     address_space_destroy(&pci_dev->bus_master_as);
904 }
905 
906 /* Extract PCIReqIDCache into BDF format */
907 static uint16_t pci_req_id_cache_extract(PCIReqIDCache *cache)
908 {
909     uint8_t bus_n;
910     uint16_t result;
911 
912     switch (cache->type) {
913     case PCI_REQ_ID_BDF:
914         result = pci_get_bdf(cache->dev);
915         break;
916     case PCI_REQ_ID_SECONDARY_BUS:
917         bus_n = pci_dev_bus_num(cache->dev);
918         result = PCI_BUILD_BDF(bus_n, 0);
919         break;
920     default:
921         error_report("Invalid PCI requester ID cache type: %d",
922                      cache->type);
923         exit(1);
924         break;
925     }
926 
927     return result;
928 }
929 
930 /* Parse bridges up to the root complex and return requester ID
931  * cache for specific device.  For full PCIe topology, the cache
932  * result would be exactly the same as getting BDF of the device.
933  * However, several tricks are required when system mixed up with
934  * legacy PCI devices and PCIe-to-PCI bridges.
935  *
936  * Here we cache the proxy device (and type) not requester ID since
937  * bus number might change from time to time.
938  */
939 static PCIReqIDCache pci_req_id_cache_get(PCIDevice *dev)
940 {
941     PCIDevice *parent;
942     PCIReqIDCache cache = {
943         .dev = dev,
944         .type = PCI_REQ_ID_BDF,
945     };
946 
947     while (!pci_bus_is_root(pci_get_bus(dev))) {
948         /* We are under PCI/PCIe bridges */
949         parent = pci_get_bus(dev)->parent_dev;
950         if (pci_is_express(parent)) {
951             if (pcie_cap_get_type(parent) == PCI_EXP_TYPE_PCI_BRIDGE) {
952                 /* When we pass through PCIe-to-PCI/PCIX bridges, we
953                  * override the requester ID using secondary bus
954                  * number of parent bridge with zeroed devfn
955                  * (pcie-to-pci bridge spec chap 2.3). */
956                 cache.type = PCI_REQ_ID_SECONDARY_BUS;
957                 cache.dev = dev;
958             }
959         } else {
960             /* Legacy PCI, override requester ID with the bridge's
961              * BDF upstream.  When the root complex connects to
962              * legacy PCI devices (including buses), it can only
963              * obtain requester ID info from directly attached
964              * devices.  If devices are attached under bridges, only
965              * the requester ID of the bridge that is directly
966              * attached to the root complex can be recognized. */
967             cache.type = PCI_REQ_ID_BDF;
968             cache.dev = parent;
969         }
970         dev = parent;
971     }
972 
973     return cache;
974 }
975 
976 uint16_t pci_requester_id(PCIDevice *dev)
977 {
978     return pci_req_id_cache_extract(&dev->requester_id_cache);
979 }
980 
981 static bool pci_bus_devfn_available(PCIBus *bus, int devfn)
982 {
983     return !(bus->devices[devfn]);
984 }
985 
986 static bool pci_bus_devfn_reserved(PCIBus *bus, int devfn)
987 {
988     return bus->slot_reserved_mask & (1UL << PCI_SLOT(devfn));
989 }
990 
991 /* -1 for devfn means auto assign */
992 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev,
993                                          const char *name, int devfn,
994                                          Error **errp)
995 {
996     PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
997     PCIConfigReadFunc *config_read = pc->config_read;
998     PCIConfigWriteFunc *config_write = pc->config_write;
999     Error *local_err = NULL;
1000     DeviceState *dev = DEVICE(pci_dev);
1001     PCIBus *bus = pci_get_bus(pci_dev);
1002 
1003     /* Only pci bridges can be attached to extra PCI root buses */
1004     if (pci_bus_is_root(bus) && bus->parent_dev && !pc->is_bridge) {
1005         error_setg(errp,
1006                    "PCI: Only PCI/PCIe bridges can be plugged into %s",
1007                     bus->parent_dev->name);
1008         return NULL;
1009     }
1010 
1011     if (devfn < 0) {
1012         for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
1013             devfn += PCI_FUNC_MAX) {
1014             if (pci_bus_devfn_available(bus, devfn) &&
1015                    !pci_bus_devfn_reserved(bus, devfn)) {
1016                 goto found;
1017             }
1018         }
1019         error_setg(errp, "PCI: no slot/function available for %s, all in use "
1020                    "or reserved", name);
1021         return NULL;
1022     found: ;
1023     } else if (pci_bus_devfn_reserved(bus, devfn)) {
1024         error_setg(errp, "PCI: slot %d function %d not available for %s,"
1025                    " reserved",
1026                    PCI_SLOT(devfn), PCI_FUNC(devfn), name);
1027         return NULL;
1028     } else if (!pci_bus_devfn_available(bus, devfn)) {
1029         error_setg(errp, "PCI: slot %d function %d not available for %s,"
1030                    " in use by %s",
1031                    PCI_SLOT(devfn), PCI_FUNC(devfn), name,
1032                    bus->devices[devfn]->name);
1033         return NULL;
1034     } else if (dev->hotplugged &&
1035                pci_get_function_0(pci_dev)) {
1036         error_setg(errp, "PCI: slot %d function 0 already ocuppied by %s,"
1037                    " new func %s cannot be exposed to guest.",
1038                    PCI_SLOT(pci_get_function_0(pci_dev)->devfn),
1039                    pci_get_function_0(pci_dev)->name,
1040                    name);
1041 
1042        return NULL;
1043     }
1044 
1045     pci_dev->devfn = devfn;
1046     pci_dev->requester_id_cache = pci_req_id_cache_get(pci_dev);
1047     pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
1048 
1049     memory_region_init(&pci_dev->bus_master_container_region, OBJECT(pci_dev),
1050                        "bus master container", UINT64_MAX);
1051     address_space_init(&pci_dev->bus_master_as,
1052                        &pci_dev->bus_master_container_region, pci_dev->name);
1053 
1054     if (qdev_hotplug) {
1055         pci_init_bus_master(pci_dev);
1056     }
1057     pci_dev->irq_state = 0;
1058     pci_config_alloc(pci_dev);
1059 
1060     pci_config_set_vendor_id(pci_dev->config, pc->vendor_id);
1061     pci_config_set_device_id(pci_dev->config, pc->device_id);
1062     pci_config_set_revision(pci_dev->config, pc->revision);
1063     pci_config_set_class(pci_dev->config, pc->class_id);
1064 
1065     if (!pc->is_bridge) {
1066         if (pc->subsystem_vendor_id || pc->subsystem_id) {
1067             pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
1068                          pc->subsystem_vendor_id);
1069             pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
1070                          pc->subsystem_id);
1071         } else {
1072             pci_set_default_subsystem_id(pci_dev);
1073         }
1074     } else {
1075         /* subsystem_vendor_id/subsystem_id are only for header type 0 */
1076         assert(!pc->subsystem_vendor_id);
1077         assert(!pc->subsystem_id);
1078     }
1079     pci_init_cmask(pci_dev);
1080     pci_init_wmask(pci_dev);
1081     pci_init_w1cmask(pci_dev);
1082     if (pc->is_bridge) {
1083         pci_init_mask_bridge(pci_dev);
1084     }
1085     pci_init_multifunction(bus, pci_dev, &local_err);
1086     if (local_err) {
1087         error_propagate(errp, local_err);
1088         do_pci_unregister_device(pci_dev);
1089         return NULL;
1090     }
1091 
1092     if (!config_read)
1093         config_read = pci_default_read_config;
1094     if (!config_write)
1095         config_write = pci_default_write_config;
1096     pci_dev->config_read = config_read;
1097     pci_dev->config_write = config_write;
1098     bus->devices[devfn] = pci_dev;
1099     pci_dev->version_id = 2; /* Current pci device vmstate version */
1100     return pci_dev;
1101 }
1102 
1103 static void pci_unregister_io_regions(PCIDevice *pci_dev)
1104 {
1105     PCIIORegion *r;
1106     int i;
1107 
1108     for(i = 0; i < PCI_NUM_REGIONS; i++) {
1109         r = &pci_dev->io_regions[i];
1110         if (!r->size || r->addr == PCI_BAR_UNMAPPED)
1111             continue;
1112         memory_region_del_subregion(r->address_space, r->memory);
1113     }
1114 
1115     pci_unregister_vga(pci_dev);
1116 }
1117 
1118 static void pci_qdev_unrealize(DeviceState *dev, Error **errp)
1119 {
1120     PCIDevice *pci_dev = PCI_DEVICE(dev);
1121     PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
1122 
1123     pci_unregister_io_regions(pci_dev);
1124     pci_del_option_rom(pci_dev);
1125 
1126     if (pc->exit) {
1127         pc->exit(pci_dev);
1128     }
1129 
1130     pci_device_deassert_intx(pci_dev);
1131     do_pci_unregister_device(pci_dev);
1132 }
1133 
1134 void pci_register_bar(PCIDevice *pci_dev, int region_num,
1135                       uint8_t type, MemoryRegion *memory)
1136 {
1137     PCIIORegion *r;
1138     uint32_t addr; /* offset in pci config space */
1139     uint64_t wmask;
1140     pcibus_t size = memory_region_size(memory);
1141 
1142     assert(region_num >= 0);
1143     assert(region_num < PCI_NUM_REGIONS);
1144     if (size & (size-1)) {
1145         error_report("ERROR: PCI region size must be pow2 "
1146                     "type=0x%x, size=0x%"FMT_PCIBUS"", type, size);
1147         exit(1);
1148     }
1149 
1150     r = &pci_dev->io_regions[region_num];
1151     r->addr = PCI_BAR_UNMAPPED;
1152     r->size = size;
1153     r->type = type;
1154     r->memory = memory;
1155     r->address_space = type & PCI_BASE_ADDRESS_SPACE_IO
1156                         ? pci_get_bus(pci_dev)->address_space_io
1157                         : pci_get_bus(pci_dev)->address_space_mem;
1158 
1159     wmask = ~(size - 1);
1160     if (region_num == PCI_ROM_SLOT) {
1161         /* ROM enable bit is writable */
1162         wmask |= PCI_ROM_ADDRESS_ENABLE;
1163     }
1164 
1165     addr = pci_bar(pci_dev, region_num);
1166     pci_set_long(pci_dev->config + addr, type);
1167 
1168     if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
1169         r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
1170         pci_set_quad(pci_dev->wmask + addr, wmask);
1171         pci_set_quad(pci_dev->cmask + addr, ~0ULL);
1172     } else {
1173         pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
1174         pci_set_long(pci_dev->cmask + addr, 0xffffffff);
1175     }
1176 }
1177 
1178 static void pci_update_vga(PCIDevice *pci_dev)
1179 {
1180     uint16_t cmd;
1181 
1182     if (!pci_dev->has_vga) {
1183         return;
1184     }
1185 
1186     cmd = pci_get_word(pci_dev->config + PCI_COMMAND);
1187 
1188     memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_MEM],
1189                               cmd & PCI_COMMAND_MEMORY);
1190     memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO],
1191                               cmd & PCI_COMMAND_IO);
1192     memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI],
1193                               cmd & PCI_COMMAND_IO);
1194 }
1195 
1196 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
1197                       MemoryRegion *io_lo, MemoryRegion *io_hi)
1198 {
1199     PCIBus *bus = pci_get_bus(pci_dev);
1200 
1201     assert(!pci_dev->has_vga);
1202 
1203     assert(memory_region_size(mem) == QEMU_PCI_VGA_MEM_SIZE);
1204     pci_dev->vga_regions[QEMU_PCI_VGA_MEM] = mem;
1205     memory_region_add_subregion_overlap(bus->address_space_mem,
1206                                         QEMU_PCI_VGA_MEM_BASE, mem, 1);
1207 
1208     assert(memory_region_size(io_lo) == QEMU_PCI_VGA_IO_LO_SIZE);
1209     pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO] = io_lo;
1210     memory_region_add_subregion_overlap(bus->address_space_io,
1211                                         QEMU_PCI_VGA_IO_LO_BASE, io_lo, 1);
1212 
1213     assert(memory_region_size(io_hi) == QEMU_PCI_VGA_IO_HI_SIZE);
1214     pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI] = io_hi;
1215     memory_region_add_subregion_overlap(bus->address_space_io,
1216                                         QEMU_PCI_VGA_IO_HI_BASE, io_hi, 1);
1217     pci_dev->has_vga = true;
1218 
1219     pci_update_vga(pci_dev);
1220 }
1221 
1222 void pci_unregister_vga(PCIDevice *pci_dev)
1223 {
1224     PCIBus *bus = pci_get_bus(pci_dev);
1225 
1226     if (!pci_dev->has_vga) {
1227         return;
1228     }
1229 
1230     memory_region_del_subregion(bus->address_space_mem,
1231                                 pci_dev->vga_regions[QEMU_PCI_VGA_MEM]);
1232     memory_region_del_subregion(bus->address_space_io,
1233                                 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO]);
1234     memory_region_del_subregion(bus->address_space_io,
1235                                 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI]);
1236     pci_dev->has_vga = false;
1237 }
1238 
1239 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num)
1240 {
1241     return pci_dev->io_regions[region_num].addr;
1242 }
1243 
1244 static pcibus_t pci_bar_address(PCIDevice *d,
1245                                 int reg, uint8_t type, pcibus_t size)
1246 {
1247     pcibus_t new_addr, last_addr;
1248     int bar = pci_bar(d, reg);
1249     uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
1250     Object *machine = qdev_get_machine();
1251     ObjectClass *oc = object_get_class(machine);
1252     MachineClass *mc = MACHINE_CLASS(oc);
1253     bool allow_0_address = mc->pci_allow_0_address;
1254 
1255     if (type & PCI_BASE_ADDRESS_SPACE_IO) {
1256         if (!(cmd & PCI_COMMAND_IO)) {
1257             return PCI_BAR_UNMAPPED;
1258         }
1259         new_addr = pci_get_long(d->config + bar) & ~(size - 1);
1260         last_addr = new_addr + size - 1;
1261         /* Check if 32 bit BAR wraps around explicitly.
1262          * TODO: make priorities correct and remove this work around.
1263          */
1264         if (last_addr <= new_addr || last_addr >= UINT32_MAX ||
1265             (!allow_0_address && new_addr == 0)) {
1266             return PCI_BAR_UNMAPPED;
1267         }
1268         return new_addr;
1269     }
1270 
1271     if (!(cmd & PCI_COMMAND_MEMORY)) {
1272         return PCI_BAR_UNMAPPED;
1273     }
1274     if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
1275         new_addr = pci_get_quad(d->config + bar);
1276     } else {
1277         new_addr = pci_get_long(d->config + bar);
1278     }
1279     /* the ROM slot has a specific enable bit */
1280     if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
1281         return PCI_BAR_UNMAPPED;
1282     }
1283     new_addr &= ~(size - 1);
1284     last_addr = new_addr + size - 1;
1285     /* NOTE: we do not support wrapping */
1286     /* XXX: as we cannot support really dynamic
1287        mappings, we handle specific values as invalid
1288        mappings. */
1289     if (last_addr <= new_addr || last_addr == PCI_BAR_UNMAPPED ||
1290         (!allow_0_address && new_addr == 0)) {
1291         return PCI_BAR_UNMAPPED;
1292     }
1293 
1294     /* Now pcibus_t is 64bit.
1295      * Check if 32 bit BAR wraps around explicitly.
1296      * Without this, PC ide doesn't work well.
1297      * TODO: remove this work around.
1298      */
1299     if  (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
1300         return PCI_BAR_UNMAPPED;
1301     }
1302 
1303     /*
1304      * OS is allowed to set BAR beyond its addressable
1305      * bits. For example, 32 bit OS can set 64bit bar
1306      * to >4G. Check it. TODO: we might need to support
1307      * it in the future for e.g. PAE.
1308      */
1309     if (last_addr >= HWADDR_MAX) {
1310         return PCI_BAR_UNMAPPED;
1311     }
1312 
1313     return new_addr;
1314 }
1315 
1316 static void pci_update_mappings(PCIDevice *d)
1317 {
1318     PCIIORegion *r;
1319     int i;
1320     pcibus_t new_addr;
1321 
1322     for(i = 0; i < PCI_NUM_REGIONS; i++) {
1323         r = &d->io_regions[i];
1324 
1325         /* this region isn't registered */
1326         if (!r->size)
1327             continue;
1328 
1329         new_addr = pci_bar_address(d, i, r->type, r->size);
1330 
1331         /* This bar isn't changed */
1332         if (new_addr == r->addr)
1333             continue;
1334 
1335         /* now do the real mapping */
1336         if (r->addr != PCI_BAR_UNMAPPED) {
1337             trace_pci_update_mappings_del(d, pci_dev_bus_num(d),
1338                                           PCI_SLOT(d->devfn),
1339                                           PCI_FUNC(d->devfn),
1340                                           i, r->addr, r->size);
1341             memory_region_del_subregion(r->address_space, r->memory);
1342         }
1343         r->addr = new_addr;
1344         if (r->addr != PCI_BAR_UNMAPPED) {
1345             trace_pci_update_mappings_add(d, pci_dev_bus_num(d),
1346                                           PCI_SLOT(d->devfn),
1347                                           PCI_FUNC(d->devfn),
1348                                           i, r->addr, r->size);
1349             memory_region_add_subregion_overlap(r->address_space,
1350                                                 r->addr, r->memory, 1);
1351         }
1352     }
1353 
1354     pci_update_vga(d);
1355 }
1356 
1357 static inline int pci_irq_disabled(PCIDevice *d)
1358 {
1359     return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE;
1360 }
1361 
1362 /* Called after interrupt disabled field update in config space,
1363  * assert/deassert interrupts if necessary.
1364  * Gets original interrupt disable bit value (before update). */
1365 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled)
1366 {
1367     int i, disabled = pci_irq_disabled(d);
1368     if (disabled == was_irq_disabled)
1369         return;
1370     for (i = 0; i < PCI_NUM_PINS; ++i) {
1371         int state = pci_irq_state(d, i);
1372         pci_change_irq_level(d, i, disabled ? -state : state);
1373     }
1374 }
1375 
1376 uint32_t pci_default_read_config(PCIDevice *d,
1377                                  uint32_t address, int len)
1378 {
1379     uint32_t val = 0;
1380 
1381     if (pci_is_express_downstream_port(d) &&
1382         ranges_overlap(address, len, d->exp.exp_cap + PCI_EXP_LNKSTA, 2)) {
1383         pcie_sync_bridge_lnk(d);
1384     }
1385     memcpy(&val, d->config + address, len);
1386     return le32_to_cpu(val);
1387 }
1388 
1389 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val_in, int l)
1390 {
1391     int i, was_irq_disabled = pci_irq_disabled(d);
1392     uint32_t val = val_in;
1393 
1394     for (i = 0; i < l; val >>= 8, ++i) {
1395         uint8_t wmask = d->wmask[addr + i];
1396         uint8_t w1cmask = d->w1cmask[addr + i];
1397         assert(!(wmask & w1cmask));
1398         d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
1399         d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
1400     }
1401     if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
1402         ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
1403         ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
1404         range_covers_byte(addr, l, PCI_COMMAND))
1405         pci_update_mappings(d);
1406 
1407     if (range_covers_byte(addr, l, PCI_COMMAND)) {
1408         pci_update_irq_disabled(d, was_irq_disabled);
1409         memory_region_set_enabled(&d->bus_master_enable_region,
1410                                   pci_get_word(d->config + PCI_COMMAND)
1411                                     & PCI_COMMAND_MASTER);
1412     }
1413 
1414     msi_write_config(d, addr, val_in, l);
1415     msix_write_config(d, addr, val_in, l);
1416 }
1417 
1418 /***********************************************************/
1419 /* generic PCI irq support */
1420 
1421 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1422 static void pci_irq_handler(void *opaque, int irq_num, int level)
1423 {
1424     PCIDevice *pci_dev = opaque;
1425     int change;
1426 
1427     change = level - pci_irq_state(pci_dev, irq_num);
1428     if (!change)
1429         return;
1430 
1431     pci_set_irq_state(pci_dev, irq_num, level);
1432     pci_update_irq_status(pci_dev);
1433     if (pci_irq_disabled(pci_dev))
1434         return;
1435     pci_change_irq_level(pci_dev, irq_num, change);
1436 }
1437 
1438 static inline int pci_intx(PCIDevice *pci_dev)
1439 {
1440     return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1;
1441 }
1442 
1443 qemu_irq pci_allocate_irq(PCIDevice *pci_dev)
1444 {
1445     int intx = pci_intx(pci_dev);
1446 
1447     return qemu_allocate_irq(pci_irq_handler, pci_dev, intx);
1448 }
1449 
1450 void pci_set_irq(PCIDevice *pci_dev, int level)
1451 {
1452     int intx = pci_intx(pci_dev);
1453     pci_irq_handler(pci_dev, intx, level);
1454 }
1455 
1456 /* Special hooks used by device assignment */
1457 void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq)
1458 {
1459     assert(pci_bus_is_root(bus));
1460     bus->route_intx_to_irq = route_intx_to_irq;
1461 }
1462 
1463 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin)
1464 {
1465     PCIBus *bus;
1466 
1467     do {
1468         bus = pci_get_bus(dev);
1469         pin = bus->map_irq(dev, pin);
1470         dev = bus->parent_dev;
1471     } while (dev);
1472 
1473     if (!bus->route_intx_to_irq) {
1474         error_report("PCI: Bug - unimplemented PCI INTx routing (%s)",
1475                      object_get_typename(OBJECT(bus->qbus.parent)));
1476         return (PCIINTxRoute) { PCI_INTX_DISABLED, -1 };
1477     }
1478 
1479     return bus->route_intx_to_irq(bus->irq_opaque, pin);
1480 }
1481 
1482 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new)
1483 {
1484     return old->mode != new->mode || old->irq != new->irq;
1485 }
1486 
1487 void pci_bus_fire_intx_routing_notifier(PCIBus *bus)
1488 {
1489     PCIDevice *dev;
1490     PCIBus *sec;
1491     int i;
1492 
1493     for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
1494         dev = bus->devices[i];
1495         if (dev && dev->intx_routing_notifier) {
1496             dev->intx_routing_notifier(dev);
1497         }
1498     }
1499 
1500     QLIST_FOREACH(sec, &bus->child, sibling) {
1501         pci_bus_fire_intx_routing_notifier(sec);
1502     }
1503 }
1504 
1505 void pci_device_set_intx_routing_notifier(PCIDevice *dev,
1506                                           PCIINTxRoutingNotifier notifier)
1507 {
1508     dev->intx_routing_notifier = notifier;
1509 }
1510 
1511 /*
1512  * PCI-to-PCI bridge specification
1513  * 9.1: Interrupt routing. Table 9-1
1514  *
1515  * the PCI Express Base Specification, Revision 2.1
1516  * 2.2.8.1: INTx interrutp signaling - Rules
1517  *          the Implementation Note
1518  *          Table 2-20
1519  */
1520 /*
1521  * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD
1522  * 0-origin unlike PCI interrupt pin register.
1523  */
1524 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin)
1525 {
1526     return pci_swizzle(PCI_SLOT(pci_dev->devfn), pin);
1527 }
1528 
1529 /***********************************************************/
1530 /* monitor info on PCI */
1531 
1532 typedef struct {
1533     uint16_t class;
1534     const char *desc;
1535     const char *fw_name;
1536     uint16_t fw_ign_bits;
1537 } pci_class_desc;
1538 
1539 static const pci_class_desc pci_class_descriptions[] =
1540 {
1541     { 0x0001, "VGA controller", "display"},
1542     { 0x0100, "SCSI controller", "scsi"},
1543     { 0x0101, "IDE controller", "ide"},
1544     { 0x0102, "Floppy controller", "fdc"},
1545     { 0x0103, "IPI controller", "ipi"},
1546     { 0x0104, "RAID controller", "raid"},
1547     { 0x0106, "SATA controller"},
1548     { 0x0107, "SAS controller"},
1549     { 0x0180, "Storage controller"},
1550     { 0x0200, "Ethernet controller", "ethernet"},
1551     { 0x0201, "Token Ring controller", "token-ring"},
1552     { 0x0202, "FDDI controller", "fddi"},
1553     { 0x0203, "ATM controller", "atm"},
1554     { 0x0280, "Network controller"},
1555     { 0x0300, "VGA controller", "display", 0x00ff},
1556     { 0x0301, "XGA controller"},
1557     { 0x0302, "3D controller"},
1558     { 0x0380, "Display controller"},
1559     { 0x0400, "Video controller", "video"},
1560     { 0x0401, "Audio controller", "sound"},
1561     { 0x0402, "Phone"},
1562     { 0x0403, "Audio controller", "sound"},
1563     { 0x0480, "Multimedia controller"},
1564     { 0x0500, "RAM controller", "memory"},
1565     { 0x0501, "Flash controller", "flash"},
1566     { 0x0580, "Memory controller"},
1567     { 0x0600, "Host bridge", "host"},
1568     { 0x0601, "ISA bridge", "isa"},
1569     { 0x0602, "EISA bridge", "eisa"},
1570     { 0x0603, "MC bridge", "mca"},
1571     { 0x0604, "PCI bridge", "pci-bridge"},
1572     { 0x0605, "PCMCIA bridge", "pcmcia"},
1573     { 0x0606, "NUBUS bridge", "nubus"},
1574     { 0x0607, "CARDBUS bridge", "cardbus"},
1575     { 0x0608, "RACEWAY bridge"},
1576     { 0x0680, "Bridge"},
1577     { 0x0700, "Serial port", "serial"},
1578     { 0x0701, "Parallel port", "parallel"},
1579     { 0x0800, "Interrupt controller", "interrupt-controller"},
1580     { 0x0801, "DMA controller", "dma-controller"},
1581     { 0x0802, "Timer", "timer"},
1582     { 0x0803, "RTC", "rtc"},
1583     { 0x0900, "Keyboard", "keyboard"},
1584     { 0x0901, "Pen", "pen"},
1585     { 0x0902, "Mouse", "mouse"},
1586     { 0x0A00, "Dock station", "dock", 0x00ff},
1587     { 0x0B00, "i386 cpu", "cpu", 0x00ff},
1588     { 0x0c00, "Fireware contorller", "fireware"},
1589     { 0x0c01, "Access bus controller", "access-bus"},
1590     { 0x0c02, "SSA controller", "ssa"},
1591     { 0x0c03, "USB controller", "usb"},
1592     { 0x0c04, "Fibre channel controller", "fibre-channel"},
1593     { 0x0c05, "SMBus"},
1594     { 0, NULL}
1595 };
1596 
1597 static void pci_for_each_device_under_bus_reverse(PCIBus *bus,
1598                                                   void (*fn)(PCIBus *b,
1599                                                              PCIDevice *d,
1600                                                              void *opaque),
1601                                                   void *opaque)
1602 {
1603     PCIDevice *d;
1604     int devfn;
1605 
1606     for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1607         d = bus->devices[ARRAY_SIZE(bus->devices) - 1 - devfn];
1608         if (d) {
1609             fn(bus, d, opaque);
1610         }
1611     }
1612 }
1613 
1614 void pci_for_each_device_reverse(PCIBus *bus, int bus_num,
1615                          void (*fn)(PCIBus *b, PCIDevice *d, void *opaque),
1616                          void *opaque)
1617 {
1618     bus = pci_find_bus_nr(bus, bus_num);
1619 
1620     if (bus) {
1621         pci_for_each_device_under_bus_reverse(bus, fn, opaque);
1622     }
1623 }
1624 
1625 static void pci_for_each_device_under_bus(PCIBus *bus,
1626                                           void (*fn)(PCIBus *b, PCIDevice *d,
1627                                                      void *opaque),
1628                                           void *opaque)
1629 {
1630     PCIDevice *d;
1631     int devfn;
1632 
1633     for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1634         d = bus->devices[devfn];
1635         if (d) {
1636             fn(bus, d, opaque);
1637         }
1638     }
1639 }
1640 
1641 void pci_for_each_device(PCIBus *bus, int bus_num,
1642                          void (*fn)(PCIBus *b, PCIDevice *d, void *opaque),
1643                          void *opaque)
1644 {
1645     bus = pci_find_bus_nr(bus, bus_num);
1646 
1647     if (bus) {
1648         pci_for_each_device_under_bus(bus, fn, opaque);
1649     }
1650 }
1651 
1652 static const pci_class_desc *get_class_desc(int class)
1653 {
1654     const pci_class_desc *desc;
1655 
1656     desc = pci_class_descriptions;
1657     while (desc->desc && class != desc->class) {
1658         desc++;
1659     }
1660 
1661     return desc;
1662 }
1663 
1664 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num);
1665 
1666 static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev)
1667 {
1668     PciMemoryRegionList *head = NULL, *cur_item = NULL;
1669     int i;
1670 
1671     for (i = 0; i < PCI_NUM_REGIONS; i++) {
1672         const PCIIORegion *r = &dev->io_regions[i];
1673         PciMemoryRegionList *region;
1674 
1675         if (!r->size) {
1676             continue;
1677         }
1678 
1679         region = g_malloc0(sizeof(*region));
1680         region->value = g_malloc0(sizeof(*region->value));
1681 
1682         if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1683             region->value->type = g_strdup("io");
1684         } else {
1685             region->value->type = g_strdup("memory");
1686             region->value->has_prefetch = true;
1687             region->value->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH);
1688             region->value->has_mem_type_64 = true;
1689             region->value->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64);
1690         }
1691 
1692         region->value->bar = i;
1693         region->value->address = r->addr;
1694         region->value->size = r->size;
1695 
1696         /* XXX: waiting for the qapi to support GSList */
1697         if (!cur_item) {
1698             head = cur_item = region;
1699         } else {
1700             cur_item->next = region;
1701             cur_item = region;
1702         }
1703     }
1704 
1705     return head;
1706 }
1707 
1708 static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus,
1709                                            int bus_num)
1710 {
1711     PciBridgeInfo *info;
1712     PciMemoryRange *range;
1713 
1714     info = g_new0(PciBridgeInfo, 1);
1715 
1716     info->bus = g_new0(PciBusInfo, 1);
1717     info->bus->number = dev->config[PCI_PRIMARY_BUS];
1718     info->bus->secondary = dev->config[PCI_SECONDARY_BUS];
1719     info->bus->subordinate = dev->config[PCI_SUBORDINATE_BUS];
1720 
1721     range = info->bus->io_range = g_new0(PciMemoryRange, 1);
1722     range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
1723     range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
1724 
1725     range = info->bus->memory_range = g_new0(PciMemoryRange, 1);
1726     range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
1727     range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
1728 
1729     range = info->bus->prefetchable_range = g_new0(PciMemoryRange, 1);
1730     range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
1731     range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
1732 
1733     if (dev->config[PCI_SECONDARY_BUS] != 0) {
1734         PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]);
1735         if (child_bus) {
1736             info->has_devices = true;
1737             info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]);
1738         }
1739     }
1740 
1741     return info;
1742 }
1743 
1744 static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus,
1745                                            int bus_num)
1746 {
1747     const pci_class_desc *desc;
1748     PciDeviceInfo *info;
1749     uint8_t type;
1750     int class;
1751 
1752     info = g_new0(PciDeviceInfo, 1);
1753     info->bus = bus_num;
1754     info->slot = PCI_SLOT(dev->devfn);
1755     info->function = PCI_FUNC(dev->devfn);
1756 
1757     info->class_info = g_new0(PciDeviceClass, 1);
1758     class = pci_get_word(dev->config + PCI_CLASS_DEVICE);
1759     info->class_info->q_class = class;
1760     desc = get_class_desc(class);
1761     if (desc->desc) {
1762         info->class_info->has_desc = true;
1763         info->class_info->desc = g_strdup(desc->desc);
1764     }
1765 
1766     info->id = g_new0(PciDeviceId, 1);
1767     info->id->vendor = pci_get_word(dev->config + PCI_VENDOR_ID);
1768     info->id->device = pci_get_word(dev->config + PCI_DEVICE_ID);
1769     info->regions = qmp_query_pci_regions(dev);
1770     info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : "");
1771 
1772     if (dev->config[PCI_INTERRUPT_PIN] != 0) {
1773         info->has_irq = true;
1774         info->irq = dev->config[PCI_INTERRUPT_LINE];
1775     }
1776 
1777     type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
1778     if (type == PCI_HEADER_TYPE_BRIDGE) {
1779         info->has_pci_bridge = true;
1780         info->pci_bridge = qmp_query_pci_bridge(dev, bus, bus_num);
1781     } else if (type == PCI_HEADER_TYPE_NORMAL) {
1782         info->id->has_subsystem = info->id->has_subsystem_vendor = true;
1783         info->id->subsystem = pci_get_word(dev->config + PCI_SUBSYSTEM_ID);
1784         info->id->subsystem_vendor =
1785             pci_get_word(dev->config + PCI_SUBSYSTEM_VENDOR_ID);
1786     } else if (type == PCI_HEADER_TYPE_CARDBUS) {
1787         info->id->has_subsystem = info->id->has_subsystem_vendor = true;
1788         info->id->subsystem = pci_get_word(dev->config + PCI_CB_SUBSYSTEM_ID);
1789         info->id->subsystem_vendor =
1790             pci_get_word(dev->config + PCI_CB_SUBSYSTEM_VENDOR_ID);
1791     }
1792 
1793     return info;
1794 }
1795 
1796 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num)
1797 {
1798     PciDeviceInfoList *info, *head = NULL, *cur_item = NULL;
1799     PCIDevice *dev;
1800     int devfn;
1801 
1802     for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1803         dev = bus->devices[devfn];
1804         if (dev) {
1805             info = g_malloc0(sizeof(*info));
1806             info->value = qmp_query_pci_device(dev, bus, bus_num);
1807 
1808             /* XXX: waiting for the qapi to support GSList */
1809             if (!cur_item) {
1810                 head = cur_item = info;
1811             } else {
1812                 cur_item->next = info;
1813                 cur_item = info;
1814             }
1815         }
1816     }
1817 
1818     return head;
1819 }
1820 
1821 static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num)
1822 {
1823     PciInfo *info = NULL;
1824 
1825     bus = pci_find_bus_nr(bus, bus_num);
1826     if (bus) {
1827         info = g_malloc0(sizeof(*info));
1828         info->bus = bus_num;
1829         info->devices = qmp_query_pci_devices(bus, bus_num);
1830     }
1831 
1832     return info;
1833 }
1834 
1835 PciInfoList *qmp_query_pci(Error **errp)
1836 {
1837     PciInfoList *info, *head = NULL, *cur_item = NULL;
1838     PCIHostState *host_bridge;
1839 
1840     QLIST_FOREACH(host_bridge, &pci_host_bridges, next) {
1841         info = g_malloc0(sizeof(*info));
1842         info->value = qmp_query_pci_bus(host_bridge->bus,
1843                                         pci_bus_num(host_bridge->bus));
1844 
1845         /* XXX: waiting for the qapi to support GSList */
1846         if (!cur_item) {
1847             head = cur_item = info;
1848         } else {
1849             cur_item->next = info;
1850             cur_item = info;
1851         }
1852     }
1853 
1854     return head;
1855 }
1856 
1857 /* Initialize a PCI NIC.  */
1858 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus,
1859                                const char *default_model,
1860                                const char *default_devaddr)
1861 {
1862     const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
1863     GSList *list;
1864     GPtrArray *pci_nic_models;
1865     PCIBus *bus;
1866     PCIDevice *pci_dev;
1867     DeviceState *dev;
1868     int devfn;
1869     int i;
1870     int dom, busnr;
1871     unsigned slot;
1872 
1873     if (nd->model && !strcmp(nd->model, "virtio")) {
1874         g_free(nd->model);
1875         nd->model = g_strdup("virtio-net-pci");
1876     }
1877 
1878     list = object_class_get_list_sorted(TYPE_PCI_DEVICE, false);
1879     pci_nic_models = g_ptr_array_new();
1880     while (list) {
1881         DeviceClass *dc = OBJECT_CLASS_CHECK(DeviceClass, list->data,
1882                                              TYPE_DEVICE);
1883         GSList *next;
1884         if (test_bit(DEVICE_CATEGORY_NETWORK, dc->categories) &&
1885             dc->user_creatable) {
1886             const char *name = object_class_get_name(list->data);
1887             g_ptr_array_add(pci_nic_models, (gpointer)name);
1888         }
1889         next = list->next;
1890         g_slist_free_1(list);
1891         list = next;
1892     }
1893     g_ptr_array_add(pci_nic_models, NULL);
1894 
1895     if (qemu_show_nic_models(nd->model, (const char **)pci_nic_models->pdata)) {
1896         exit(0);
1897     }
1898 
1899     i = qemu_find_nic_model(nd, (const char **)pci_nic_models->pdata,
1900                             default_model);
1901     if (i < 0) {
1902         exit(1);
1903     }
1904 
1905     if (!rootbus) {
1906         error_report("No primary PCI bus");
1907         exit(1);
1908     }
1909 
1910     assert(!rootbus->parent_dev);
1911 
1912     if (!devaddr) {
1913         devfn = -1;
1914         busnr = 0;
1915     } else {
1916         if (pci_parse_devaddr(devaddr, &dom, &busnr, &slot, NULL) < 0) {
1917             error_report("Invalid PCI device address %s for device %s",
1918                          devaddr, nd->model);
1919             exit(1);
1920         }
1921 
1922         if (dom != 0) {
1923             error_report("No support for non-zero PCI domains");
1924             exit(1);
1925         }
1926 
1927         devfn = PCI_DEVFN(slot, 0);
1928     }
1929 
1930     bus = pci_find_bus_nr(rootbus, busnr);
1931     if (!bus) {
1932         error_report("Invalid PCI device address %s for device %s",
1933                      devaddr, nd->model);
1934         exit(1);
1935     }
1936 
1937     pci_dev = pci_create(bus, devfn, nd->model);
1938     dev = &pci_dev->qdev;
1939     qdev_set_nic_properties(dev, nd);
1940     qdev_init_nofail(dev);
1941     g_ptr_array_free(pci_nic_models, true);
1942     return pci_dev;
1943 }
1944 
1945 PCIDevice *pci_vga_init(PCIBus *bus)
1946 {
1947     switch (vga_interface_type) {
1948     case VGA_CIRRUS:
1949         return pci_create_simple(bus, -1, "cirrus-vga");
1950     case VGA_QXL:
1951         return pci_create_simple(bus, -1, "qxl-vga");
1952     case VGA_STD:
1953         return pci_create_simple(bus, -1, "VGA");
1954     case VGA_VMWARE:
1955         return pci_create_simple(bus, -1, "vmware-svga");
1956     case VGA_VIRTIO:
1957         return pci_create_simple(bus, -1, "virtio-vga");
1958     case VGA_NONE:
1959     default: /* Other non-PCI types. Checking for unsupported types is already
1960                 done in vl.c. */
1961         return NULL;
1962     }
1963 }
1964 
1965 /* Whether a given bus number is in range of the secondary
1966  * bus of the given bridge device. */
1967 static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num)
1968 {
1969     return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) &
1970              PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ &&
1971         dev->config[PCI_SECONDARY_BUS] <= bus_num &&
1972         bus_num <= dev->config[PCI_SUBORDINATE_BUS];
1973 }
1974 
1975 /* Whether a given bus number is in a range of a root bus */
1976 static bool pci_root_bus_in_range(PCIBus *bus, int bus_num)
1977 {
1978     int i;
1979 
1980     for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
1981         PCIDevice *dev = bus->devices[i];
1982 
1983         if (dev && PCI_DEVICE_GET_CLASS(dev)->is_bridge) {
1984             if (pci_secondary_bus_in_range(dev, bus_num)) {
1985                 return true;
1986             }
1987         }
1988     }
1989 
1990     return false;
1991 }
1992 
1993 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num)
1994 {
1995     PCIBus *sec;
1996 
1997     if (!bus) {
1998         return NULL;
1999     }
2000 
2001     if (pci_bus_num(bus) == bus_num) {
2002         return bus;
2003     }
2004 
2005     /* Consider all bus numbers in range for the host pci bridge. */
2006     if (!pci_bus_is_root(bus) &&
2007         !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) {
2008         return NULL;
2009     }
2010 
2011     /* try child bus */
2012     for (; bus; bus = sec) {
2013         QLIST_FOREACH(sec, &bus->child, sibling) {
2014             if (pci_bus_num(sec) == bus_num) {
2015                 return sec;
2016             }
2017             /* PXB buses assumed to be children of bus 0 */
2018             if (pci_bus_is_root(sec)) {
2019                 if (pci_root_bus_in_range(sec, bus_num)) {
2020                     break;
2021                 }
2022             } else {
2023                 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) {
2024                     break;
2025                 }
2026             }
2027         }
2028     }
2029 
2030     return NULL;
2031 }
2032 
2033 void pci_for_each_bus_depth_first(PCIBus *bus,
2034                                   void *(*begin)(PCIBus *bus, void *parent_state),
2035                                   void (*end)(PCIBus *bus, void *state),
2036                                   void *parent_state)
2037 {
2038     PCIBus *sec;
2039     void *state;
2040 
2041     if (!bus) {
2042         return;
2043     }
2044 
2045     if (begin) {
2046         state = begin(bus, parent_state);
2047     } else {
2048         state = parent_state;
2049     }
2050 
2051     QLIST_FOREACH(sec, &bus->child, sibling) {
2052         pci_for_each_bus_depth_first(sec, begin, end, state);
2053     }
2054 
2055     if (end) {
2056         end(bus, state);
2057     }
2058 }
2059 
2060 
2061 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn)
2062 {
2063     bus = pci_find_bus_nr(bus, bus_num);
2064 
2065     if (!bus)
2066         return NULL;
2067 
2068     return bus->devices[devfn];
2069 }
2070 
2071 static void pci_qdev_realize(DeviceState *qdev, Error **errp)
2072 {
2073     PCIDevice *pci_dev = (PCIDevice *)qdev;
2074     PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
2075     ObjectClass *klass = OBJECT_CLASS(pc);
2076     Error *local_err = NULL;
2077     bool is_default_rom;
2078 
2079     /* initialize cap_present for pci_is_express() and pci_config_size(),
2080      * Note that hybrid PCIs are not set automatically and need to manage
2081      * QEMU_PCI_CAP_EXPRESS manually */
2082     if (object_class_dynamic_cast(klass, INTERFACE_PCIE_DEVICE) &&
2083        !object_class_dynamic_cast(klass, INTERFACE_CONVENTIONAL_PCI_DEVICE)) {
2084         pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
2085     }
2086 
2087     pci_dev = do_pci_register_device(pci_dev,
2088                                      object_get_typename(OBJECT(qdev)),
2089                                      pci_dev->devfn, errp);
2090     if (pci_dev == NULL)
2091         return;
2092 
2093     if (pc->realize) {
2094         pc->realize(pci_dev, &local_err);
2095         if (local_err) {
2096             error_propagate(errp, local_err);
2097             do_pci_unregister_device(pci_dev);
2098             return;
2099         }
2100     }
2101 
2102     /* rom loading */
2103     is_default_rom = false;
2104     if (pci_dev->romfile == NULL && pc->romfile != NULL) {
2105         pci_dev->romfile = g_strdup(pc->romfile);
2106         is_default_rom = true;
2107     }
2108 
2109     pci_add_option_rom(pci_dev, is_default_rom, &local_err);
2110     if (local_err) {
2111         error_propagate(errp, local_err);
2112         pci_qdev_unrealize(DEVICE(pci_dev), NULL);
2113         return;
2114     }
2115 }
2116 
2117 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
2118                                     const char *name)
2119 {
2120     DeviceState *dev;
2121 
2122     dev = qdev_create(&bus->qbus, name);
2123     qdev_prop_set_int32(dev, "addr", devfn);
2124     qdev_prop_set_bit(dev, "multifunction", multifunction);
2125     return PCI_DEVICE(dev);
2126 }
2127 
2128 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
2129                                            bool multifunction,
2130                                            const char *name)
2131 {
2132     PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name);
2133     qdev_init_nofail(&dev->qdev);
2134     return dev;
2135 }
2136 
2137 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
2138 {
2139     return pci_create_multifunction(bus, devfn, false, name);
2140 }
2141 
2142 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
2143 {
2144     return pci_create_simple_multifunction(bus, devfn, false, name);
2145 }
2146 
2147 static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size)
2148 {
2149     int offset = PCI_CONFIG_HEADER_SIZE;
2150     int i;
2151     for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) {
2152         if (pdev->used[i])
2153             offset = i + 1;
2154         else if (i - offset + 1 == size)
2155             return offset;
2156     }
2157     return 0;
2158 }
2159 
2160 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
2161                                         uint8_t *prev_p)
2162 {
2163     uint8_t next, prev;
2164 
2165     if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
2166         return 0;
2167 
2168     for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
2169          prev = next + PCI_CAP_LIST_NEXT)
2170         if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
2171             break;
2172 
2173     if (prev_p)
2174         *prev_p = prev;
2175     return next;
2176 }
2177 
2178 static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset)
2179 {
2180     uint8_t next, prev, found = 0;
2181 
2182     if (!(pdev->used[offset])) {
2183         return 0;
2184     }
2185 
2186     assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST);
2187 
2188     for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
2189          prev = next + PCI_CAP_LIST_NEXT) {
2190         if (next <= offset && next > found) {
2191             found = next;
2192         }
2193     }
2194     return found;
2195 }
2196 
2197 /* Patch the PCI vendor and device ids in a PCI rom image if necessary.
2198    This is needed for an option rom which is used for more than one device. */
2199 static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size)
2200 {
2201     uint16_t vendor_id;
2202     uint16_t device_id;
2203     uint16_t rom_vendor_id;
2204     uint16_t rom_device_id;
2205     uint16_t rom_magic;
2206     uint16_t pcir_offset;
2207     uint8_t checksum;
2208 
2209     /* Words in rom data are little endian (like in PCI configuration),
2210        so they can be read / written with pci_get_word / pci_set_word. */
2211 
2212     /* Only a valid rom will be patched. */
2213     rom_magic = pci_get_word(ptr);
2214     if (rom_magic != 0xaa55) {
2215         PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic);
2216         return;
2217     }
2218     pcir_offset = pci_get_word(ptr + 0x18);
2219     if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) {
2220         PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset);
2221         return;
2222     }
2223 
2224     vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID);
2225     device_id = pci_get_word(pdev->config + PCI_DEVICE_ID);
2226     rom_vendor_id = pci_get_word(ptr + pcir_offset + 4);
2227     rom_device_id = pci_get_word(ptr + pcir_offset + 6);
2228 
2229     PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile,
2230                 vendor_id, device_id, rom_vendor_id, rom_device_id);
2231 
2232     checksum = ptr[6];
2233 
2234     if (vendor_id != rom_vendor_id) {
2235         /* Patch vendor id and checksum (at offset 6 for etherboot roms). */
2236         checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8);
2237         checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8);
2238         PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
2239         ptr[6] = checksum;
2240         pci_set_word(ptr + pcir_offset + 4, vendor_id);
2241     }
2242 
2243     if (device_id != rom_device_id) {
2244         /* Patch device id and checksum (at offset 6 for etherboot roms). */
2245         checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8);
2246         checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8);
2247         PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
2248         ptr[6] = checksum;
2249         pci_set_word(ptr + pcir_offset + 6, device_id);
2250     }
2251 }
2252 
2253 /* Add an option rom for the device */
2254 static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom,
2255                                Error **errp)
2256 {
2257     int size;
2258     char *path;
2259     void *ptr;
2260     char name[32];
2261     const VMStateDescription *vmsd;
2262 
2263     if (!pdev->romfile)
2264         return;
2265     if (strlen(pdev->romfile) == 0)
2266         return;
2267 
2268     if (!pdev->rom_bar) {
2269         /*
2270          * Load rom via fw_cfg instead of creating a rom bar,
2271          * for 0.11 compatibility.
2272          */
2273         int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
2274 
2275         /*
2276          * Hot-plugged devices can't use the option ROM
2277          * if the rom bar is disabled.
2278          */
2279         if (DEVICE(pdev)->hotplugged) {
2280             error_setg(errp, "Hot-plugged device without ROM bar"
2281                        " can't have an option ROM");
2282             return;
2283         }
2284 
2285         if (class == 0x0300) {
2286             rom_add_vga(pdev->romfile);
2287         } else {
2288             rom_add_option(pdev->romfile, -1);
2289         }
2290         return;
2291     }
2292 
2293     path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile);
2294     if (path == NULL) {
2295         path = g_strdup(pdev->romfile);
2296     }
2297 
2298     size = get_image_size(path);
2299     if (size < 0) {
2300         error_setg(errp, "failed to find romfile \"%s\"", pdev->romfile);
2301         g_free(path);
2302         return;
2303     } else if (size == 0) {
2304         error_setg(errp, "romfile \"%s\" is empty", pdev->romfile);
2305         g_free(path);
2306         return;
2307     }
2308     size = pow2ceil(size);
2309 
2310     vmsd = qdev_get_vmsd(DEVICE(pdev));
2311 
2312     if (vmsd) {
2313         snprintf(name, sizeof(name), "%s.rom", vmsd->name);
2314     } else {
2315         snprintf(name, sizeof(name), "%s.rom", object_get_typename(OBJECT(pdev)));
2316     }
2317     pdev->has_rom = true;
2318     memory_region_init_rom(&pdev->rom, OBJECT(pdev), name, size, &error_fatal);
2319     ptr = memory_region_get_ram_ptr(&pdev->rom);
2320     if (load_image_size(path, ptr, size) < 0) {
2321         error_setg(errp, "failed to load romfile \"%s\"", pdev->romfile);
2322         g_free(path);
2323         return;
2324     }
2325     g_free(path);
2326 
2327     if (is_default_rom) {
2328         /* Only the default rom images will be patched (if needed). */
2329         pci_patch_ids(pdev, ptr, size);
2330     }
2331 
2332     pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom);
2333 }
2334 
2335 static void pci_del_option_rom(PCIDevice *pdev)
2336 {
2337     if (!pdev->has_rom)
2338         return;
2339 
2340     vmstate_unregister_ram(&pdev->rom, &pdev->qdev);
2341     pdev->has_rom = false;
2342 }
2343 
2344 /*
2345  * On success, pci_add_capability() returns a positive value
2346  * that the offset of the pci capability.
2347  * On failure, it sets an error and returns a negative error
2348  * code.
2349  */
2350 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
2351                        uint8_t offset, uint8_t size,
2352                        Error **errp)
2353 {
2354     uint8_t *config;
2355     int i, overlapping_cap;
2356 
2357     if (!offset) {
2358         offset = pci_find_space(pdev, size);
2359         /* out of PCI config space is programming error */
2360         assert(offset);
2361     } else {
2362         /* Verify that capabilities don't overlap.  Note: device assignment
2363          * depends on this check to verify that the device is not broken.
2364          * Should never trigger for emulated devices, but it's helpful
2365          * for debugging these. */
2366         for (i = offset; i < offset + size; i++) {
2367             overlapping_cap = pci_find_capability_at_offset(pdev, i);
2368             if (overlapping_cap) {
2369                 error_setg(errp, "%s:%02x:%02x.%x "
2370                            "Attempt to add PCI capability %x at offset "
2371                            "%x overlaps existing capability %x at offset %x",
2372                            pci_root_bus_path(pdev), pci_dev_bus_num(pdev),
2373                            PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
2374                            cap_id, offset, overlapping_cap, i);
2375                 return -EINVAL;
2376             }
2377         }
2378     }
2379 
2380     config = pdev->config + offset;
2381     config[PCI_CAP_LIST_ID] = cap_id;
2382     config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
2383     pdev->config[PCI_CAPABILITY_LIST] = offset;
2384     pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
2385     memset(pdev->used + offset, 0xFF, QEMU_ALIGN_UP(size, 4));
2386     /* Make capability read-only by default */
2387     memset(pdev->wmask + offset, 0, size);
2388     /* Check capability by default */
2389     memset(pdev->cmask + offset, 0xFF, size);
2390     return offset;
2391 }
2392 
2393 /* Unlink capability from the pci config space. */
2394 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
2395 {
2396     uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
2397     if (!offset)
2398         return;
2399     pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
2400     /* Make capability writable again */
2401     memset(pdev->wmask + offset, 0xff, size);
2402     memset(pdev->w1cmask + offset, 0, size);
2403     /* Clear cmask as device-specific registers can't be checked */
2404     memset(pdev->cmask + offset, 0, size);
2405     memset(pdev->used + offset, 0, QEMU_ALIGN_UP(size, 4));
2406 
2407     if (!pdev->config[PCI_CAPABILITY_LIST])
2408         pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
2409 }
2410 
2411 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
2412 {
2413     return pci_find_capability_list(pdev, cap_id, NULL);
2414 }
2415 
2416 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
2417 {
2418     PCIDevice *d = (PCIDevice *)dev;
2419     const pci_class_desc *desc;
2420     char ctxt[64];
2421     PCIIORegion *r;
2422     int i, class;
2423 
2424     class = pci_get_word(d->config + PCI_CLASS_DEVICE);
2425     desc = pci_class_descriptions;
2426     while (desc->desc && class != desc->class)
2427         desc++;
2428     if (desc->desc) {
2429         snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
2430     } else {
2431         snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
2432     }
2433 
2434     monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
2435                    "pci id %04x:%04x (sub %04x:%04x)\n",
2436                    indent, "", ctxt, pci_dev_bus_num(d),
2437                    PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
2438                    pci_get_word(d->config + PCI_VENDOR_ID),
2439                    pci_get_word(d->config + PCI_DEVICE_ID),
2440                    pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
2441                    pci_get_word(d->config + PCI_SUBSYSTEM_ID));
2442     for (i = 0; i < PCI_NUM_REGIONS; i++) {
2443         r = &d->io_regions[i];
2444         if (!r->size)
2445             continue;
2446         monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
2447                        " [0x%"FMT_PCIBUS"]\n",
2448                        indent, "",
2449                        i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
2450                        r->addr, r->addr + r->size - 1);
2451     }
2452 }
2453 
2454 static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len)
2455 {
2456     PCIDevice *d = (PCIDevice *)dev;
2457     const char *name = NULL;
2458     const pci_class_desc *desc =  pci_class_descriptions;
2459     int class = pci_get_word(d->config + PCI_CLASS_DEVICE);
2460 
2461     while (desc->desc &&
2462           (class & ~desc->fw_ign_bits) !=
2463           (desc->class & ~desc->fw_ign_bits)) {
2464         desc++;
2465     }
2466 
2467     if (desc->desc) {
2468         name = desc->fw_name;
2469     }
2470 
2471     if (name) {
2472         pstrcpy(buf, len, name);
2473     } else {
2474         snprintf(buf, len, "pci%04x,%04x",
2475                  pci_get_word(d->config + PCI_VENDOR_ID),
2476                  pci_get_word(d->config + PCI_DEVICE_ID));
2477     }
2478 
2479     return buf;
2480 }
2481 
2482 static char *pcibus_get_fw_dev_path(DeviceState *dev)
2483 {
2484     PCIDevice *d = (PCIDevice *)dev;
2485     char path[50], name[33];
2486     int off;
2487 
2488     off = snprintf(path, sizeof(path), "%s@%x",
2489                    pci_dev_fw_name(dev, name, sizeof name),
2490                    PCI_SLOT(d->devfn));
2491     if (PCI_FUNC(d->devfn))
2492         snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn));
2493     return g_strdup(path);
2494 }
2495 
2496 static char *pcibus_get_dev_path(DeviceState *dev)
2497 {
2498     PCIDevice *d = container_of(dev, PCIDevice, qdev);
2499     PCIDevice *t;
2500     int slot_depth;
2501     /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function.
2502      * 00 is added here to make this format compatible with
2503      * domain:Bus:Slot.Func for systems without nested PCI bridges.
2504      * Slot.Function list specifies the slot and function numbers for all
2505      * devices on the path from root to the specific device. */
2506     const char *root_bus_path;
2507     int root_bus_len;
2508     char slot[] = ":SS.F";
2509     int slot_len = sizeof slot - 1 /* For '\0' */;
2510     int path_len;
2511     char *path, *p;
2512     int s;
2513 
2514     root_bus_path = pci_root_bus_path(d);
2515     root_bus_len = strlen(root_bus_path);
2516 
2517     /* Calculate # of slots on path between device and root. */;
2518     slot_depth = 0;
2519     for (t = d; t; t = pci_get_bus(t)->parent_dev) {
2520         ++slot_depth;
2521     }
2522 
2523     path_len = root_bus_len + slot_len * slot_depth;
2524 
2525     /* Allocate memory, fill in the terminating null byte. */
2526     path = g_malloc(path_len + 1 /* For '\0' */);
2527     path[path_len] = '\0';
2528 
2529     memcpy(path, root_bus_path, root_bus_len);
2530 
2531     /* Fill in slot numbers. We walk up from device to root, so need to print
2532      * them in the reverse order, last to first. */
2533     p = path + path_len;
2534     for (t = d; t; t = pci_get_bus(t)->parent_dev) {
2535         p -= slot_len;
2536         s = snprintf(slot, sizeof slot, ":%02x.%x",
2537                      PCI_SLOT(t->devfn), PCI_FUNC(t->devfn));
2538         assert(s == slot_len);
2539         memcpy(p, slot, slot_len);
2540     }
2541 
2542     return path;
2543 }
2544 
2545 static int pci_qdev_find_recursive(PCIBus *bus,
2546                                    const char *id, PCIDevice **pdev)
2547 {
2548     DeviceState *qdev = qdev_find_recursive(&bus->qbus, id);
2549     if (!qdev) {
2550         return -ENODEV;
2551     }
2552 
2553     /* roughly check if given qdev is pci device */
2554     if (object_dynamic_cast(OBJECT(qdev), TYPE_PCI_DEVICE)) {
2555         *pdev = PCI_DEVICE(qdev);
2556         return 0;
2557     }
2558     return -EINVAL;
2559 }
2560 
2561 int pci_qdev_find_device(const char *id, PCIDevice **pdev)
2562 {
2563     PCIHostState *host_bridge;
2564     int rc = -ENODEV;
2565 
2566     QLIST_FOREACH(host_bridge, &pci_host_bridges, next) {
2567         int tmp = pci_qdev_find_recursive(host_bridge->bus, id, pdev);
2568         if (!tmp) {
2569             rc = 0;
2570             break;
2571         }
2572         if (tmp != -ENODEV) {
2573             rc = tmp;
2574         }
2575     }
2576 
2577     return rc;
2578 }
2579 
2580 MemoryRegion *pci_address_space(PCIDevice *dev)
2581 {
2582     return pci_get_bus(dev)->address_space_mem;
2583 }
2584 
2585 MemoryRegion *pci_address_space_io(PCIDevice *dev)
2586 {
2587     return pci_get_bus(dev)->address_space_io;
2588 }
2589 
2590 static void pci_device_class_init(ObjectClass *klass, void *data)
2591 {
2592     DeviceClass *k = DEVICE_CLASS(klass);
2593 
2594     k->realize = pci_qdev_realize;
2595     k->unrealize = pci_qdev_unrealize;
2596     k->bus_type = TYPE_PCI_BUS;
2597     k->props = pci_props;
2598 }
2599 
2600 static void pci_device_class_base_init(ObjectClass *klass, void *data)
2601 {
2602     if (!object_class_is_abstract(klass)) {
2603         ObjectClass *conventional =
2604             object_class_dynamic_cast(klass, INTERFACE_CONVENTIONAL_PCI_DEVICE);
2605         ObjectClass *pcie =
2606             object_class_dynamic_cast(klass, INTERFACE_PCIE_DEVICE);
2607         assert(conventional || pcie);
2608     }
2609 }
2610 
2611 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev)
2612 {
2613     PCIBus *bus = pci_get_bus(dev);
2614     PCIBus *iommu_bus = bus;
2615 
2616     while(iommu_bus && !iommu_bus->iommu_fn && iommu_bus->parent_dev) {
2617         iommu_bus = pci_get_bus(iommu_bus->parent_dev);
2618     }
2619     if (iommu_bus && iommu_bus->iommu_fn) {
2620         return iommu_bus->iommu_fn(bus, iommu_bus->iommu_opaque, dev->devfn);
2621     }
2622     return &address_space_memory;
2623 }
2624 
2625 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque)
2626 {
2627     bus->iommu_fn = fn;
2628     bus->iommu_opaque = opaque;
2629 }
2630 
2631 static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque)
2632 {
2633     Range *range = opaque;
2634     PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
2635     uint16_t cmd = pci_get_word(dev->config + PCI_COMMAND);
2636     int i;
2637 
2638     if (!(cmd & PCI_COMMAND_MEMORY)) {
2639         return;
2640     }
2641 
2642     if (pc->is_bridge) {
2643         pcibus_t base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
2644         pcibus_t limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
2645 
2646         base = MAX(base, 0x1ULL << 32);
2647 
2648         if (limit >= base) {
2649             Range pref_range;
2650             range_set_bounds(&pref_range, base, limit);
2651             range_extend(range, &pref_range);
2652         }
2653     }
2654     for (i = 0; i < PCI_NUM_REGIONS; ++i) {
2655         PCIIORegion *r = &dev->io_regions[i];
2656         pcibus_t lob, upb;
2657         Range region_range;
2658 
2659         if (!r->size ||
2660             (r->type & PCI_BASE_ADDRESS_SPACE_IO) ||
2661             !(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64)) {
2662             continue;
2663         }
2664 
2665         lob = pci_bar_address(dev, i, r->type, r->size);
2666         upb = lob + r->size - 1;
2667         if (lob == PCI_BAR_UNMAPPED) {
2668             continue;
2669         }
2670 
2671         lob = MAX(lob, 0x1ULL << 32);
2672 
2673         if (upb >= lob) {
2674             range_set_bounds(&region_range, lob, upb);
2675             range_extend(range, &region_range);
2676         }
2677     }
2678 }
2679 
2680 void pci_bus_get_w64_range(PCIBus *bus, Range *range)
2681 {
2682     range_make_empty(range);
2683     pci_for_each_device_under_bus(bus, pci_dev_get_w64, range);
2684 }
2685 
2686 static bool pcie_has_upstream_port(PCIDevice *dev)
2687 {
2688     PCIDevice *parent_dev = pci_bridge_get_device(pci_get_bus(dev));
2689 
2690     /* Device associated with an upstream port.
2691      * As there are several types of these, it's easier to check the
2692      * parent device: upstream ports are always connected to
2693      * root or downstream ports.
2694      */
2695     return parent_dev &&
2696         pci_is_express(parent_dev) &&
2697         parent_dev->exp.exp_cap &&
2698         (pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_ROOT_PORT ||
2699          pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_DOWNSTREAM);
2700 }
2701 
2702 PCIDevice *pci_get_function_0(PCIDevice *pci_dev)
2703 {
2704     PCIBus *bus = pci_get_bus(pci_dev);
2705 
2706     if(pcie_has_upstream_port(pci_dev)) {
2707         /* With an upstream PCIe port, we only support 1 device at slot 0 */
2708         return bus->devices[0];
2709     } else {
2710         /* Other bus types might support multiple devices at slots 0-31 */
2711         return bus->devices[PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 0)];
2712     }
2713 }
2714 
2715 MSIMessage pci_get_msi_message(PCIDevice *dev, int vector)
2716 {
2717     MSIMessage msg;
2718     if (msix_enabled(dev)) {
2719         msg = msix_get_message(dev, vector);
2720     } else if (msi_enabled(dev)) {
2721         msg = msi_get_message(dev, vector);
2722     } else {
2723         /* Should never happen */
2724         error_report("%s: unknown interrupt type", __func__);
2725         abort();
2726     }
2727     return msg;
2728 }
2729 
2730 static const TypeInfo pci_device_type_info = {
2731     .name = TYPE_PCI_DEVICE,
2732     .parent = TYPE_DEVICE,
2733     .instance_size = sizeof(PCIDevice),
2734     .abstract = true,
2735     .class_size = sizeof(PCIDeviceClass),
2736     .class_init = pci_device_class_init,
2737     .class_base_init = pci_device_class_base_init,
2738 };
2739 
2740 static void pci_register_types(void)
2741 {
2742     type_register_static(&pci_bus_info);
2743     type_register_static(&pcie_bus_info);
2744     type_register_static(&conventional_pci_interface_info);
2745     type_register_static(&pcie_interface_info);
2746     type_register_static(&pci_device_type_info);
2747 }
2748 
2749 type_init(pci_register_types)
2750