1 /* 2 * QEMU PCI bus manager 3 * 4 * Copyright (c) 2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/hw.h" 25 #include "hw/pci/pci.h" 26 #include "hw/pci/pci_bridge.h" 27 #include "hw/pci/pci_bus.h" 28 #include "hw/pci/pci_host.h" 29 #include "monitor/monitor.h" 30 #include "net/net.h" 31 #include "sysemu/sysemu.h" 32 #include "hw/loader.h" 33 #include "qemu/error-report.h" 34 #include "qemu/range.h" 35 #include "qmp-commands.h" 36 #include "trace.h" 37 #include "hw/pci/msi.h" 38 #include "hw/pci/msix.h" 39 #include "exec/address-spaces.h" 40 #include "hw/hotplug.h" 41 #include "hw/boards.h" 42 43 //#define DEBUG_PCI 44 #ifdef DEBUG_PCI 45 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) 46 #else 47 # define PCI_DPRINTF(format, ...) do { } while (0) 48 #endif 49 50 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent); 51 static char *pcibus_get_dev_path(DeviceState *dev); 52 static char *pcibus_get_fw_dev_path(DeviceState *dev); 53 static void pcibus_reset(BusState *qbus); 54 55 static Property pci_props[] = { 56 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1), 57 DEFINE_PROP_STRING("romfile", PCIDevice, romfile), 58 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1), 59 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present, 60 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false), 61 DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present, 62 QEMU_PCI_CAP_SERR_BITNR, true), 63 DEFINE_PROP_END_OF_LIST() 64 }; 65 66 static const VMStateDescription vmstate_pcibus = { 67 .name = "PCIBUS", 68 .version_id = 1, 69 .minimum_version_id = 1, 70 .fields = (VMStateField[]) { 71 VMSTATE_INT32_EQUAL(nirq, PCIBus), 72 VMSTATE_VARRAY_INT32(irq_count, PCIBus, 73 nirq, 0, vmstate_info_int32, 74 int32_t), 75 VMSTATE_END_OF_LIST() 76 } 77 }; 78 79 static void pci_bus_realize(BusState *qbus, Error **errp) 80 { 81 PCIBus *bus = PCI_BUS(qbus); 82 83 vmstate_register(NULL, -1, &vmstate_pcibus, bus); 84 } 85 86 static void pci_bus_unrealize(BusState *qbus, Error **errp) 87 { 88 PCIBus *bus = PCI_BUS(qbus); 89 90 vmstate_unregister(NULL, &vmstate_pcibus, bus); 91 } 92 93 static bool pcibus_is_root(PCIBus *bus) 94 { 95 return !bus->parent_dev; 96 } 97 98 static int pcibus_num(PCIBus *bus) 99 { 100 if (pcibus_is_root(bus)) { 101 return 0; /* pci host bridge */ 102 } 103 return bus->parent_dev->config[PCI_SECONDARY_BUS]; 104 } 105 106 static uint16_t pcibus_numa_node(PCIBus *bus) 107 { 108 return NUMA_NODE_UNASSIGNED; 109 } 110 111 static void pci_bus_class_init(ObjectClass *klass, void *data) 112 { 113 BusClass *k = BUS_CLASS(klass); 114 PCIBusClass *pbc = PCI_BUS_CLASS(klass); 115 116 k->print_dev = pcibus_dev_print; 117 k->get_dev_path = pcibus_get_dev_path; 118 k->get_fw_dev_path = pcibus_get_fw_dev_path; 119 k->realize = pci_bus_realize; 120 k->unrealize = pci_bus_unrealize; 121 k->reset = pcibus_reset; 122 123 pbc->is_root = pcibus_is_root; 124 pbc->bus_num = pcibus_num; 125 pbc->numa_node = pcibus_numa_node; 126 } 127 128 static const TypeInfo pci_bus_info = { 129 .name = TYPE_PCI_BUS, 130 .parent = TYPE_BUS, 131 .instance_size = sizeof(PCIBus), 132 .class_size = sizeof(PCIBusClass), 133 .class_init = pci_bus_class_init, 134 }; 135 136 static const TypeInfo pcie_bus_info = { 137 .name = TYPE_PCIE_BUS, 138 .parent = TYPE_PCI_BUS, 139 }; 140 141 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num); 142 static void pci_update_mappings(PCIDevice *d); 143 static void pci_irq_handler(void *opaque, int irq_num, int level); 144 static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, Error **); 145 static void pci_del_option_rom(PCIDevice *pdev); 146 147 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET; 148 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU; 149 150 static QLIST_HEAD(, PCIHostState) pci_host_bridges; 151 152 int pci_bar(PCIDevice *d, int reg) 153 { 154 uint8_t type; 155 156 if (reg != PCI_ROM_SLOT) 157 return PCI_BASE_ADDRESS_0 + reg * 4; 158 159 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 160 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS; 161 } 162 163 static inline int pci_irq_state(PCIDevice *d, int irq_num) 164 { 165 return (d->irq_state >> irq_num) & 0x1; 166 } 167 168 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level) 169 { 170 d->irq_state &= ~(0x1 << irq_num); 171 d->irq_state |= level << irq_num; 172 } 173 174 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change) 175 { 176 PCIBus *bus; 177 for (;;) { 178 bus = pci_dev->bus; 179 irq_num = bus->map_irq(pci_dev, irq_num); 180 if (bus->set_irq) 181 break; 182 pci_dev = bus->parent_dev; 183 } 184 bus->irq_count[irq_num] += change; 185 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0); 186 } 187 188 int pci_bus_get_irq_level(PCIBus *bus, int irq_num) 189 { 190 assert(irq_num >= 0); 191 assert(irq_num < bus->nirq); 192 return !!bus->irq_count[irq_num]; 193 } 194 195 /* Update interrupt status bit in config space on interrupt 196 * state change. */ 197 static void pci_update_irq_status(PCIDevice *dev) 198 { 199 if (dev->irq_state) { 200 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT; 201 } else { 202 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; 203 } 204 } 205 206 void pci_device_deassert_intx(PCIDevice *dev) 207 { 208 int i; 209 for (i = 0; i < PCI_NUM_PINS; ++i) { 210 pci_irq_handler(dev, i, 0); 211 } 212 } 213 214 static void pci_do_device_reset(PCIDevice *dev) 215 { 216 int r; 217 218 pci_device_deassert_intx(dev); 219 assert(dev->irq_state == 0); 220 221 /* Clear all writable bits */ 222 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND, 223 pci_get_word(dev->wmask + PCI_COMMAND) | 224 pci_get_word(dev->w1cmask + PCI_COMMAND)); 225 pci_word_test_and_clear_mask(dev->config + PCI_STATUS, 226 pci_get_word(dev->wmask + PCI_STATUS) | 227 pci_get_word(dev->w1cmask + PCI_STATUS)); 228 dev->config[PCI_CACHE_LINE_SIZE] = 0x0; 229 dev->config[PCI_INTERRUPT_LINE] = 0x0; 230 for (r = 0; r < PCI_NUM_REGIONS; ++r) { 231 PCIIORegion *region = &dev->io_regions[r]; 232 if (!region->size) { 233 continue; 234 } 235 236 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) && 237 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 238 pci_set_quad(dev->config + pci_bar(dev, r), region->type); 239 } else { 240 pci_set_long(dev->config + pci_bar(dev, r), region->type); 241 } 242 } 243 pci_update_mappings(dev); 244 245 msi_reset(dev); 246 msix_reset(dev); 247 } 248 249 /* 250 * This function is called on #RST and FLR. 251 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set 252 */ 253 void pci_device_reset(PCIDevice *dev) 254 { 255 qdev_reset_all(&dev->qdev); 256 pci_do_device_reset(dev); 257 } 258 259 /* 260 * Trigger pci bus reset under a given bus. 261 * Called via qbus_reset_all on RST# assert, after the devices 262 * have been reset qdev_reset_all-ed already. 263 */ 264 static void pcibus_reset(BusState *qbus) 265 { 266 PCIBus *bus = DO_UPCAST(PCIBus, qbus, qbus); 267 int i; 268 269 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 270 if (bus->devices[i]) { 271 pci_do_device_reset(bus->devices[i]); 272 } 273 } 274 275 for (i = 0; i < bus->nirq; i++) { 276 assert(bus->irq_count[i] == 0); 277 } 278 } 279 280 static void pci_host_bus_register(PCIBus *bus, DeviceState *parent) 281 { 282 PCIHostState *host_bridge = PCI_HOST_BRIDGE(parent); 283 284 QLIST_INSERT_HEAD(&pci_host_bridges, host_bridge, next); 285 } 286 287 PCIBus *pci_find_primary_bus(void) 288 { 289 PCIBus *primary_bus = NULL; 290 PCIHostState *host; 291 292 QLIST_FOREACH(host, &pci_host_bridges, next) { 293 if (primary_bus) { 294 /* We have multiple root buses, refuse to select a primary */ 295 return NULL; 296 } 297 primary_bus = host->bus; 298 } 299 300 return primary_bus; 301 } 302 303 PCIBus *pci_device_root_bus(const PCIDevice *d) 304 { 305 PCIBus *bus = d->bus; 306 307 while (!pci_bus_is_root(bus)) { 308 d = bus->parent_dev; 309 assert(d != NULL); 310 311 bus = d->bus; 312 } 313 314 return bus; 315 } 316 317 const char *pci_root_bus_path(PCIDevice *dev) 318 { 319 PCIBus *rootbus = pci_device_root_bus(dev); 320 PCIHostState *host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent); 321 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_GET_CLASS(host_bridge); 322 323 assert(host_bridge->bus == rootbus); 324 325 if (hc->root_bus_path) { 326 return (*hc->root_bus_path)(host_bridge, rootbus); 327 } 328 329 return rootbus->qbus.name; 330 } 331 332 static void pci_bus_init(PCIBus *bus, DeviceState *parent, 333 const char *name, 334 MemoryRegion *address_space_mem, 335 MemoryRegion *address_space_io, 336 uint8_t devfn_min) 337 { 338 assert(PCI_FUNC(devfn_min) == 0); 339 bus->devfn_min = devfn_min; 340 bus->address_space_mem = address_space_mem; 341 bus->address_space_io = address_space_io; 342 343 /* host bridge */ 344 QLIST_INIT(&bus->child); 345 346 pci_host_bus_register(bus, parent); 347 } 348 349 bool pci_bus_is_express(PCIBus *bus) 350 { 351 return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS); 352 } 353 354 bool pci_bus_is_root(PCIBus *bus) 355 { 356 return PCI_BUS_GET_CLASS(bus)->is_root(bus); 357 } 358 359 void pci_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent, 360 const char *name, 361 MemoryRegion *address_space_mem, 362 MemoryRegion *address_space_io, 363 uint8_t devfn_min, const char *typename) 364 { 365 qbus_create_inplace(bus, bus_size, typename, parent, name); 366 pci_bus_init(bus, parent, name, address_space_mem, 367 address_space_io, devfn_min); 368 } 369 370 PCIBus *pci_bus_new(DeviceState *parent, const char *name, 371 MemoryRegion *address_space_mem, 372 MemoryRegion *address_space_io, 373 uint8_t devfn_min, const char *typename) 374 { 375 PCIBus *bus; 376 377 bus = PCI_BUS(qbus_create(typename, parent, name)); 378 pci_bus_init(bus, parent, name, address_space_mem, 379 address_space_io, devfn_min); 380 return bus; 381 } 382 383 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 384 void *irq_opaque, int nirq) 385 { 386 bus->set_irq = set_irq; 387 bus->map_irq = map_irq; 388 bus->irq_opaque = irq_opaque; 389 bus->nirq = nirq; 390 bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0])); 391 } 392 393 PCIBus *pci_register_bus(DeviceState *parent, const char *name, 394 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 395 void *irq_opaque, 396 MemoryRegion *address_space_mem, 397 MemoryRegion *address_space_io, 398 uint8_t devfn_min, int nirq, const char *typename) 399 { 400 PCIBus *bus; 401 402 bus = pci_bus_new(parent, name, address_space_mem, 403 address_space_io, devfn_min, typename); 404 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq); 405 return bus; 406 } 407 408 int pci_bus_num(PCIBus *s) 409 { 410 return PCI_BUS_GET_CLASS(s)->bus_num(s); 411 } 412 413 int pci_bus_numa_node(PCIBus *bus) 414 { 415 return PCI_BUS_GET_CLASS(bus)->numa_node(bus); 416 } 417 418 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size) 419 { 420 PCIDevice *s = container_of(pv, PCIDevice, config); 421 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(s); 422 uint8_t *config; 423 int i; 424 425 assert(size == pci_config_size(s)); 426 config = g_malloc(size); 427 428 qemu_get_buffer(f, config, size); 429 for (i = 0; i < size; ++i) { 430 if ((config[i] ^ s->config[i]) & 431 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) { 432 error_report("%s: Bad config data: i=0x%x read: %x device: %x " 433 "cmask: %x wmask: %x w1cmask:%x", __func__, 434 i, config[i], s->config[i], 435 s->cmask[i], s->wmask[i], s->w1cmask[i]); 436 g_free(config); 437 return -EINVAL; 438 } 439 } 440 memcpy(s->config, config, size); 441 442 pci_update_mappings(s); 443 if (pc->is_bridge) { 444 PCIBridge *b = PCI_BRIDGE(s); 445 pci_bridge_update_mappings(b); 446 } 447 448 memory_region_set_enabled(&s->bus_master_enable_region, 449 pci_get_word(s->config + PCI_COMMAND) 450 & PCI_COMMAND_MASTER); 451 452 g_free(config); 453 return 0; 454 } 455 456 /* just put buffer */ 457 static void put_pci_config_device(QEMUFile *f, void *pv, size_t size) 458 { 459 const uint8_t **v = pv; 460 assert(size == pci_config_size(container_of(pv, PCIDevice, config))); 461 qemu_put_buffer(f, *v, size); 462 } 463 464 static VMStateInfo vmstate_info_pci_config = { 465 .name = "pci config", 466 .get = get_pci_config_device, 467 .put = put_pci_config_device, 468 }; 469 470 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size) 471 { 472 PCIDevice *s = container_of(pv, PCIDevice, irq_state); 473 uint32_t irq_state[PCI_NUM_PINS]; 474 int i; 475 for (i = 0; i < PCI_NUM_PINS; ++i) { 476 irq_state[i] = qemu_get_be32(f); 477 if (irq_state[i] != 0x1 && irq_state[i] != 0) { 478 fprintf(stderr, "irq state %d: must be 0 or 1.\n", 479 irq_state[i]); 480 return -EINVAL; 481 } 482 } 483 484 for (i = 0; i < PCI_NUM_PINS; ++i) { 485 pci_set_irq_state(s, i, irq_state[i]); 486 } 487 488 return 0; 489 } 490 491 static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size) 492 { 493 int i; 494 PCIDevice *s = container_of(pv, PCIDevice, irq_state); 495 496 for (i = 0; i < PCI_NUM_PINS; ++i) { 497 qemu_put_be32(f, pci_irq_state(s, i)); 498 } 499 } 500 501 static VMStateInfo vmstate_info_pci_irq_state = { 502 .name = "pci irq state", 503 .get = get_pci_irq_state, 504 .put = put_pci_irq_state, 505 }; 506 507 const VMStateDescription vmstate_pci_device = { 508 .name = "PCIDevice", 509 .version_id = 2, 510 .minimum_version_id = 1, 511 .fields = (VMStateField[]) { 512 VMSTATE_INT32_POSITIVE_LE(version_id, PCIDevice), 513 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0, 514 vmstate_info_pci_config, 515 PCI_CONFIG_SPACE_SIZE), 516 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2, 517 vmstate_info_pci_irq_state, 518 PCI_NUM_PINS * sizeof(int32_t)), 519 VMSTATE_END_OF_LIST() 520 } 521 }; 522 523 const VMStateDescription vmstate_pcie_device = { 524 .name = "PCIEDevice", 525 .version_id = 2, 526 .minimum_version_id = 1, 527 .fields = (VMStateField[]) { 528 VMSTATE_INT32_POSITIVE_LE(version_id, PCIDevice), 529 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0, 530 vmstate_info_pci_config, 531 PCIE_CONFIG_SPACE_SIZE), 532 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2, 533 vmstate_info_pci_irq_state, 534 PCI_NUM_PINS * sizeof(int32_t)), 535 VMSTATE_END_OF_LIST() 536 } 537 }; 538 539 static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s) 540 { 541 return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device; 542 } 543 544 void pci_device_save(PCIDevice *s, QEMUFile *f) 545 { 546 /* Clear interrupt status bit: it is implicit 547 * in irq_state which we are saving. 548 * This makes us compatible with old devices 549 * which never set or clear this bit. */ 550 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; 551 vmstate_save_state(f, pci_get_vmstate(s), s, NULL); 552 /* Restore the interrupt status bit. */ 553 pci_update_irq_status(s); 554 } 555 556 int pci_device_load(PCIDevice *s, QEMUFile *f) 557 { 558 int ret; 559 ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id); 560 /* Restore the interrupt status bit. */ 561 pci_update_irq_status(s); 562 return ret; 563 } 564 565 static void pci_set_default_subsystem_id(PCIDevice *pci_dev) 566 { 567 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, 568 pci_default_sub_vendor_id); 569 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 570 pci_default_sub_device_id); 571 } 572 573 /* 574 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL 575 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error 576 */ 577 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, 578 unsigned int *slotp, unsigned int *funcp) 579 { 580 const char *p; 581 char *e; 582 unsigned long val; 583 unsigned long dom = 0, bus = 0; 584 unsigned int slot = 0; 585 unsigned int func = 0; 586 587 p = addr; 588 val = strtoul(p, &e, 16); 589 if (e == p) 590 return -1; 591 if (*e == ':') { 592 bus = val; 593 p = e + 1; 594 val = strtoul(p, &e, 16); 595 if (e == p) 596 return -1; 597 if (*e == ':') { 598 dom = bus; 599 bus = val; 600 p = e + 1; 601 val = strtoul(p, &e, 16); 602 if (e == p) 603 return -1; 604 } 605 } 606 607 slot = val; 608 609 if (funcp != NULL) { 610 if (*e != '.') 611 return -1; 612 613 p = e + 1; 614 val = strtoul(p, &e, 16); 615 if (e == p) 616 return -1; 617 618 func = val; 619 } 620 621 /* if funcp == NULL func is 0 */ 622 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7) 623 return -1; 624 625 if (*e) 626 return -1; 627 628 *domp = dom; 629 *busp = bus; 630 *slotp = slot; 631 if (funcp != NULL) 632 *funcp = func; 633 return 0; 634 } 635 636 static PCIBus *pci_get_bus_devfn(int *devfnp, PCIBus *root, 637 const char *devaddr) 638 { 639 int dom, bus; 640 unsigned slot; 641 642 if (!root) { 643 fprintf(stderr, "No primary PCI bus\n"); 644 return NULL; 645 } 646 647 assert(!root->parent_dev); 648 649 if (!devaddr) { 650 *devfnp = -1; 651 return pci_find_bus_nr(root, 0); 652 } 653 654 if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) { 655 return NULL; 656 } 657 658 if (dom != 0) { 659 fprintf(stderr, "No support for non-zero PCI domains\n"); 660 return NULL; 661 } 662 663 *devfnp = PCI_DEVFN(slot, 0); 664 return pci_find_bus_nr(root, bus); 665 } 666 667 static void pci_init_cmask(PCIDevice *dev) 668 { 669 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff); 670 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff); 671 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST; 672 dev->cmask[PCI_REVISION_ID] = 0xff; 673 dev->cmask[PCI_CLASS_PROG] = 0xff; 674 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff); 675 dev->cmask[PCI_HEADER_TYPE] = 0xff; 676 dev->cmask[PCI_CAPABILITY_LIST] = 0xff; 677 } 678 679 static void pci_init_wmask(PCIDevice *dev) 680 { 681 int config_size = pci_config_size(dev); 682 683 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff; 684 dev->wmask[PCI_INTERRUPT_LINE] = 0xff; 685 pci_set_word(dev->wmask + PCI_COMMAND, 686 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | 687 PCI_COMMAND_INTX_DISABLE); 688 if (dev->cap_present & QEMU_PCI_CAP_SERR) { 689 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR); 690 } 691 692 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff, 693 config_size - PCI_CONFIG_HEADER_SIZE); 694 } 695 696 static void pci_init_w1cmask(PCIDevice *dev) 697 { 698 /* 699 * Note: It's okay to set w1cmask even for readonly bits as 700 * long as their value is hardwired to 0. 701 */ 702 pci_set_word(dev->w1cmask + PCI_STATUS, 703 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT | 704 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT | 705 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY); 706 } 707 708 static void pci_init_mask_bridge(PCIDevice *d) 709 { 710 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and 711 PCI_SEC_LETENCY_TIMER */ 712 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4); 713 714 /* base and limit */ 715 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff; 716 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff; 717 pci_set_word(d->wmask + PCI_MEMORY_BASE, 718 PCI_MEMORY_RANGE_MASK & 0xffff); 719 pci_set_word(d->wmask + PCI_MEMORY_LIMIT, 720 PCI_MEMORY_RANGE_MASK & 0xffff); 721 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE, 722 PCI_PREF_RANGE_MASK & 0xffff); 723 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT, 724 PCI_PREF_RANGE_MASK & 0xffff); 725 726 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */ 727 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8); 728 729 /* Supported memory and i/o types */ 730 d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16; 731 d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16; 732 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE, 733 PCI_PREF_RANGE_TYPE_64); 734 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT, 735 PCI_PREF_RANGE_TYPE_64); 736 737 /* 738 * TODO: Bridges default to 10-bit VGA decoding but we currently only 739 * implement 16-bit decoding (no alias support). 740 */ 741 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 742 PCI_BRIDGE_CTL_PARITY | 743 PCI_BRIDGE_CTL_SERR | 744 PCI_BRIDGE_CTL_ISA | 745 PCI_BRIDGE_CTL_VGA | 746 PCI_BRIDGE_CTL_VGA_16BIT | 747 PCI_BRIDGE_CTL_MASTER_ABORT | 748 PCI_BRIDGE_CTL_BUS_RESET | 749 PCI_BRIDGE_CTL_FAST_BACK | 750 PCI_BRIDGE_CTL_DISCARD | 751 PCI_BRIDGE_CTL_SEC_DISCARD | 752 PCI_BRIDGE_CTL_DISCARD_SERR); 753 /* Below does not do anything as we never set this bit, put here for 754 * completeness. */ 755 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL, 756 PCI_BRIDGE_CTL_DISCARD_STATUS); 757 d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK; 758 d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK; 759 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE, 760 PCI_PREF_RANGE_TYPE_MASK); 761 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT, 762 PCI_PREF_RANGE_TYPE_MASK); 763 } 764 765 static void pci_init_multifunction(PCIBus *bus, PCIDevice *dev, Error **errp) 766 { 767 uint8_t slot = PCI_SLOT(dev->devfn); 768 uint8_t func; 769 770 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 771 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION; 772 } 773 774 /* 775 * multifunction bit is interpreted in two ways as follows. 776 * - all functions must set the bit to 1. 777 * Example: Intel X53 778 * - function 0 must set the bit, but the rest function (> 0) 779 * is allowed to leave the bit to 0. 780 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10, 781 * 782 * So OS (at least Linux) checks the bit of only function 0, 783 * and doesn't see the bit of function > 0. 784 * 785 * The below check allows both interpretation. 786 */ 787 if (PCI_FUNC(dev->devfn)) { 788 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)]; 789 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) { 790 /* function 0 should set multifunction bit */ 791 error_setg(errp, "PCI: single function device can't be populated " 792 "in function %x.%x", slot, PCI_FUNC(dev->devfn)); 793 return; 794 } 795 return; 796 } 797 798 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 799 return; 800 } 801 /* function 0 indicates single function, so function > 0 must be NULL */ 802 for (func = 1; func < PCI_FUNC_MAX; ++func) { 803 if (bus->devices[PCI_DEVFN(slot, func)]) { 804 error_setg(errp, "PCI: %x.0 indicates single function, " 805 "but %x.%x is already populated.", 806 slot, slot, func); 807 return; 808 } 809 } 810 } 811 812 static void pci_config_alloc(PCIDevice *pci_dev) 813 { 814 int config_size = pci_config_size(pci_dev); 815 816 pci_dev->config = g_malloc0(config_size); 817 pci_dev->cmask = g_malloc0(config_size); 818 pci_dev->wmask = g_malloc0(config_size); 819 pci_dev->w1cmask = g_malloc0(config_size); 820 pci_dev->used = g_malloc0(config_size); 821 } 822 823 static void pci_config_free(PCIDevice *pci_dev) 824 { 825 g_free(pci_dev->config); 826 g_free(pci_dev->cmask); 827 g_free(pci_dev->wmask); 828 g_free(pci_dev->w1cmask); 829 g_free(pci_dev->used); 830 } 831 832 static void do_pci_unregister_device(PCIDevice *pci_dev) 833 { 834 pci_dev->bus->devices[pci_dev->devfn] = NULL; 835 pci_config_free(pci_dev); 836 837 address_space_destroy(&pci_dev->bus_master_as); 838 } 839 840 /* -1 for devfn means auto assign */ 841 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus, 842 const char *name, int devfn, 843 Error **errp) 844 { 845 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 846 PCIConfigReadFunc *config_read = pc->config_read; 847 PCIConfigWriteFunc *config_write = pc->config_write; 848 Error *local_err = NULL; 849 AddressSpace *dma_as; 850 DeviceState *dev = DEVICE(pci_dev); 851 852 pci_dev->bus = bus; 853 854 if (devfn < 0) { 855 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices); 856 devfn += PCI_FUNC_MAX) { 857 if (!bus->devices[devfn]) 858 goto found; 859 } 860 error_setg(errp, "PCI: no slot/function available for %s, all in use", 861 name); 862 return NULL; 863 found: ; 864 } else if (bus->devices[devfn]) { 865 error_setg(errp, "PCI: slot %d function %d not available for %s," 866 " in use by %s", 867 PCI_SLOT(devfn), PCI_FUNC(devfn), name, 868 bus->devices[devfn]->name); 869 return NULL; 870 } else if (dev->hotplugged && 871 pci_get_function_0(pci_dev)) { 872 error_setg(errp, "PCI: slot %d function 0 already ocuppied by %s," 873 " new func %s cannot be exposed to guest.", 874 PCI_SLOT(devfn), 875 bus->devices[PCI_DEVFN(PCI_SLOT(devfn), 0)]->name, 876 name); 877 878 return NULL; 879 } 880 881 pci_dev->devfn = devfn; 882 dma_as = pci_device_iommu_address_space(pci_dev); 883 884 memory_region_init_alias(&pci_dev->bus_master_enable_region, 885 OBJECT(pci_dev), "bus master", 886 dma_as->root, 0, memory_region_size(dma_as->root)); 887 memory_region_set_enabled(&pci_dev->bus_master_enable_region, false); 888 address_space_init(&pci_dev->bus_master_as, &pci_dev->bus_master_enable_region, 889 name); 890 891 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name); 892 pci_dev->irq_state = 0; 893 pci_config_alloc(pci_dev); 894 895 pci_config_set_vendor_id(pci_dev->config, pc->vendor_id); 896 pci_config_set_device_id(pci_dev->config, pc->device_id); 897 pci_config_set_revision(pci_dev->config, pc->revision); 898 pci_config_set_class(pci_dev->config, pc->class_id); 899 900 if (!pc->is_bridge) { 901 if (pc->subsystem_vendor_id || pc->subsystem_id) { 902 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, 903 pc->subsystem_vendor_id); 904 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 905 pc->subsystem_id); 906 } else { 907 pci_set_default_subsystem_id(pci_dev); 908 } 909 } else { 910 /* subsystem_vendor_id/subsystem_id are only for header type 0 */ 911 assert(!pc->subsystem_vendor_id); 912 assert(!pc->subsystem_id); 913 } 914 pci_init_cmask(pci_dev); 915 pci_init_wmask(pci_dev); 916 pci_init_w1cmask(pci_dev); 917 if (pc->is_bridge) { 918 pci_init_mask_bridge(pci_dev); 919 } 920 pci_init_multifunction(bus, pci_dev, &local_err); 921 if (local_err) { 922 error_propagate(errp, local_err); 923 do_pci_unregister_device(pci_dev); 924 return NULL; 925 } 926 927 if (!config_read) 928 config_read = pci_default_read_config; 929 if (!config_write) 930 config_write = pci_default_write_config; 931 pci_dev->config_read = config_read; 932 pci_dev->config_write = config_write; 933 bus->devices[devfn] = pci_dev; 934 pci_dev->version_id = 2; /* Current pci device vmstate version */ 935 return pci_dev; 936 } 937 938 static void pci_unregister_io_regions(PCIDevice *pci_dev) 939 { 940 PCIIORegion *r; 941 int i; 942 943 for(i = 0; i < PCI_NUM_REGIONS; i++) { 944 r = &pci_dev->io_regions[i]; 945 if (!r->size || r->addr == PCI_BAR_UNMAPPED) 946 continue; 947 memory_region_del_subregion(r->address_space, r->memory); 948 } 949 950 pci_unregister_vga(pci_dev); 951 } 952 953 static void pci_qdev_unrealize(DeviceState *dev, Error **errp) 954 { 955 PCIDevice *pci_dev = PCI_DEVICE(dev); 956 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 957 958 pci_unregister_io_regions(pci_dev); 959 pci_del_option_rom(pci_dev); 960 961 if (pc->exit) { 962 pc->exit(pci_dev); 963 } 964 965 do_pci_unregister_device(pci_dev); 966 } 967 968 void pci_register_bar(PCIDevice *pci_dev, int region_num, 969 uint8_t type, MemoryRegion *memory) 970 { 971 PCIIORegion *r; 972 uint32_t addr; 973 uint64_t wmask; 974 pcibus_t size = memory_region_size(memory); 975 976 assert(region_num >= 0); 977 assert(region_num < PCI_NUM_REGIONS); 978 if (size & (size-1)) { 979 fprintf(stderr, "ERROR: PCI region size must be pow2 " 980 "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size); 981 exit(1); 982 } 983 984 r = &pci_dev->io_regions[region_num]; 985 r->addr = PCI_BAR_UNMAPPED; 986 r->size = size; 987 r->type = type; 988 r->memory = NULL; 989 990 wmask = ~(size - 1); 991 addr = pci_bar(pci_dev, region_num); 992 if (region_num == PCI_ROM_SLOT) { 993 /* ROM enable bit is writable */ 994 wmask |= PCI_ROM_ADDRESS_ENABLE; 995 } 996 pci_set_long(pci_dev->config + addr, type); 997 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) && 998 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 999 pci_set_quad(pci_dev->wmask + addr, wmask); 1000 pci_set_quad(pci_dev->cmask + addr, ~0ULL); 1001 } else { 1002 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff); 1003 pci_set_long(pci_dev->cmask + addr, 0xffffffff); 1004 } 1005 pci_dev->io_regions[region_num].memory = memory; 1006 pci_dev->io_regions[region_num].address_space 1007 = type & PCI_BASE_ADDRESS_SPACE_IO 1008 ? pci_dev->bus->address_space_io 1009 : pci_dev->bus->address_space_mem; 1010 } 1011 1012 static void pci_update_vga(PCIDevice *pci_dev) 1013 { 1014 uint16_t cmd; 1015 1016 if (!pci_dev->has_vga) { 1017 return; 1018 } 1019 1020 cmd = pci_get_word(pci_dev->config + PCI_COMMAND); 1021 1022 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_MEM], 1023 cmd & PCI_COMMAND_MEMORY); 1024 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO], 1025 cmd & PCI_COMMAND_IO); 1026 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI], 1027 cmd & PCI_COMMAND_IO); 1028 } 1029 1030 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, 1031 MemoryRegion *io_lo, MemoryRegion *io_hi) 1032 { 1033 assert(!pci_dev->has_vga); 1034 1035 assert(memory_region_size(mem) == QEMU_PCI_VGA_MEM_SIZE); 1036 pci_dev->vga_regions[QEMU_PCI_VGA_MEM] = mem; 1037 memory_region_add_subregion_overlap(pci_dev->bus->address_space_mem, 1038 QEMU_PCI_VGA_MEM_BASE, mem, 1); 1039 1040 assert(memory_region_size(io_lo) == QEMU_PCI_VGA_IO_LO_SIZE); 1041 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO] = io_lo; 1042 memory_region_add_subregion_overlap(pci_dev->bus->address_space_io, 1043 QEMU_PCI_VGA_IO_LO_BASE, io_lo, 1); 1044 1045 assert(memory_region_size(io_hi) == QEMU_PCI_VGA_IO_HI_SIZE); 1046 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI] = io_hi; 1047 memory_region_add_subregion_overlap(pci_dev->bus->address_space_io, 1048 QEMU_PCI_VGA_IO_HI_BASE, io_hi, 1); 1049 pci_dev->has_vga = true; 1050 1051 pci_update_vga(pci_dev); 1052 } 1053 1054 void pci_unregister_vga(PCIDevice *pci_dev) 1055 { 1056 if (!pci_dev->has_vga) { 1057 return; 1058 } 1059 1060 memory_region_del_subregion(pci_dev->bus->address_space_mem, 1061 pci_dev->vga_regions[QEMU_PCI_VGA_MEM]); 1062 memory_region_del_subregion(pci_dev->bus->address_space_io, 1063 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO]); 1064 memory_region_del_subregion(pci_dev->bus->address_space_io, 1065 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI]); 1066 pci_dev->has_vga = false; 1067 } 1068 1069 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num) 1070 { 1071 return pci_dev->io_regions[region_num].addr; 1072 } 1073 1074 static pcibus_t pci_bar_address(PCIDevice *d, 1075 int reg, uint8_t type, pcibus_t size) 1076 { 1077 pcibus_t new_addr, last_addr; 1078 int bar = pci_bar(d, reg); 1079 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND); 1080 Object *machine = qdev_get_machine(); 1081 ObjectClass *oc = object_get_class(machine); 1082 MachineClass *mc = MACHINE_CLASS(oc); 1083 bool allow_0_address = mc->pci_allow_0_address; 1084 1085 if (type & PCI_BASE_ADDRESS_SPACE_IO) { 1086 if (!(cmd & PCI_COMMAND_IO)) { 1087 return PCI_BAR_UNMAPPED; 1088 } 1089 new_addr = pci_get_long(d->config + bar) & ~(size - 1); 1090 last_addr = new_addr + size - 1; 1091 /* Check if 32 bit BAR wraps around explicitly. 1092 * TODO: make priorities correct and remove this work around. 1093 */ 1094 if (last_addr <= new_addr || last_addr >= UINT32_MAX || 1095 (!allow_0_address && new_addr == 0)) { 1096 return PCI_BAR_UNMAPPED; 1097 } 1098 return new_addr; 1099 } 1100 1101 if (!(cmd & PCI_COMMAND_MEMORY)) { 1102 return PCI_BAR_UNMAPPED; 1103 } 1104 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 1105 new_addr = pci_get_quad(d->config + bar); 1106 } else { 1107 new_addr = pci_get_long(d->config + bar); 1108 } 1109 /* the ROM slot has a specific enable bit */ 1110 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) { 1111 return PCI_BAR_UNMAPPED; 1112 } 1113 new_addr &= ~(size - 1); 1114 last_addr = new_addr + size - 1; 1115 /* NOTE: we do not support wrapping */ 1116 /* XXX: as we cannot support really dynamic 1117 mappings, we handle specific values as invalid 1118 mappings. */ 1119 if (last_addr <= new_addr || last_addr == PCI_BAR_UNMAPPED || 1120 (!allow_0_address && new_addr == 0)) { 1121 return PCI_BAR_UNMAPPED; 1122 } 1123 1124 /* Now pcibus_t is 64bit. 1125 * Check if 32 bit BAR wraps around explicitly. 1126 * Without this, PC ide doesn't work well. 1127 * TODO: remove this work around. 1128 */ 1129 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) { 1130 return PCI_BAR_UNMAPPED; 1131 } 1132 1133 /* 1134 * OS is allowed to set BAR beyond its addressable 1135 * bits. For example, 32 bit OS can set 64bit bar 1136 * to >4G. Check it. TODO: we might need to support 1137 * it in the future for e.g. PAE. 1138 */ 1139 if (last_addr >= HWADDR_MAX) { 1140 return PCI_BAR_UNMAPPED; 1141 } 1142 1143 return new_addr; 1144 } 1145 1146 static void pci_update_mappings(PCIDevice *d) 1147 { 1148 PCIIORegion *r; 1149 int i; 1150 pcibus_t new_addr; 1151 1152 for(i = 0; i < PCI_NUM_REGIONS; i++) { 1153 r = &d->io_regions[i]; 1154 1155 /* this region isn't registered */ 1156 if (!r->size) 1157 continue; 1158 1159 new_addr = pci_bar_address(d, i, r->type, r->size); 1160 1161 /* This bar isn't changed */ 1162 if (new_addr == r->addr) 1163 continue; 1164 1165 /* now do the real mapping */ 1166 if (r->addr != PCI_BAR_UNMAPPED) { 1167 trace_pci_update_mappings_del(d, pci_bus_num(d->bus), 1168 PCI_SLOT(d->devfn), 1169 PCI_FUNC(d->devfn), 1170 i, r->addr, r->size); 1171 memory_region_del_subregion(r->address_space, r->memory); 1172 } 1173 r->addr = new_addr; 1174 if (r->addr != PCI_BAR_UNMAPPED) { 1175 trace_pci_update_mappings_add(d, pci_bus_num(d->bus), 1176 PCI_SLOT(d->devfn), 1177 PCI_FUNC(d->devfn), 1178 i, r->addr, r->size); 1179 memory_region_add_subregion_overlap(r->address_space, 1180 r->addr, r->memory, 1); 1181 } 1182 } 1183 1184 pci_update_vga(d); 1185 } 1186 1187 static inline int pci_irq_disabled(PCIDevice *d) 1188 { 1189 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE; 1190 } 1191 1192 /* Called after interrupt disabled field update in config space, 1193 * assert/deassert interrupts if necessary. 1194 * Gets original interrupt disable bit value (before update). */ 1195 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled) 1196 { 1197 int i, disabled = pci_irq_disabled(d); 1198 if (disabled == was_irq_disabled) 1199 return; 1200 for (i = 0; i < PCI_NUM_PINS; ++i) { 1201 int state = pci_irq_state(d, i); 1202 pci_change_irq_level(d, i, disabled ? -state : state); 1203 } 1204 } 1205 1206 uint32_t pci_default_read_config(PCIDevice *d, 1207 uint32_t address, int len) 1208 { 1209 uint32_t val = 0; 1210 1211 memcpy(&val, d->config + address, len); 1212 return le32_to_cpu(val); 1213 } 1214 1215 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val_in, int l) 1216 { 1217 int i, was_irq_disabled = pci_irq_disabled(d); 1218 uint32_t val = val_in; 1219 1220 for (i = 0; i < l; val >>= 8, ++i) { 1221 uint8_t wmask = d->wmask[addr + i]; 1222 uint8_t w1cmask = d->w1cmask[addr + i]; 1223 assert(!(wmask & w1cmask)); 1224 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask); 1225 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */ 1226 } 1227 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) || 1228 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) || 1229 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) || 1230 range_covers_byte(addr, l, PCI_COMMAND)) 1231 pci_update_mappings(d); 1232 1233 if (range_covers_byte(addr, l, PCI_COMMAND)) { 1234 pci_update_irq_disabled(d, was_irq_disabled); 1235 memory_region_set_enabled(&d->bus_master_enable_region, 1236 pci_get_word(d->config + PCI_COMMAND) 1237 & PCI_COMMAND_MASTER); 1238 } 1239 1240 msi_write_config(d, addr, val_in, l); 1241 msix_write_config(d, addr, val_in, l); 1242 } 1243 1244 /***********************************************************/ 1245 /* generic PCI irq support */ 1246 1247 /* 0 <= irq_num <= 3. level must be 0 or 1 */ 1248 static void pci_irq_handler(void *opaque, int irq_num, int level) 1249 { 1250 PCIDevice *pci_dev = opaque; 1251 int change; 1252 1253 change = level - pci_irq_state(pci_dev, irq_num); 1254 if (!change) 1255 return; 1256 1257 pci_set_irq_state(pci_dev, irq_num, level); 1258 pci_update_irq_status(pci_dev); 1259 if (pci_irq_disabled(pci_dev)) 1260 return; 1261 pci_change_irq_level(pci_dev, irq_num, change); 1262 } 1263 1264 static inline int pci_intx(PCIDevice *pci_dev) 1265 { 1266 return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1; 1267 } 1268 1269 qemu_irq pci_allocate_irq(PCIDevice *pci_dev) 1270 { 1271 int intx = pci_intx(pci_dev); 1272 1273 return qemu_allocate_irq(pci_irq_handler, pci_dev, intx); 1274 } 1275 1276 void pci_set_irq(PCIDevice *pci_dev, int level) 1277 { 1278 int intx = pci_intx(pci_dev); 1279 pci_irq_handler(pci_dev, intx, level); 1280 } 1281 1282 /* Special hooks used by device assignment */ 1283 void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq) 1284 { 1285 assert(pci_bus_is_root(bus)); 1286 bus->route_intx_to_irq = route_intx_to_irq; 1287 } 1288 1289 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin) 1290 { 1291 PCIBus *bus; 1292 1293 do { 1294 bus = dev->bus; 1295 pin = bus->map_irq(dev, pin); 1296 dev = bus->parent_dev; 1297 } while (dev); 1298 1299 if (!bus->route_intx_to_irq) { 1300 error_report("PCI: Bug - unimplemented PCI INTx routing (%s)", 1301 object_get_typename(OBJECT(bus->qbus.parent))); 1302 return (PCIINTxRoute) { PCI_INTX_DISABLED, -1 }; 1303 } 1304 1305 return bus->route_intx_to_irq(bus->irq_opaque, pin); 1306 } 1307 1308 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new) 1309 { 1310 return old->mode != new->mode || old->irq != new->irq; 1311 } 1312 1313 void pci_bus_fire_intx_routing_notifier(PCIBus *bus) 1314 { 1315 PCIDevice *dev; 1316 PCIBus *sec; 1317 int i; 1318 1319 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 1320 dev = bus->devices[i]; 1321 if (dev && dev->intx_routing_notifier) { 1322 dev->intx_routing_notifier(dev); 1323 } 1324 } 1325 1326 QLIST_FOREACH(sec, &bus->child, sibling) { 1327 pci_bus_fire_intx_routing_notifier(sec); 1328 } 1329 } 1330 1331 void pci_device_set_intx_routing_notifier(PCIDevice *dev, 1332 PCIINTxRoutingNotifier notifier) 1333 { 1334 dev->intx_routing_notifier = notifier; 1335 } 1336 1337 /* 1338 * PCI-to-PCI bridge specification 1339 * 9.1: Interrupt routing. Table 9-1 1340 * 1341 * the PCI Express Base Specification, Revision 2.1 1342 * 2.2.8.1: INTx interrutp signaling - Rules 1343 * the Implementation Note 1344 * Table 2-20 1345 */ 1346 /* 1347 * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD 1348 * 0-origin unlike PCI interrupt pin register. 1349 */ 1350 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin) 1351 { 1352 return (pin + PCI_SLOT(pci_dev->devfn)) % PCI_NUM_PINS; 1353 } 1354 1355 /***********************************************************/ 1356 /* monitor info on PCI */ 1357 1358 typedef struct { 1359 uint16_t class; 1360 const char *desc; 1361 const char *fw_name; 1362 uint16_t fw_ign_bits; 1363 } pci_class_desc; 1364 1365 static const pci_class_desc pci_class_descriptions[] = 1366 { 1367 { 0x0001, "VGA controller", "display"}, 1368 { 0x0100, "SCSI controller", "scsi"}, 1369 { 0x0101, "IDE controller", "ide"}, 1370 { 0x0102, "Floppy controller", "fdc"}, 1371 { 0x0103, "IPI controller", "ipi"}, 1372 { 0x0104, "RAID controller", "raid"}, 1373 { 0x0106, "SATA controller"}, 1374 { 0x0107, "SAS controller"}, 1375 { 0x0180, "Storage controller"}, 1376 { 0x0200, "Ethernet controller", "ethernet"}, 1377 { 0x0201, "Token Ring controller", "token-ring"}, 1378 { 0x0202, "FDDI controller", "fddi"}, 1379 { 0x0203, "ATM controller", "atm"}, 1380 { 0x0280, "Network controller"}, 1381 { 0x0300, "VGA controller", "display", 0x00ff}, 1382 { 0x0301, "XGA controller"}, 1383 { 0x0302, "3D controller"}, 1384 { 0x0380, "Display controller"}, 1385 { 0x0400, "Video controller", "video"}, 1386 { 0x0401, "Audio controller", "sound"}, 1387 { 0x0402, "Phone"}, 1388 { 0x0403, "Audio controller", "sound"}, 1389 { 0x0480, "Multimedia controller"}, 1390 { 0x0500, "RAM controller", "memory"}, 1391 { 0x0501, "Flash controller", "flash"}, 1392 { 0x0580, "Memory controller"}, 1393 { 0x0600, "Host bridge", "host"}, 1394 { 0x0601, "ISA bridge", "isa"}, 1395 { 0x0602, "EISA bridge", "eisa"}, 1396 { 0x0603, "MC bridge", "mca"}, 1397 { 0x0604, "PCI bridge", "pci-bridge"}, 1398 { 0x0605, "PCMCIA bridge", "pcmcia"}, 1399 { 0x0606, "NUBUS bridge", "nubus"}, 1400 { 0x0607, "CARDBUS bridge", "cardbus"}, 1401 { 0x0608, "RACEWAY bridge"}, 1402 { 0x0680, "Bridge"}, 1403 { 0x0700, "Serial port", "serial"}, 1404 { 0x0701, "Parallel port", "parallel"}, 1405 { 0x0800, "Interrupt controller", "interrupt-controller"}, 1406 { 0x0801, "DMA controller", "dma-controller"}, 1407 { 0x0802, "Timer", "timer"}, 1408 { 0x0803, "RTC", "rtc"}, 1409 { 0x0900, "Keyboard", "keyboard"}, 1410 { 0x0901, "Pen", "pen"}, 1411 { 0x0902, "Mouse", "mouse"}, 1412 { 0x0A00, "Dock station", "dock", 0x00ff}, 1413 { 0x0B00, "i386 cpu", "cpu", 0x00ff}, 1414 { 0x0c00, "Fireware contorller", "fireware"}, 1415 { 0x0c01, "Access bus controller", "access-bus"}, 1416 { 0x0c02, "SSA controller", "ssa"}, 1417 { 0x0c03, "USB controller", "usb"}, 1418 { 0x0c04, "Fibre channel controller", "fibre-channel"}, 1419 { 0x0c05, "SMBus"}, 1420 { 0, NULL} 1421 }; 1422 1423 static void pci_for_each_device_under_bus(PCIBus *bus, 1424 void (*fn)(PCIBus *b, PCIDevice *d, 1425 void *opaque), 1426 void *opaque) 1427 { 1428 PCIDevice *d; 1429 int devfn; 1430 1431 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1432 d = bus->devices[devfn]; 1433 if (d) { 1434 fn(bus, d, opaque); 1435 } 1436 } 1437 } 1438 1439 void pci_for_each_device(PCIBus *bus, int bus_num, 1440 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque), 1441 void *opaque) 1442 { 1443 bus = pci_find_bus_nr(bus, bus_num); 1444 1445 if (bus) { 1446 pci_for_each_device_under_bus(bus, fn, opaque); 1447 } 1448 } 1449 1450 static const pci_class_desc *get_class_desc(int class) 1451 { 1452 const pci_class_desc *desc; 1453 1454 desc = pci_class_descriptions; 1455 while (desc->desc && class != desc->class) { 1456 desc++; 1457 } 1458 1459 return desc; 1460 } 1461 1462 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num); 1463 1464 static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev) 1465 { 1466 PciMemoryRegionList *head = NULL, *cur_item = NULL; 1467 int i; 1468 1469 for (i = 0; i < PCI_NUM_REGIONS; i++) { 1470 const PCIIORegion *r = &dev->io_regions[i]; 1471 PciMemoryRegionList *region; 1472 1473 if (!r->size) { 1474 continue; 1475 } 1476 1477 region = g_malloc0(sizeof(*region)); 1478 region->value = g_malloc0(sizeof(*region->value)); 1479 1480 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { 1481 region->value->type = g_strdup("io"); 1482 } else { 1483 region->value->type = g_strdup("memory"); 1484 region->value->has_prefetch = true; 1485 region->value->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH); 1486 region->value->has_mem_type_64 = true; 1487 region->value->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64); 1488 } 1489 1490 region->value->bar = i; 1491 region->value->address = r->addr; 1492 region->value->size = r->size; 1493 1494 /* XXX: waiting for the qapi to support GSList */ 1495 if (!cur_item) { 1496 head = cur_item = region; 1497 } else { 1498 cur_item->next = region; 1499 cur_item = region; 1500 } 1501 } 1502 1503 return head; 1504 } 1505 1506 static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus, 1507 int bus_num) 1508 { 1509 PciBridgeInfo *info; 1510 PciMemoryRange *range; 1511 1512 info = g_new0(PciBridgeInfo, 1); 1513 1514 info->bus = g_new0(PciBusInfo, 1); 1515 info->bus->number = dev->config[PCI_PRIMARY_BUS]; 1516 info->bus->secondary = dev->config[PCI_SECONDARY_BUS]; 1517 info->bus->subordinate = dev->config[PCI_SUBORDINATE_BUS]; 1518 1519 range = info->bus->io_range = g_new0(PciMemoryRange, 1); 1520 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO); 1521 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO); 1522 1523 range = info->bus->memory_range = g_new0(PciMemoryRange, 1); 1524 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 1525 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 1526 1527 range = info->bus->prefetchable_range = g_new0(PciMemoryRange, 1); 1528 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 1529 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 1530 1531 if (dev->config[PCI_SECONDARY_BUS] != 0) { 1532 PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]); 1533 if (child_bus) { 1534 info->has_devices = true; 1535 info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]); 1536 } 1537 } 1538 1539 return info; 1540 } 1541 1542 static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus, 1543 int bus_num) 1544 { 1545 const pci_class_desc *desc; 1546 PciDeviceInfo *info; 1547 uint8_t type; 1548 int class; 1549 1550 info = g_new0(PciDeviceInfo, 1); 1551 info->bus = bus_num; 1552 info->slot = PCI_SLOT(dev->devfn); 1553 info->function = PCI_FUNC(dev->devfn); 1554 1555 info->class_info = g_new0(PciDeviceClass, 1); 1556 class = pci_get_word(dev->config + PCI_CLASS_DEVICE); 1557 info->class_info->q_class = class; 1558 desc = get_class_desc(class); 1559 if (desc->desc) { 1560 info->class_info->has_desc = true; 1561 info->class_info->desc = g_strdup(desc->desc); 1562 } 1563 1564 info->id = g_new0(PciDeviceId, 1); 1565 info->id->vendor = pci_get_word(dev->config + PCI_VENDOR_ID); 1566 info->id->device = pci_get_word(dev->config + PCI_DEVICE_ID); 1567 info->regions = qmp_query_pci_regions(dev); 1568 info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : ""); 1569 1570 if (dev->config[PCI_INTERRUPT_PIN] != 0) { 1571 info->has_irq = true; 1572 info->irq = dev->config[PCI_INTERRUPT_LINE]; 1573 } 1574 1575 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 1576 if (type == PCI_HEADER_TYPE_BRIDGE) { 1577 info->has_pci_bridge = true; 1578 info->pci_bridge = qmp_query_pci_bridge(dev, bus, bus_num); 1579 } 1580 1581 return info; 1582 } 1583 1584 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num) 1585 { 1586 PciDeviceInfoList *info, *head = NULL, *cur_item = NULL; 1587 PCIDevice *dev; 1588 int devfn; 1589 1590 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1591 dev = bus->devices[devfn]; 1592 if (dev) { 1593 info = g_malloc0(sizeof(*info)); 1594 info->value = qmp_query_pci_device(dev, bus, bus_num); 1595 1596 /* XXX: waiting for the qapi to support GSList */ 1597 if (!cur_item) { 1598 head = cur_item = info; 1599 } else { 1600 cur_item->next = info; 1601 cur_item = info; 1602 } 1603 } 1604 } 1605 1606 return head; 1607 } 1608 1609 static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num) 1610 { 1611 PciInfo *info = NULL; 1612 1613 bus = pci_find_bus_nr(bus, bus_num); 1614 if (bus) { 1615 info = g_malloc0(sizeof(*info)); 1616 info->bus = bus_num; 1617 info->devices = qmp_query_pci_devices(bus, bus_num); 1618 } 1619 1620 return info; 1621 } 1622 1623 PciInfoList *qmp_query_pci(Error **errp) 1624 { 1625 PciInfoList *info, *head = NULL, *cur_item = NULL; 1626 PCIHostState *host_bridge; 1627 1628 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { 1629 info = g_malloc0(sizeof(*info)); 1630 info->value = qmp_query_pci_bus(host_bridge->bus, 1631 pci_bus_num(host_bridge->bus)); 1632 1633 /* XXX: waiting for the qapi to support GSList */ 1634 if (!cur_item) { 1635 head = cur_item = info; 1636 } else { 1637 cur_item->next = info; 1638 cur_item = info; 1639 } 1640 } 1641 1642 return head; 1643 } 1644 1645 static const char * const pci_nic_models[] = { 1646 "ne2k_pci", 1647 "i82551", 1648 "i82557b", 1649 "i82559er", 1650 "rtl8139", 1651 "e1000", 1652 "pcnet", 1653 "virtio", 1654 NULL 1655 }; 1656 1657 static const char * const pci_nic_names[] = { 1658 "ne2k_pci", 1659 "i82551", 1660 "i82557b", 1661 "i82559er", 1662 "rtl8139", 1663 "e1000", 1664 "pcnet", 1665 "virtio-net-pci", 1666 NULL 1667 }; 1668 1669 /* Initialize a PCI NIC. */ 1670 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus, 1671 const char *default_model, 1672 const char *default_devaddr) 1673 { 1674 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr; 1675 Error *err = NULL; 1676 PCIBus *bus; 1677 PCIDevice *pci_dev; 1678 DeviceState *dev; 1679 int devfn; 1680 int i; 1681 1682 if (qemu_show_nic_models(nd->model, pci_nic_models)) { 1683 exit(0); 1684 } 1685 1686 i = qemu_find_nic_model(nd, pci_nic_models, default_model); 1687 if (i < 0) { 1688 exit(1); 1689 } 1690 1691 bus = pci_get_bus_devfn(&devfn, rootbus, devaddr); 1692 if (!bus) { 1693 error_report("Invalid PCI device address %s for device %s", 1694 devaddr, pci_nic_names[i]); 1695 exit(1); 1696 } 1697 1698 pci_dev = pci_create(bus, devfn, pci_nic_names[i]); 1699 dev = &pci_dev->qdev; 1700 qdev_set_nic_properties(dev, nd); 1701 1702 object_property_set_bool(OBJECT(dev), true, "realized", &err); 1703 if (err) { 1704 error_report_err(err); 1705 object_unparent(OBJECT(dev)); 1706 exit(1); 1707 } 1708 1709 return pci_dev; 1710 } 1711 1712 PCIDevice *pci_vga_init(PCIBus *bus) 1713 { 1714 switch (vga_interface_type) { 1715 case VGA_CIRRUS: 1716 return pci_create_simple(bus, -1, "cirrus-vga"); 1717 case VGA_QXL: 1718 return pci_create_simple(bus, -1, "qxl-vga"); 1719 case VGA_STD: 1720 return pci_create_simple(bus, -1, "VGA"); 1721 case VGA_VMWARE: 1722 return pci_create_simple(bus, -1, "vmware-svga"); 1723 case VGA_VIRTIO: 1724 return pci_create_simple(bus, -1, "virtio-vga"); 1725 case VGA_NONE: 1726 default: /* Other non-PCI types. Checking for unsupported types is already 1727 done in vl.c. */ 1728 return NULL; 1729 } 1730 } 1731 1732 /* Whether a given bus number is in range of the secondary 1733 * bus of the given bridge device. */ 1734 static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num) 1735 { 1736 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) & 1737 PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ && 1738 dev->config[PCI_SECONDARY_BUS] <= bus_num && 1739 bus_num <= dev->config[PCI_SUBORDINATE_BUS]; 1740 } 1741 1742 /* Whether a given bus number is in a range of a root bus */ 1743 static bool pci_root_bus_in_range(PCIBus *bus, int bus_num) 1744 { 1745 int i; 1746 1747 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 1748 PCIDevice *dev = bus->devices[i]; 1749 1750 if (dev && PCI_DEVICE_GET_CLASS(dev)->is_bridge) { 1751 if (pci_secondary_bus_in_range(dev, bus_num)) { 1752 return true; 1753 } 1754 } 1755 } 1756 1757 return false; 1758 } 1759 1760 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num) 1761 { 1762 PCIBus *sec; 1763 1764 if (!bus) { 1765 return NULL; 1766 } 1767 1768 if (pci_bus_num(bus) == bus_num) { 1769 return bus; 1770 } 1771 1772 /* Consider all bus numbers in range for the host pci bridge. */ 1773 if (!pci_bus_is_root(bus) && 1774 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) { 1775 return NULL; 1776 } 1777 1778 /* try child bus */ 1779 for (; bus; bus = sec) { 1780 QLIST_FOREACH(sec, &bus->child, sibling) { 1781 if (pci_bus_num(sec) == bus_num) { 1782 return sec; 1783 } 1784 /* PXB buses assumed to be children of bus 0 */ 1785 if (pci_bus_is_root(sec)) { 1786 if (pci_root_bus_in_range(sec, bus_num)) { 1787 break; 1788 } 1789 } else { 1790 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) { 1791 break; 1792 } 1793 } 1794 } 1795 } 1796 1797 return NULL; 1798 } 1799 1800 void pci_for_each_bus_depth_first(PCIBus *bus, 1801 void *(*begin)(PCIBus *bus, void *parent_state), 1802 void (*end)(PCIBus *bus, void *state), 1803 void *parent_state) 1804 { 1805 PCIBus *sec; 1806 void *state; 1807 1808 if (!bus) { 1809 return; 1810 } 1811 1812 if (begin) { 1813 state = begin(bus, parent_state); 1814 } else { 1815 state = parent_state; 1816 } 1817 1818 QLIST_FOREACH(sec, &bus->child, sibling) { 1819 pci_for_each_bus_depth_first(sec, begin, end, state); 1820 } 1821 1822 if (end) { 1823 end(bus, state); 1824 } 1825 } 1826 1827 1828 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn) 1829 { 1830 bus = pci_find_bus_nr(bus, bus_num); 1831 1832 if (!bus) 1833 return NULL; 1834 1835 return bus->devices[devfn]; 1836 } 1837 1838 static void pci_qdev_realize(DeviceState *qdev, Error **errp) 1839 { 1840 PCIDevice *pci_dev = (PCIDevice *)qdev; 1841 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 1842 Error *local_err = NULL; 1843 PCIBus *bus; 1844 bool is_default_rom; 1845 1846 /* initialize cap_present for pci_is_express() and pci_config_size() */ 1847 if (pc->is_express) { 1848 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; 1849 } 1850 1851 bus = PCI_BUS(qdev_get_parent_bus(qdev)); 1852 pci_dev = do_pci_register_device(pci_dev, bus, 1853 object_get_typename(OBJECT(qdev)), 1854 pci_dev->devfn, errp); 1855 if (pci_dev == NULL) 1856 return; 1857 1858 if (pc->realize) { 1859 pc->realize(pci_dev, &local_err); 1860 if (local_err) { 1861 error_propagate(errp, local_err); 1862 do_pci_unregister_device(pci_dev); 1863 return; 1864 } 1865 } 1866 1867 /* rom loading */ 1868 is_default_rom = false; 1869 if (pci_dev->romfile == NULL && pc->romfile != NULL) { 1870 pci_dev->romfile = g_strdup(pc->romfile); 1871 is_default_rom = true; 1872 } 1873 1874 pci_add_option_rom(pci_dev, is_default_rom, &local_err); 1875 if (local_err) { 1876 error_propagate(errp, local_err); 1877 pci_qdev_unrealize(DEVICE(pci_dev), NULL); 1878 return; 1879 } 1880 } 1881 1882 static void pci_default_realize(PCIDevice *dev, Error **errp) 1883 { 1884 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 1885 1886 if (pc->init) { 1887 if (pc->init(dev) < 0) { 1888 error_setg(errp, "Device initialization failed"); 1889 return; 1890 } 1891 } 1892 } 1893 1894 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction, 1895 const char *name) 1896 { 1897 DeviceState *dev; 1898 1899 dev = qdev_create(&bus->qbus, name); 1900 qdev_prop_set_int32(dev, "addr", devfn); 1901 qdev_prop_set_bit(dev, "multifunction", multifunction); 1902 return PCI_DEVICE(dev); 1903 } 1904 1905 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, 1906 bool multifunction, 1907 const char *name) 1908 { 1909 PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name); 1910 qdev_init_nofail(&dev->qdev); 1911 return dev; 1912 } 1913 1914 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name) 1915 { 1916 return pci_create_multifunction(bus, devfn, false, name); 1917 } 1918 1919 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name) 1920 { 1921 return pci_create_simple_multifunction(bus, devfn, false, name); 1922 } 1923 1924 static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size) 1925 { 1926 int offset = PCI_CONFIG_HEADER_SIZE; 1927 int i; 1928 for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) { 1929 if (pdev->used[i]) 1930 offset = i + 1; 1931 else if (i - offset + 1 == size) 1932 return offset; 1933 } 1934 return 0; 1935 } 1936 1937 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id, 1938 uint8_t *prev_p) 1939 { 1940 uint8_t next, prev; 1941 1942 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST)) 1943 return 0; 1944 1945 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); 1946 prev = next + PCI_CAP_LIST_NEXT) 1947 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id) 1948 break; 1949 1950 if (prev_p) 1951 *prev_p = prev; 1952 return next; 1953 } 1954 1955 static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset) 1956 { 1957 uint8_t next, prev, found = 0; 1958 1959 if (!(pdev->used[offset])) { 1960 return 0; 1961 } 1962 1963 assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST); 1964 1965 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); 1966 prev = next + PCI_CAP_LIST_NEXT) { 1967 if (next <= offset && next > found) { 1968 found = next; 1969 } 1970 } 1971 return found; 1972 } 1973 1974 /* Patch the PCI vendor and device ids in a PCI rom image if necessary. 1975 This is needed for an option rom which is used for more than one device. */ 1976 static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size) 1977 { 1978 uint16_t vendor_id; 1979 uint16_t device_id; 1980 uint16_t rom_vendor_id; 1981 uint16_t rom_device_id; 1982 uint16_t rom_magic; 1983 uint16_t pcir_offset; 1984 uint8_t checksum; 1985 1986 /* Words in rom data are little endian (like in PCI configuration), 1987 so they can be read / written with pci_get_word / pci_set_word. */ 1988 1989 /* Only a valid rom will be patched. */ 1990 rom_magic = pci_get_word(ptr); 1991 if (rom_magic != 0xaa55) { 1992 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic); 1993 return; 1994 } 1995 pcir_offset = pci_get_word(ptr + 0x18); 1996 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) { 1997 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset); 1998 return; 1999 } 2000 2001 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID); 2002 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID); 2003 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4); 2004 rom_device_id = pci_get_word(ptr + pcir_offset + 6); 2005 2006 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile, 2007 vendor_id, device_id, rom_vendor_id, rom_device_id); 2008 2009 checksum = ptr[6]; 2010 2011 if (vendor_id != rom_vendor_id) { 2012 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */ 2013 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8); 2014 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8); 2015 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); 2016 ptr[6] = checksum; 2017 pci_set_word(ptr + pcir_offset + 4, vendor_id); 2018 } 2019 2020 if (device_id != rom_device_id) { 2021 /* Patch device id and checksum (at offset 6 for etherboot roms). */ 2022 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8); 2023 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8); 2024 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); 2025 ptr[6] = checksum; 2026 pci_set_word(ptr + pcir_offset + 6, device_id); 2027 } 2028 } 2029 2030 /* Add an option rom for the device */ 2031 static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, 2032 Error **errp) 2033 { 2034 int size; 2035 char *path; 2036 void *ptr; 2037 char name[32]; 2038 const VMStateDescription *vmsd; 2039 2040 if (!pdev->romfile) 2041 return; 2042 if (strlen(pdev->romfile) == 0) 2043 return; 2044 2045 if (!pdev->rom_bar) { 2046 /* 2047 * Load rom via fw_cfg instead of creating a rom bar, 2048 * for 0.11 compatibility. 2049 */ 2050 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE); 2051 2052 /* 2053 * Hot-plugged devices can't use the option ROM 2054 * if the rom bar is disabled. 2055 */ 2056 if (DEVICE(pdev)->hotplugged) { 2057 error_setg(errp, "Hot-plugged device without ROM bar" 2058 " can't have an option ROM"); 2059 return; 2060 } 2061 2062 if (class == 0x0300) { 2063 rom_add_vga(pdev->romfile); 2064 } else { 2065 rom_add_option(pdev->romfile, -1); 2066 } 2067 return; 2068 } 2069 2070 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile); 2071 if (path == NULL) { 2072 path = g_strdup(pdev->romfile); 2073 } 2074 2075 size = get_image_size(path); 2076 if (size < 0) { 2077 error_setg(errp, "failed to find romfile \"%s\"", pdev->romfile); 2078 g_free(path); 2079 return; 2080 } else if (size == 0) { 2081 error_setg(errp, "romfile \"%s\" is empty", pdev->romfile); 2082 g_free(path); 2083 return; 2084 } 2085 size = pow2ceil(size); 2086 2087 vmsd = qdev_get_vmsd(DEVICE(pdev)); 2088 2089 if (vmsd) { 2090 snprintf(name, sizeof(name), "%s.rom", vmsd->name); 2091 } else { 2092 snprintf(name, sizeof(name), "%s.rom", object_get_typename(OBJECT(pdev))); 2093 } 2094 pdev->has_rom = true; 2095 memory_region_init_ram(&pdev->rom, OBJECT(pdev), name, size, &error_fatal); 2096 vmstate_register_ram(&pdev->rom, &pdev->qdev); 2097 ptr = memory_region_get_ram_ptr(&pdev->rom); 2098 load_image(path, ptr); 2099 g_free(path); 2100 2101 if (is_default_rom) { 2102 /* Only the default rom images will be patched (if needed). */ 2103 pci_patch_ids(pdev, ptr, size); 2104 } 2105 2106 pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom); 2107 } 2108 2109 static void pci_del_option_rom(PCIDevice *pdev) 2110 { 2111 if (!pdev->has_rom) 2112 return; 2113 2114 vmstate_unregister_ram(&pdev->rom, &pdev->qdev); 2115 pdev->has_rom = false; 2116 } 2117 2118 /* 2119 * if offset = 0, 2120 * Find and reserve space and add capability to the linked list 2121 * in pci config space 2122 */ 2123 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, 2124 uint8_t offset, uint8_t size) 2125 { 2126 int ret; 2127 Error *local_err = NULL; 2128 2129 ret = pci_add_capability2(pdev, cap_id, offset, size, &local_err); 2130 if (local_err) { 2131 assert(ret < 0); 2132 error_report_err(local_err); 2133 } else { 2134 /* success implies a positive offset in config space */ 2135 assert(ret > 0); 2136 } 2137 return ret; 2138 } 2139 2140 int pci_add_capability2(PCIDevice *pdev, uint8_t cap_id, 2141 uint8_t offset, uint8_t size, 2142 Error **errp) 2143 { 2144 uint8_t *config; 2145 int i, overlapping_cap; 2146 2147 if (!offset) { 2148 offset = pci_find_space(pdev, size); 2149 if (!offset) { 2150 error_setg(errp, "out of PCI config space"); 2151 return -ENOSPC; 2152 } 2153 } else { 2154 /* Verify that capabilities don't overlap. Note: device assignment 2155 * depends on this check to verify that the device is not broken. 2156 * Should never trigger for emulated devices, but it's helpful 2157 * for debugging these. */ 2158 for (i = offset; i < offset + size; i++) { 2159 overlapping_cap = pci_find_capability_at_offset(pdev, i); 2160 if (overlapping_cap) { 2161 error_setg(errp, "%s:%02x:%02x.%x " 2162 "Attempt to add PCI capability %x at offset " 2163 "%x overlaps existing capability %x at offset %x", 2164 pci_root_bus_path(pdev), pci_bus_num(pdev->bus), 2165 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), 2166 cap_id, offset, overlapping_cap, i); 2167 return -EINVAL; 2168 } 2169 } 2170 } 2171 2172 config = pdev->config + offset; 2173 config[PCI_CAP_LIST_ID] = cap_id; 2174 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST]; 2175 pdev->config[PCI_CAPABILITY_LIST] = offset; 2176 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST; 2177 memset(pdev->used + offset, 0xFF, QEMU_ALIGN_UP(size, 4)); 2178 /* Make capability read-only by default */ 2179 memset(pdev->wmask + offset, 0, size); 2180 /* Check capability by default */ 2181 memset(pdev->cmask + offset, 0xFF, size); 2182 return offset; 2183 } 2184 2185 /* Unlink capability from the pci config space. */ 2186 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size) 2187 { 2188 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev); 2189 if (!offset) 2190 return; 2191 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT]; 2192 /* Make capability writable again */ 2193 memset(pdev->wmask + offset, 0xff, size); 2194 memset(pdev->w1cmask + offset, 0, size); 2195 /* Clear cmask as device-specific registers can't be checked */ 2196 memset(pdev->cmask + offset, 0, size); 2197 memset(pdev->used + offset, 0, QEMU_ALIGN_UP(size, 4)); 2198 2199 if (!pdev->config[PCI_CAPABILITY_LIST]) 2200 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST; 2201 } 2202 2203 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id) 2204 { 2205 return pci_find_capability_list(pdev, cap_id, NULL); 2206 } 2207 2208 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent) 2209 { 2210 PCIDevice *d = (PCIDevice *)dev; 2211 const pci_class_desc *desc; 2212 char ctxt[64]; 2213 PCIIORegion *r; 2214 int i, class; 2215 2216 class = pci_get_word(d->config + PCI_CLASS_DEVICE); 2217 desc = pci_class_descriptions; 2218 while (desc->desc && class != desc->class) 2219 desc++; 2220 if (desc->desc) { 2221 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc); 2222 } else { 2223 snprintf(ctxt, sizeof(ctxt), "Class %04x", class); 2224 } 2225 2226 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, " 2227 "pci id %04x:%04x (sub %04x:%04x)\n", 2228 indent, "", ctxt, pci_bus_num(d->bus), 2229 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn), 2230 pci_get_word(d->config + PCI_VENDOR_ID), 2231 pci_get_word(d->config + PCI_DEVICE_ID), 2232 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID), 2233 pci_get_word(d->config + PCI_SUBSYSTEM_ID)); 2234 for (i = 0; i < PCI_NUM_REGIONS; i++) { 2235 r = &d->io_regions[i]; 2236 if (!r->size) 2237 continue; 2238 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS 2239 " [0x%"FMT_PCIBUS"]\n", 2240 indent, "", 2241 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem", 2242 r->addr, r->addr + r->size - 1); 2243 } 2244 } 2245 2246 static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len) 2247 { 2248 PCIDevice *d = (PCIDevice *)dev; 2249 const char *name = NULL; 2250 const pci_class_desc *desc = pci_class_descriptions; 2251 int class = pci_get_word(d->config + PCI_CLASS_DEVICE); 2252 2253 while (desc->desc && 2254 (class & ~desc->fw_ign_bits) != 2255 (desc->class & ~desc->fw_ign_bits)) { 2256 desc++; 2257 } 2258 2259 if (desc->desc) { 2260 name = desc->fw_name; 2261 } 2262 2263 if (name) { 2264 pstrcpy(buf, len, name); 2265 } else { 2266 snprintf(buf, len, "pci%04x,%04x", 2267 pci_get_word(d->config + PCI_VENDOR_ID), 2268 pci_get_word(d->config + PCI_DEVICE_ID)); 2269 } 2270 2271 return buf; 2272 } 2273 2274 static char *pcibus_get_fw_dev_path(DeviceState *dev) 2275 { 2276 PCIDevice *d = (PCIDevice *)dev; 2277 char path[50], name[33]; 2278 int off; 2279 2280 off = snprintf(path, sizeof(path), "%s@%x", 2281 pci_dev_fw_name(dev, name, sizeof name), 2282 PCI_SLOT(d->devfn)); 2283 if (PCI_FUNC(d->devfn)) 2284 snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn)); 2285 return g_strdup(path); 2286 } 2287 2288 static char *pcibus_get_dev_path(DeviceState *dev) 2289 { 2290 PCIDevice *d = container_of(dev, PCIDevice, qdev); 2291 PCIDevice *t; 2292 int slot_depth; 2293 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function. 2294 * 00 is added here to make this format compatible with 2295 * domain:Bus:Slot.Func for systems without nested PCI bridges. 2296 * Slot.Function list specifies the slot and function numbers for all 2297 * devices on the path from root to the specific device. */ 2298 const char *root_bus_path; 2299 int root_bus_len; 2300 char slot[] = ":SS.F"; 2301 int slot_len = sizeof slot - 1 /* For '\0' */; 2302 int path_len; 2303 char *path, *p; 2304 int s; 2305 2306 root_bus_path = pci_root_bus_path(d); 2307 root_bus_len = strlen(root_bus_path); 2308 2309 /* Calculate # of slots on path between device and root. */; 2310 slot_depth = 0; 2311 for (t = d; t; t = t->bus->parent_dev) { 2312 ++slot_depth; 2313 } 2314 2315 path_len = root_bus_len + slot_len * slot_depth; 2316 2317 /* Allocate memory, fill in the terminating null byte. */ 2318 path = g_malloc(path_len + 1 /* For '\0' */); 2319 path[path_len] = '\0'; 2320 2321 memcpy(path, root_bus_path, root_bus_len); 2322 2323 /* Fill in slot numbers. We walk up from device to root, so need to print 2324 * them in the reverse order, last to first. */ 2325 p = path + path_len; 2326 for (t = d; t; t = t->bus->parent_dev) { 2327 p -= slot_len; 2328 s = snprintf(slot, sizeof slot, ":%02x.%x", 2329 PCI_SLOT(t->devfn), PCI_FUNC(t->devfn)); 2330 assert(s == slot_len); 2331 memcpy(p, slot, slot_len); 2332 } 2333 2334 return path; 2335 } 2336 2337 static int pci_qdev_find_recursive(PCIBus *bus, 2338 const char *id, PCIDevice **pdev) 2339 { 2340 DeviceState *qdev = qdev_find_recursive(&bus->qbus, id); 2341 if (!qdev) { 2342 return -ENODEV; 2343 } 2344 2345 /* roughly check if given qdev is pci device */ 2346 if (object_dynamic_cast(OBJECT(qdev), TYPE_PCI_DEVICE)) { 2347 *pdev = PCI_DEVICE(qdev); 2348 return 0; 2349 } 2350 return -EINVAL; 2351 } 2352 2353 int pci_qdev_find_device(const char *id, PCIDevice **pdev) 2354 { 2355 PCIHostState *host_bridge; 2356 int rc = -ENODEV; 2357 2358 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { 2359 int tmp = pci_qdev_find_recursive(host_bridge->bus, id, pdev); 2360 if (!tmp) { 2361 rc = 0; 2362 break; 2363 } 2364 if (tmp != -ENODEV) { 2365 rc = tmp; 2366 } 2367 } 2368 2369 return rc; 2370 } 2371 2372 MemoryRegion *pci_address_space(PCIDevice *dev) 2373 { 2374 return dev->bus->address_space_mem; 2375 } 2376 2377 MemoryRegion *pci_address_space_io(PCIDevice *dev) 2378 { 2379 return dev->bus->address_space_io; 2380 } 2381 2382 static void pci_device_class_init(ObjectClass *klass, void *data) 2383 { 2384 DeviceClass *k = DEVICE_CLASS(klass); 2385 PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass); 2386 2387 k->realize = pci_qdev_realize; 2388 k->unrealize = pci_qdev_unrealize; 2389 k->bus_type = TYPE_PCI_BUS; 2390 k->props = pci_props; 2391 pc->realize = pci_default_realize; 2392 } 2393 2394 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev) 2395 { 2396 PCIBus *bus = PCI_BUS(dev->bus); 2397 PCIBus *iommu_bus = bus; 2398 2399 while(iommu_bus && !iommu_bus->iommu_fn && iommu_bus->parent_dev) { 2400 iommu_bus = PCI_BUS(iommu_bus->parent_dev->bus); 2401 } 2402 if (iommu_bus && iommu_bus->iommu_fn) { 2403 return iommu_bus->iommu_fn(bus, iommu_bus->iommu_opaque, dev->devfn); 2404 } 2405 return &address_space_memory; 2406 } 2407 2408 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque) 2409 { 2410 bus->iommu_fn = fn; 2411 bus->iommu_opaque = opaque; 2412 } 2413 2414 static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque) 2415 { 2416 Range *range = opaque; 2417 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 2418 uint16_t cmd = pci_get_word(dev->config + PCI_COMMAND); 2419 int i; 2420 2421 if (!(cmd & PCI_COMMAND_MEMORY)) { 2422 return; 2423 } 2424 2425 if (pc->is_bridge) { 2426 pcibus_t base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 2427 pcibus_t limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 2428 2429 base = MAX(base, 0x1ULL << 32); 2430 2431 if (limit >= base) { 2432 Range pref_range; 2433 pref_range.begin = base; 2434 pref_range.end = limit + 1; 2435 range_extend(range, &pref_range); 2436 } 2437 } 2438 for (i = 0; i < PCI_NUM_REGIONS; ++i) { 2439 PCIIORegion *r = &dev->io_regions[i]; 2440 Range region_range; 2441 2442 if (!r->size || 2443 (r->type & PCI_BASE_ADDRESS_SPACE_IO) || 2444 !(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64)) { 2445 continue; 2446 } 2447 region_range.begin = pci_bar_address(dev, i, r->type, r->size); 2448 region_range.end = region_range.begin + r->size; 2449 2450 if (region_range.begin == PCI_BAR_UNMAPPED) { 2451 continue; 2452 } 2453 2454 region_range.begin = MAX(region_range.begin, 0x1ULL << 32); 2455 2456 if (region_range.end - 1 >= region_range.begin) { 2457 range_extend(range, ®ion_range); 2458 } 2459 } 2460 } 2461 2462 void pci_bus_get_w64_range(PCIBus *bus, Range *range) 2463 { 2464 range->begin = range->end = 0; 2465 pci_for_each_device_under_bus(bus, pci_dev_get_w64, range); 2466 } 2467 2468 static bool pcie_has_upstream_port(PCIDevice *dev) 2469 { 2470 PCIDevice *parent_dev = pci_bridge_get_device(dev->bus); 2471 2472 /* Device associated with an upstream port. 2473 * As there are several types of these, it's easier to check the 2474 * parent device: upstream ports are always connected to 2475 * root or downstream ports. 2476 */ 2477 return parent_dev && 2478 pci_is_express(parent_dev) && 2479 parent_dev->exp.exp_cap && 2480 (pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_ROOT_PORT || 2481 pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_DOWNSTREAM); 2482 } 2483 2484 PCIDevice *pci_get_function_0(PCIDevice *pci_dev) 2485 { 2486 if(pcie_has_upstream_port(pci_dev)) { 2487 /* With an upstream PCIe port, we only support 1 device at slot 0 */ 2488 return pci_dev->bus->devices[0]; 2489 } else { 2490 /* Other bus types might support multiple devices at slots 0-31 */ 2491 return pci_dev->bus->devices[PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 0)]; 2492 } 2493 } 2494 2495 static const TypeInfo pci_device_type_info = { 2496 .name = TYPE_PCI_DEVICE, 2497 .parent = TYPE_DEVICE, 2498 .instance_size = sizeof(PCIDevice), 2499 .abstract = true, 2500 .class_size = sizeof(PCIDeviceClass), 2501 .class_init = pci_device_class_init, 2502 }; 2503 2504 static void pci_register_types(void) 2505 { 2506 type_register_static(&pci_bus_info); 2507 type_register_static(&pcie_bus_info); 2508 type_register_static(&pci_device_type_info); 2509 } 2510 2511 type_init(pci_register_types) 2512