1 /* 2 * QEMU PCI bus manager 3 * 4 * Copyright (c) 2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/hw.h" 25 #include "hw/pci/pci.h" 26 #include "hw/pci/pci_bridge.h" 27 #include "hw/pci/pci_bus.h" 28 #include "monitor/monitor.h" 29 #include "net/net.h" 30 #include "sysemu/sysemu.h" 31 #include "hw/loader.h" 32 #include "qemu/range.h" 33 #include "qmp-commands.h" 34 #include "hw/pci/msi.h" 35 #include "hw/pci/msix.h" 36 #include "exec/address-spaces.h" 37 38 //#define DEBUG_PCI 39 #ifdef DEBUG_PCI 40 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) 41 #else 42 # define PCI_DPRINTF(format, ...) do { } while (0) 43 #endif 44 45 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent); 46 static char *pcibus_get_dev_path(DeviceState *dev); 47 static char *pcibus_get_fw_dev_path(DeviceState *dev); 48 static int pcibus_reset(BusState *qbus); 49 50 static Property pci_props[] = { 51 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1), 52 DEFINE_PROP_STRING("romfile", PCIDevice, romfile), 53 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1), 54 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present, 55 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false), 56 DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present, 57 QEMU_PCI_CAP_SERR_BITNR, true), 58 DEFINE_PROP_END_OF_LIST() 59 }; 60 61 static void pci_bus_class_init(ObjectClass *klass, void *data) 62 { 63 BusClass *k = BUS_CLASS(klass); 64 65 k->print_dev = pcibus_dev_print; 66 k->get_dev_path = pcibus_get_dev_path; 67 k->get_fw_dev_path = pcibus_get_fw_dev_path; 68 k->reset = pcibus_reset; 69 } 70 71 static const TypeInfo pci_bus_info = { 72 .name = TYPE_PCI_BUS, 73 .parent = TYPE_BUS, 74 .instance_size = sizeof(PCIBus), 75 .class_init = pci_bus_class_init, 76 }; 77 78 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num); 79 static void pci_update_mappings(PCIDevice *d); 80 static void pci_set_irq(void *opaque, int irq_num, int level); 81 static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom); 82 static void pci_del_option_rom(PCIDevice *pdev); 83 84 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET; 85 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU; 86 87 struct PCIHostBus { 88 int domain; 89 struct PCIBus *bus; 90 QLIST_ENTRY(PCIHostBus) next; 91 }; 92 static QLIST_HEAD(, PCIHostBus) host_buses; 93 94 static const VMStateDescription vmstate_pcibus = { 95 .name = "PCIBUS", 96 .version_id = 1, 97 .minimum_version_id = 1, 98 .minimum_version_id_old = 1, 99 .fields = (VMStateField []) { 100 VMSTATE_INT32_EQUAL(nirq, PCIBus), 101 VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t), 102 VMSTATE_END_OF_LIST() 103 } 104 }; 105 static int pci_bar(PCIDevice *d, int reg) 106 { 107 uint8_t type; 108 109 if (reg != PCI_ROM_SLOT) 110 return PCI_BASE_ADDRESS_0 + reg * 4; 111 112 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 113 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS; 114 } 115 116 static inline int pci_irq_state(PCIDevice *d, int irq_num) 117 { 118 return (d->irq_state >> irq_num) & 0x1; 119 } 120 121 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level) 122 { 123 d->irq_state &= ~(0x1 << irq_num); 124 d->irq_state |= level << irq_num; 125 } 126 127 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change) 128 { 129 PCIBus *bus; 130 for (;;) { 131 bus = pci_dev->bus; 132 irq_num = bus->map_irq(pci_dev, irq_num); 133 if (bus->set_irq) 134 break; 135 pci_dev = bus->parent_dev; 136 } 137 bus->irq_count[irq_num] += change; 138 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0); 139 } 140 141 int pci_bus_get_irq_level(PCIBus *bus, int irq_num) 142 { 143 assert(irq_num >= 0); 144 assert(irq_num < bus->nirq); 145 return !!bus->irq_count[irq_num]; 146 } 147 148 /* Update interrupt status bit in config space on interrupt 149 * state change. */ 150 static void pci_update_irq_status(PCIDevice *dev) 151 { 152 if (dev->irq_state) { 153 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT; 154 } else { 155 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; 156 } 157 } 158 159 void pci_device_deassert_intx(PCIDevice *dev) 160 { 161 int i; 162 for (i = 0; i < PCI_NUM_PINS; ++i) { 163 qemu_set_irq(dev->irq[i], 0); 164 } 165 } 166 167 /* 168 * This function is called on #RST and FLR. 169 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set 170 */ 171 void pci_device_reset(PCIDevice *dev) 172 { 173 int r; 174 175 qdev_reset_all(&dev->qdev); 176 177 dev->irq_state = 0; 178 pci_update_irq_status(dev); 179 pci_device_deassert_intx(dev); 180 /* Clear all writable bits */ 181 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND, 182 pci_get_word(dev->wmask + PCI_COMMAND) | 183 pci_get_word(dev->w1cmask + PCI_COMMAND)); 184 pci_word_test_and_clear_mask(dev->config + PCI_STATUS, 185 pci_get_word(dev->wmask + PCI_STATUS) | 186 pci_get_word(dev->w1cmask + PCI_STATUS)); 187 dev->config[PCI_CACHE_LINE_SIZE] = 0x0; 188 dev->config[PCI_INTERRUPT_LINE] = 0x0; 189 for (r = 0; r < PCI_NUM_REGIONS; ++r) { 190 PCIIORegion *region = &dev->io_regions[r]; 191 if (!region->size) { 192 continue; 193 } 194 195 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) && 196 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 197 pci_set_quad(dev->config + pci_bar(dev, r), region->type); 198 } else { 199 pci_set_long(dev->config + pci_bar(dev, r), region->type); 200 } 201 } 202 pci_update_mappings(dev); 203 204 msi_reset(dev); 205 msix_reset(dev); 206 } 207 208 /* 209 * Trigger pci bus reset under a given bus. 210 * To be called on RST# assert. 211 */ 212 void pci_bus_reset(PCIBus *bus) 213 { 214 int i; 215 216 for (i = 0; i < bus->nirq; i++) { 217 bus->irq_count[i] = 0; 218 } 219 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 220 if (bus->devices[i]) { 221 pci_device_reset(bus->devices[i]); 222 } 223 } 224 } 225 226 static int pcibus_reset(BusState *qbus) 227 { 228 pci_bus_reset(DO_UPCAST(PCIBus, qbus, qbus)); 229 230 /* topology traverse is done by pci_bus_reset(). 231 Tell qbus/qdev walker not to traverse the tree */ 232 return 1; 233 } 234 235 static void pci_host_bus_register(int domain, PCIBus *bus) 236 { 237 struct PCIHostBus *host; 238 host = g_malloc0(sizeof(*host)); 239 host->domain = domain; 240 host->bus = bus; 241 QLIST_INSERT_HEAD(&host_buses, host, next); 242 } 243 244 PCIBus *pci_find_root_bus(int domain) 245 { 246 struct PCIHostBus *host; 247 248 QLIST_FOREACH(host, &host_buses, next) { 249 if (host->domain == domain) { 250 return host->bus; 251 } 252 } 253 254 return NULL; 255 } 256 257 int pci_find_domain(const PCIBus *bus) 258 { 259 PCIDevice *d; 260 struct PCIHostBus *host; 261 262 /* obtain root bus */ 263 while ((d = bus->parent_dev) != NULL) { 264 bus = d->bus; 265 } 266 267 QLIST_FOREACH(host, &host_buses, next) { 268 if (host->bus == bus) { 269 return host->domain; 270 } 271 } 272 273 abort(); /* should not be reached */ 274 return -1; 275 } 276 277 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent, 278 const char *name, 279 MemoryRegion *address_space_mem, 280 MemoryRegion *address_space_io, 281 uint8_t devfn_min) 282 { 283 qbus_create_inplace(&bus->qbus, TYPE_PCI_BUS, parent, name); 284 assert(PCI_FUNC(devfn_min) == 0); 285 bus->devfn_min = devfn_min; 286 bus->address_space_mem = address_space_mem; 287 bus->address_space_io = address_space_io; 288 289 /* host bridge */ 290 QLIST_INIT(&bus->child); 291 pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */ 292 293 vmstate_register(NULL, -1, &vmstate_pcibus, bus); 294 } 295 296 PCIBus *pci_bus_new(DeviceState *parent, const char *name, 297 MemoryRegion *address_space_mem, 298 MemoryRegion *address_space_io, 299 uint8_t devfn_min) 300 { 301 PCIBus *bus; 302 303 bus = g_malloc0(sizeof(*bus)); 304 pci_bus_new_inplace(bus, parent, name, address_space_mem, 305 address_space_io, devfn_min); 306 OBJECT(bus)->free = g_free; 307 return bus; 308 } 309 310 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 311 void *irq_opaque, int nirq) 312 { 313 bus->set_irq = set_irq; 314 bus->map_irq = map_irq; 315 bus->irq_opaque = irq_opaque; 316 bus->nirq = nirq; 317 bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0])); 318 } 319 320 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *qdev) 321 { 322 bus->qbus.allow_hotplug = 1; 323 bus->hotplug = hotplug; 324 bus->hotplug_qdev = qdev; 325 } 326 327 PCIBus *pci_register_bus(DeviceState *parent, const char *name, 328 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 329 void *irq_opaque, 330 MemoryRegion *address_space_mem, 331 MemoryRegion *address_space_io, 332 uint8_t devfn_min, int nirq) 333 { 334 PCIBus *bus; 335 336 bus = pci_bus_new(parent, name, address_space_mem, 337 address_space_io, devfn_min); 338 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq); 339 return bus; 340 } 341 342 int pci_bus_num(PCIBus *s) 343 { 344 if (!s->parent_dev) 345 return 0; /* pci host bridge */ 346 return s->parent_dev->config[PCI_SECONDARY_BUS]; 347 } 348 349 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size) 350 { 351 PCIDevice *s = container_of(pv, PCIDevice, config); 352 uint8_t *config; 353 int i; 354 355 assert(size == pci_config_size(s)); 356 config = g_malloc(size); 357 358 qemu_get_buffer(f, config, size); 359 for (i = 0; i < size; ++i) { 360 if ((config[i] ^ s->config[i]) & 361 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) { 362 g_free(config); 363 return -EINVAL; 364 } 365 } 366 memcpy(s->config, config, size); 367 368 pci_update_mappings(s); 369 370 memory_region_set_enabled(&s->bus_master_enable_region, 371 pci_get_word(s->config + PCI_COMMAND) 372 & PCI_COMMAND_MASTER); 373 374 g_free(config); 375 return 0; 376 } 377 378 /* just put buffer */ 379 static void put_pci_config_device(QEMUFile *f, void *pv, size_t size) 380 { 381 const uint8_t **v = pv; 382 assert(size == pci_config_size(container_of(pv, PCIDevice, config))); 383 qemu_put_buffer(f, *v, size); 384 } 385 386 static VMStateInfo vmstate_info_pci_config = { 387 .name = "pci config", 388 .get = get_pci_config_device, 389 .put = put_pci_config_device, 390 }; 391 392 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size) 393 { 394 PCIDevice *s = container_of(pv, PCIDevice, irq_state); 395 uint32_t irq_state[PCI_NUM_PINS]; 396 int i; 397 for (i = 0; i < PCI_NUM_PINS; ++i) { 398 irq_state[i] = qemu_get_be32(f); 399 if (irq_state[i] != 0x1 && irq_state[i] != 0) { 400 fprintf(stderr, "irq state %d: must be 0 or 1.\n", 401 irq_state[i]); 402 return -EINVAL; 403 } 404 } 405 406 for (i = 0; i < PCI_NUM_PINS; ++i) { 407 pci_set_irq_state(s, i, irq_state[i]); 408 } 409 410 return 0; 411 } 412 413 static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size) 414 { 415 int i; 416 PCIDevice *s = container_of(pv, PCIDevice, irq_state); 417 418 for (i = 0; i < PCI_NUM_PINS; ++i) { 419 qemu_put_be32(f, pci_irq_state(s, i)); 420 } 421 } 422 423 static VMStateInfo vmstate_info_pci_irq_state = { 424 .name = "pci irq state", 425 .get = get_pci_irq_state, 426 .put = put_pci_irq_state, 427 }; 428 429 const VMStateDescription vmstate_pci_device = { 430 .name = "PCIDevice", 431 .version_id = 2, 432 .minimum_version_id = 1, 433 .minimum_version_id_old = 1, 434 .fields = (VMStateField []) { 435 VMSTATE_INT32_LE(version_id, PCIDevice), 436 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0, 437 vmstate_info_pci_config, 438 PCI_CONFIG_SPACE_SIZE), 439 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2, 440 vmstate_info_pci_irq_state, 441 PCI_NUM_PINS * sizeof(int32_t)), 442 VMSTATE_END_OF_LIST() 443 } 444 }; 445 446 const VMStateDescription vmstate_pcie_device = { 447 .name = "PCIEDevice", 448 .version_id = 2, 449 .minimum_version_id = 1, 450 .minimum_version_id_old = 1, 451 .fields = (VMStateField []) { 452 VMSTATE_INT32_LE(version_id, PCIDevice), 453 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0, 454 vmstate_info_pci_config, 455 PCIE_CONFIG_SPACE_SIZE), 456 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2, 457 vmstate_info_pci_irq_state, 458 PCI_NUM_PINS * sizeof(int32_t)), 459 VMSTATE_END_OF_LIST() 460 } 461 }; 462 463 static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s) 464 { 465 return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device; 466 } 467 468 void pci_device_save(PCIDevice *s, QEMUFile *f) 469 { 470 /* Clear interrupt status bit: it is implicit 471 * in irq_state which we are saving. 472 * This makes us compatible with old devices 473 * which never set or clear this bit. */ 474 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; 475 vmstate_save_state(f, pci_get_vmstate(s), s); 476 /* Restore the interrupt status bit. */ 477 pci_update_irq_status(s); 478 } 479 480 int pci_device_load(PCIDevice *s, QEMUFile *f) 481 { 482 int ret; 483 ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id); 484 /* Restore the interrupt status bit. */ 485 pci_update_irq_status(s); 486 return ret; 487 } 488 489 static void pci_set_default_subsystem_id(PCIDevice *pci_dev) 490 { 491 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, 492 pci_default_sub_vendor_id); 493 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 494 pci_default_sub_device_id); 495 } 496 497 /* 498 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL 499 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error 500 */ 501 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, 502 unsigned int *slotp, unsigned int *funcp) 503 { 504 const char *p; 505 char *e; 506 unsigned long val; 507 unsigned long dom = 0, bus = 0; 508 unsigned int slot = 0; 509 unsigned int func = 0; 510 511 p = addr; 512 val = strtoul(p, &e, 16); 513 if (e == p) 514 return -1; 515 if (*e == ':') { 516 bus = val; 517 p = e + 1; 518 val = strtoul(p, &e, 16); 519 if (e == p) 520 return -1; 521 if (*e == ':') { 522 dom = bus; 523 bus = val; 524 p = e + 1; 525 val = strtoul(p, &e, 16); 526 if (e == p) 527 return -1; 528 } 529 } 530 531 slot = val; 532 533 if (funcp != NULL) { 534 if (*e != '.') 535 return -1; 536 537 p = e + 1; 538 val = strtoul(p, &e, 16); 539 if (e == p) 540 return -1; 541 542 func = val; 543 } 544 545 /* if funcp == NULL func is 0 */ 546 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7) 547 return -1; 548 549 if (*e) 550 return -1; 551 552 *domp = dom; 553 *busp = bus; 554 *slotp = slot; 555 if (funcp != NULL) 556 *funcp = func; 557 return 0; 558 } 559 560 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp, 561 unsigned *slotp) 562 { 563 /* strip legacy tag */ 564 if (!strncmp(addr, "pci_addr=", 9)) { 565 addr += 9; 566 } 567 if (pci_parse_devaddr(addr, domp, busp, slotp, NULL)) { 568 monitor_printf(mon, "Invalid pci address\n"); 569 return -1; 570 } 571 return 0; 572 } 573 574 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr) 575 { 576 int dom, bus; 577 unsigned slot; 578 579 if (!devaddr) { 580 *devfnp = -1; 581 return pci_find_bus_nr(pci_find_root_bus(0), 0); 582 } 583 584 if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) { 585 return NULL; 586 } 587 588 *devfnp = PCI_DEVFN(slot, 0); 589 return pci_find_bus_nr(pci_find_root_bus(dom), bus); 590 } 591 592 static void pci_init_cmask(PCIDevice *dev) 593 { 594 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff); 595 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff); 596 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST; 597 dev->cmask[PCI_REVISION_ID] = 0xff; 598 dev->cmask[PCI_CLASS_PROG] = 0xff; 599 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff); 600 dev->cmask[PCI_HEADER_TYPE] = 0xff; 601 dev->cmask[PCI_CAPABILITY_LIST] = 0xff; 602 } 603 604 static void pci_init_wmask(PCIDevice *dev) 605 { 606 int config_size = pci_config_size(dev); 607 608 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff; 609 dev->wmask[PCI_INTERRUPT_LINE] = 0xff; 610 pci_set_word(dev->wmask + PCI_COMMAND, 611 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | 612 PCI_COMMAND_INTX_DISABLE); 613 if (dev->cap_present & QEMU_PCI_CAP_SERR) { 614 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR); 615 } 616 617 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff, 618 config_size - PCI_CONFIG_HEADER_SIZE); 619 } 620 621 static void pci_init_w1cmask(PCIDevice *dev) 622 { 623 /* 624 * Note: It's okay to set w1cmask even for readonly bits as 625 * long as their value is hardwired to 0. 626 */ 627 pci_set_word(dev->w1cmask + PCI_STATUS, 628 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT | 629 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT | 630 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY); 631 } 632 633 static void pci_init_mask_bridge(PCIDevice *d) 634 { 635 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and 636 PCI_SEC_LETENCY_TIMER */ 637 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4); 638 639 /* base and limit */ 640 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff; 641 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff; 642 pci_set_word(d->wmask + PCI_MEMORY_BASE, 643 PCI_MEMORY_RANGE_MASK & 0xffff); 644 pci_set_word(d->wmask + PCI_MEMORY_LIMIT, 645 PCI_MEMORY_RANGE_MASK & 0xffff); 646 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE, 647 PCI_PREF_RANGE_MASK & 0xffff); 648 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT, 649 PCI_PREF_RANGE_MASK & 0xffff); 650 651 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */ 652 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8); 653 654 /* Supported memory and i/o types */ 655 d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16; 656 d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16; 657 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE, 658 PCI_PREF_RANGE_TYPE_64); 659 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT, 660 PCI_PREF_RANGE_TYPE_64); 661 662 /* TODO: add this define to pci_regs.h in linux and then in qemu. */ 663 #define PCI_BRIDGE_CTL_VGA_16BIT 0x10 /* VGA 16-bit decode */ 664 #define PCI_BRIDGE_CTL_DISCARD 0x100 /* Primary discard timer */ 665 #define PCI_BRIDGE_CTL_SEC_DISCARD 0x200 /* Secondary discard timer */ 666 #define PCI_BRIDGE_CTL_DISCARD_STATUS 0x400 /* Discard timer status */ 667 #define PCI_BRIDGE_CTL_DISCARD_SERR 0x800 /* Discard timer SERR# enable */ 668 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 669 PCI_BRIDGE_CTL_PARITY | 670 PCI_BRIDGE_CTL_SERR | 671 PCI_BRIDGE_CTL_ISA | 672 PCI_BRIDGE_CTL_VGA | 673 PCI_BRIDGE_CTL_VGA_16BIT | 674 PCI_BRIDGE_CTL_MASTER_ABORT | 675 PCI_BRIDGE_CTL_BUS_RESET | 676 PCI_BRIDGE_CTL_FAST_BACK | 677 PCI_BRIDGE_CTL_DISCARD | 678 PCI_BRIDGE_CTL_SEC_DISCARD | 679 PCI_BRIDGE_CTL_DISCARD_SERR); 680 /* Below does not do anything as we never set this bit, put here for 681 * completeness. */ 682 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL, 683 PCI_BRIDGE_CTL_DISCARD_STATUS); 684 d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK; 685 d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK; 686 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE, 687 PCI_PREF_RANGE_TYPE_MASK); 688 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT, 689 PCI_PREF_RANGE_TYPE_MASK); 690 } 691 692 static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev) 693 { 694 uint8_t slot = PCI_SLOT(dev->devfn); 695 uint8_t func; 696 697 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 698 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION; 699 } 700 701 /* 702 * multifunction bit is interpreted in two ways as follows. 703 * - all functions must set the bit to 1. 704 * Example: Intel X53 705 * - function 0 must set the bit, but the rest function (> 0) 706 * is allowed to leave the bit to 0. 707 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10, 708 * 709 * So OS (at least Linux) checks the bit of only function 0, 710 * and doesn't see the bit of function > 0. 711 * 712 * The below check allows both interpretation. 713 */ 714 if (PCI_FUNC(dev->devfn)) { 715 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)]; 716 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) { 717 /* function 0 should set multifunction bit */ 718 error_report("PCI: single function device can't be populated " 719 "in function %x.%x", slot, PCI_FUNC(dev->devfn)); 720 return -1; 721 } 722 return 0; 723 } 724 725 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 726 return 0; 727 } 728 /* function 0 indicates single function, so function > 0 must be NULL */ 729 for (func = 1; func < PCI_FUNC_MAX; ++func) { 730 if (bus->devices[PCI_DEVFN(slot, func)]) { 731 error_report("PCI: %x.0 indicates single function, " 732 "but %x.%x is already populated.", 733 slot, slot, func); 734 return -1; 735 } 736 } 737 return 0; 738 } 739 740 static void pci_config_alloc(PCIDevice *pci_dev) 741 { 742 int config_size = pci_config_size(pci_dev); 743 744 pci_dev->config = g_malloc0(config_size); 745 pci_dev->cmask = g_malloc0(config_size); 746 pci_dev->wmask = g_malloc0(config_size); 747 pci_dev->w1cmask = g_malloc0(config_size); 748 pci_dev->used = g_malloc0(config_size); 749 } 750 751 static void pci_config_free(PCIDevice *pci_dev) 752 { 753 g_free(pci_dev->config); 754 g_free(pci_dev->cmask); 755 g_free(pci_dev->wmask); 756 g_free(pci_dev->w1cmask); 757 g_free(pci_dev->used); 758 } 759 760 /* -1 for devfn means auto assign */ 761 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus, 762 const char *name, int devfn) 763 { 764 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 765 PCIConfigReadFunc *config_read = pc->config_read; 766 PCIConfigWriteFunc *config_write = pc->config_write; 767 768 if (devfn < 0) { 769 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices); 770 devfn += PCI_FUNC_MAX) { 771 if (!bus->devices[devfn]) 772 goto found; 773 } 774 error_report("PCI: no slot/function available for %s, all in use", name); 775 return NULL; 776 found: ; 777 } else if (bus->devices[devfn]) { 778 error_report("PCI: slot %d function %d not available for %s, in use by %s", 779 PCI_SLOT(devfn), PCI_FUNC(devfn), name, bus->devices[devfn]->name); 780 return NULL; 781 } 782 pci_dev->bus = bus; 783 if (bus->dma_context_fn) { 784 pci_dev->dma = bus->dma_context_fn(bus, bus->dma_context_opaque, devfn); 785 } else { 786 /* FIXME: Make dma_context_fn use MemoryRegions instead, so this path is 787 * taken unconditionally */ 788 /* FIXME: inherit memory region from bus creator */ 789 memory_region_init_alias(&pci_dev->bus_master_enable_region, "bus master", 790 get_system_memory(), 0, 791 memory_region_size(get_system_memory())); 792 memory_region_set_enabled(&pci_dev->bus_master_enable_region, false); 793 address_space_init(&pci_dev->bus_master_as, &pci_dev->bus_master_enable_region); 794 pci_dev->dma = g_new(DMAContext, 1); 795 dma_context_init(pci_dev->dma, &pci_dev->bus_master_as, NULL, NULL, NULL); 796 } 797 pci_dev->devfn = devfn; 798 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name); 799 pci_dev->irq_state = 0; 800 pci_config_alloc(pci_dev); 801 802 pci_config_set_vendor_id(pci_dev->config, pc->vendor_id); 803 pci_config_set_device_id(pci_dev->config, pc->device_id); 804 pci_config_set_revision(pci_dev->config, pc->revision); 805 pci_config_set_class(pci_dev->config, pc->class_id); 806 807 if (!pc->is_bridge) { 808 if (pc->subsystem_vendor_id || pc->subsystem_id) { 809 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, 810 pc->subsystem_vendor_id); 811 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 812 pc->subsystem_id); 813 } else { 814 pci_set_default_subsystem_id(pci_dev); 815 } 816 } else { 817 /* subsystem_vendor_id/subsystem_id are only for header type 0 */ 818 assert(!pc->subsystem_vendor_id); 819 assert(!pc->subsystem_id); 820 } 821 pci_init_cmask(pci_dev); 822 pci_init_wmask(pci_dev); 823 pci_init_w1cmask(pci_dev); 824 if (pc->is_bridge) { 825 pci_init_mask_bridge(pci_dev); 826 } 827 if (pci_init_multifunction(bus, pci_dev)) { 828 pci_config_free(pci_dev); 829 return NULL; 830 } 831 832 if (!config_read) 833 config_read = pci_default_read_config; 834 if (!config_write) 835 config_write = pci_default_write_config; 836 pci_dev->config_read = config_read; 837 pci_dev->config_write = config_write; 838 bus->devices[devfn] = pci_dev; 839 pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS); 840 pci_dev->version_id = 2; /* Current pci device vmstate version */ 841 return pci_dev; 842 } 843 844 static void do_pci_unregister_device(PCIDevice *pci_dev) 845 { 846 qemu_free_irqs(pci_dev->irq); 847 pci_dev->bus->devices[pci_dev->devfn] = NULL; 848 pci_config_free(pci_dev); 849 850 if (!pci_dev->bus->dma_context_fn) { 851 address_space_destroy(&pci_dev->bus_master_as); 852 memory_region_destroy(&pci_dev->bus_master_enable_region); 853 g_free(pci_dev->dma); 854 pci_dev->dma = NULL; 855 } 856 } 857 858 static void pci_unregister_io_regions(PCIDevice *pci_dev) 859 { 860 PCIIORegion *r; 861 int i; 862 863 for(i = 0; i < PCI_NUM_REGIONS; i++) { 864 r = &pci_dev->io_regions[i]; 865 if (!r->size || r->addr == PCI_BAR_UNMAPPED) 866 continue; 867 memory_region_del_subregion(r->address_space, r->memory); 868 } 869 } 870 871 static int pci_unregister_device(DeviceState *dev) 872 { 873 PCIDevice *pci_dev = PCI_DEVICE(dev); 874 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 875 876 pci_unregister_io_regions(pci_dev); 877 pci_del_option_rom(pci_dev); 878 879 if (pc->exit) { 880 pc->exit(pci_dev); 881 } 882 883 do_pci_unregister_device(pci_dev); 884 return 0; 885 } 886 887 void pci_register_bar(PCIDevice *pci_dev, int region_num, 888 uint8_t type, MemoryRegion *memory) 889 { 890 PCIIORegion *r; 891 uint32_t addr; 892 uint64_t wmask; 893 pcibus_t size = memory_region_size(memory); 894 895 assert(region_num >= 0); 896 assert(region_num < PCI_NUM_REGIONS); 897 if (size & (size-1)) { 898 fprintf(stderr, "ERROR: PCI region size must be pow2 " 899 "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size); 900 exit(1); 901 } 902 903 r = &pci_dev->io_regions[region_num]; 904 r->addr = PCI_BAR_UNMAPPED; 905 r->size = size; 906 r->type = type; 907 r->memory = NULL; 908 909 wmask = ~(size - 1); 910 addr = pci_bar(pci_dev, region_num); 911 if (region_num == PCI_ROM_SLOT) { 912 /* ROM enable bit is writable */ 913 wmask |= PCI_ROM_ADDRESS_ENABLE; 914 } 915 pci_set_long(pci_dev->config + addr, type); 916 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) && 917 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 918 pci_set_quad(pci_dev->wmask + addr, wmask); 919 pci_set_quad(pci_dev->cmask + addr, ~0ULL); 920 } else { 921 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff); 922 pci_set_long(pci_dev->cmask + addr, 0xffffffff); 923 } 924 pci_dev->io_regions[region_num].memory = memory; 925 pci_dev->io_regions[region_num].address_space 926 = type & PCI_BASE_ADDRESS_SPACE_IO 927 ? pci_dev->bus->address_space_io 928 : pci_dev->bus->address_space_mem; 929 } 930 931 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num) 932 { 933 return pci_dev->io_regions[region_num].addr; 934 } 935 936 static pcibus_t pci_bar_address(PCIDevice *d, 937 int reg, uint8_t type, pcibus_t size) 938 { 939 pcibus_t new_addr, last_addr; 940 int bar = pci_bar(d, reg); 941 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND); 942 943 if (type & PCI_BASE_ADDRESS_SPACE_IO) { 944 if (!(cmd & PCI_COMMAND_IO)) { 945 return PCI_BAR_UNMAPPED; 946 } 947 new_addr = pci_get_long(d->config + bar) & ~(size - 1); 948 last_addr = new_addr + size - 1; 949 /* NOTE: we have only 64K ioports on PC */ 950 if (last_addr <= new_addr || new_addr == 0 || last_addr > UINT16_MAX) { 951 return PCI_BAR_UNMAPPED; 952 } 953 return new_addr; 954 } 955 956 if (!(cmd & PCI_COMMAND_MEMORY)) { 957 return PCI_BAR_UNMAPPED; 958 } 959 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 960 new_addr = pci_get_quad(d->config + bar); 961 } else { 962 new_addr = pci_get_long(d->config + bar); 963 } 964 /* the ROM slot has a specific enable bit */ 965 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) { 966 return PCI_BAR_UNMAPPED; 967 } 968 new_addr &= ~(size - 1); 969 last_addr = new_addr + size - 1; 970 /* NOTE: we do not support wrapping */ 971 /* XXX: as we cannot support really dynamic 972 mappings, we handle specific values as invalid 973 mappings. */ 974 if (last_addr <= new_addr || new_addr == 0 || 975 last_addr == PCI_BAR_UNMAPPED) { 976 return PCI_BAR_UNMAPPED; 977 } 978 979 /* Now pcibus_t is 64bit. 980 * Check if 32 bit BAR wraps around explicitly. 981 * Without this, PC ide doesn't work well. 982 * TODO: remove this work around. 983 */ 984 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) { 985 return PCI_BAR_UNMAPPED; 986 } 987 988 /* 989 * OS is allowed to set BAR beyond its addressable 990 * bits. For example, 32 bit OS can set 64bit bar 991 * to >4G. Check it. TODO: we might need to support 992 * it in the future for e.g. PAE. 993 */ 994 if (last_addr >= HWADDR_MAX) { 995 return PCI_BAR_UNMAPPED; 996 } 997 998 return new_addr; 999 } 1000 1001 static void pci_update_mappings(PCIDevice *d) 1002 { 1003 PCIIORegion *r; 1004 int i; 1005 pcibus_t new_addr; 1006 1007 for(i = 0; i < PCI_NUM_REGIONS; i++) { 1008 r = &d->io_regions[i]; 1009 1010 /* this region isn't registered */ 1011 if (!r->size) 1012 continue; 1013 1014 new_addr = pci_bar_address(d, i, r->type, r->size); 1015 1016 /* This bar isn't changed */ 1017 if (new_addr == r->addr) 1018 continue; 1019 1020 /* now do the real mapping */ 1021 if (r->addr != PCI_BAR_UNMAPPED) { 1022 memory_region_del_subregion(r->address_space, r->memory); 1023 } 1024 r->addr = new_addr; 1025 if (r->addr != PCI_BAR_UNMAPPED) { 1026 memory_region_add_subregion_overlap(r->address_space, 1027 r->addr, r->memory, 1); 1028 } 1029 } 1030 } 1031 1032 static inline int pci_irq_disabled(PCIDevice *d) 1033 { 1034 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE; 1035 } 1036 1037 /* Called after interrupt disabled field update in config space, 1038 * assert/deassert interrupts if necessary. 1039 * Gets original interrupt disable bit value (before update). */ 1040 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled) 1041 { 1042 int i, disabled = pci_irq_disabled(d); 1043 if (disabled == was_irq_disabled) 1044 return; 1045 for (i = 0; i < PCI_NUM_PINS; ++i) { 1046 int state = pci_irq_state(d, i); 1047 pci_change_irq_level(d, i, disabled ? -state : state); 1048 } 1049 } 1050 1051 uint32_t pci_default_read_config(PCIDevice *d, 1052 uint32_t address, int len) 1053 { 1054 uint32_t val = 0; 1055 1056 memcpy(&val, d->config + address, len); 1057 return le32_to_cpu(val); 1058 } 1059 1060 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l) 1061 { 1062 int i, was_irq_disabled = pci_irq_disabled(d); 1063 1064 for (i = 0; i < l; val >>= 8, ++i) { 1065 uint8_t wmask = d->wmask[addr + i]; 1066 uint8_t w1cmask = d->w1cmask[addr + i]; 1067 assert(!(wmask & w1cmask)); 1068 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask); 1069 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */ 1070 } 1071 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) || 1072 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) || 1073 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) || 1074 range_covers_byte(addr, l, PCI_COMMAND)) 1075 pci_update_mappings(d); 1076 1077 if (range_covers_byte(addr, l, PCI_COMMAND)) { 1078 pci_update_irq_disabled(d, was_irq_disabled); 1079 memory_region_set_enabled(&d->bus_master_enable_region, 1080 pci_get_word(d->config + PCI_COMMAND) 1081 & PCI_COMMAND_MASTER); 1082 } 1083 1084 msi_write_config(d, addr, val, l); 1085 msix_write_config(d, addr, val, l); 1086 } 1087 1088 /***********************************************************/ 1089 /* generic PCI irq support */ 1090 1091 /* 0 <= irq_num <= 3. level must be 0 or 1 */ 1092 static void pci_set_irq(void *opaque, int irq_num, int level) 1093 { 1094 PCIDevice *pci_dev = opaque; 1095 int change; 1096 1097 change = level - pci_irq_state(pci_dev, irq_num); 1098 if (!change) 1099 return; 1100 1101 pci_set_irq_state(pci_dev, irq_num, level); 1102 pci_update_irq_status(pci_dev); 1103 if (pci_irq_disabled(pci_dev)) 1104 return; 1105 pci_change_irq_level(pci_dev, irq_num, change); 1106 } 1107 1108 /* Special hooks used by device assignment */ 1109 void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq) 1110 { 1111 assert(!bus->parent_dev); 1112 bus->route_intx_to_irq = route_intx_to_irq; 1113 } 1114 1115 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin) 1116 { 1117 PCIBus *bus; 1118 1119 do { 1120 bus = dev->bus; 1121 pin = bus->map_irq(dev, pin); 1122 dev = bus->parent_dev; 1123 } while (dev); 1124 1125 if (!bus->route_intx_to_irq) { 1126 error_report("PCI: Bug - unimplemented PCI INTx routing (%s)\n", 1127 object_get_typename(OBJECT(bus->qbus.parent))); 1128 return (PCIINTxRoute) { PCI_INTX_DISABLED, -1 }; 1129 } 1130 1131 return bus->route_intx_to_irq(bus->irq_opaque, pin); 1132 } 1133 1134 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new) 1135 { 1136 return old->mode != new->mode || old->irq != new->irq; 1137 } 1138 1139 void pci_bus_fire_intx_routing_notifier(PCIBus *bus) 1140 { 1141 PCIDevice *dev; 1142 PCIBus *sec; 1143 int i; 1144 1145 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 1146 dev = bus->devices[i]; 1147 if (dev && dev->intx_routing_notifier) { 1148 dev->intx_routing_notifier(dev); 1149 } 1150 QLIST_FOREACH(sec, &bus->child, sibling) { 1151 pci_bus_fire_intx_routing_notifier(sec); 1152 } 1153 } 1154 } 1155 1156 void pci_device_set_intx_routing_notifier(PCIDevice *dev, 1157 PCIINTxRoutingNotifier notifier) 1158 { 1159 dev->intx_routing_notifier = notifier; 1160 } 1161 1162 /* 1163 * PCI-to-PCI bridge specification 1164 * 9.1: Interrupt routing. Table 9-1 1165 * 1166 * the PCI Express Base Specification, Revision 2.1 1167 * 2.2.8.1: INTx interrutp signaling - Rules 1168 * the Implementation Note 1169 * Table 2-20 1170 */ 1171 /* 1172 * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD 1173 * 0-origin unlike PCI interrupt pin register. 1174 */ 1175 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin) 1176 { 1177 return (pin + PCI_SLOT(pci_dev->devfn)) % PCI_NUM_PINS; 1178 } 1179 1180 /***********************************************************/ 1181 /* monitor info on PCI */ 1182 1183 typedef struct { 1184 uint16_t class; 1185 const char *desc; 1186 const char *fw_name; 1187 uint16_t fw_ign_bits; 1188 } pci_class_desc; 1189 1190 static const pci_class_desc pci_class_descriptions[] = 1191 { 1192 { 0x0001, "VGA controller", "display"}, 1193 { 0x0100, "SCSI controller", "scsi"}, 1194 { 0x0101, "IDE controller", "ide"}, 1195 { 0x0102, "Floppy controller", "fdc"}, 1196 { 0x0103, "IPI controller", "ipi"}, 1197 { 0x0104, "RAID controller", "raid"}, 1198 { 0x0106, "SATA controller"}, 1199 { 0x0107, "SAS controller"}, 1200 { 0x0180, "Storage controller"}, 1201 { 0x0200, "Ethernet controller", "ethernet"}, 1202 { 0x0201, "Token Ring controller", "token-ring"}, 1203 { 0x0202, "FDDI controller", "fddi"}, 1204 { 0x0203, "ATM controller", "atm"}, 1205 { 0x0280, "Network controller"}, 1206 { 0x0300, "VGA controller", "display", 0x00ff}, 1207 { 0x0301, "XGA controller"}, 1208 { 0x0302, "3D controller"}, 1209 { 0x0380, "Display controller"}, 1210 { 0x0400, "Video controller", "video"}, 1211 { 0x0401, "Audio controller", "sound"}, 1212 { 0x0402, "Phone"}, 1213 { 0x0403, "Audio controller", "sound"}, 1214 { 0x0480, "Multimedia controller"}, 1215 { 0x0500, "RAM controller", "memory"}, 1216 { 0x0501, "Flash controller", "flash"}, 1217 { 0x0580, "Memory controller"}, 1218 { 0x0600, "Host bridge", "host"}, 1219 { 0x0601, "ISA bridge", "isa"}, 1220 { 0x0602, "EISA bridge", "eisa"}, 1221 { 0x0603, "MC bridge", "mca"}, 1222 { 0x0604, "PCI bridge", "pci"}, 1223 { 0x0605, "PCMCIA bridge", "pcmcia"}, 1224 { 0x0606, "NUBUS bridge", "nubus"}, 1225 { 0x0607, "CARDBUS bridge", "cardbus"}, 1226 { 0x0608, "RACEWAY bridge"}, 1227 { 0x0680, "Bridge"}, 1228 { 0x0700, "Serial port", "serial"}, 1229 { 0x0701, "Parallel port", "parallel"}, 1230 { 0x0800, "Interrupt controller", "interrupt-controller"}, 1231 { 0x0801, "DMA controller", "dma-controller"}, 1232 { 0x0802, "Timer", "timer"}, 1233 { 0x0803, "RTC", "rtc"}, 1234 { 0x0900, "Keyboard", "keyboard"}, 1235 { 0x0901, "Pen", "pen"}, 1236 { 0x0902, "Mouse", "mouse"}, 1237 { 0x0A00, "Dock station", "dock", 0x00ff}, 1238 { 0x0B00, "i386 cpu", "cpu", 0x00ff}, 1239 { 0x0c00, "Fireware contorller", "fireware"}, 1240 { 0x0c01, "Access bus controller", "access-bus"}, 1241 { 0x0c02, "SSA controller", "ssa"}, 1242 { 0x0c03, "USB controller", "usb"}, 1243 { 0x0c04, "Fibre channel controller", "fibre-channel"}, 1244 { 0x0c05, "SMBus"}, 1245 { 0, NULL} 1246 }; 1247 1248 static void pci_for_each_device_under_bus(PCIBus *bus, 1249 void (*fn)(PCIBus *b, PCIDevice *d, 1250 void *opaque), 1251 void *opaque) 1252 { 1253 PCIDevice *d; 1254 int devfn; 1255 1256 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1257 d = bus->devices[devfn]; 1258 if (d) { 1259 fn(bus, d, opaque); 1260 } 1261 } 1262 } 1263 1264 void pci_for_each_device(PCIBus *bus, int bus_num, 1265 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque), 1266 void *opaque) 1267 { 1268 bus = pci_find_bus_nr(bus, bus_num); 1269 1270 if (bus) { 1271 pci_for_each_device_under_bus(bus, fn, opaque); 1272 } 1273 } 1274 1275 static const pci_class_desc *get_class_desc(int class) 1276 { 1277 const pci_class_desc *desc; 1278 1279 desc = pci_class_descriptions; 1280 while (desc->desc && class != desc->class) { 1281 desc++; 1282 } 1283 1284 return desc; 1285 } 1286 1287 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num); 1288 1289 static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev) 1290 { 1291 PciMemoryRegionList *head = NULL, *cur_item = NULL; 1292 int i; 1293 1294 for (i = 0; i < PCI_NUM_REGIONS; i++) { 1295 const PCIIORegion *r = &dev->io_regions[i]; 1296 PciMemoryRegionList *region; 1297 1298 if (!r->size) { 1299 continue; 1300 } 1301 1302 region = g_malloc0(sizeof(*region)); 1303 region->value = g_malloc0(sizeof(*region->value)); 1304 1305 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { 1306 region->value->type = g_strdup("io"); 1307 } else { 1308 region->value->type = g_strdup("memory"); 1309 region->value->has_prefetch = true; 1310 region->value->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH); 1311 region->value->has_mem_type_64 = true; 1312 region->value->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64); 1313 } 1314 1315 region->value->bar = i; 1316 region->value->address = r->addr; 1317 region->value->size = r->size; 1318 1319 /* XXX: waiting for the qapi to support GSList */ 1320 if (!cur_item) { 1321 head = cur_item = region; 1322 } else { 1323 cur_item->next = region; 1324 cur_item = region; 1325 } 1326 } 1327 1328 return head; 1329 } 1330 1331 static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus, 1332 int bus_num) 1333 { 1334 PciBridgeInfo *info; 1335 1336 info = g_malloc0(sizeof(*info)); 1337 1338 info->bus.number = dev->config[PCI_PRIMARY_BUS]; 1339 info->bus.secondary = dev->config[PCI_SECONDARY_BUS]; 1340 info->bus.subordinate = dev->config[PCI_SUBORDINATE_BUS]; 1341 1342 info->bus.io_range = g_malloc0(sizeof(*info->bus.io_range)); 1343 info->bus.io_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO); 1344 info->bus.io_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO); 1345 1346 info->bus.memory_range = g_malloc0(sizeof(*info->bus.memory_range)); 1347 info->bus.memory_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 1348 info->bus.memory_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 1349 1350 info->bus.prefetchable_range = g_malloc0(sizeof(*info->bus.prefetchable_range)); 1351 info->bus.prefetchable_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 1352 info->bus.prefetchable_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 1353 1354 if (dev->config[PCI_SECONDARY_BUS] != 0) { 1355 PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]); 1356 if (child_bus) { 1357 info->has_devices = true; 1358 info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]); 1359 } 1360 } 1361 1362 return info; 1363 } 1364 1365 static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus, 1366 int bus_num) 1367 { 1368 const pci_class_desc *desc; 1369 PciDeviceInfo *info; 1370 uint8_t type; 1371 int class; 1372 1373 info = g_malloc0(sizeof(*info)); 1374 info->bus = bus_num; 1375 info->slot = PCI_SLOT(dev->devfn); 1376 info->function = PCI_FUNC(dev->devfn); 1377 1378 class = pci_get_word(dev->config + PCI_CLASS_DEVICE); 1379 info->class_info.class = class; 1380 desc = get_class_desc(class); 1381 if (desc->desc) { 1382 info->class_info.has_desc = true; 1383 info->class_info.desc = g_strdup(desc->desc); 1384 } 1385 1386 info->id.vendor = pci_get_word(dev->config + PCI_VENDOR_ID); 1387 info->id.device = pci_get_word(dev->config + PCI_DEVICE_ID); 1388 info->regions = qmp_query_pci_regions(dev); 1389 info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : ""); 1390 1391 if (dev->config[PCI_INTERRUPT_PIN] != 0) { 1392 info->has_irq = true; 1393 info->irq = dev->config[PCI_INTERRUPT_LINE]; 1394 } 1395 1396 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 1397 if (type == PCI_HEADER_TYPE_BRIDGE) { 1398 info->has_pci_bridge = true; 1399 info->pci_bridge = qmp_query_pci_bridge(dev, bus, bus_num); 1400 } 1401 1402 return info; 1403 } 1404 1405 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num) 1406 { 1407 PciDeviceInfoList *info, *head = NULL, *cur_item = NULL; 1408 PCIDevice *dev; 1409 int devfn; 1410 1411 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1412 dev = bus->devices[devfn]; 1413 if (dev) { 1414 info = g_malloc0(sizeof(*info)); 1415 info->value = qmp_query_pci_device(dev, bus, bus_num); 1416 1417 /* XXX: waiting for the qapi to support GSList */ 1418 if (!cur_item) { 1419 head = cur_item = info; 1420 } else { 1421 cur_item->next = info; 1422 cur_item = info; 1423 } 1424 } 1425 } 1426 1427 return head; 1428 } 1429 1430 static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num) 1431 { 1432 PciInfo *info = NULL; 1433 1434 bus = pci_find_bus_nr(bus, bus_num); 1435 if (bus) { 1436 info = g_malloc0(sizeof(*info)); 1437 info->bus = bus_num; 1438 info->devices = qmp_query_pci_devices(bus, bus_num); 1439 } 1440 1441 return info; 1442 } 1443 1444 PciInfoList *qmp_query_pci(Error **errp) 1445 { 1446 PciInfoList *info, *head = NULL, *cur_item = NULL; 1447 struct PCIHostBus *host; 1448 1449 QLIST_FOREACH(host, &host_buses, next) { 1450 info = g_malloc0(sizeof(*info)); 1451 info->value = qmp_query_pci_bus(host->bus, 0); 1452 1453 /* XXX: waiting for the qapi to support GSList */ 1454 if (!cur_item) { 1455 head = cur_item = info; 1456 } else { 1457 cur_item->next = info; 1458 cur_item = info; 1459 } 1460 } 1461 1462 return head; 1463 } 1464 1465 static const char * const pci_nic_models[] = { 1466 "ne2k_pci", 1467 "i82551", 1468 "i82557b", 1469 "i82559er", 1470 "rtl8139", 1471 "e1000", 1472 "pcnet", 1473 "virtio", 1474 NULL 1475 }; 1476 1477 static const char * const pci_nic_names[] = { 1478 "ne2k_pci", 1479 "i82551", 1480 "i82557b", 1481 "i82559er", 1482 "rtl8139", 1483 "e1000", 1484 "pcnet", 1485 "virtio-net-pci", 1486 NULL 1487 }; 1488 1489 /* Initialize a PCI NIC. */ 1490 /* FIXME callers should check for failure, but don't */ 1491 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model, 1492 const char *default_devaddr) 1493 { 1494 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr; 1495 PCIBus *bus; 1496 int devfn; 1497 PCIDevice *pci_dev; 1498 DeviceState *dev; 1499 int i; 1500 1501 i = qemu_find_nic_model(nd, pci_nic_models, default_model); 1502 if (i < 0) 1503 return NULL; 1504 1505 bus = pci_get_bus_devfn(&devfn, devaddr); 1506 if (!bus) { 1507 error_report("Invalid PCI device address %s for device %s", 1508 devaddr, pci_nic_names[i]); 1509 return NULL; 1510 } 1511 1512 pci_dev = pci_create(bus, devfn, pci_nic_names[i]); 1513 dev = &pci_dev->qdev; 1514 qdev_set_nic_properties(dev, nd); 1515 if (qdev_init(dev) < 0) 1516 return NULL; 1517 return pci_dev; 1518 } 1519 1520 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model, 1521 const char *default_devaddr) 1522 { 1523 PCIDevice *res; 1524 1525 if (qemu_show_nic_models(nd->model, pci_nic_models)) 1526 exit(0); 1527 1528 res = pci_nic_init(nd, default_model, default_devaddr); 1529 if (!res) 1530 exit(1); 1531 return res; 1532 } 1533 1534 PCIDevice *pci_vga_init(PCIBus *bus) 1535 { 1536 switch (vga_interface_type) { 1537 case VGA_CIRRUS: 1538 return pci_create_simple(bus, -1, "cirrus-vga"); 1539 case VGA_QXL: 1540 return pci_create_simple(bus, -1, "qxl-vga"); 1541 case VGA_STD: 1542 return pci_create_simple(bus, -1, "VGA"); 1543 case VGA_VMWARE: 1544 return pci_create_simple(bus, -1, "vmware-svga"); 1545 case VGA_NONE: 1546 default: /* Other non-PCI types. Checking for unsupported types is already 1547 done in vl.c. */ 1548 return NULL; 1549 } 1550 } 1551 1552 /* Whether a given bus number is in range of the secondary 1553 * bus of the given bridge device. */ 1554 static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num) 1555 { 1556 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) & 1557 PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ && 1558 dev->config[PCI_SECONDARY_BUS] < bus_num && 1559 bus_num <= dev->config[PCI_SUBORDINATE_BUS]; 1560 } 1561 1562 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num) 1563 { 1564 PCIBus *sec; 1565 1566 if (!bus) { 1567 return NULL; 1568 } 1569 1570 if (pci_bus_num(bus) == bus_num) { 1571 return bus; 1572 } 1573 1574 /* Consider all bus numbers in range for the host pci bridge. */ 1575 if (bus->parent_dev && 1576 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) { 1577 return NULL; 1578 } 1579 1580 /* try child bus */ 1581 for (; bus; bus = sec) { 1582 QLIST_FOREACH(sec, &bus->child, sibling) { 1583 assert(sec->parent_dev); 1584 if (sec->parent_dev->config[PCI_SECONDARY_BUS] == bus_num) { 1585 return sec; 1586 } 1587 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) { 1588 break; 1589 } 1590 } 1591 } 1592 1593 return NULL; 1594 } 1595 1596 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn) 1597 { 1598 bus = pci_find_bus_nr(bus, bus_num); 1599 1600 if (!bus) 1601 return NULL; 1602 1603 return bus->devices[devfn]; 1604 } 1605 1606 static int pci_qdev_init(DeviceState *qdev) 1607 { 1608 PCIDevice *pci_dev = (PCIDevice *)qdev; 1609 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 1610 PCIBus *bus; 1611 int rc; 1612 bool is_default_rom; 1613 1614 /* initialize cap_present for pci_is_express() and pci_config_size() */ 1615 if (pc->is_express) { 1616 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; 1617 } 1618 1619 bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev)); 1620 pci_dev = do_pci_register_device(pci_dev, bus, 1621 object_get_typename(OBJECT(qdev)), 1622 pci_dev->devfn); 1623 if (pci_dev == NULL) 1624 return -1; 1625 if (qdev->hotplugged && pc->no_hotplug) { 1626 qerror_report(QERR_DEVICE_NO_HOTPLUG, object_get_typename(OBJECT(pci_dev))); 1627 do_pci_unregister_device(pci_dev); 1628 return -1; 1629 } 1630 if (pc->init) { 1631 rc = pc->init(pci_dev); 1632 if (rc != 0) { 1633 do_pci_unregister_device(pci_dev); 1634 return rc; 1635 } 1636 } 1637 1638 /* rom loading */ 1639 is_default_rom = false; 1640 if (pci_dev->romfile == NULL && pc->romfile != NULL) { 1641 pci_dev->romfile = g_strdup(pc->romfile); 1642 is_default_rom = true; 1643 } 1644 pci_add_option_rom(pci_dev, is_default_rom); 1645 1646 if (bus->hotplug) { 1647 /* Let buses differentiate between hotplug and when device is 1648 * enabled during qemu machine creation. */ 1649 rc = bus->hotplug(bus->hotplug_qdev, pci_dev, 1650 qdev->hotplugged ? PCI_HOTPLUG_ENABLED: 1651 PCI_COLDPLUG_ENABLED); 1652 if (rc != 0) { 1653 int r = pci_unregister_device(&pci_dev->qdev); 1654 assert(!r); 1655 return rc; 1656 } 1657 } 1658 return 0; 1659 } 1660 1661 static int pci_unplug_device(DeviceState *qdev) 1662 { 1663 PCIDevice *dev = PCI_DEVICE(qdev); 1664 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 1665 1666 if (pc->no_hotplug) { 1667 qerror_report(QERR_DEVICE_NO_HOTPLUG, object_get_typename(OBJECT(dev))); 1668 return -1; 1669 } 1670 return dev->bus->hotplug(dev->bus->hotplug_qdev, dev, 1671 PCI_HOTPLUG_DISABLED); 1672 } 1673 1674 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction, 1675 const char *name) 1676 { 1677 DeviceState *dev; 1678 1679 dev = qdev_create(&bus->qbus, name); 1680 qdev_prop_set_int32(dev, "addr", devfn); 1681 qdev_prop_set_bit(dev, "multifunction", multifunction); 1682 return PCI_DEVICE(dev); 1683 } 1684 1685 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, 1686 bool multifunction, 1687 const char *name) 1688 { 1689 PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name); 1690 qdev_init_nofail(&dev->qdev); 1691 return dev; 1692 } 1693 1694 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name) 1695 { 1696 return pci_create_multifunction(bus, devfn, false, name); 1697 } 1698 1699 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name) 1700 { 1701 return pci_create_simple_multifunction(bus, devfn, false, name); 1702 } 1703 1704 static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size) 1705 { 1706 int offset = PCI_CONFIG_HEADER_SIZE; 1707 int i; 1708 for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) { 1709 if (pdev->used[i]) 1710 offset = i + 1; 1711 else if (i - offset + 1 == size) 1712 return offset; 1713 } 1714 return 0; 1715 } 1716 1717 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id, 1718 uint8_t *prev_p) 1719 { 1720 uint8_t next, prev; 1721 1722 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST)) 1723 return 0; 1724 1725 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); 1726 prev = next + PCI_CAP_LIST_NEXT) 1727 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id) 1728 break; 1729 1730 if (prev_p) 1731 *prev_p = prev; 1732 return next; 1733 } 1734 1735 static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset) 1736 { 1737 uint8_t next, prev, found = 0; 1738 1739 if (!(pdev->used[offset])) { 1740 return 0; 1741 } 1742 1743 assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST); 1744 1745 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); 1746 prev = next + PCI_CAP_LIST_NEXT) { 1747 if (next <= offset && next > found) { 1748 found = next; 1749 } 1750 } 1751 return found; 1752 } 1753 1754 /* Patch the PCI vendor and device ids in a PCI rom image if necessary. 1755 This is needed for an option rom which is used for more than one device. */ 1756 static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size) 1757 { 1758 uint16_t vendor_id; 1759 uint16_t device_id; 1760 uint16_t rom_vendor_id; 1761 uint16_t rom_device_id; 1762 uint16_t rom_magic; 1763 uint16_t pcir_offset; 1764 uint8_t checksum; 1765 1766 /* Words in rom data are little endian (like in PCI configuration), 1767 so they can be read / written with pci_get_word / pci_set_word. */ 1768 1769 /* Only a valid rom will be patched. */ 1770 rom_magic = pci_get_word(ptr); 1771 if (rom_magic != 0xaa55) { 1772 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic); 1773 return; 1774 } 1775 pcir_offset = pci_get_word(ptr + 0x18); 1776 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) { 1777 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset); 1778 return; 1779 } 1780 1781 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID); 1782 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID); 1783 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4); 1784 rom_device_id = pci_get_word(ptr + pcir_offset + 6); 1785 1786 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile, 1787 vendor_id, device_id, rom_vendor_id, rom_device_id); 1788 1789 checksum = ptr[6]; 1790 1791 if (vendor_id != rom_vendor_id) { 1792 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */ 1793 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8); 1794 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8); 1795 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); 1796 ptr[6] = checksum; 1797 pci_set_word(ptr + pcir_offset + 4, vendor_id); 1798 } 1799 1800 if (device_id != rom_device_id) { 1801 /* Patch device id and checksum (at offset 6 for etherboot roms). */ 1802 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8); 1803 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8); 1804 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); 1805 ptr[6] = checksum; 1806 pci_set_word(ptr + pcir_offset + 6, device_id); 1807 } 1808 } 1809 1810 /* Add an option rom for the device */ 1811 static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom) 1812 { 1813 int size; 1814 char *path; 1815 void *ptr; 1816 char name[32]; 1817 const VMStateDescription *vmsd; 1818 1819 if (!pdev->romfile) 1820 return 0; 1821 if (strlen(pdev->romfile) == 0) 1822 return 0; 1823 1824 if (!pdev->rom_bar) { 1825 /* 1826 * Load rom via fw_cfg instead of creating a rom bar, 1827 * for 0.11 compatibility. 1828 */ 1829 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE); 1830 if (class == 0x0300) { 1831 rom_add_vga(pdev->romfile); 1832 } else { 1833 rom_add_option(pdev->romfile, -1); 1834 } 1835 return 0; 1836 } 1837 1838 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile); 1839 if (path == NULL) { 1840 path = g_strdup(pdev->romfile); 1841 } 1842 1843 size = get_image_size(path); 1844 if (size < 0) { 1845 error_report("%s: failed to find romfile \"%s\"", 1846 __FUNCTION__, pdev->romfile); 1847 g_free(path); 1848 return -1; 1849 } 1850 if (size & (size - 1)) { 1851 size = 1 << qemu_fls(size); 1852 } 1853 1854 vmsd = qdev_get_vmsd(DEVICE(pdev)); 1855 1856 if (vmsd) { 1857 snprintf(name, sizeof(name), "%s.rom", vmsd->name); 1858 } else { 1859 snprintf(name, sizeof(name), "%s.rom", object_get_typename(OBJECT(pdev))); 1860 } 1861 pdev->has_rom = true; 1862 memory_region_init_ram(&pdev->rom, name, size); 1863 vmstate_register_ram(&pdev->rom, &pdev->qdev); 1864 ptr = memory_region_get_ram_ptr(&pdev->rom); 1865 load_image(path, ptr); 1866 g_free(path); 1867 1868 if (is_default_rom) { 1869 /* Only the default rom images will be patched (if needed). */ 1870 pci_patch_ids(pdev, ptr, size); 1871 } 1872 1873 qemu_put_ram_ptr(ptr); 1874 1875 pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom); 1876 1877 return 0; 1878 } 1879 1880 static void pci_del_option_rom(PCIDevice *pdev) 1881 { 1882 if (!pdev->has_rom) 1883 return; 1884 1885 vmstate_unregister_ram(&pdev->rom, &pdev->qdev); 1886 memory_region_destroy(&pdev->rom); 1887 pdev->has_rom = false; 1888 } 1889 1890 /* 1891 * if !offset 1892 * Reserve space and add capability to the linked list in pci config space 1893 * 1894 * if offset = 0, 1895 * Find and reserve space and add capability to the linked list 1896 * in pci config space */ 1897 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, 1898 uint8_t offset, uint8_t size) 1899 { 1900 uint8_t *config; 1901 int i, overlapping_cap; 1902 1903 if (!offset) { 1904 offset = pci_find_space(pdev, size); 1905 if (!offset) { 1906 return -ENOSPC; 1907 } 1908 } else { 1909 /* Verify that capabilities don't overlap. Note: device assignment 1910 * depends on this check to verify that the device is not broken. 1911 * Should never trigger for emulated devices, but it's helpful 1912 * for debugging these. */ 1913 for (i = offset; i < offset + size; i++) { 1914 overlapping_cap = pci_find_capability_at_offset(pdev, i); 1915 if (overlapping_cap) { 1916 fprintf(stderr, "ERROR: %04x:%02x:%02x.%x " 1917 "Attempt to add PCI capability %x at offset " 1918 "%x overlaps existing capability %x at offset %x\n", 1919 pci_find_domain(pdev->bus), pci_bus_num(pdev->bus), 1920 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), 1921 cap_id, offset, overlapping_cap, i); 1922 return -EINVAL; 1923 } 1924 } 1925 } 1926 1927 config = pdev->config + offset; 1928 config[PCI_CAP_LIST_ID] = cap_id; 1929 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST]; 1930 pdev->config[PCI_CAPABILITY_LIST] = offset; 1931 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST; 1932 memset(pdev->used + offset, 0xFF, QEMU_ALIGN_UP(size, 4)); 1933 /* Make capability read-only by default */ 1934 memset(pdev->wmask + offset, 0, size); 1935 /* Check capability by default */ 1936 memset(pdev->cmask + offset, 0xFF, size); 1937 return offset; 1938 } 1939 1940 /* Unlink capability from the pci config space. */ 1941 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size) 1942 { 1943 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev); 1944 if (!offset) 1945 return; 1946 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT]; 1947 /* Make capability writable again */ 1948 memset(pdev->wmask + offset, 0xff, size); 1949 memset(pdev->w1cmask + offset, 0, size); 1950 /* Clear cmask as device-specific registers can't be checked */ 1951 memset(pdev->cmask + offset, 0, size); 1952 memset(pdev->used + offset, 0, QEMU_ALIGN_UP(size, 4)); 1953 1954 if (!pdev->config[PCI_CAPABILITY_LIST]) 1955 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST; 1956 } 1957 1958 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id) 1959 { 1960 return pci_find_capability_list(pdev, cap_id, NULL); 1961 } 1962 1963 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent) 1964 { 1965 PCIDevice *d = (PCIDevice *)dev; 1966 const pci_class_desc *desc; 1967 char ctxt[64]; 1968 PCIIORegion *r; 1969 int i, class; 1970 1971 class = pci_get_word(d->config + PCI_CLASS_DEVICE); 1972 desc = pci_class_descriptions; 1973 while (desc->desc && class != desc->class) 1974 desc++; 1975 if (desc->desc) { 1976 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc); 1977 } else { 1978 snprintf(ctxt, sizeof(ctxt), "Class %04x", class); 1979 } 1980 1981 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, " 1982 "pci id %04x:%04x (sub %04x:%04x)\n", 1983 indent, "", ctxt, pci_bus_num(d->bus), 1984 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn), 1985 pci_get_word(d->config + PCI_VENDOR_ID), 1986 pci_get_word(d->config + PCI_DEVICE_ID), 1987 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID), 1988 pci_get_word(d->config + PCI_SUBSYSTEM_ID)); 1989 for (i = 0; i < PCI_NUM_REGIONS; i++) { 1990 r = &d->io_regions[i]; 1991 if (!r->size) 1992 continue; 1993 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS 1994 " [0x%"FMT_PCIBUS"]\n", 1995 indent, "", 1996 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem", 1997 r->addr, r->addr + r->size - 1); 1998 } 1999 } 2000 2001 static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len) 2002 { 2003 PCIDevice *d = (PCIDevice *)dev; 2004 const char *name = NULL; 2005 const pci_class_desc *desc = pci_class_descriptions; 2006 int class = pci_get_word(d->config + PCI_CLASS_DEVICE); 2007 2008 while (desc->desc && 2009 (class & ~desc->fw_ign_bits) != 2010 (desc->class & ~desc->fw_ign_bits)) { 2011 desc++; 2012 } 2013 2014 if (desc->desc) { 2015 name = desc->fw_name; 2016 } 2017 2018 if (name) { 2019 pstrcpy(buf, len, name); 2020 } else { 2021 snprintf(buf, len, "pci%04x,%04x", 2022 pci_get_word(d->config + PCI_VENDOR_ID), 2023 pci_get_word(d->config + PCI_DEVICE_ID)); 2024 } 2025 2026 return buf; 2027 } 2028 2029 static char *pcibus_get_fw_dev_path(DeviceState *dev) 2030 { 2031 PCIDevice *d = (PCIDevice *)dev; 2032 char path[50], name[33]; 2033 int off; 2034 2035 off = snprintf(path, sizeof(path), "%s@%x", 2036 pci_dev_fw_name(dev, name, sizeof name), 2037 PCI_SLOT(d->devfn)); 2038 if (PCI_FUNC(d->devfn)) 2039 snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn)); 2040 return g_strdup(path); 2041 } 2042 2043 static char *pcibus_get_dev_path(DeviceState *dev) 2044 { 2045 PCIDevice *d = container_of(dev, PCIDevice, qdev); 2046 PCIDevice *t; 2047 int slot_depth; 2048 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function. 2049 * 00 is added here to make this format compatible with 2050 * domain:Bus:Slot.Func for systems without nested PCI bridges. 2051 * Slot.Function list specifies the slot and function numbers for all 2052 * devices on the path from root to the specific device. */ 2053 char domain[] = "DDDD:00"; 2054 char slot[] = ":SS.F"; 2055 int domain_len = sizeof domain - 1 /* For '\0' */; 2056 int slot_len = sizeof slot - 1 /* For '\0' */; 2057 int path_len; 2058 char *path, *p; 2059 int s; 2060 2061 /* Calculate # of slots on path between device and root. */; 2062 slot_depth = 0; 2063 for (t = d; t; t = t->bus->parent_dev) { 2064 ++slot_depth; 2065 } 2066 2067 path_len = domain_len + slot_len * slot_depth; 2068 2069 /* Allocate memory, fill in the terminating null byte. */ 2070 path = g_malloc(path_len + 1 /* For '\0' */); 2071 path[path_len] = '\0'; 2072 2073 /* First field is the domain. */ 2074 s = snprintf(domain, sizeof domain, "%04x:00", pci_find_domain(d->bus)); 2075 assert(s == domain_len); 2076 memcpy(path, domain, domain_len); 2077 2078 /* Fill in slot numbers. We walk up from device to root, so need to print 2079 * them in the reverse order, last to first. */ 2080 p = path + path_len; 2081 for (t = d; t; t = t->bus->parent_dev) { 2082 p -= slot_len; 2083 s = snprintf(slot, sizeof slot, ":%02x.%x", 2084 PCI_SLOT(t->devfn), PCI_FUNC(t->devfn)); 2085 assert(s == slot_len); 2086 memcpy(p, slot, slot_len); 2087 } 2088 2089 return path; 2090 } 2091 2092 static int pci_qdev_find_recursive(PCIBus *bus, 2093 const char *id, PCIDevice **pdev) 2094 { 2095 DeviceState *qdev = qdev_find_recursive(&bus->qbus, id); 2096 if (!qdev) { 2097 return -ENODEV; 2098 } 2099 2100 /* roughly check if given qdev is pci device */ 2101 if (object_dynamic_cast(OBJECT(qdev), TYPE_PCI_DEVICE)) { 2102 *pdev = PCI_DEVICE(qdev); 2103 return 0; 2104 } 2105 return -EINVAL; 2106 } 2107 2108 int pci_qdev_find_device(const char *id, PCIDevice **pdev) 2109 { 2110 struct PCIHostBus *host; 2111 int rc = -ENODEV; 2112 2113 QLIST_FOREACH(host, &host_buses, next) { 2114 int tmp = pci_qdev_find_recursive(host->bus, id, pdev); 2115 if (!tmp) { 2116 rc = 0; 2117 break; 2118 } 2119 if (tmp != -ENODEV) { 2120 rc = tmp; 2121 } 2122 } 2123 2124 return rc; 2125 } 2126 2127 MemoryRegion *pci_address_space(PCIDevice *dev) 2128 { 2129 return dev->bus->address_space_mem; 2130 } 2131 2132 MemoryRegion *pci_address_space_io(PCIDevice *dev) 2133 { 2134 return dev->bus->address_space_io; 2135 } 2136 2137 static void pci_device_class_init(ObjectClass *klass, void *data) 2138 { 2139 DeviceClass *k = DEVICE_CLASS(klass); 2140 k->init = pci_qdev_init; 2141 k->unplug = pci_unplug_device; 2142 k->exit = pci_unregister_device; 2143 k->bus_type = TYPE_PCI_BUS; 2144 k->props = pci_props; 2145 } 2146 2147 void pci_setup_iommu(PCIBus *bus, PCIDMAContextFunc fn, void *opaque) 2148 { 2149 bus->dma_context_fn = fn; 2150 bus->dma_context_opaque = opaque; 2151 } 2152 2153 static const TypeInfo pci_device_type_info = { 2154 .name = TYPE_PCI_DEVICE, 2155 .parent = TYPE_DEVICE, 2156 .instance_size = sizeof(PCIDevice), 2157 .abstract = true, 2158 .class_size = sizeof(PCIDeviceClass), 2159 .class_init = pci_device_class_init, 2160 }; 2161 2162 static void pci_register_types(void) 2163 { 2164 type_register_static(&pci_bus_info); 2165 type_register_static(&pci_device_type_info); 2166 } 2167 2168 type_init(pci_register_types) 2169