1 /* 2 * QEMU PCI bus manager 3 * 4 * Copyright (c) 2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu-common.h" 27 #include "hw/irq.h" 28 #include "hw/pci/pci.h" 29 #include "hw/pci/pci_bridge.h" 30 #include "hw/pci/pci_bus.h" 31 #include "hw/pci/pci_host.h" 32 #include "hw/qdev-properties.h" 33 #include "migration/qemu-file-types.h" 34 #include "migration/vmstate.h" 35 #include "monitor/monitor.h" 36 #include "net/net.h" 37 #include "sysemu/numa.h" 38 #include "sysemu/sysemu.h" 39 #include "hw/loader.h" 40 #include "qemu/error-report.h" 41 #include "qemu/range.h" 42 #include "trace.h" 43 #include "hw/pci/msi.h" 44 #include "hw/pci/msix.h" 45 #include "exec/address-spaces.h" 46 #include "hw/hotplug.h" 47 #include "hw/boards.h" 48 #include "qapi/error.h" 49 #include "qapi/qapi-commands-misc.h" 50 #include "qemu/cutils.h" 51 52 //#define DEBUG_PCI 53 #ifdef DEBUG_PCI 54 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) 55 #else 56 # define PCI_DPRINTF(format, ...) do { } while (0) 57 #endif 58 59 bool pci_available = true; 60 61 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent); 62 static char *pcibus_get_dev_path(DeviceState *dev); 63 static char *pcibus_get_fw_dev_path(DeviceState *dev); 64 static void pcibus_reset(BusState *qbus); 65 66 static Property pci_props[] = { 67 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1), 68 DEFINE_PROP_STRING("romfile", PCIDevice, romfile), 69 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1), 70 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present, 71 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false), 72 DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present, 73 QEMU_PCI_CAP_SERR_BITNR, true), 74 DEFINE_PROP_BIT("x-pcie-lnksta-dllla", PCIDevice, cap_present, 75 QEMU_PCIE_LNKSTA_DLLLA_BITNR, true), 76 DEFINE_PROP_BIT("x-pcie-extcap-init", PCIDevice, cap_present, 77 QEMU_PCIE_EXTCAP_INIT_BITNR, true), 78 DEFINE_PROP_STRING("failover_pair_id", PCIDevice, 79 failover_pair_id), 80 DEFINE_PROP_END_OF_LIST() 81 }; 82 83 static const VMStateDescription vmstate_pcibus = { 84 .name = "PCIBUS", 85 .version_id = 1, 86 .minimum_version_id = 1, 87 .fields = (VMStateField[]) { 88 VMSTATE_INT32_EQUAL(nirq, PCIBus, NULL), 89 VMSTATE_VARRAY_INT32(irq_count, PCIBus, 90 nirq, 0, vmstate_info_int32, 91 int32_t), 92 VMSTATE_END_OF_LIST() 93 } 94 }; 95 96 static void pci_init_bus_master(PCIDevice *pci_dev) 97 { 98 AddressSpace *dma_as = pci_device_iommu_address_space(pci_dev); 99 100 memory_region_init_alias(&pci_dev->bus_master_enable_region, 101 OBJECT(pci_dev), "bus master", 102 dma_as->root, 0, memory_region_size(dma_as->root)); 103 memory_region_set_enabled(&pci_dev->bus_master_enable_region, false); 104 memory_region_add_subregion(&pci_dev->bus_master_container_region, 0, 105 &pci_dev->bus_master_enable_region); 106 } 107 108 static void pcibus_machine_done(Notifier *notifier, void *data) 109 { 110 PCIBus *bus = container_of(notifier, PCIBus, machine_done); 111 int i; 112 113 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 114 if (bus->devices[i]) { 115 pci_init_bus_master(bus->devices[i]); 116 } 117 } 118 } 119 120 static void pci_bus_realize(BusState *qbus, Error **errp) 121 { 122 PCIBus *bus = PCI_BUS(qbus); 123 124 bus->machine_done.notify = pcibus_machine_done; 125 qemu_add_machine_init_done_notifier(&bus->machine_done); 126 127 vmstate_register(NULL, -1, &vmstate_pcibus, bus); 128 } 129 130 static void pcie_bus_realize(BusState *qbus, Error **errp) 131 { 132 PCIBus *bus = PCI_BUS(qbus); 133 134 pci_bus_realize(qbus, errp); 135 136 /* 137 * A PCI-E bus can support extended config space if it's the root 138 * bus, or if the bus/bridge above it does as well 139 */ 140 if (pci_bus_is_root(bus)) { 141 bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE; 142 } else { 143 PCIBus *parent_bus = pci_get_bus(bus->parent_dev); 144 145 if (pci_bus_allows_extended_config_space(parent_bus)) { 146 bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE; 147 } 148 } 149 } 150 151 static void pci_bus_unrealize(BusState *qbus, Error **errp) 152 { 153 PCIBus *bus = PCI_BUS(qbus); 154 155 qemu_remove_machine_init_done_notifier(&bus->machine_done); 156 157 vmstate_unregister(NULL, &vmstate_pcibus, bus); 158 } 159 160 static int pcibus_num(PCIBus *bus) 161 { 162 if (pci_bus_is_root(bus)) { 163 return 0; /* pci host bridge */ 164 } 165 return bus->parent_dev->config[PCI_SECONDARY_BUS]; 166 } 167 168 static uint16_t pcibus_numa_node(PCIBus *bus) 169 { 170 return NUMA_NODE_UNASSIGNED; 171 } 172 173 static void pci_bus_class_init(ObjectClass *klass, void *data) 174 { 175 BusClass *k = BUS_CLASS(klass); 176 PCIBusClass *pbc = PCI_BUS_CLASS(klass); 177 178 k->print_dev = pcibus_dev_print; 179 k->get_dev_path = pcibus_get_dev_path; 180 k->get_fw_dev_path = pcibus_get_fw_dev_path; 181 k->realize = pci_bus_realize; 182 k->unrealize = pci_bus_unrealize; 183 k->reset = pcibus_reset; 184 185 pbc->bus_num = pcibus_num; 186 pbc->numa_node = pcibus_numa_node; 187 } 188 189 static const TypeInfo pci_bus_info = { 190 .name = TYPE_PCI_BUS, 191 .parent = TYPE_BUS, 192 .instance_size = sizeof(PCIBus), 193 .class_size = sizeof(PCIBusClass), 194 .class_init = pci_bus_class_init, 195 }; 196 197 static const TypeInfo pcie_interface_info = { 198 .name = INTERFACE_PCIE_DEVICE, 199 .parent = TYPE_INTERFACE, 200 }; 201 202 static const TypeInfo conventional_pci_interface_info = { 203 .name = INTERFACE_CONVENTIONAL_PCI_DEVICE, 204 .parent = TYPE_INTERFACE, 205 }; 206 207 static void pcie_bus_class_init(ObjectClass *klass, void *data) 208 { 209 BusClass *k = BUS_CLASS(klass); 210 211 k->realize = pcie_bus_realize; 212 } 213 214 static const TypeInfo pcie_bus_info = { 215 .name = TYPE_PCIE_BUS, 216 .parent = TYPE_PCI_BUS, 217 .class_init = pcie_bus_class_init, 218 }; 219 220 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num); 221 static void pci_update_mappings(PCIDevice *d); 222 static void pci_irq_handler(void *opaque, int irq_num, int level); 223 static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, Error **); 224 static void pci_del_option_rom(PCIDevice *pdev); 225 226 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET; 227 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU; 228 229 static QLIST_HEAD(, PCIHostState) pci_host_bridges; 230 231 int pci_bar(PCIDevice *d, int reg) 232 { 233 uint8_t type; 234 235 if (reg != PCI_ROM_SLOT) 236 return PCI_BASE_ADDRESS_0 + reg * 4; 237 238 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 239 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS; 240 } 241 242 static inline int pci_irq_state(PCIDevice *d, int irq_num) 243 { 244 return (d->irq_state >> irq_num) & 0x1; 245 } 246 247 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level) 248 { 249 d->irq_state &= ~(0x1 << irq_num); 250 d->irq_state |= level << irq_num; 251 } 252 253 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change) 254 { 255 PCIBus *bus; 256 for (;;) { 257 bus = pci_get_bus(pci_dev); 258 irq_num = bus->map_irq(pci_dev, irq_num); 259 if (bus->set_irq) 260 break; 261 pci_dev = bus->parent_dev; 262 } 263 bus->irq_count[irq_num] += change; 264 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0); 265 } 266 267 int pci_bus_get_irq_level(PCIBus *bus, int irq_num) 268 { 269 assert(irq_num >= 0); 270 assert(irq_num < bus->nirq); 271 return !!bus->irq_count[irq_num]; 272 } 273 274 /* Update interrupt status bit in config space on interrupt 275 * state change. */ 276 static void pci_update_irq_status(PCIDevice *dev) 277 { 278 if (dev->irq_state) { 279 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT; 280 } else { 281 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; 282 } 283 } 284 285 void pci_device_deassert_intx(PCIDevice *dev) 286 { 287 int i; 288 for (i = 0; i < PCI_NUM_PINS; ++i) { 289 pci_irq_handler(dev, i, 0); 290 } 291 } 292 293 static void pci_do_device_reset(PCIDevice *dev) 294 { 295 int r; 296 297 pci_device_deassert_intx(dev); 298 assert(dev->irq_state == 0); 299 300 /* Clear all writable bits */ 301 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND, 302 pci_get_word(dev->wmask + PCI_COMMAND) | 303 pci_get_word(dev->w1cmask + PCI_COMMAND)); 304 pci_word_test_and_clear_mask(dev->config + PCI_STATUS, 305 pci_get_word(dev->wmask + PCI_STATUS) | 306 pci_get_word(dev->w1cmask + PCI_STATUS)); 307 dev->config[PCI_CACHE_LINE_SIZE] = 0x0; 308 dev->config[PCI_INTERRUPT_LINE] = 0x0; 309 for (r = 0; r < PCI_NUM_REGIONS; ++r) { 310 PCIIORegion *region = &dev->io_regions[r]; 311 if (!region->size) { 312 continue; 313 } 314 315 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) && 316 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 317 pci_set_quad(dev->config + pci_bar(dev, r), region->type); 318 } else { 319 pci_set_long(dev->config + pci_bar(dev, r), region->type); 320 } 321 } 322 pci_update_mappings(dev); 323 324 msi_reset(dev); 325 msix_reset(dev); 326 } 327 328 /* 329 * This function is called on #RST and FLR. 330 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set 331 */ 332 void pci_device_reset(PCIDevice *dev) 333 { 334 qdev_reset_all(&dev->qdev); 335 pci_do_device_reset(dev); 336 } 337 338 /* 339 * Trigger pci bus reset under a given bus. 340 * Called via qbus_reset_all on RST# assert, after the devices 341 * have been reset qdev_reset_all-ed already. 342 */ 343 static void pcibus_reset(BusState *qbus) 344 { 345 PCIBus *bus = DO_UPCAST(PCIBus, qbus, qbus); 346 int i; 347 348 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 349 if (bus->devices[i]) { 350 pci_do_device_reset(bus->devices[i]); 351 } 352 } 353 354 for (i = 0; i < bus->nirq; i++) { 355 assert(bus->irq_count[i] == 0); 356 } 357 } 358 359 static void pci_host_bus_register(DeviceState *host) 360 { 361 PCIHostState *host_bridge = PCI_HOST_BRIDGE(host); 362 363 QLIST_INSERT_HEAD(&pci_host_bridges, host_bridge, next); 364 } 365 366 static void pci_host_bus_unregister(DeviceState *host) 367 { 368 PCIHostState *host_bridge = PCI_HOST_BRIDGE(host); 369 370 QLIST_REMOVE(host_bridge, next); 371 } 372 373 PCIBus *pci_device_root_bus(const PCIDevice *d) 374 { 375 PCIBus *bus = pci_get_bus(d); 376 377 while (!pci_bus_is_root(bus)) { 378 d = bus->parent_dev; 379 assert(d != NULL); 380 381 bus = pci_get_bus(d); 382 } 383 384 return bus; 385 } 386 387 const char *pci_root_bus_path(PCIDevice *dev) 388 { 389 PCIBus *rootbus = pci_device_root_bus(dev); 390 PCIHostState *host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent); 391 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_GET_CLASS(host_bridge); 392 393 assert(host_bridge->bus == rootbus); 394 395 if (hc->root_bus_path) { 396 return (*hc->root_bus_path)(host_bridge, rootbus); 397 } 398 399 return rootbus->qbus.name; 400 } 401 402 static void pci_root_bus_init(PCIBus *bus, DeviceState *parent, 403 MemoryRegion *address_space_mem, 404 MemoryRegion *address_space_io, 405 uint8_t devfn_min) 406 { 407 assert(PCI_FUNC(devfn_min) == 0); 408 bus->devfn_min = devfn_min; 409 bus->slot_reserved_mask = 0x0; 410 bus->address_space_mem = address_space_mem; 411 bus->address_space_io = address_space_io; 412 bus->flags |= PCI_BUS_IS_ROOT; 413 414 /* host bridge */ 415 QLIST_INIT(&bus->child); 416 417 pci_host_bus_register(parent); 418 } 419 420 static void pci_bus_uninit(PCIBus *bus) 421 { 422 pci_host_bus_unregister(BUS(bus)->parent); 423 } 424 425 bool pci_bus_is_express(PCIBus *bus) 426 { 427 return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS); 428 } 429 430 void pci_root_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent, 431 const char *name, 432 MemoryRegion *address_space_mem, 433 MemoryRegion *address_space_io, 434 uint8_t devfn_min, const char *typename) 435 { 436 qbus_create_inplace(bus, bus_size, typename, parent, name); 437 pci_root_bus_init(bus, parent, address_space_mem, address_space_io, 438 devfn_min); 439 } 440 441 PCIBus *pci_root_bus_new(DeviceState *parent, const char *name, 442 MemoryRegion *address_space_mem, 443 MemoryRegion *address_space_io, 444 uint8_t devfn_min, const char *typename) 445 { 446 PCIBus *bus; 447 448 bus = PCI_BUS(qbus_create(typename, parent, name)); 449 pci_root_bus_init(bus, parent, address_space_mem, address_space_io, 450 devfn_min); 451 return bus; 452 } 453 454 void pci_root_bus_cleanup(PCIBus *bus) 455 { 456 pci_bus_uninit(bus); 457 /* the caller of the unplug hotplug handler will delete this device */ 458 object_property_set_bool(OBJECT(bus), false, "realized", NULL); 459 } 460 461 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 462 void *irq_opaque, int nirq) 463 { 464 bus->set_irq = set_irq; 465 bus->map_irq = map_irq; 466 bus->irq_opaque = irq_opaque; 467 bus->nirq = nirq; 468 bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0])); 469 } 470 471 void pci_bus_irqs_cleanup(PCIBus *bus) 472 { 473 bus->set_irq = NULL; 474 bus->map_irq = NULL; 475 bus->irq_opaque = NULL; 476 bus->nirq = 0; 477 g_free(bus->irq_count); 478 } 479 480 PCIBus *pci_register_root_bus(DeviceState *parent, const char *name, 481 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 482 void *irq_opaque, 483 MemoryRegion *address_space_mem, 484 MemoryRegion *address_space_io, 485 uint8_t devfn_min, int nirq, 486 const char *typename) 487 { 488 PCIBus *bus; 489 490 bus = pci_root_bus_new(parent, name, address_space_mem, 491 address_space_io, devfn_min, typename); 492 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq); 493 return bus; 494 } 495 496 void pci_unregister_root_bus(PCIBus *bus) 497 { 498 pci_bus_irqs_cleanup(bus); 499 pci_root_bus_cleanup(bus); 500 } 501 502 int pci_bus_num(PCIBus *s) 503 { 504 return PCI_BUS_GET_CLASS(s)->bus_num(s); 505 } 506 507 int pci_bus_numa_node(PCIBus *bus) 508 { 509 return PCI_BUS_GET_CLASS(bus)->numa_node(bus); 510 } 511 512 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size, 513 const VMStateField *field) 514 { 515 PCIDevice *s = container_of(pv, PCIDevice, config); 516 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(s); 517 uint8_t *config; 518 int i; 519 520 assert(size == pci_config_size(s)); 521 config = g_malloc(size); 522 523 qemu_get_buffer(f, config, size); 524 for (i = 0; i < size; ++i) { 525 if ((config[i] ^ s->config[i]) & 526 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) { 527 error_report("%s: Bad config data: i=0x%x read: %x device: %x " 528 "cmask: %x wmask: %x w1cmask:%x", __func__, 529 i, config[i], s->config[i], 530 s->cmask[i], s->wmask[i], s->w1cmask[i]); 531 g_free(config); 532 return -EINVAL; 533 } 534 } 535 memcpy(s->config, config, size); 536 537 pci_update_mappings(s); 538 if (pc->is_bridge) { 539 PCIBridge *b = PCI_BRIDGE(s); 540 pci_bridge_update_mappings(b); 541 } 542 543 memory_region_set_enabled(&s->bus_master_enable_region, 544 pci_get_word(s->config + PCI_COMMAND) 545 & PCI_COMMAND_MASTER); 546 547 g_free(config); 548 return 0; 549 } 550 551 /* just put buffer */ 552 static int put_pci_config_device(QEMUFile *f, void *pv, size_t size, 553 const VMStateField *field, QJSON *vmdesc) 554 { 555 const uint8_t **v = pv; 556 assert(size == pci_config_size(container_of(pv, PCIDevice, config))); 557 qemu_put_buffer(f, *v, size); 558 559 return 0; 560 } 561 562 static VMStateInfo vmstate_info_pci_config = { 563 .name = "pci config", 564 .get = get_pci_config_device, 565 .put = put_pci_config_device, 566 }; 567 568 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size, 569 const VMStateField *field) 570 { 571 PCIDevice *s = container_of(pv, PCIDevice, irq_state); 572 uint32_t irq_state[PCI_NUM_PINS]; 573 int i; 574 for (i = 0; i < PCI_NUM_PINS; ++i) { 575 irq_state[i] = qemu_get_be32(f); 576 if (irq_state[i] != 0x1 && irq_state[i] != 0) { 577 fprintf(stderr, "irq state %d: must be 0 or 1.\n", 578 irq_state[i]); 579 return -EINVAL; 580 } 581 } 582 583 for (i = 0; i < PCI_NUM_PINS; ++i) { 584 pci_set_irq_state(s, i, irq_state[i]); 585 } 586 587 return 0; 588 } 589 590 static int put_pci_irq_state(QEMUFile *f, void *pv, size_t size, 591 const VMStateField *field, QJSON *vmdesc) 592 { 593 int i; 594 PCIDevice *s = container_of(pv, PCIDevice, irq_state); 595 596 for (i = 0; i < PCI_NUM_PINS; ++i) { 597 qemu_put_be32(f, pci_irq_state(s, i)); 598 } 599 600 return 0; 601 } 602 603 static VMStateInfo vmstate_info_pci_irq_state = { 604 .name = "pci irq state", 605 .get = get_pci_irq_state, 606 .put = put_pci_irq_state, 607 }; 608 609 static bool migrate_is_pcie(void *opaque, int version_id) 610 { 611 return pci_is_express((PCIDevice *)opaque); 612 } 613 614 static bool migrate_is_not_pcie(void *opaque, int version_id) 615 { 616 return !pci_is_express((PCIDevice *)opaque); 617 } 618 619 const VMStateDescription vmstate_pci_device = { 620 .name = "PCIDevice", 621 .version_id = 2, 622 .minimum_version_id = 1, 623 .fields = (VMStateField[]) { 624 VMSTATE_INT32_POSITIVE_LE(version_id, PCIDevice), 625 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice, 626 migrate_is_not_pcie, 627 0, vmstate_info_pci_config, 628 PCI_CONFIG_SPACE_SIZE), 629 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice, 630 migrate_is_pcie, 631 0, vmstate_info_pci_config, 632 PCIE_CONFIG_SPACE_SIZE), 633 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2, 634 vmstate_info_pci_irq_state, 635 PCI_NUM_PINS * sizeof(int32_t)), 636 VMSTATE_END_OF_LIST() 637 } 638 }; 639 640 641 void pci_device_save(PCIDevice *s, QEMUFile *f) 642 { 643 /* Clear interrupt status bit: it is implicit 644 * in irq_state which we are saving. 645 * This makes us compatible with old devices 646 * which never set or clear this bit. */ 647 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; 648 vmstate_save_state(f, &vmstate_pci_device, s, NULL); 649 /* Restore the interrupt status bit. */ 650 pci_update_irq_status(s); 651 } 652 653 int pci_device_load(PCIDevice *s, QEMUFile *f) 654 { 655 int ret; 656 ret = vmstate_load_state(f, &vmstate_pci_device, s, s->version_id); 657 /* Restore the interrupt status bit. */ 658 pci_update_irq_status(s); 659 return ret; 660 } 661 662 static void pci_set_default_subsystem_id(PCIDevice *pci_dev) 663 { 664 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, 665 pci_default_sub_vendor_id); 666 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 667 pci_default_sub_device_id); 668 } 669 670 /* 671 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL 672 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error 673 */ 674 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, 675 unsigned int *slotp, unsigned int *funcp) 676 { 677 const char *p; 678 char *e; 679 unsigned long val; 680 unsigned long dom = 0, bus = 0; 681 unsigned int slot = 0; 682 unsigned int func = 0; 683 684 p = addr; 685 val = strtoul(p, &e, 16); 686 if (e == p) 687 return -1; 688 if (*e == ':') { 689 bus = val; 690 p = e + 1; 691 val = strtoul(p, &e, 16); 692 if (e == p) 693 return -1; 694 if (*e == ':') { 695 dom = bus; 696 bus = val; 697 p = e + 1; 698 val = strtoul(p, &e, 16); 699 if (e == p) 700 return -1; 701 } 702 } 703 704 slot = val; 705 706 if (funcp != NULL) { 707 if (*e != '.') 708 return -1; 709 710 p = e + 1; 711 val = strtoul(p, &e, 16); 712 if (e == p) 713 return -1; 714 715 func = val; 716 } 717 718 /* if funcp == NULL func is 0 */ 719 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7) 720 return -1; 721 722 if (*e) 723 return -1; 724 725 *domp = dom; 726 *busp = bus; 727 *slotp = slot; 728 if (funcp != NULL) 729 *funcp = func; 730 return 0; 731 } 732 733 static void pci_init_cmask(PCIDevice *dev) 734 { 735 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff); 736 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff); 737 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST; 738 dev->cmask[PCI_REVISION_ID] = 0xff; 739 dev->cmask[PCI_CLASS_PROG] = 0xff; 740 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff); 741 dev->cmask[PCI_HEADER_TYPE] = 0xff; 742 dev->cmask[PCI_CAPABILITY_LIST] = 0xff; 743 } 744 745 static void pci_init_wmask(PCIDevice *dev) 746 { 747 int config_size = pci_config_size(dev); 748 749 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff; 750 dev->wmask[PCI_INTERRUPT_LINE] = 0xff; 751 pci_set_word(dev->wmask + PCI_COMMAND, 752 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | 753 PCI_COMMAND_INTX_DISABLE); 754 if (dev->cap_present & QEMU_PCI_CAP_SERR) { 755 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR); 756 } 757 758 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff, 759 config_size - PCI_CONFIG_HEADER_SIZE); 760 } 761 762 static void pci_init_w1cmask(PCIDevice *dev) 763 { 764 /* 765 * Note: It's okay to set w1cmask even for readonly bits as 766 * long as their value is hardwired to 0. 767 */ 768 pci_set_word(dev->w1cmask + PCI_STATUS, 769 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT | 770 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT | 771 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY); 772 } 773 774 static void pci_init_mask_bridge(PCIDevice *d) 775 { 776 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and 777 PCI_SEC_LETENCY_TIMER */ 778 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4); 779 780 /* base and limit */ 781 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff; 782 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff; 783 pci_set_word(d->wmask + PCI_MEMORY_BASE, 784 PCI_MEMORY_RANGE_MASK & 0xffff); 785 pci_set_word(d->wmask + PCI_MEMORY_LIMIT, 786 PCI_MEMORY_RANGE_MASK & 0xffff); 787 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE, 788 PCI_PREF_RANGE_MASK & 0xffff); 789 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT, 790 PCI_PREF_RANGE_MASK & 0xffff); 791 792 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */ 793 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8); 794 795 /* Supported memory and i/o types */ 796 d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16; 797 d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16; 798 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE, 799 PCI_PREF_RANGE_TYPE_64); 800 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT, 801 PCI_PREF_RANGE_TYPE_64); 802 803 /* 804 * TODO: Bridges default to 10-bit VGA decoding but we currently only 805 * implement 16-bit decoding (no alias support). 806 */ 807 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 808 PCI_BRIDGE_CTL_PARITY | 809 PCI_BRIDGE_CTL_SERR | 810 PCI_BRIDGE_CTL_ISA | 811 PCI_BRIDGE_CTL_VGA | 812 PCI_BRIDGE_CTL_VGA_16BIT | 813 PCI_BRIDGE_CTL_MASTER_ABORT | 814 PCI_BRIDGE_CTL_BUS_RESET | 815 PCI_BRIDGE_CTL_FAST_BACK | 816 PCI_BRIDGE_CTL_DISCARD | 817 PCI_BRIDGE_CTL_SEC_DISCARD | 818 PCI_BRIDGE_CTL_DISCARD_SERR); 819 /* Below does not do anything as we never set this bit, put here for 820 * completeness. */ 821 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL, 822 PCI_BRIDGE_CTL_DISCARD_STATUS); 823 d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK; 824 d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK; 825 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE, 826 PCI_PREF_RANGE_TYPE_MASK); 827 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT, 828 PCI_PREF_RANGE_TYPE_MASK); 829 } 830 831 static void pci_init_multifunction(PCIBus *bus, PCIDevice *dev, Error **errp) 832 { 833 uint8_t slot = PCI_SLOT(dev->devfn); 834 uint8_t func; 835 836 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 837 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION; 838 } 839 840 /* 841 * multifunction bit is interpreted in two ways as follows. 842 * - all functions must set the bit to 1. 843 * Example: Intel X53 844 * - function 0 must set the bit, but the rest function (> 0) 845 * is allowed to leave the bit to 0. 846 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10, 847 * 848 * So OS (at least Linux) checks the bit of only function 0, 849 * and doesn't see the bit of function > 0. 850 * 851 * The below check allows both interpretation. 852 */ 853 if (PCI_FUNC(dev->devfn)) { 854 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)]; 855 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) { 856 /* function 0 should set multifunction bit */ 857 error_setg(errp, "PCI: single function device can't be populated " 858 "in function %x.%x", slot, PCI_FUNC(dev->devfn)); 859 return; 860 } 861 return; 862 } 863 864 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 865 return; 866 } 867 /* function 0 indicates single function, so function > 0 must be NULL */ 868 for (func = 1; func < PCI_FUNC_MAX; ++func) { 869 if (bus->devices[PCI_DEVFN(slot, func)]) { 870 error_setg(errp, "PCI: %x.0 indicates single function, " 871 "but %x.%x is already populated.", 872 slot, slot, func); 873 return; 874 } 875 } 876 } 877 878 static void pci_config_alloc(PCIDevice *pci_dev) 879 { 880 int config_size = pci_config_size(pci_dev); 881 882 pci_dev->config = g_malloc0(config_size); 883 pci_dev->cmask = g_malloc0(config_size); 884 pci_dev->wmask = g_malloc0(config_size); 885 pci_dev->w1cmask = g_malloc0(config_size); 886 pci_dev->used = g_malloc0(config_size); 887 } 888 889 static void pci_config_free(PCIDevice *pci_dev) 890 { 891 g_free(pci_dev->config); 892 g_free(pci_dev->cmask); 893 g_free(pci_dev->wmask); 894 g_free(pci_dev->w1cmask); 895 g_free(pci_dev->used); 896 } 897 898 static void do_pci_unregister_device(PCIDevice *pci_dev) 899 { 900 pci_get_bus(pci_dev)->devices[pci_dev->devfn] = NULL; 901 pci_config_free(pci_dev); 902 903 if (memory_region_is_mapped(&pci_dev->bus_master_enable_region)) { 904 memory_region_del_subregion(&pci_dev->bus_master_container_region, 905 &pci_dev->bus_master_enable_region); 906 } 907 address_space_destroy(&pci_dev->bus_master_as); 908 } 909 910 /* Extract PCIReqIDCache into BDF format */ 911 static uint16_t pci_req_id_cache_extract(PCIReqIDCache *cache) 912 { 913 uint8_t bus_n; 914 uint16_t result; 915 916 switch (cache->type) { 917 case PCI_REQ_ID_BDF: 918 result = pci_get_bdf(cache->dev); 919 break; 920 case PCI_REQ_ID_SECONDARY_BUS: 921 bus_n = pci_dev_bus_num(cache->dev); 922 result = PCI_BUILD_BDF(bus_n, 0); 923 break; 924 default: 925 error_report("Invalid PCI requester ID cache type: %d", 926 cache->type); 927 exit(1); 928 break; 929 } 930 931 return result; 932 } 933 934 /* Parse bridges up to the root complex and return requester ID 935 * cache for specific device. For full PCIe topology, the cache 936 * result would be exactly the same as getting BDF of the device. 937 * However, several tricks are required when system mixed up with 938 * legacy PCI devices and PCIe-to-PCI bridges. 939 * 940 * Here we cache the proxy device (and type) not requester ID since 941 * bus number might change from time to time. 942 */ 943 static PCIReqIDCache pci_req_id_cache_get(PCIDevice *dev) 944 { 945 PCIDevice *parent; 946 PCIReqIDCache cache = { 947 .dev = dev, 948 .type = PCI_REQ_ID_BDF, 949 }; 950 951 while (!pci_bus_is_root(pci_get_bus(dev))) { 952 /* We are under PCI/PCIe bridges */ 953 parent = pci_get_bus(dev)->parent_dev; 954 if (pci_is_express(parent)) { 955 if (pcie_cap_get_type(parent) == PCI_EXP_TYPE_PCI_BRIDGE) { 956 /* When we pass through PCIe-to-PCI/PCIX bridges, we 957 * override the requester ID using secondary bus 958 * number of parent bridge with zeroed devfn 959 * (pcie-to-pci bridge spec chap 2.3). */ 960 cache.type = PCI_REQ_ID_SECONDARY_BUS; 961 cache.dev = dev; 962 } 963 } else { 964 /* Legacy PCI, override requester ID with the bridge's 965 * BDF upstream. When the root complex connects to 966 * legacy PCI devices (including buses), it can only 967 * obtain requester ID info from directly attached 968 * devices. If devices are attached under bridges, only 969 * the requester ID of the bridge that is directly 970 * attached to the root complex can be recognized. */ 971 cache.type = PCI_REQ_ID_BDF; 972 cache.dev = parent; 973 } 974 dev = parent; 975 } 976 977 return cache; 978 } 979 980 uint16_t pci_requester_id(PCIDevice *dev) 981 { 982 return pci_req_id_cache_extract(&dev->requester_id_cache); 983 } 984 985 static bool pci_bus_devfn_available(PCIBus *bus, int devfn) 986 { 987 return !(bus->devices[devfn]); 988 } 989 990 static bool pci_bus_devfn_reserved(PCIBus *bus, int devfn) 991 { 992 return bus->slot_reserved_mask & (1UL << PCI_SLOT(devfn)); 993 } 994 995 /* -1 for devfn means auto assign */ 996 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, 997 const char *name, int devfn, 998 Error **errp) 999 { 1000 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 1001 PCIConfigReadFunc *config_read = pc->config_read; 1002 PCIConfigWriteFunc *config_write = pc->config_write; 1003 Error *local_err = NULL; 1004 DeviceState *dev = DEVICE(pci_dev); 1005 PCIBus *bus = pci_get_bus(pci_dev); 1006 1007 /* Only pci bridges can be attached to extra PCI root buses */ 1008 if (pci_bus_is_root(bus) && bus->parent_dev && !pc->is_bridge) { 1009 error_setg(errp, 1010 "PCI: Only PCI/PCIe bridges can be plugged into %s", 1011 bus->parent_dev->name); 1012 return NULL; 1013 } 1014 1015 if (devfn < 0) { 1016 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices); 1017 devfn += PCI_FUNC_MAX) { 1018 if (pci_bus_devfn_available(bus, devfn) && 1019 !pci_bus_devfn_reserved(bus, devfn)) { 1020 goto found; 1021 } 1022 } 1023 error_setg(errp, "PCI: no slot/function available for %s, all in use " 1024 "or reserved", name); 1025 return NULL; 1026 found: ; 1027 } else if (pci_bus_devfn_reserved(bus, devfn)) { 1028 error_setg(errp, "PCI: slot %d function %d not available for %s," 1029 " reserved", 1030 PCI_SLOT(devfn), PCI_FUNC(devfn), name); 1031 return NULL; 1032 } else if (!pci_bus_devfn_available(bus, devfn)) { 1033 error_setg(errp, "PCI: slot %d function %d not available for %s," 1034 " in use by %s", 1035 PCI_SLOT(devfn), PCI_FUNC(devfn), name, 1036 bus->devices[devfn]->name); 1037 return NULL; 1038 } else if (dev->hotplugged && 1039 pci_get_function_0(pci_dev)) { 1040 error_setg(errp, "PCI: slot %d function 0 already ocuppied by %s," 1041 " new func %s cannot be exposed to guest.", 1042 PCI_SLOT(pci_get_function_0(pci_dev)->devfn), 1043 pci_get_function_0(pci_dev)->name, 1044 name); 1045 1046 return NULL; 1047 } 1048 1049 pci_dev->devfn = devfn; 1050 pci_dev->requester_id_cache = pci_req_id_cache_get(pci_dev); 1051 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name); 1052 1053 memory_region_init(&pci_dev->bus_master_container_region, OBJECT(pci_dev), 1054 "bus master container", UINT64_MAX); 1055 address_space_init(&pci_dev->bus_master_as, 1056 &pci_dev->bus_master_container_region, pci_dev->name); 1057 1058 if (qdev_hotplug) { 1059 pci_init_bus_master(pci_dev); 1060 } 1061 pci_dev->irq_state = 0; 1062 pci_config_alloc(pci_dev); 1063 1064 pci_config_set_vendor_id(pci_dev->config, pc->vendor_id); 1065 pci_config_set_device_id(pci_dev->config, pc->device_id); 1066 pci_config_set_revision(pci_dev->config, pc->revision); 1067 pci_config_set_class(pci_dev->config, pc->class_id); 1068 1069 if (!pc->is_bridge) { 1070 if (pc->subsystem_vendor_id || pc->subsystem_id) { 1071 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, 1072 pc->subsystem_vendor_id); 1073 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 1074 pc->subsystem_id); 1075 } else { 1076 pci_set_default_subsystem_id(pci_dev); 1077 } 1078 } else { 1079 /* subsystem_vendor_id/subsystem_id are only for header type 0 */ 1080 assert(!pc->subsystem_vendor_id); 1081 assert(!pc->subsystem_id); 1082 } 1083 pci_init_cmask(pci_dev); 1084 pci_init_wmask(pci_dev); 1085 pci_init_w1cmask(pci_dev); 1086 if (pc->is_bridge) { 1087 pci_init_mask_bridge(pci_dev); 1088 } 1089 pci_init_multifunction(bus, pci_dev, &local_err); 1090 if (local_err) { 1091 error_propagate(errp, local_err); 1092 do_pci_unregister_device(pci_dev); 1093 return NULL; 1094 } 1095 1096 if (!config_read) 1097 config_read = pci_default_read_config; 1098 if (!config_write) 1099 config_write = pci_default_write_config; 1100 pci_dev->config_read = config_read; 1101 pci_dev->config_write = config_write; 1102 bus->devices[devfn] = pci_dev; 1103 pci_dev->version_id = 2; /* Current pci device vmstate version */ 1104 return pci_dev; 1105 } 1106 1107 static void pci_unregister_io_regions(PCIDevice *pci_dev) 1108 { 1109 PCIIORegion *r; 1110 int i; 1111 1112 for(i = 0; i < PCI_NUM_REGIONS; i++) { 1113 r = &pci_dev->io_regions[i]; 1114 if (!r->size || r->addr == PCI_BAR_UNMAPPED) 1115 continue; 1116 memory_region_del_subregion(r->address_space, r->memory); 1117 } 1118 1119 pci_unregister_vga(pci_dev); 1120 } 1121 1122 static void pci_qdev_unrealize(DeviceState *dev, Error **errp) 1123 { 1124 PCIDevice *pci_dev = PCI_DEVICE(dev); 1125 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 1126 1127 pci_unregister_io_regions(pci_dev); 1128 pci_del_option_rom(pci_dev); 1129 1130 if (pc->exit) { 1131 pc->exit(pci_dev); 1132 } 1133 1134 pci_device_deassert_intx(pci_dev); 1135 do_pci_unregister_device(pci_dev); 1136 } 1137 1138 void pci_register_bar(PCIDevice *pci_dev, int region_num, 1139 uint8_t type, MemoryRegion *memory) 1140 { 1141 PCIIORegion *r; 1142 uint32_t addr; /* offset in pci config space */ 1143 uint64_t wmask; 1144 pcibus_t size = memory_region_size(memory); 1145 1146 assert(region_num >= 0); 1147 assert(region_num < PCI_NUM_REGIONS); 1148 if (size & (size-1)) { 1149 error_report("ERROR: PCI region size must be pow2 " 1150 "type=0x%x, size=0x%"FMT_PCIBUS"", type, size); 1151 exit(1); 1152 } 1153 1154 r = &pci_dev->io_regions[region_num]; 1155 r->addr = PCI_BAR_UNMAPPED; 1156 r->size = size; 1157 r->type = type; 1158 r->memory = memory; 1159 r->address_space = type & PCI_BASE_ADDRESS_SPACE_IO 1160 ? pci_get_bus(pci_dev)->address_space_io 1161 : pci_get_bus(pci_dev)->address_space_mem; 1162 1163 wmask = ~(size - 1); 1164 if (region_num == PCI_ROM_SLOT) { 1165 /* ROM enable bit is writable */ 1166 wmask |= PCI_ROM_ADDRESS_ENABLE; 1167 } 1168 1169 addr = pci_bar(pci_dev, region_num); 1170 pci_set_long(pci_dev->config + addr, type); 1171 1172 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) && 1173 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 1174 pci_set_quad(pci_dev->wmask + addr, wmask); 1175 pci_set_quad(pci_dev->cmask + addr, ~0ULL); 1176 } else { 1177 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff); 1178 pci_set_long(pci_dev->cmask + addr, 0xffffffff); 1179 } 1180 } 1181 1182 static void pci_update_vga(PCIDevice *pci_dev) 1183 { 1184 uint16_t cmd; 1185 1186 if (!pci_dev->has_vga) { 1187 return; 1188 } 1189 1190 cmd = pci_get_word(pci_dev->config + PCI_COMMAND); 1191 1192 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_MEM], 1193 cmd & PCI_COMMAND_MEMORY); 1194 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO], 1195 cmd & PCI_COMMAND_IO); 1196 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI], 1197 cmd & PCI_COMMAND_IO); 1198 } 1199 1200 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, 1201 MemoryRegion *io_lo, MemoryRegion *io_hi) 1202 { 1203 PCIBus *bus = pci_get_bus(pci_dev); 1204 1205 assert(!pci_dev->has_vga); 1206 1207 assert(memory_region_size(mem) == QEMU_PCI_VGA_MEM_SIZE); 1208 pci_dev->vga_regions[QEMU_PCI_VGA_MEM] = mem; 1209 memory_region_add_subregion_overlap(bus->address_space_mem, 1210 QEMU_PCI_VGA_MEM_BASE, mem, 1); 1211 1212 assert(memory_region_size(io_lo) == QEMU_PCI_VGA_IO_LO_SIZE); 1213 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO] = io_lo; 1214 memory_region_add_subregion_overlap(bus->address_space_io, 1215 QEMU_PCI_VGA_IO_LO_BASE, io_lo, 1); 1216 1217 assert(memory_region_size(io_hi) == QEMU_PCI_VGA_IO_HI_SIZE); 1218 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI] = io_hi; 1219 memory_region_add_subregion_overlap(bus->address_space_io, 1220 QEMU_PCI_VGA_IO_HI_BASE, io_hi, 1); 1221 pci_dev->has_vga = true; 1222 1223 pci_update_vga(pci_dev); 1224 } 1225 1226 void pci_unregister_vga(PCIDevice *pci_dev) 1227 { 1228 PCIBus *bus = pci_get_bus(pci_dev); 1229 1230 if (!pci_dev->has_vga) { 1231 return; 1232 } 1233 1234 memory_region_del_subregion(bus->address_space_mem, 1235 pci_dev->vga_regions[QEMU_PCI_VGA_MEM]); 1236 memory_region_del_subregion(bus->address_space_io, 1237 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO]); 1238 memory_region_del_subregion(bus->address_space_io, 1239 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI]); 1240 pci_dev->has_vga = false; 1241 } 1242 1243 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num) 1244 { 1245 return pci_dev->io_regions[region_num].addr; 1246 } 1247 1248 static pcibus_t pci_bar_address(PCIDevice *d, 1249 int reg, uint8_t type, pcibus_t size) 1250 { 1251 pcibus_t new_addr, last_addr; 1252 int bar = pci_bar(d, reg); 1253 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND); 1254 Object *machine = qdev_get_machine(); 1255 ObjectClass *oc = object_get_class(machine); 1256 MachineClass *mc = MACHINE_CLASS(oc); 1257 bool allow_0_address = mc->pci_allow_0_address; 1258 1259 if (type & PCI_BASE_ADDRESS_SPACE_IO) { 1260 if (!(cmd & PCI_COMMAND_IO)) { 1261 return PCI_BAR_UNMAPPED; 1262 } 1263 new_addr = pci_get_long(d->config + bar) & ~(size - 1); 1264 last_addr = new_addr + size - 1; 1265 /* Check if 32 bit BAR wraps around explicitly. 1266 * TODO: make priorities correct and remove this work around. 1267 */ 1268 if (last_addr <= new_addr || last_addr >= UINT32_MAX || 1269 (!allow_0_address && new_addr == 0)) { 1270 return PCI_BAR_UNMAPPED; 1271 } 1272 return new_addr; 1273 } 1274 1275 if (!(cmd & PCI_COMMAND_MEMORY)) { 1276 return PCI_BAR_UNMAPPED; 1277 } 1278 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 1279 new_addr = pci_get_quad(d->config + bar); 1280 } else { 1281 new_addr = pci_get_long(d->config + bar); 1282 } 1283 /* the ROM slot has a specific enable bit */ 1284 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) { 1285 return PCI_BAR_UNMAPPED; 1286 } 1287 new_addr &= ~(size - 1); 1288 last_addr = new_addr + size - 1; 1289 /* NOTE: we do not support wrapping */ 1290 /* XXX: as we cannot support really dynamic 1291 mappings, we handle specific values as invalid 1292 mappings. */ 1293 if (last_addr <= new_addr || last_addr == PCI_BAR_UNMAPPED || 1294 (!allow_0_address && new_addr == 0)) { 1295 return PCI_BAR_UNMAPPED; 1296 } 1297 1298 /* Now pcibus_t is 64bit. 1299 * Check if 32 bit BAR wraps around explicitly. 1300 * Without this, PC ide doesn't work well. 1301 * TODO: remove this work around. 1302 */ 1303 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) { 1304 return PCI_BAR_UNMAPPED; 1305 } 1306 1307 /* 1308 * OS is allowed to set BAR beyond its addressable 1309 * bits. For example, 32 bit OS can set 64bit bar 1310 * to >4G. Check it. TODO: we might need to support 1311 * it in the future for e.g. PAE. 1312 */ 1313 if (last_addr >= HWADDR_MAX) { 1314 return PCI_BAR_UNMAPPED; 1315 } 1316 1317 return new_addr; 1318 } 1319 1320 static void pci_update_mappings(PCIDevice *d) 1321 { 1322 PCIIORegion *r; 1323 int i; 1324 pcibus_t new_addr; 1325 1326 for(i = 0; i < PCI_NUM_REGIONS; i++) { 1327 r = &d->io_regions[i]; 1328 1329 /* this region isn't registered */ 1330 if (!r->size) 1331 continue; 1332 1333 new_addr = pci_bar_address(d, i, r->type, r->size); 1334 1335 /* This bar isn't changed */ 1336 if (new_addr == r->addr) 1337 continue; 1338 1339 /* now do the real mapping */ 1340 if (r->addr != PCI_BAR_UNMAPPED) { 1341 trace_pci_update_mappings_del(d, pci_dev_bus_num(d), 1342 PCI_SLOT(d->devfn), 1343 PCI_FUNC(d->devfn), 1344 i, r->addr, r->size); 1345 memory_region_del_subregion(r->address_space, r->memory); 1346 } 1347 r->addr = new_addr; 1348 if (r->addr != PCI_BAR_UNMAPPED) { 1349 trace_pci_update_mappings_add(d, pci_dev_bus_num(d), 1350 PCI_SLOT(d->devfn), 1351 PCI_FUNC(d->devfn), 1352 i, r->addr, r->size); 1353 memory_region_add_subregion_overlap(r->address_space, 1354 r->addr, r->memory, 1); 1355 } 1356 } 1357 1358 pci_update_vga(d); 1359 } 1360 1361 static inline int pci_irq_disabled(PCIDevice *d) 1362 { 1363 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE; 1364 } 1365 1366 /* Called after interrupt disabled field update in config space, 1367 * assert/deassert interrupts if necessary. 1368 * Gets original interrupt disable bit value (before update). */ 1369 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled) 1370 { 1371 int i, disabled = pci_irq_disabled(d); 1372 if (disabled == was_irq_disabled) 1373 return; 1374 for (i = 0; i < PCI_NUM_PINS; ++i) { 1375 int state = pci_irq_state(d, i); 1376 pci_change_irq_level(d, i, disabled ? -state : state); 1377 } 1378 } 1379 1380 uint32_t pci_default_read_config(PCIDevice *d, 1381 uint32_t address, int len) 1382 { 1383 uint32_t val = 0; 1384 1385 if (pci_is_express_downstream_port(d) && 1386 ranges_overlap(address, len, d->exp.exp_cap + PCI_EXP_LNKSTA, 2)) { 1387 pcie_sync_bridge_lnk(d); 1388 } 1389 memcpy(&val, d->config + address, len); 1390 return le32_to_cpu(val); 1391 } 1392 1393 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val_in, int l) 1394 { 1395 int i, was_irq_disabled = pci_irq_disabled(d); 1396 uint32_t val = val_in; 1397 1398 for (i = 0; i < l; val >>= 8, ++i) { 1399 uint8_t wmask = d->wmask[addr + i]; 1400 uint8_t w1cmask = d->w1cmask[addr + i]; 1401 assert(!(wmask & w1cmask)); 1402 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask); 1403 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */ 1404 } 1405 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) || 1406 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) || 1407 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) || 1408 range_covers_byte(addr, l, PCI_COMMAND)) 1409 pci_update_mappings(d); 1410 1411 if (range_covers_byte(addr, l, PCI_COMMAND)) { 1412 pci_update_irq_disabled(d, was_irq_disabled); 1413 memory_region_set_enabled(&d->bus_master_enable_region, 1414 pci_get_word(d->config + PCI_COMMAND) 1415 & PCI_COMMAND_MASTER); 1416 } 1417 1418 msi_write_config(d, addr, val_in, l); 1419 msix_write_config(d, addr, val_in, l); 1420 } 1421 1422 /***********************************************************/ 1423 /* generic PCI irq support */ 1424 1425 /* 0 <= irq_num <= 3. level must be 0 or 1 */ 1426 static void pci_irq_handler(void *opaque, int irq_num, int level) 1427 { 1428 PCIDevice *pci_dev = opaque; 1429 int change; 1430 1431 change = level - pci_irq_state(pci_dev, irq_num); 1432 if (!change) 1433 return; 1434 1435 pci_set_irq_state(pci_dev, irq_num, level); 1436 pci_update_irq_status(pci_dev); 1437 if (pci_irq_disabled(pci_dev)) 1438 return; 1439 pci_change_irq_level(pci_dev, irq_num, change); 1440 } 1441 1442 static inline int pci_intx(PCIDevice *pci_dev) 1443 { 1444 return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1; 1445 } 1446 1447 qemu_irq pci_allocate_irq(PCIDevice *pci_dev) 1448 { 1449 int intx = pci_intx(pci_dev); 1450 1451 return qemu_allocate_irq(pci_irq_handler, pci_dev, intx); 1452 } 1453 1454 void pci_set_irq(PCIDevice *pci_dev, int level) 1455 { 1456 int intx = pci_intx(pci_dev); 1457 pci_irq_handler(pci_dev, intx, level); 1458 } 1459 1460 /* Special hooks used by device assignment */ 1461 void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq) 1462 { 1463 assert(pci_bus_is_root(bus)); 1464 bus->route_intx_to_irq = route_intx_to_irq; 1465 } 1466 1467 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin) 1468 { 1469 PCIBus *bus; 1470 1471 do { 1472 bus = pci_get_bus(dev); 1473 pin = bus->map_irq(dev, pin); 1474 dev = bus->parent_dev; 1475 } while (dev); 1476 1477 if (!bus->route_intx_to_irq) { 1478 error_report("PCI: Bug - unimplemented PCI INTx routing (%s)", 1479 object_get_typename(OBJECT(bus->qbus.parent))); 1480 return (PCIINTxRoute) { PCI_INTX_DISABLED, -1 }; 1481 } 1482 1483 return bus->route_intx_to_irq(bus->irq_opaque, pin); 1484 } 1485 1486 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new) 1487 { 1488 return old->mode != new->mode || old->irq != new->irq; 1489 } 1490 1491 void pci_bus_fire_intx_routing_notifier(PCIBus *bus) 1492 { 1493 PCIDevice *dev; 1494 PCIBus *sec; 1495 int i; 1496 1497 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 1498 dev = bus->devices[i]; 1499 if (dev && dev->intx_routing_notifier) { 1500 dev->intx_routing_notifier(dev); 1501 } 1502 } 1503 1504 QLIST_FOREACH(sec, &bus->child, sibling) { 1505 pci_bus_fire_intx_routing_notifier(sec); 1506 } 1507 } 1508 1509 void pci_device_set_intx_routing_notifier(PCIDevice *dev, 1510 PCIINTxRoutingNotifier notifier) 1511 { 1512 dev->intx_routing_notifier = notifier; 1513 } 1514 1515 /* 1516 * PCI-to-PCI bridge specification 1517 * 9.1: Interrupt routing. Table 9-1 1518 * 1519 * the PCI Express Base Specification, Revision 2.1 1520 * 2.2.8.1: INTx interrutp signaling - Rules 1521 * the Implementation Note 1522 * Table 2-20 1523 */ 1524 /* 1525 * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD 1526 * 0-origin unlike PCI interrupt pin register. 1527 */ 1528 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin) 1529 { 1530 return pci_swizzle(PCI_SLOT(pci_dev->devfn), pin); 1531 } 1532 1533 /***********************************************************/ 1534 /* monitor info on PCI */ 1535 1536 typedef struct { 1537 uint16_t class; 1538 const char *desc; 1539 const char *fw_name; 1540 uint16_t fw_ign_bits; 1541 } pci_class_desc; 1542 1543 static const pci_class_desc pci_class_descriptions[] = 1544 { 1545 { 0x0001, "VGA controller", "display"}, 1546 { 0x0100, "SCSI controller", "scsi"}, 1547 { 0x0101, "IDE controller", "ide"}, 1548 { 0x0102, "Floppy controller", "fdc"}, 1549 { 0x0103, "IPI controller", "ipi"}, 1550 { 0x0104, "RAID controller", "raid"}, 1551 { 0x0106, "SATA controller"}, 1552 { 0x0107, "SAS controller"}, 1553 { 0x0180, "Storage controller"}, 1554 { 0x0200, "Ethernet controller", "ethernet"}, 1555 { 0x0201, "Token Ring controller", "token-ring"}, 1556 { 0x0202, "FDDI controller", "fddi"}, 1557 { 0x0203, "ATM controller", "atm"}, 1558 { 0x0280, "Network controller"}, 1559 { 0x0300, "VGA controller", "display", 0x00ff}, 1560 { 0x0301, "XGA controller"}, 1561 { 0x0302, "3D controller"}, 1562 { 0x0380, "Display controller"}, 1563 { 0x0400, "Video controller", "video"}, 1564 { 0x0401, "Audio controller", "sound"}, 1565 { 0x0402, "Phone"}, 1566 { 0x0403, "Audio controller", "sound"}, 1567 { 0x0480, "Multimedia controller"}, 1568 { 0x0500, "RAM controller", "memory"}, 1569 { 0x0501, "Flash controller", "flash"}, 1570 { 0x0580, "Memory controller"}, 1571 { 0x0600, "Host bridge", "host"}, 1572 { 0x0601, "ISA bridge", "isa"}, 1573 { 0x0602, "EISA bridge", "eisa"}, 1574 { 0x0603, "MC bridge", "mca"}, 1575 { 0x0604, "PCI bridge", "pci-bridge"}, 1576 { 0x0605, "PCMCIA bridge", "pcmcia"}, 1577 { 0x0606, "NUBUS bridge", "nubus"}, 1578 { 0x0607, "CARDBUS bridge", "cardbus"}, 1579 { 0x0608, "RACEWAY bridge"}, 1580 { 0x0680, "Bridge"}, 1581 { 0x0700, "Serial port", "serial"}, 1582 { 0x0701, "Parallel port", "parallel"}, 1583 { 0x0800, "Interrupt controller", "interrupt-controller"}, 1584 { 0x0801, "DMA controller", "dma-controller"}, 1585 { 0x0802, "Timer", "timer"}, 1586 { 0x0803, "RTC", "rtc"}, 1587 { 0x0900, "Keyboard", "keyboard"}, 1588 { 0x0901, "Pen", "pen"}, 1589 { 0x0902, "Mouse", "mouse"}, 1590 { 0x0A00, "Dock station", "dock", 0x00ff}, 1591 { 0x0B00, "i386 cpu", "cpu", 0x00ff}, 1592 { 0x0c00, "Fireware contorller", "fireware"}, 1593 { 0x0c01, "Access bus controller", "access-bus"}, 1594 { 0x0c02, "SSA controller", "ssa"}, 1595 { 0x0c03, "USB controller", "usb"}, 1596 { 0x0c04, "Fibre channel controller", "fibre-channel"}, 1597 { 0x0c05, "SMBus"}, 1598 { 0, NULL} 1599 }; 1600 1601 static void pci_for_each_device_under_bus_reverse(PCIBus *bus, 1602 void (*fn)(PCIBus *b, 1603 PCIDevice *d, 1604 void *opaque), 1605 void *opaque) 1606 { 1607 PCIDevice *d; 1608 int devfn; 1609 1610 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1611 d = bus->devices[ARRAY_SIZE(bus->devices) - 1 - devfn]; 1612 if (d) { 1613 fn(bus, d, opaque); 1614 } 1615 } 1616 } 1617 1618 void pci_for_each_device_reverse(PCIBus *bus, int bus_num, 1619 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque), 1620 void *opaque) 1621 { 1622 bus = pci_find_bus_nr(bus, bus_num); 1623 1624 if (bus) { 1625 pci_for_each_device_under_bus_reverse(bus, fn, opaque); 1626 } 1627 } 1628 1629 static void pci_for_each_device_under_bus(PCIBus *bus, 1630 void (*fn)(PCIBus *b, PCIDevice *d, 1631 void *opaque), 1632 void *opaque) 1633 { 1634 PCIDevice *d; 1635 int devfn; 1636 1637 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1638 d = bus->devices[devfn]; 1639 if (d) { 1640 fn(bus, d, opaque); 1641 } 1642 } 1643 } 1644 1645 void pci_for_each_device(PCIBus *bus, int bus_num, 1646 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque), 1647 void *opaque) 1648 { 1649 bus = pci_find_bus_nr(bus, bus_num); 1650 1651 if (bus) { 1652 pci_for_each_device_under_bus(bus, fn, opaque); 1653 } 1654 } 1655 1656 static const pci_class_desc *get_class_desc(int class) 1657 { 1658 const pci_class_desc *desc; 1659 1660 desc = pci_class_descriptions; 1661 while (desc->desc && class != desc->class) { 1662 desc++; 1663 } 1664 1665 return desc; 1666 } 1667 1668 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num); 1669 1670 static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev) 1671 { 1672 PciMemoryRegionList *head = NULL, *cur_item = NULL; 1673 int i; 1674 1675 for (i = 0; i < PCI_NUM_REGIONS; i++) { 1676 const PCIIORegion *r = &dev->io_regions[i]; 1677 PciMemoryRegionList *region; 1678 1679 if (!r->size) { 1680 continue; 1681 } 1682 1683 region = g_malloc0(sizeof(*region)); 1684 region->value = g_malloc0(sizeof(*region->value)); 1685 1686 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { 1687 region->value->type = g_strdup("io"); 1688 } else { 1689 region->value->type = g_strdup("memory"); 1690 region->value->has_prefetch = true; 1691 region->value->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH); 1692 region->value->has_mem_type_64 = true; 1693 region->value->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64); 1694 } 1695 1696 region->value->bar = i; 1697 region->value->address = r->addr; 1698 region->value->size = r->size; 1699 1700 /* XXX: waiting for the qapi to support GSList */ 1701 if (!cur_item) { 1702 head = cur_item = region; 1703 } else { 1704 cur_item->next = region; 1705 cur_item = region; 1706 } 1707 } 1708 1709 return head; 1710 } 1711 1712 static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus, 1713 int bus_num) 1714 { 1715 PciBridgeInfo *info; 1716 PciMemoryRange *range; 1717 1718 info = g_new0(PciBridgeInfo, 1); 1719 1720 info->bus = g_new0(PciBusInfo, 1); 1721 info->bus->number = dev->config[PCI_PRIMARY_BUS]; 1722 info->bus->secondary = dev->config[PCI_SECONDARY_BUS]; 1723 info->bus->subordinate = dev->config[PCI_SUBORDINATE_BUS]; 1724 1725 range = info->bus->io_range = g_new0(PciMemoryRange, 1); 1726 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO); 1727 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO); 1728 1729 range = info->bus->memory_range = g_new0(PciMemoryRange, 1); 1730 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 1731 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 1732 1733 range = info->bus->prefetchable_range = g_new0(PciMemoryRange, 1); 1734 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 1735 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 1736 1737 if (dev->config[PCI_SECONDARY_BUS] != 0) { 1738 PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]); 1739 if (child_bus) { 1740 info->has_devices = true; 1741 info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]); 1742 } 1743 } 1744 1745 return info; 1746 } 1747 1748 static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus, 1749 int bus_num) 1750 { 1751 const pci_class_desc *desc; 1752 PciDeviceInfo *info; 1753 uint8_t type; 1754 int class; 1755 1756 info = g_new0(PciDeviceInfo, 1); 1757 info->bus = bus_num; 1758 info->slot = PCI_SLOT(dev->devfn); 1759 info->function = PCI_FUNC(dev->devfn); 1760 1761 info->class_info = g_new0(PciDeviceClass, 1); 1762 class = pci_get_word(dev->config + PCI_CLASS_DEVICE); 1763 info->class_info->q_class = class; 1764 desc = get_class_desc(class); 1765 if (desc->desc) { 1766 info->class_info->has_desc = true; 1767 info->class_info->desc = g_strdup(desc->desc); 1768 } 1769 1770 info->id = g_new0(PciDeviceId, 1); 1771 info->id->vendor = pci_get_word(dev->config + PCI_VENDOR_ID); 1772 info->id->device = pci_get_word(dev->config + PCI_DEVICE_ID); 1773 info->regions = qmp_query_pci_regions(dev); 1774 info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : ""); 1775 1776 if (dev->config[PCI_INTERRUPT_PIN] != 0) { 1777 info->has_irq = true; 1778 info->irq = dev->config[PCI_INTERRUPT_LINE]; 1779 } 1780 1781 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 1782 if (type == PCI_HEADER_TYPE_BRIDGE) { 1783 info->has_pci_bridge = true; 1784 info->pci_bridge = qmp_query_pci_bridge(dev, bus, bus_num); 1785 } else if (type == PCI_HEADER_TYPE_NORMAL) { 1786 info->id->has_subsystem = info->id->has_subsystem_vendor = true; 1787 info->id->subsystem = pci_get_word(dev->config + PCI_SUBSYSTEM_ID); 1788 info->id->subsystem_vendor = 1789 pci_get_word(dev->config + PCI_SUBSYSTEM_VENDOR_ID); 1790 } else if (type == PCI_HEADER_TYPE_CARDBUS) { 1791 info->id->has_subsystem = info->id->has_subsystem_vendor = true; 1792 info->id->subsystem = pci_get_word(dev->config + PCI_CB_SUBSYSTEM_ID); 1793 info->id->subsystem_vendor = 1794 pci_get_word(dev->config + PCI_CB_SUBSYSTEM_VENDOR_ID); 1795 } 1796 1797 return info; 1798 } 1799 1800 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num) 1801 { 1802 PciDeviceInfoList *info, *head = NULL, *cur_item = NULL; 1803 PCIDevice *dev; 1804 int devfn; 1805 1806 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1807 dev = bus->devices[devfn]; 1808 if (dev) { 1809 info = g_malloc0(sizeof(*info)); 1810 info->value = qmp_query_pci_device(dev, bus, bus_num); 1811 1812 /* XXX: waiting for the qapi to support GSList */ 1813 if (!cur_item) { 1814 head = cur_item = info; 1815 } else { 1816 cur_item->next = info; 1817 cur_item = info; 1818 } 1819 } 1820 } 1821 1822 return head; 1823 } 1824 1825 static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num) 1826 { 1827 PciInfo *info = NULL; 1828 1829 bus = pci_find_bus_nr(bus, bus_num); 1830 if (bus) { 1831 info = g_malloc0(sizeof(*info)); 1832 info->bus = bus_num; 1833 info->devices = qmp_query_pci_devices(bus, bus_num); 1834 } 1835 1836 return info; 1837 } 1838 1839 PciInfoList *qmp_query_pci(Error **errp) 1840 { 1841 PciInfoList *info, *head = NULL, *cur_item = NULL; 1842 PCIHostState *host_bridge; 1843 1844 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { 1845 info = g_malloc0(sizeof(*info)); 1846 info->value = qmp_query_pci_bus(host_bridge->bus, 1847 pci_bus_num(host_bridge->bus)); 1848 1849 /* XXX: waiting for the qapi to support GSList */ 1850 if (!cur_item) { 1851 head = cur_item = info; 1852 } else { 1853 cur_item->next = info; 1854 cur_item = info; 1855 } 1856 } 1857 1858 return head; 1859 } 1860 1861 /* Initialize a PCI NIC. */ 1862 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus, 1863 const char *default_model, 1864 const char *default_devaddr) 1865 { 1866 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr; 1867 GSList *list; 1868 GPtrArray *pci_nic_models; 1869 PCIBus *bus; 1870 PCIDevice *pci_dev; 1871 DeviceState *dev; 1872 int devfn; 1873 int i; 1874 int dom, busnr; 1875 unsigned slot; 1876 1877 if (nd->model && !strcmp(nd->model, "virtio")) { 1878 g_free(nd->model); 1879 nd->model = g_strdup("virtio-net-pci"); 1880 } 1881 1882 list = object_class_get_list_sorted(TYPE_PCI_DEVICE, false); 1883 pci_nic_models = g_ptr_array_new(); 1884 while (list) { 1885 DeviceClass *dc = OBJECT_CLASS_CHECK(DeviceClass, list->data, 1886 TYPE_DEVICE); 1887 GSList *next; 1888 if (test_bit(DEVICE_CATEGORY_NETWORK, dc->categories) && 1889 dc->user_creatable) { 1890 const char *name = object_class_get_name(list->data); 1891 g_ptr_array_add(pci_nic_models, (gpointer)name); 1892 } 1893 next = list->next; 1894 g_slist_free_1(list); 1895 list = next; 1896 } 1897 g_ptr_array_add(pci_nic_models, NULL); 1898 1899 if (qemu_show_nic_models(nd->model, (const char **)pci_nic_models->pdata)) { 1900 exit(0); 1901 } 1902 1903 i = qemu_find_nic_model(nd, (const char **)pci_nic_models->pdata, 1904 default_model); 1905 if (i < 0) { 1906 exit(1); 1907 } 1908 1909 if (!rootbus) { 1910 error_report("No primary PCI bus"); 1911 exit(1); 1912 } 1913 1914 assert(!rootbus->parent_dev); 1915 1916 if (!devaddr) { 1917 devfn = -1; 1918 busnr = 0; 1919 } else { 1920 if (pci_parse_devaddr(devaddr, &dom, &busnr, &slot, NULL) < 0) { 1921 error_report("Invalid PCI device address %s for device %s", 1922 devaddr, nd->model); 1923 exit(1); 1924 } 1925 1926 if (dom != 0) { 1927 error_report("No support for non-zero PCI domains"); 1928 exit(1); 1929 } 1930 1931 devfn = PCI_DEVFN(slot, 0); 1932 } 1933 1934 bus = pci_find_bus_nr(rootbus, busnr); 1935 if (!bus) { 1936 error_report("Invalid PCI device address %s for device %s", 1937 devaddr, nd->model); 1938 exit(1); 1939 } 1940 1941 pci_dev = pci_create(bus, devfn, nd->model); 1942 dev = &pci_dev->qdev; 1943 qdev_set_nic_properties(dev, nd); 1944 qdev_init_nofail(dev); 1945 g_ptr_array_free(pci_nic_models, true); 1946 return pci_dev; 1947 } 1948 1949 PCIDevice *pci_vga_init(PCIBus *bus) 1950 { 1951 switch (vga_interface_type) { 1952 case VGA_CIRRUS: 1953 return pci_create_simple(bus, -1, "cirrus-vga"); 1954 case VGA_QXL: 1955 return pci_create_simple(bus, -1, "qxl-vga"); 1956 case VGA_STD: 1957 return pci_create_simple(bus, -1, "VGA"); 1958 case VGA_VMWARE: 1959 return pci_create_simple(bus, -1, "vmware-svga"); 1960 case VGA_VIRTIO: 1961 return pci_create_simple(bus, -1, "virtio-vga"); 1962 case VGA_NONE: 1963 default: /* Other non-PCI types. Checking for unsupported types is already 1964 done in vl.c. */ 1965 return NULL; 1966 } 1967 } 1968 1969 /* Whether a given bus number is in range of the secondary 1970 * bus of the given bridge device. */ 1971 static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num) 1972 { 1973 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) & 1974 PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ && 1975 dev->config[PCI_SECONDARY_BUS] <= bus_num && 1976 bus_num <= dev->config[PCI_SUBORDINATE_BUS]; 1977 } 1978 1979 /* Whether a given bus number is in a range of a root bus */ 1980 static bool pci_root_bus_in_range(PCIBus *bus, int bus_num) 1981 { 1982 int i; 1983 1984 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 1985 PCIDevice *dev = bus->devices[i]; 1986 1987 if (dev && PCI_DEVICE_GET_CLASS(dev)->is_bridge) { 1988 if (pci_secondary_bus_in_range(dev, bus_num)) { 1989 return true; 1990 } 1991 } 1992 } 1993 1994 return false; 1995 } 1996 1997 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num) 1998 { 1999 PCIBus *sec; 2000 2001 if (!bus) { 2002 return NULL; 2003 } 2004 2005 if (pci_bus_num(bus) == bus_num) { 2006 return bus; 2007 } 2008 2009 /* Consider all bus numbers in range for the host pci bridge. */ 2010 if (!pci_bus_is_root(bus) && 2011 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) { 2012 return NULL; 2013 } 2014 2015 /* try child bus */ 2016 for (; bus; bus = sec) { 2017 QLIST_FOREACH(sec, &bus->child, sibling) { 2018 if (pci_bus_num(sec) == bus_num) { 2019 return sec; 2020 } 2021 /* PXB buses assumed to be children of bus 0 */ 2022 if (pci_bus_is_root(sec)) { 2023 if (pci_root_bus_in_range(sec, bus_num)) { 2024 break; 2025 } 2026 } else { 2027 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) { 2028 break; 2029 } 2030 } 2031 } 2032 } 2033 2034 return NULL; 2035 } 2036 2037 void pci_for_each_bus_depth_first(PCIBus *bus, 2038 void *(*begin)(PCIBus *bus, void *parent_state), 2039 void (*end)(PCIBus *bus, void *state), 2040 void *parent_state) 2041 { 2042 PCIBus *sec; 2043 void *state; 2044 2045 if (!bus) { 2046 return; 2047 } 2048 2049 if (begin) { 2050 state = begin(bus, parent_state); 2051 } else { 2052 state = parent_state; 2053 } 2054 2055 QLIST_FOREACH(sec, &bus->child, sibling) { 2056 pci_for_each_bus_depth_first(sec, begin, end, state); 2057 } 2058 2059 if (end) { 2060 end(bus, state); 2061 } 2062 } 2063 2064 2065 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn) 2066 { 2067 bus = pci_find_bus_nr(bus, bus_num); 2068 2069 if (!bus) 2070 return NULL; 2071 2072 return bus->devices[devfn]; 2073 } 2074 2075 static void pci_qdev_realize(DeviceState *qdev, Error **errp) 2076 { 2077 PCIDevice *pci_dev = (PCIDevice *)qdev; 2078 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 2079 ObjectClass *klass = OBJECT_CLASS(pc); 2080 Error *local_err = NULL; 2081 bool is_default_rom; 2082 uint16_t class_id; 2083 2084 /* initialize cap_present for pci_is_express() and pci_config_size(), 2085 * Note that hybrid PCIs are not set automatically and need to manage 2086 * QEMU_PCI_CAP_EXPRESS manually */ 2087 if (object_class_dynamic_cast(klass, INTERFACE_PCIE_DEVICE) && 2088 !object_class_dynamic_cast(klass, INTERFACE_CONVENTIONAL_PCI_DEVICE)) { 2089 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; 2090 } 2091 2092 pci_dev = do_pci_register_device(pci_dev, 2093 object_get_typename(OBJECT(qdev)), 2094 pci_dev->devfn, errp); 2095 if (pci_dev == NULL) 2096 return; 2097 2098 if (pc->realize) { 2099 pc->realize(pci_dev, &local_err); 2100 if (local_err) { 2101 error_propagate(errp, local_err); 2102 do_pci_unregister_device(pci_dev); 2103 return; 2104 } 2105 } 2106 2107 if (pci_dev->failover_pair_id) { 2108 if (!pci_bus_is_express(pci_get_bus(pci_dev))) { 2109 error_setg(errp, "failover primary device must be on " 2110 "PCIExpress bus"); 2111 error_propagate(errp, local_err); 2112 pci_qdev_unrealize(DEVICE(pci_dev), NULL); 2113 return; 2114 } 2115 class_id = pci_get_word(pci_dev->config + PCI_CLASS_DEVICE); 2116 if (class_id != PCI_CLASS_NETWORK_ETHERNET) { 2117 error_setg(errp, "failover primary device is not an " 2118 "Ethernet device"); 2119 error_propagate(errp, local_err); 2120 pci_qdev_unrealize(DEVICE(pci_dev), NULL); 2121 return; 2122 } 2123 if (!(pci_dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) 2124 && (PCI_FUNC(pci_dev->devfn) == 0)) { 2125 qdev->allow_unplug_during_migration = true; 2126 } else { 2127 error_setg(errp, "failover: primary device must be in its own " 2128 "PCI slot"); 2129 error_propagate(errp, local_err); 2130 pci_qdev_unrealize(DEVICE(pci_dev), NULL); 2131 return; 2132 } 2133 qdev->allow_unplug_during_migration = true; 2134 } 2135 2136 /* rom loading */ 2137 is_default_rom = false; 2138 if (pci_dev->romfile == NULL && pc->romfile != NULL) { 2139 pci_dev->romfile = g_strdup(pc->romfile); 2140 is_default_rom = true; 2141 } 2142 2143 pci_add_option_rom(pci_dev, is_default_rom, &local_err); 2144 if (local_err) { 2145 error_propagate(errp, local_err); 2146 pci_qdev_unrealize(DEVICE(pci_dev), NULL); 2147 return; 2148 } 2149 } 2150 2151 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction, 2152 const char *name) 2153 { 2154 DeviceState *dev; 2155 2156 dev = qdev_create(&bus->qbus, name); 2157 qdev_prop_set_int32(dev, "addr", devfn); 2158 qdev_prop_set_bit(dev, "multifunction", multifunction); 2159 return PCI_DEVICE(dev); 2160 } 2161 2162 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, 2163 bool multifunction, 2164 const char *name) 2165 { 2166 PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name); 2167 qdev_init_nofail(&dev->qdev); 2168 return dev; 2169 } 2170 2171 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name) 2172 { 2173 return pci_create_multifunction(bus, devfn, false, name); 2174 } 2175 2176 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name) 2177 { 2178 return pci_create_simple_multifunction(bus, devfn, false, name); 2179 } 2180 2181 static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size) 2182 { 2183 int offset = PCI_CONFIG_HEADER_SIZE; 2184 int i; 2185 for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) { 2186 if (pdev->used[i]) 2187 offset = i + 1; 2188 else if (i - offset + 1 == size) 2189 return offset; 2190 } 2191 return 0; 2192 } 2193 2194 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id, 2195 uint8_t *prev_p) 2196 { 2197 uint8_t next, prev; 2198 2199 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST)) 2200 return 0; 2201 2202 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); 2203 prev = next + PCI_CAP_LIST_NEXT) 2204 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id) 2205 break; 2206 2207 if (prev_p) 2208 *prev_p = prev; 2209 return next; 2210 } 2211 2212 static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset) 2213 { 2214 uint8_t next, prev, found = 0; 2215 2216 if (!(pdev->used[offset])) { 2217 return 0; 2218 } 2219 2220 assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST); 2221 2222 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); 2223 prev = next + PCI_CAP_LIST_NEXT) { 2224 if (next <= offset && next > found) { 2225 found = next; 2226 } 2227 } 2228 return found; 2229 } 2230 2231 /* Patch the PCI vendor and device ids in a PCI rom image if necessary. 2232 This is needed for an option rom which is used for more than one device. */ 2233 static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size) 2234 { 2235 uint16_t vendor_id; 2236 uint16_t device_id; 2237 uint16_t rom_vendor_id; 2238 uint16_t rom_device_id; 2239 uint16_t rom_magic; 2240 uint16_t pcir_offset; 2241 uint8_t checksum; 2242 2243 /* Words in rom data are little endian (like in PCI configuration), 2244 so they can be read / written with pci_get_word / pci_set_word. */ 2245 2246 /* Only a valid rom will be patched. */ 2247 rom_magic = pci_get_word(ptr); 2248 if (rom_magic != 0xaa55) { 2249 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic); 2250 return; 2251 } 2252 pcir_offset = pci_get_word(ptr + 0x18); 2253 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) { 2254 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset); 2255 return; 2256 } 2257 2258 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID); 2259 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID); 2260 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4); 2261 rom_device_id = pci_get_word(ptr + pcir_offset + 6); 2262 2263 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile, 2264 vendor_id, device_id, rom_vendor_id, rom_device_id); 2265 2266 checksum = ptr[6]; 2267 2268 if (vendor_id != rom_vendor_id) { 2269 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */ 2270 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8); 2271 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8); 2272 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); 2273 ptr[6] = checksum; 2274 pci_set_word(ptr + pcir_offset + 4, vendor_id); 2275 } 2276 2277 if (device_id != rom_device_id) { 2278 /* Patch device id and checksum (at offset 6 for etherboot roms). */ 2279 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8); 2280 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8); 2281 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); 2282 ptr[6] = checksum; 2283 pci_set_word(ptr + pcir_offset + 6, device_id); 2284 } 2285 } 2286 2287 /* Add an option rom for the device */ 2288 static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, 2289 Error **errp) 2290 { 2291 int size; 2292 char *path; 2293 void *ptr; 2294 char name[32]; 2295 const VMStateDescription *vmsd; 2296 2297 if (!pdev->romfile) 2298 return; 2299 if (strlen(pdev->romfile) == 0) 2300 return; 2301 2302 if (!pdev->rom_bar) { 2303 /* 2304 * Load rom via fw_cfg instead of creating a rom bar, 2305 * for 0.11 compatibility. 2306 */ 2307 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE); 2308 2309 /* 2310 * Hot-plugged devices can't use the option ROM 2311 * if the rom bar is disabled. 2312 */ 2313 if (DEVICE(pdev)->hotplugged) { 2314 error_setg(errp, "Hot-plugged device without ROM bar" 2315 " can't have an option ROM"); 2316 return; 2317 } 2318 2319 if (class == 0x0300) { 2320 rom_add_vga(pdev->romfile); 2321 } else { 2322 rom_add_option(pdev->romfile, -1); 2323 } 2324 return; 2325 } 2326 2327 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile); 2328 if (path == NULL) { 2329 path = g_strdup(pdev->romfile); 2330 } 2331 2332 size = get_image_size(path); 2333 if (size < 0) { 2334 error_setg(errp, "failed to find romfile \"%s\"", pdev->romfile); 2335 g_free(path); 2336 return; 2337 } else if (size == 0) { 2338 error_setg(errp, "romfile \"%s\" is empty", pdev->romfile); 2339 g_free(path); 2340 return; 2341 } 2342 size = pow2ceil(size); 2343 2344 vmsd = qdev_get_vmsd(DEVICE(pdev)); 2345 2346 if (vmsd) { 2347 snprintf(name, sizeof(name), "%s.rom", vmsd->name); 2348 } else { 2349 snprintf(name, sizeof(name), "%s.rom", object_get_typename(OBJECT(pdev))); 2350 } 2351 pdev->has_rom = true; 2352 memory_region_init_rom(&pdev->rom, OBJECT(pdev), name, size, &error_fatal); 2353 ptr = memory_region_get_ram_ptr(&pdev->rom); 2354 if (load_image_size(path, ptr, size) < 0) { 2355 error_setg(errp, "failed to load romfile \"%s\"", pdev->romfile); 2356 g_free(path); 2357 return; 2358 } 2359 g_free(path); 2360 2361 if (is_default_rom) { 2362 /* Only the default rom images will be patched (if needed). */ 2363 pci_patch_ids(pdev, ptr, size); 2364 } 2365 2366 pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom); 2367 } 2368 2369 static void pci_del_option_rom(PCIDevice *pdev) 2370 { 2371 if (!pdev->has_rom) 2372 return; 2373 2374 vmstate_unregister_ram(&pdev->rom, &pdev->qdev); 2375 pdev->has_rom = false; 2376 } 2377 2378 /* 2379 * On success, pci_add_capability() returns a positive value 2380 * that the offset of the pci capability. 2381 * On failure, it sets an error and returns a negative error 2382 * code. 2383 */ 2384 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, 2385 uint8_t offset, uint8_t size, 2386 Error **errp) 2387 { 2388 uint8_t *config; 2389 int i, overlapping_cap; 2390 2391 if (!offset) { 2392 offset = pci_find_space(pdev, size); 2393 /* out of PCI config space is programming error */ 2394 assert(offset); 2395 } else { 2396 /* Verify that capabilities don't overlap. Note: device assignment 2397 * depends on this check to verify that the device is not broken. 2398 * Should never trigger for emulated devices, but it's helpful 2399 * for debugging these. */ 2400 for (i = offset; i < offset + size; i++) { 2401 overlapping_cap = pci_find_capability_at_offset(pdev, i); 2402 if (overlapping_cap) { 2403 error_setg(errp, "%s:%02x:%02x.%x " 2404 "Attempt to add PCI capability %x at offset " 2405 "%x overlaps existing capability %x at offset %x", 2406 pci_root_bus_path(pdev), pci_dev_bus_num(pdev), 2407 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), 2408 cap_id, offset, overlapping_cap, i); 2409 return -EINVAL; 2410 } 2411 } 2412 } 2413 2414 config = pdev->config + offset; 2415 config[PCI_CAP_LIST_ID] = cap_id; 2416 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST]; 2417 pdev->config[PCI_CAPABILITY_LIST] = offset; 2418 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST; 2419 memset(pdev->used + offset, 0xFF, QEMU_ALIGN_UP(size, 4)); 2420 /* Make capability read-only by default */ 2421 memset(pdev->wmask + offset, 0, size); 2422 /* Check capability by default */ 2423 memset(pdev->cmask + offset, 0xFF, size); 2424 return offset; 2425 } 2426 2427 /* Unlink capability from the pci config space. */ 2428 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size) 2429 { 2430 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev); 2431 if (!offset) 2432 return; 2433 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT]; 2434 /* Make capability writable again */ 2435 memset(pdev->wmask + offset, 0xff, size); 2436 memset(pdev->w1cmask + offset, 0, size); 2437 /* Clear cmask as device-specific registers can't be checked */ 2438 memset(pdev->cmask + offset, 0, size); 2439 memset(pdev->used + offset, 0, QEMU_ALIGN_UP(size, 4)); 2440 2441 if (!pdev->config[PCI_CAPABILITY_LIST]) 2442 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST; 2443 } 2444 2445 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id) 2446 { 2447 return pci_find_capability_list(pdev, cap_id, NULL); 2448 } 2449 2450 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent) 2451 { 2452 PCIDevice *d = (PCIDevice *)dev; 2453 const pci_class_desc *desc; 2454 char ctxt[64]; 2455 PCIIORegion *r; 2456 int i, class; 2457 2458 class = pci_get_word(d->config + PCI_CLASS_DEVICE); 2459 desc = pci_class_descriptions; 2460 while (desc->desc && class != desc->class) 2461 desc++; 2462 if (desc->desc) { 2463 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc); 2464 } else { 2465 snprintf(ctxt, sizeof(ctxt), "Class %04x", class); 2466 } 2467 2468 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, " 2469 "pci id %04x:%04x (sub %04x:%04x)\n", 2470 indent, "", ctxt, pci_dev_bus_num(d), 2471 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn), 2472 pci_get_word(d->config + PCI_VENDOR_ID), 2473 pci_get_word(d->config + PCI_DEVICE_ID), 2474 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID), 2475 pci_get_word(d->config + PCI_SUBSYSTEM_ID)); 2476 for (i = 0; i < PCI_NUM_REGIONS; i++) { 2477 r = &d->io_regions[i]; 2478 if (!r->size) 2479 continue; 2480 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS 2481 " [0x%"FMT_PCIBUS"]\n", 2482 indent, "", 2483 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem", 2484 r->addr, r->addr + r->size - 1); 2485 } 2486 } 2487 2488 static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len) 2489 { 2490 PCIDevice *d = (PCIDevice *)dev; 2491 const char *name = NULL; 2492 const pci_class_desc *desc = pci_class_descriptions; 2493 int class = pci_get_word(d->config + PCI_CLASS_DEVICE); 2494 2495 while (desc->desc && 2496 (class & ~desc->fw_ign_bits) != 2497 (desc->class & ~desc->fw_ign_bits)) { 2498 desc++; 2499 } 2500 2501 if (desc->desc) { 2502 name = desc->fw_name; 2503 } 2504 2505 if (name) { 2506 pstrcpy(buf, len, name); 2507 } else { 2508 snprintf(buf, len, "pci%04x,%04x", 2509 pci_get_word(d->config + PCI_VENDOR_ID), 2510 pci_get_word(d->config + PCI_DEVICE_ID)); 2511 } 2512 2513 return buf; 2514 } 2515 2516 static char *pcibus_get_fw_dev_path(DeviceState *dev) 2517 { 2518 PCIDevice *d = (PCIDevice *)dev; 2519 char path[50], name[33]; 2520 int off; 2521 2522 off = snprintf(path, sizeof(path), "%s@%x", 2523 pci_dev_fw_name(dev, name, sizeof name), 2524 PCI_SLOT(d->devfn)); 2525 if (PCI_FUNC(d->devfn)) 2526 snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn)); 2527 return g_strdup(path); 2528 } 2529 2530 static char *pcibus_get_dev_path(DeviceState *dev) 2531 { 2532 PCIDevice *d = container_of(dev, PCIDevice, qdev); 2533 PCIDevice *t; 2534 int slot_depth; 2535 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function. 2536 * 00 is added here to make this format compatible with 2537 * domain:Bus:Slot.Func for systems without nested PCI bridges. 2538 * Slot.Function list specifies the slot and function numbers for all 2539 * devices on the path from root to the specific device. */ 2540 const char *root_bus_path; 2541 int root_bus_len; 2542 char slot[] = ":SS.F"; 2543 int slot_len = sizeof slot - 1 /* For '\0' */; 2544 int path_len; 2545 char *path, *p; 2546 int s; 2547 2548 root_bus_path = pci_root_bus_path(d); 2549 root_bus_len = strlen(root_bus_path); 2550 2551 /* Calculate # of slots on path between device and root. */; 2552 slot_depth = 0; 2553 for (t = d; t; t = pci_get_bus(t)->parent_dev) { 2554 ++slot_depth; 2555 } 2556 2557 path_len = root_bus_len + slot_len * slot_depth; 2558 2559 /* Allocate memory, fill in the terminating null byte. */ 2560 path = g_malloc(path_len + 1 /* For '\0' */); 2561 path[path_len] = '\0'; 2562 2563 memcpy(path, root_bus_path, root_bus_len); 2564 2565 /* Fill in slot numbers. We walk up from device to root, so need to print 2566 * them in the reverse order, last to first. */ 2567 p = path + path_len; 2568 for (t = d; t; t = pci_get_bus(t)->parent_dev) { 2569 p -= slot_len; 2570 s = snprintf(slot, sizeof slot, ":%02x.%x", 2571 PCI_SLOT(t->devfn), PCI_FUNC(t->devfn)); 2572 assert(s == slot_len); 2573 memcpy(p, slot, slot_len); 2574 } 2575 2576 return path; 2577 } 2578 2579 static int pci_qdev_find_recursive(PCIBus *bus, 2580 const char *id, PCIDevice **pdev) 2581 { 2582 DeviceState *qdev = qdev_find_recursive(&bus->qbus, id); 2583 if (!qdev) { 2584 return -ENODEV; 2585 } 2586 2587 /* roughly check if given qdev is pci device */ 2588 if (object_dynamic_cast(OBJECT(qdev), TYPE_PCI_DEVICE)) { 2589 *pdev = PCI_DEVICE(qdev); 2590 return 0; 2591 } 2592 return -EINVAL; 2593 } 2594 2595 int pci_qdev_find_device(const char *id, PCIDevice **pdev) 2596 { 2597 PCIHostState *host_bridge; 2598 int rc = -ENODEV; 2599 2600 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { 2601 int tmp = pci_qdev_find_recursive(host_bridge->bus, id, pdev); 2602 if (!tmp) { 2603 rc = 0; 2604 break; 2605 } 2606 if (tmp != -ENODEV) { 2607 rc = tmp; 2608 } 2609 } 2610 2611 return rc; 2612 } 2613 2614 MemoryRegion *pci_address_space(PCIDevice *dev) 2615 { 2616 return pci_get_bus(dev)->address_space_mem; 2617 } 2618 2619 MemoryRegion *pci_address_space_io(PCIDevice *dev) 2620 { 2621 return pci_get_bus(dev)->address_space_io; 2622 } 2623 2624 static void pci_device_class_init(ObjectClass *klass, void *data) 2625 { 2626 DeviceClass *k = DEVICE_CLASS(klass); 2627 2628 k->realize = pci_qdev_realize; 2629 k->unrealize = pci_qdev_unrealize; 2630 k->bus_type = TYPE_PCI_BUS; 2631 k->props = pci_props; 2632 } 2633 2634 static void pci_device_class_base_init(ObjectClass *klass, void *data) 2635 { 2636 if (!object_class_is_abstract(klass)) { 2637 ObjectClass *conventional = 2638 object_class_dynamic_cast(klass, INTERFACE_CONVENTIONAL_PCI_DEVICE); 2639 ObjectClass *pcie = 2640 object_class_dynamic_cast(klass, INTERFACE_PCIE_DEVICE); 2641 assert(conventional || pcie); 2642 } 2643 } 2644 2645 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev) 2646 { 2647 PCIBus *bus = pci_get_bus(dev); 2648 PCIBus *iommu_bus = bus; 2649 uint8_t devfn = dev->devfn; 2650 2651 while (iommu_bus && !iommu_bus->iommu_fn && iommu_bus->parent_dev) { 2652 PCIBus *parent_bus = pci_get_bus(iommu_bus->parent_dev); 2653 2654 /* 2655 * The requester ID of the provided device may be aliased, as seen from 2656 * the IOMMU, due to topology limitations. The IOMMU relies on a 2657 * requester ID to provide a unique AddressSpace for devices, but 2658 * conventional PCI buses pre-date such concepts. Instead, the PCIe- 2659 * to-PCI bridge creates and accepts transactions on behalf of down- 2660 * stream devices. When doing so, all downstream devices are masked 2661 * (aliased) behind a single requester ID. The requester ID used 2662 * depends on the format of the bridge devices. Proper PCIe-to-PCI 2663 * bridges, with a PCIe capability indicating such, follow the 2664 * guidelines of chapter 2.3 of the PCIe-to-PCI/X bridge specification, 2665 * where the bridge uses the seconary bus as the bridge portion of the 2666 * requester ID and devfn of 00.0. For other bridges, typically those 2667 * found on the root complex such as the dmi-to-pci-bridge, we follow 2668 * the convention of typical bare-metal hardware, which uses the 2669 * requester ID of the bridge itself. There are device specific 2670 * exceptions to these rules, but these are the defaults that the 2671 * Linux kernel uses when determining DMA aliases itself and believed 2672 * to be true for the bare metal equivalents of the devices emulated 2673 * in QEMU. 2674 */ 2675 if (!pci_bus_is_express(iommu_bus)) { 2676 PCIDevice *parent = iommu_bus->parent_dev; 2677 2678 if (pci_is_express(parent) && 2679 pcie_cap_get_type(parent) == PCI_EXP_TYPE_PCI_BRIDGE) { 2680 devfn = PCI_DEVFN(0, 0); 2681 bus = iommu_bus; 2682 } else { 2683 devfn = parent->devfn; 2684 bus = parent_bus; 2685 } 2686 } 2687 2688 iommu_bus = parent_bus; 2689 } 2690 if (iommu_bus && iommu_bus->iommu_fn) { 2691 return iommu_bus->iommu_fn(bus, iommu_bus->iommu_opaque, devfn); 2692 } 2693 return &address_space_memory; 2694 } 2695 2696 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque) 2697 { 2698 bus->iommu_fn = fn; 2699 bus->iommu_opaque = opaque; 2700 } 2701 2702 static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque) 2703 { 2704 Range *range = opaque; 2705 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 2706 uint16_t cmd = pci_get_word(dev->config + PCI_COMMAND); 2707 int i; 2708 2709 if (!(cmd & PCI_COMMAND_MEMORY)) { 2710 return; 2711 } 2712 2713 if (pc->is_bridge) { 2714 pcibus_t base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 2715 pcibus_t limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 2716 2717 base = MAX(base, 0x1ULL << 32); 2718 2719 if (limit >= base) { 2720 Range pref_range; 2721 range_set_bounds(&pref_range, base, limit); 2722 range_extend(range, &pref_range); 2723 } 2724 } 2725 for (i = 0; i < PCI_NUM_REGIONS; ++i) { 2726 PCIIORegion *r = &dev->io_regions[i]; 2727 pcibus_t lob, upb; 2728 Range region_range; 2729 2730 if (!r->size || 2731 (r->type & PCI_BASE_ADDRESS_SPACE_IO) || 2732 !(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64)) { 2733 continue; 2734 } 2735 2736 lob = pci_bar_address(dev, i, r->type, r->size); 2737 upb = lob + r->size - 1; 2738 if (lob == PCI_BAR_UNMAPPED) { 2739 continue; 2740 } 2741 2742 lob = MAX(lob, 0x1ULL << 32); 2743 2744 if (upb >= lob) { 2745 range_set_bounds(®ion_range, lob, upb); 2746 range_extend(range, ®ion_range); 2747 } 2748 } 2749 } 2750 2751 void pci_bus_get_w64_range(PCIBus *bus, Range *range) 2752 { 2753 range_make_empty(range); 2754 pci_for_each_device_under_bus(bus, pci_dev_get_w64, range); 2755 } 2756 2757 static bool pcie_has_upstream_port(PCIDevice *dev) 2758 { 2759 PCIDevice *parent_dev = pci_bridge_get_device(pci_get_bus(dev)); 2760 2761 /* Device associated with an upstream port. 2762 * As there are several types of these, it's easier to check the 2763 * parent device: upstream ports are always connected to 2764 * root or downstream ports. 2765 */ 2766 return parent_dev && 2767 pci_is_express(parent_dev) && 2768 parent_dev->exp.exp_cap && 2769 (pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_ROOT_PORT || 2770 pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_DOWNSTREAM); 2771 } 2772 2773 PCIDevice *pci_get_function_0(PCIDevice *pci_dev) 2774 { 2775 PCIBus *bus = pci_get_bus(pci_dev); 2776 2777 if(pcie_has_upstream_port(pci_dev)) { 2778 /* With an upstream PCIe port, we only support 1 device at slot 0 */ 2779 return bus->devices[0]; 2780 } else { 2781 /* Other bus types might support multiple devices at slots 0-31 */ 2782 return bus->devices[PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 0)]; 2783 } 2784 } 2785 2786 MSIMessage pci_get_msi_message(PCIDevice *dev, int vector) 2787 { 2788 MSIMessage msg; 2789 if (msix_enabled(dev)) { 2790 msg = msix_get_message(dev, vector); 2791 } else if (msi_enabled(dev)) { 2792 msg = msi_get_message(dev, vector); 2793 } else { 2794 /* Should never happen */ 2795 error_report("%s: unknown interrupt type", __func__); 2796 abort(); 2797 } 2798 return msg; 2799 } 2800 2801 static const TypeInfo pci_device_type_info = { 2802 .name = TYPE_PCI_DEVICE, 2803 .parent = TYPE_DEVICE, 2804 .instance_size = sizeof(PCIDevice), 2805 .abstract = true, 2806 .class_size = sizeof(PCIDeviceClass), 2807 .class_init = pci_device_class_init, 2808 .class_base_init = pci_device_class_base_init, 2809 }; 2810 2811 static void pci_register_types(void) 2812 { 2813 type_register_static(&pci_bus_info); 2814 type_register_static(&pcie_bus_info); 2815 type_register_static(&conventional_pci_interface_info); 2816 type_register_static(&pcie_interface_info); 2817 type_register_static(&pci_device_type_info); 2818 } 2819 2820 type_init(pci_register_types) 2821