1 /* 2 * QEMU PCI bus manager 3 * 4 * Copyright (c) 2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu-common.h" 27 #include "hw/irq.h" 28 #include "hw/pci/pci.h" 29 #include "hw/pci/pci_bridge.h" 30 #include "hw/pci/pci_bus.h" 31 #include "hw/pci/pci_host.h" 32 #include "hw/qdev-properties.h" 33 #include "migration/qemu-file-types.h" 34 #include "migration/vmstate.h" 35 #include "monitor/monitor.h" 36 #include "net/net.h" 37 #include "sysemu/numa.h" 38 #include "sysemu/sysemu.h" 39 #include "hw/loader.h" 40 #include "qemu/error-report.h" 41 #include "qemu/range.h" 42 #include "trace.h" 43 #include "hw/pci/msi.h" 44 #include "hw/pci/msix.h" 45 #include "exec/address-spaces.h" 46 #include "hw/hotplug.h" 47 #include "hw/boards.h" 48 #include "qapi/error.h" 49 #include "qapi/qapi-commands-pci.h" 50 #include "qemu/cutils.h" 51 52 //#define DEBUG_PCI 53 #ifdef DEBUG_PCI 54 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) 55 #else 56 # define PCI_DPRINTF(format, ...) do { } while (0) 57 #endif 58 59 bool pci_available = true; 60 61 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent); 62 static char *pcibus_get_dev_path(DeviceState *dev); 63 static char *pcibus_get_fw_dev_path(DeviceState *dev); 64 static void pcibus_reset(BusState *qbus); 65 66 static Property pci_props[] = { 67 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1), 68 DEFINE_PROP_STRING("romfile", PCIDevice, romfile), 69 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1), 70 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present, 71 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false), 72 DEFINE_PROP_BIT("x-pcie-lnksta-dllla", PCIDevice, cap_present, 73 QEMU_PCIE_LNKSTA_DLLLA_BITNR, true), 74 DEFINE_PROP_BIT("x-pcie-extcap-init", PCIDevice, cap_present, 75 QEMU_PCIE_EXTCAP_INIT_BITNR, true), 76 DEFINE_PROP_STRING("failover_pair_id", PCIDevice, 77 failover_pair_id), 78 DEFINE_PROP_END_OF_LIST() 79 }; 80 81 static const VMStateDescription vmstate_pcibus = { 82 .name = "PCIBUS", 83 .version_id = 1, 84 .minimum_version_id = 1, 85 .fields = (VMStateField[]) { 86 VMSTATE_INT32_EQUAL(nirq, PCIBus, NULL), 87 VMSTATE_VARRAY_INT32(irq_count, PCIBus, 88 nirq, 0, vmstate_info_int32, 89 int32_t), 90 VMSTATE_END_OF_LIST() 91 } 92 }; 93 94 static void pci_init_bus_master(PCIDevice *pci_dev) 95 { 96 AddressSpace *dma_as = pci_device_iommu_address_space(pci_dev); 97 98 memory_region_init_alias(&pci_dev->bus_master_enable_region, 99 OBJECT(pci_dev), "bus master", 100 dma_as->root, 0, memory_region_size(dma_as->root)); 101 memory_region_set_enabled(&pci_dev->bus_master_enable_region, false); 102 memory_region_add_subregion(&pci_dev->bus_master_container_region, 0, 103 &pci_dev->bus_master_enable_region); 104 } 105 106 static void pcibus_machine_done(Notifier *notifier, void *data) 107 { 108 PCIBus *bus = container_of(notifier, PCIBus, machine_done); 109 int i; 110 111 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 112 if (bus->devices[i]) { 113 pci_init_bus_master(bus->devices[i]); 114 } 115 } 116 } 117 118 static void pci_bus_realize(BusState *qbus, Error **errp) 119 { 120 PCIBus *bus = PCI_BUS(qbus); 121 122 bus->machine_done.notify = pcibus_machine_done; 123 qemu_add_machine_init_done_notifier(&bus->machine_done); 124 125 vmstate_register(NULL, VMSTATE_INSTANCE_ID_ANY, &vmstate_pcibus, bus); 126 } 127 128 static void pcie_bus_realize(BusState *qbus, Error **errp) 129 { 130 PCIBus *bus = PCI_BUS(qbus); 131 132 pci_bus_realize(qbus, errp); 133 134 /* 135 * A PCI-E bus can support extended config space if it's the root 136 * bus, or if the bus/bridge above it does as well 137 */ 138 if (pci_bus_is_root(bus)) { 139 bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE; 140 } else { 141 PCIBus *parent_bus = pci_get_bus(bus->parent_dev); 142 143 if (pci_bus_allows_extended_config_space(parent_bus)) { 144 bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE; 145 } 146 } 147 } 148 149 static void pci_bus_unrealize(BusState *qbus) 150 { 151 PCIBus *bus = PCI_BUS(qbus); 152 153 qemu_remove_machine_init_done_notifier(&bus->machine_done); 154 155 vmstate_unregister(NULL, &vmstate_pcibus, bus); 156 } 157 158 static int pcibus_num(PCIBus *bus) 159 { 160 if (pci_bus_is_root(bus)) { 161 return 0; /* pci host bridge */ 162 } 163 return bus->parent_dev->config[PCI_SECONDARY_BUS]; 164 } 165 166 static uint16_t pcibus_numa_node(PCIBus *bus) 167 { 168 return NUMA_NODE_UNASSIGNED; 169 } 170 171 static void pci_bus_class_init(ObjectClass *klass, void *data) 172 { 173 BusClass *k = BUS_CLASS(klass); 174 PCIBusClass *pbc = PCI_BUS_CLASS(klass); 175 176 k->print_dev = pcibus_dev_print; 177 k->get_dev_path = pcibus_get_dev_path; 178 k->get_fw_dev_path = pcibus_get_fw_dev_path; 179 k->realize = pci_bus_realize; 180 k->unrealize = pci_bus_unrealize; 181 k->reset = pcibus_reset; 182 183 pbc->bus_num = pcibus_num; 184 pbc->numa_node = pcibus_numa_node; 185 } 186 187 static const TypeInfo pci_bus_info = { 188 .name = TYPE_PCI_BUS, 189 .parent = TYPE_BUS, 190 .instance_size = sizeof(PCIBus), 191 .class_size = sizeof(PCIBusClass), 192 .class_init = pci_bus_class_init, 193 }; 194 195 static const TypeInfo pcie_interface_info = { 196 .name = INTERFACE_PCIE_DEVICE, 197 .parent = TYPE_INTERFACE, 198 }; 199 200 static const TypeInfo conventional_pci_interface_info = { 201 .name = INTERFACE_CONVENTIONAL_PCI_DEVICE, 202 .parent = TYPE_INTERFACE, 203 }; 204 205 static void pcie_bus_class_init(ObjectClass *klass, void *data) 206 { 207 BusClass *k = BUS_CLASS(klass); 208 209 k->realize = pcie_bus_realize; 210 } 211 212 static const TypeInfo pcie_bus_info = { 213 .name = TYPE_PCIE_BUS, 214 .parent = TYPE_PCI_BUS, 215 .class_init = pcie_bus_class_init, 216 }; 217 218 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num); 219 static void pci_update_mappings(PCIDevice *d); 220 static void pci_irq_handler(void *opaque, int irq_num, int level); 221 static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, Error **); 222 static void pci_del_option_rom(PCIDevice *pdev); 223 224 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET; 225 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU; 226 227 static QLIST_HEAD(, PCIHostState) pci_host_bridges; 228 229 int pci_bar(PCIDevice *d, int reg) 230 { 231 uint8_t type; 232 233 if (reg != PCI_ROM_SLOT) 234 return PCI_BASE_ADDRESS_0 + reg * 4; 235 236 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 237 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS; 238 } 239 240 static inline int pci_irq_state(PCIDevice *d, int irq_num) 241 { 242 return (d->irq_state >> irq_num) & 0x1; 243 } 244 245 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level) 246 { 247 d->irq_state &= ~(0x1 << irq_num); 248 d->irq_state |= level << irq_num; 249 } 250 251 static void pci_bus_change_irq_level(PCIBus *bus, int irq_num, int change) 252 { 253 assert(irq_num >= 0); 254 assert(irq_num < bus->nirq); 255 bus->irq_count[irq_num] += change; 256 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0); 257 } 258 259 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change) 260 { 261 PCIBus *bus; 262 for (;;) { 263 bus = pci_get_bus(pci_dev); 264 irq_num = bus->map_irq(pci_dev, irq_num); 265 if (bus->set_irq) 266 break; 267 pci_dev = bus->parent_dev; 268 } 269 pci_bus_change_irq_level(bus, irq_num, change); 270 } 271 272 int pci_bus_get_irq_level(PCIBus *bus, int irq_num) 273 { 274 assert(irq_num >= 0); 275 assert(irq_num < bus->nirq); 276 return !!bus->irq_count[irq_num]; 277 } 278 279 /* Update interrupt status bit in config space on interrupt 280 * state change. */ 281 static void pci_update_irq_status(PCIDevice *dev) 282 { 283 if (dev->irq_state) { 284 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT; 285 } else { 286 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; 287 } 288 } 289 290 void pci_device_deassert_intx(PCIDevice *dev) 291 { 292 int i; 293 for (i = 0; i < PCI_NUM_PINS; ++i) { 294 pci_irq_handler(dev, i, 0); 295 } 296 } 297 298 static void pci_do_device_reset(PCIDevice *dev) 299 { 300 int r; 301 302 pci_device_deassert_intx(dev); 303 assert(dev->irq_state == 0); 304 305 /* Clear all writable bits */ 306 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND, 307 pci_get_word(dev->wmask + PCI_COMMAND) | 308 pci_get_word(dev->w1cmask + PCI_COMMAND)); 309 pci_word_test_and_clear_mask(dev->config + PCI_STATUS, 310 pci_get_word(dev->wmask + PCI_STATUS) | 311 pci_get_word(dev->w1cmask + PCI_STATUS)); 312 /* Some devices make bits of PCI_INTERRUPT_LINE read only */ 313 pci_byte_test_and_clear_mask(dev->config + PCI_INTERRUPT_LINE, 314 pci_get_word(dev->wmask + PCI_INTERRUPT_LINE) | 315 pci_get_word(dev->w1cmask + PCI_INTERRUPT_LINE)); 316 dev->config[PCI_CACHE_LINE_SIZE] = 0x0; 317 for (r = 0; r < PCI_NUM_REGIONS; ++r) { 318 PCIIORegion *region = &dev->io_regions[r]; 319 if (!region->size) { 320 continue; 321 } 322 323 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) && 324 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 325 pci_set_quad(dev->config + pci_bar(dev, r), region->type); 326 } else { 327 pci_set_long(dev->config + pci_bar(dev, r), region->type); 328 } 329 } 330 pci_update_mappings(dev); 331 332 msi_reset(dev); 333 msix_reset(dev); 334 } 335 336 /* 337 * This function is called on #RST and FLR. 338 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set 339 */ 340 void pci_device_reset(PCIDevice *dev) 341 { 342 qdev_reset_all(&dev->qdev); 343 pci_do_device_reset(dev); 344 } 345 346 /* 347 * Trigger pci bus reset under a given bus. 348 * Called via qbus_reset_all on RST# assert, after the devices 349 * have been reset qdev_reset_all-ed already. 350 */ 351 static void pcibus_reset(BusState *qbus) 352 { 353 PCIBus *bus = DO_UPCAST(PCIBus, qbus, qbus); 354 int i; 355 356 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 357 if (bus->devices[i]) { 358 pci_do_device_reset(bus->devices[i]); 359 } 360 } 361 362 for (i = 0; i < bus->nirq; i++) { 363 assert(bus->irq_count[i] == 0); 364 } 365 } 366 367 static void pci_host_bus_register(DeviceState *host) 368 { 369 PCIHostState *host_bridge = PCI_HOST_BRIDGE(host); 370 371 QLIST_INSERT_HEAD(&pci_host_bridges, host_bridge, next); 372 } 373 374 static void pci_host_bus_unregister(DeviceState *host) 375 { 376 PCIHostState *host_bridge = PCI_HOST_BRIDGE(host); 377 378 QLIST_REMOVE(host_bridge, next); 379 } 380 381 PCIBus *pci_device_root_bus(const PCIDevice *d) 382 { 383 PCIBus *bus = pci_get_bus(d); 384 385 while (!pci_bus_is_root(bus)) { 386 d = bus->parent_dev; 387 assert(d != NULL); 388 389 bus = pci_get_bus(d); 390 } 391 392 return bus; 393 } 394 395 const char *pci_root_bus_path(PCIDevice *dev) 396 { 397 PCIBus *rootbus = pci_device_root_bus(dev); 398 PCIHostState *host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent); 399 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_GET_CLASS(host_bridge); 400 401 assert(host_bridge->bus == rootbus); 402 403 if (hc->root_bus_path) { 404 return (*hc->root_bus_path)(host_bridge, rootbus); 405 } 406 407 return rootbus->qbus.name; 408 } 409 410 static void pci_root_bus_init(PCIBus *bus, DeviceState *parent, 411 MemoryRegion *address_space_mem, 412 MemoryRegion *address_space_io, 413 uint8_t devfn_min) 414 { 415 assert(PCI_FUNC(devfn_min) == 0); 416 bus->devfn_min = devfn_min; 417 bus->slot_reserved_mask = 0x0; 418 bus->address_space_mem = address_space_mem; 419 bus->address_space_io = address_space_io; 420 bus->flags |= PCI_BUS_IS_ROOT; 421 422 /* host bridge */ 423 QLIST_INIT(&bus->child); 424 425 pci_host_bus_register(parent); 426 } 427 428 static void pci_bus_uninit(PCIBus *bus) 429 { 430 pci_host_bus_unregister(BUS(bus)->parent); 431 } 432 433 bool pci_bus_is_express(PCIBus *bus) 434 { 435 return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS); 436 } 437 438 void pci_root_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent, 439 const char *name, 440 MemoryRegion *address_space_mem, 441 MemoryRegion *address_space_io, 442 uint8_t devfn_min, const char *typename) 443 { 444 qbus_create_inplace(bus, bus_size, typename, parent, name); 445 pci_root_bus_init(bus, parent, address_space_mem, address_space_io, 446 devfn_min); 447 } 448 449 PCIBus *pci_root_bus_new(DeviceState *parent, const char *name, 450 MemoryRegion *address_space_mem, 451 MemoryRegion *address_space_io, 452 uint8_t devfn_min, const char *typename) 453 { 454 PCIBus *bus; 455 456 bus = PCI_BUS(qbus_create(typename, parent, name)); 457 pci_root_bus_init(bus, parent, address_space_mem, address_space_io, 458 devfn_min); 459 return bus; 460 } 461 462 void pci_root_bus_cleanup(PCIBus *bus) 463 { 464 pci_bus_uninit(bus); 465 /* the caller of the unplug hotplug handler will delete this device */ 466 qbus_unrealize(BUS(bus)); 467 } 468 469 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 470 void *irq_opaque, int nirq) 471 { 472 bus->set_irq = set_irq; 473 bus->map_irq = map_irq; 474 bus->irq_opaque = irq_opaque; 475 bus->nirq = nirq; 476 bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0])); 477 } 478 479 void pci_bus_irqs_cleanup(PCIBus *bus) 480 { 481 bus->set_irq = NULL; 482 bus->map_irq = NULL; 483 bus->irq_opaque = NULL; 484 bus->nirq = 0; 485 g_free(bus->irq_count); 486 } 487 488 PCIBus *pci_register_root_bus(DeviceState *parent, const char *name, 489 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 490 void *irq_opaque, 491 MemoryRegion *address_space_mem, 492 MemoryRegion *address_space_io, 493 uint8_t devfn_min, int nirq, 494 const char *typename) 495 { 496 PCIBus *bus; 497 498 bus = pci_root_bus_new(parent, name, address_space_mem, 499 address_space_io, devfn_min, typename); 500 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq); 501 return bus; 502 } 503 504 void pci_unregister_root_bus(PCIBus *bus) 505 { 506 pci_bus_irqs_cleanup(bus); 507 pci_root_bus_cleanup(bus); 508 } 509 510 int pci_bus_num(PCIBus *s) 511 { 512 return PCI_BUS_GET_CLASS(s)->bus_num(s); 513 } 514 515 int pci_bus_numa_node(PCIBus *bus) 516 { 517 return PCI_BUS_GET_CLASS(bus)->numa_node(bus); 518 } 519 520 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size, 521 const VMStateField *field) 522 { 523 PCIDevice *s = container_of(pv, PCIDevice, config); 524 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(s); 525 uint8_t *config; 526 int i; 527 528 assert(size == pci_config_size(s)); 529 config = g_malloc(size); 530 531 qemu_get_buffer(f, config, size); 532 for (i = 0; i < size; ++i) { 533 if ((config[i] ^ s->config[i]) & 534 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) { 535 error_report("%s: Bad config data: i=0x%x read: %x device: %x " 536 "cmask: %x wmask: %x w1cmask:%x", __func__, 537 i, config[i], s->config[i], 538 s->cmask[i], s->wmask[i], s->w1cmask[i]); 539 g_free(config); 540 return -EINVAL; 541 } 542 } 543 memcpy(s->config, config, size); 544 545 pci_update_mappings(s); 546 if (pc->is_bridge) { 547 PCIBridge *b = PCI_BRIDGE(s); 548 pci_bridge_update_mappings(b); 549 } 550 551 memory_region_set_enabled(&s->bus_master_enable_region, 552 pci_get_word(s->config + PCI_COMMAND) 553 & PCI_COMMAND_MASTER); 554 555 g_free(config); 556 return 0; 557 } 558 559 /* just put buffer */ 560 static int put_pci_config_device(QEMUFile *f, void *pv, size_t size, 561 const VMStateField *field, QJSON *vmdesc) 562 { 563 const uint8_t **v = pv; 564 assert(size == pci_config_size(container_of(pv, PCIDevice, config))); 565 qemu_put_buffer(f, *v, size); 566 567 return 0; 568 } 569 570 static VMStateInfo vmstate_info_pci_config = { 571 .name = "pci config", 572 .get = get_pci_config_device, 573 .put = put_pci_config_device, 574 }; 575 576 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size, 577 const VMStateField *field) 578 { 579 PCIDevice *s = container_of(pv, PCIDevice, irq_state); 580 uint32_t irq_state[PCI_NUM_PINS]; 581 int i; 582 for (i = 0; i < PCI_NUM_PINS; ++i) { 583 irq_state[i] = qemu_get_be32(f); 584 if (irq_state[i] != 0x1 && irq_state[i] != 0) { 585 fprintf(stderr, "irq state %d: must be 0 or 1.\n", 586 irq_state[i]); 587 return -EINVAL; 588 } 589 } 590 591 for (i = 0; i < PCI_NUM_PINS; ++i) { 592 pci_set_irq_state(s, i, irq_state[i]); 593 } 594 595 return 0; 596 } 597 598 static int put_pci_irq_state(QEMUFile *f, void *pv, size_t size, 599 const VMStateField *field, QJSON *vmdesc) 600 { 601 int i; 602 PCIDevice *s = container_of(pv, PCIDevice, irq_state); 603 604 for (i = 0; i < PCI_NUM_PINS; ++i) { 605 qemu_put_be32(f, pci_irq_state(s, i)); 606 } 607 608 return 0; 609 } 610 611 static VMStateInfo vmstate_info_pci_irq_state = { 612 .name = "pci irq state", 613 .get = get_pci_irq_state, 614 .put = put_pci_irq_state, 615 }; 616 617 static bool migrate_is_pcie(void *opaque, int version_id) 618 { 619 return pci_is_express((PCIDevice *)opaque); 620 } 621 622 static bool migrate_is_not_pcie(void *opaque, int version_id) 623 { 624 return !pci_is_express((PCIDevice *)opaque); 625 } 626 627 const VMStateDescription vmstate_pci_device = { 628 .name = "PCIDevice", 629 .version_id = 2, 630 .minimum_version_id = 1, 631 .fields = (VMStateField[]) { 632 VMSTATE_INT32_POSITIVE_LE(version_id, PCIDevice), 633 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice, 634 migrate_is_not_pcie, 635 0, vmstate_info_pci_config, 636 PCI_CONFIG_SPACE_SIZE), 637 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice, 638 migrate_is_pcie, 639 0, vmstate_info_pci_config, 640 PCIE_CONFIG_SPACE_SIZE), 641 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2, 642 vmstate_info_pci_irq_state, 643 PCI_NUM_PINS * sizeof(int32_t)), 644 VMSTATE_END_OF_LIST() 645 } 646 }; 647 648 649 void pci_device_save(PCIDevice *s, QEMUFile *f) 650 { 651 /* Clear interrupt status bit: it is implicit 652 * in irq_state which we are saving. 653 * This makes us compatible with old devices 654 * which never set or clear this bit. */ 655 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; 656 vmstate_save_state(f, &vmstate_pci_device, s, NULL); 657 /* Restore the interrupt status bit. */ 658 pci_update_irq_status(s); 659 } 660 661 int pci_device_load(PCIDevice *s, QEMUFile *f) 662 { 663 int ret; 664 ret = vmstate_load_state(f, &vmstate_pci_device, s, s->version_id); 665 /* Restore the interrupt status bit. */ 666 pci_update_irq_status(s); 667 return ret; 668 } 669 670 static void pci_set_default_subsystem_id(PCIDevice *pci_dev) 671 { 672 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, 673 pci_default_sub_vendor_id); 674 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 675 pci_default_sub_device_id); 676 } 677 678 /* 679 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL 680 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error 681 */ 682 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, 683 unsigned int *slotp, unsigned int *funcp) 684 { 685 const char *p; 686 char *e; 687 unsigned long val; 688 unsigned long dom = 0, bus = 0; 689 unsigned int slot = 0; 690 unsigned int func = 0; 691 692 p = addr; 693 val = strtoul(p, &e, 16); 694 if (e == p) 695 return -1; 696 if (*e == ':') { 697 bus = val; 698 p = e + 1; 699 val = strtoul(p, &e, 16); 700 if (e == p) 701 return -1; 702 if (*e == ':') { 703 dom = bus; 704 bus = val; 705 p = e + 1; 706 val = strtoul(p, &e, 16); 707 if (e == p) 708 return -1; 709 } 710 } 711 712 slot = val; 713 714 if (funcp != NULL) { 715 if (*e != '.') 716 return -1; 717 718 p = e + 1; 719 val = strtoul(p, &e, 16); 720 if (e == p) 721 return -1; 722 723 func = val; 724 } 725 726 /* if funcp == NULL func is 0 */ 727 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7) 728 return -1; 729 730 if (*e) 731 return -1; 732 733 *domp = dom; 734 *busp = bus; 735 *slotp = slot; 736 if (funcp != NULL) 737 *funcp = func; 738 return 0; 739 } 740 741 static void pci_init_cmask(PCIDevice *dev) 742 { 743 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff); 744 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff); 745 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST; 746 dev->cmask[PCI_REVISION_ID] = 0xff; 747 dev->cmask[PCI_CLASS_PROG] = 0xff; 748 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff); 749 dev->cmask[PCI_HEADER_TYPE] = 0xff; 750 dev->cmask[PCI_CAPABILITY_LIST] = 0xff; 751 } 752 753 static void pci_init_wmask(PCIDevice *dev) 754 { 755 int config_size = pci_config_size(dev); 756 757 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff; 758 dev->wmask[PCI_INTERRUPT_LINE] = 0xff; 759 pci_set_word(dev->wmask + PCI_COMMAND, 760 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | 761 PCI_COMMAND_INTX_DISABLE); 762 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR); 763 764 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff, 765 config_size - PCI_CONFIG_HEADER_SIZE); 766 } 767 768 static void pci_init_w1cmask(PCIDevice *dev) 769 { 770 /* 771 * Note: It's okay to set w1cmask even for readonly bits as 772 * long as their value is hardwired to 0. 773 */ 774 pci_set_word(dev->w1cmask + PCI_STATUS, 775 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT | 776 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT | 777 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY); 778 } 779 780 static void pci_init_mask_bridge(PCIDevice *d) 781 { 782 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and 783 PCI_SEC_LETENCY_TIMER */ 784 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4); 785 786 /* base and limit */ 787 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff; 788 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff; 789 pci_set_word(d->wmask + PCI_MEMORY_BASE, 790 PCI_MEMORY_RANGE_MASK & 0xffff); 791 pci_set_word(d->wmask + PCI_MEMORY_LIMIT, 792 PCI_MEMORY_RANGE_MASK & 0xffff); 793 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE, 794 PCI_PREF_RANGE_MASK & 0xffff); 795 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT, 796 PCI_PREF_RANGE_MASK & 0xffff); 797 798 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */ 799 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8); 800 801 /* Supported memory and i/o types */ 802 d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16; 803 d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16; 804 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE, 805 PCI_PREF_RANGE_TYPE_64); 806 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT, 807 PCI_PREF_RANGE_TYPE_64); 808 809 /* 810 * TODO: Bridges default to 10-bit VGA decoding but we currently only 811 * implement 16-bit decoding (no alias support). 812 */ 813 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 814 PCI_BRIDGE_CTL_PARITY | 815 PCI_BRIDGE_CTL_SERR | 816 PCI_BRIDGE_CTL_ISA | 817 PCI_BRIDGE_CTL_VGA | 818 PCI_BRIDGE_CTL_VGA_16BIT | 819 PCI_BRIDGE_CTL_MASTER_ABORT | 820 PCI_BRIDGE_CTL_BUS_RESET | 821 PCI_BRIDGE_CTL_FAST_BACK | 822 PCI_BRIDGE_CTL_DISCARD | 823 PCI_BRIDGE_CTL_SEC_DISCARD | 824 PCI_BRIDGE_CTL_DISCARD_SERR); 825 /* Below does not do anything as we never set this bit, put here for 826 * completeness. */ 827 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL, 828 PCI_BRIDGE_CTL_DISCARD_STATUS); 829 d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK; 830 d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK; 831 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE, 832 PCI_PREF_RANGE_TYPE_MASK); 833 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT, 834 PCI_PREF_RANGE_TYPE_MASK); 835 } 836 837 static void pci_init_multifunction(PCIBus *bus, PCIDevice *dev, Error **errp) 838 { 839 uint8_t slot = PCI_SLOT(dev->devfn); 840 uint8_t func; 841 842 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 843 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION; 844 } 845 846 /* 847 * multifunction bit is interpreted in two ways as follows. 848 * - all functions must set the bit to 1. 849 * Example: Intel X53 850 * - function 0 must set the bit, but the rest function (> 0) 851 * is allowed to leave the bit to 0. 852 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10, 853 * 854 * So OS (at least Linux) checks the bit of only function 0, 855 * and doesn't see the bit of function > 0. 856 * 857 * The below check allows both interpretation. 858 */ 859 if (PCI_FUNC(dev->devfn)) { 860 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)]; 861 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) { 862 /* function 0 should set multifunction bit */ 863 error_setg(errp, "PCI: single function device can't be populated " 864 "in function %x.%x", slot, PCI_FUNC(dev->devfn)); 865 return; 866 } 867 return; 868 } 869 870 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 871 return; 872 } 873 /* function 0 indicates single function, so function > 0 must be NULL */ 874 for (func = 1; func < PCI_FUNC_MAX; ++func) { 875 if (bus->devices[PCI_DEVFN(slot, func)]) { 876 error_setg(errp, "PCI: %x.0 indicates single function, " 877 "but %x.%x is already populated.", 878 slot, slot, func); 879 return; 880 } 881 } 882 } 883 884 static void pci_config_alloc(PCIDevice *pci_dev) 885 { 886 int config_size = pci_config_size(pci_dev); 887 888 pci_dev->config = g_malloc0(config_size); 889 pci_dev->cmask = g_malloc0(config_size); 890 pci_dev->wmask = g_malloc0(config_size); 891 pci_dev->w1cmask = g_malloc0(config_size); 892 pci_dev->used = g_malloc0(config_size); 893 } 894 895 static void pci_config_free(PCIDevice *pci_dev) 896 { 897 g_free(pci_dev->config); 898 g_free(pci_dev->cmask); 899 g_free(pci_dev->wmask); 900 g_free(pci_dev->w1cmask); 901 g_free(pci_dev->used); 902 } 903 904 static void do_pci_unregister_device(PCIDevice *pci_dev) 905 { 906 pci_get_bus(pci_dev)->devices[pci_dev->devfn] = NULL; 907 pci_config_free(pci_dev); 908 909 if (memory_region_is_mapped(&pci_dev->bus_master_enable_region)) { 910 memory_region_del_subregion(&pci_dev->bus_master_container_region, 911 &pci_dev->bus_master_enable_region); 912 } 913 address_space_destroy(&pci_dev->bus_master_as); 914 } 915 916 /* Extract PCIReqIDCache into BDF format */ 917 static uint16_t pci_req_id_cache_extract(PCIReqIDCache *cache) 918 { 919 uint8_t bus_n; 920 uint16_t result; 921 922 switch (cache->type) { 923 case PCI_REQ_ID_BDF: 924 result = pci_get_bdf(cache->dev); 925 break; 926 case PCI_REQ_ID_SECONDARY_BUS: 927 bus_n = pci_dev_bus_num(cache->dev); 928 result = PCI_BUILD_BDF(bus_n, 0); 929 break; 930 default: 931 error_report("Invalid PCI requester ID cache type: %d", 932 cache->type); 933 exit(1); 934 break; 935 } 936 937 return result; 938 } 939 940 /* Parse bridges up to the root complex and return requester ID 941 * cache for specific device. For full PCIe topology, the cache 942 * result would be exactly the same as getting BDF of the device. 943 * However, several tricks are required when system mixed up with 944 * legacy PCI devices and PCIe-to-PCI bridges. 945 * 946 * Here we cache the proxy device (and type) not requester ID since 947 * bus number might change from time to time. 948 */ 949 static PCIReqIDCache pci_req_id_cache_get(PCIDevice *dev) 950 { 951 PCIDevice *parent; 952 PCIReqIDCache cache = { 953 .dev = dev, 954 .type = PCI_REQ_ID_BDF, 955 }; 956 957 while (!pci_bus_is_root(pci_get_bus(dev))) { 958 /* We are under PCI/PCIe bridges */ 959 parent = pci_get_bus(dev)->parent_dev; 960 if (pci_is_express(parent)) { 961 if (pcie_cap_get_type(parent) == PCI_EXP_TYPE_PCI_BRIDGE) { 962 /* When we pass through PCIe-to-PCI/PCIX bridges, we 963 * override the requester ID using secondary bus 964 * number of parent bridge with zeroed devfn 965 * (pcie-to-pci bridge spec chap 2.3). */ 966 cache.type = PCI_REQ_ID_SECONDARY_BUS; 967 cache.dev = dev; 968 } 969 } else { 970 /* Legacy PCI, override requester ID with the bridge's 971 * BDF upstream. When the root complex connects to 972 * legacy PCI devices (including buses), it can only 973 * obtain requester ID info from directly attached 974 * devices. If devices are attached under bridges, only 975 * the requester ID of the bridge that is directly 976 * attached to the root complex can be recognized. */ 977 cache.type = PCI_REQ_ID_BDF; 978 cache.dev = parent; 979 } 980 dev = parent; 981 } 982 983 return cache; 984 } 985 986 uint16_t pci_requester_id(PCIDevice *dev) 987 { 988 return pci_req_id_cache_extract(&dev->requester_id_cache); 989 } 990 991 static bool pci_bus_devfn_available(PCIBus *bus, int devfn) 992 { 993 return !(bus->devices[devfn]); 994 } 995 996 static bool pci_bus_devfn_reserved(PCIBus *bus, int devfn) 997 { 998 return bus->slot_reserved_mask & (1UL << PCI_SLOT(devfn)); 999 } 1000 1001 /* -1 for devfn means auto assign */ 1002 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, 1003 const char *name, int devfn, 1004 Error **errp) 1005 { 1006 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 1007 PCIConfigReadFunc *config_read = pc->config_read; 1008 PCIConfigWriteFunc *config_write = pc->config_write; 1009 Error *local_err = NULL; 1010 DeviceState *dev = DEVICE(pci_dev); 1011 PCIBus *bus = pci_get_bus(pci_dev); 1012 1013 /* Only pci bridges can be attached to extra PCI root buses */ 1014 if (pci_bus_is_root(bus) && bus->parent_dev && !pc->is_bridge) { 1015 error_setg(errp, 1016 "PCI: Only PCI/PCIe bridges can be plugged into %s", 1017 bus->parent_dev->name); 1018 return NULL; 1019 } 1020 1021 if (devfn < 0) { 1022 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices); 1023 devfn += PCI_FUNC_MAX) { 1024 if (pci_bus_devfn_available(bus, devfn) && 1025 !pci_bus_devfn_reserved(bus, devfn)) { 1026 goto found; 1027 } 1028 } 1029 error_setg(errp, "PCI: no slot/function available for %s, all in use " 1030 "or reserved", name); 1031 return NULL; 1032 found: ; 1033 } else if (pci_bus_devfn_reserved(bus, devfn)) { 1034 error_setg(errp, "PCI: slot %d function %d not available for %s," 1035 " reserved", 1036 PCI_SLOT(devfn), PCI_FUNC(devfn), name); 1037 return NULL; 1038 } else if (!pci_bus_devfn_available(bus, devfn)) { 1039 error_setg(errp, "PCI: slot %d function %d not available for %s," 1040 " in use by %s", 1041 PCI_SLOT(devfn), PCI_FUNC(devfn), name, 1042 bus->devices[devfn]->name); 1043 return NULL; 1044 } else if (dev->hotplugged && 1045 pci_get_function_0(pci_dev)) { 1046 error_setg(errp, "PCI: slot %d function 0 already occupied by %s," 1047 " new func %s cannot be exposed to guest.", 1048 PCI_SLOT(pci_get_function_0(pci_dev)->devfn), 1049 pci_get_function_0(pci_dev)->name, 1050 name); 1051 1052 return NULL; 1053 } 1054 1055 pci_dev->devfn = devfn; 1056 pci_dev->requester_id_cache = pci_req_id_cache_get(pci_dev); 1057 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name); 1058 1059 memory_region_init(&pci_dev->bus_master_container_region, OBJECT(pci_dev), 1060 "bus master container", UINT64_MAX); 1061 address_space_init(&pci_dev->bus_master_as, 1062 &pci_dev->bus_master_container_region, pci_dev->name); 1063 1064 if (qdev_hotplug) { 1065 pci_init_bus_master(pci_dev); 1066 } 1067 pci_dev->irq_state = 0; 1068 pci_config_alloc(pci_dev); 1069 1070 pci_config_set_vendor_id(pci_dev->config, pc->vendor_id); 1071 pci_config_set_device_id(pci_dev->config, pc->device_id); 1072 pci_config_set_revision(pci_dev->config, pc->revision); 1073 pci_config_set_class(pci_dev->config, pc->class_id); 1074 1075 if (!pc->is_bridge) { 1076 if (pc->subsystem_vendor_id || pc->subsystem_id) { 1077 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, 1078 pc->subsystem_vendor_id); 1079 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 1080 pc->subsystem_id); 1081 } else { 1082 pci_set_default_subsystem_id(pci_dev); 1083 } 1084 } else { 1085 /* subsystem_vendor_id/subsystem_id are only for header type 0 */ 1086 assert(!pc->subsystem_vendor_id); 1087 assert(!pc->subsystem_id); 1088 } 1089 pci_init_cmask(pci_dev); 1090 pci_init_wmask(pci_dev); 1091 pci_init_w1cmask(pci_dev); 1092 if (pc->is_bridge) { 1093 pci_init_mask_bridge(pci_dev); 1094 } 1095 pci_init_multifunction(bus, pci_dev, &local_err); 1096 if (local_err) { 1097 error_propagate(errp, local_err); 1098 do_pci_unregister_device(pci_dev); 1099 return NULL; 1100 } 1101 1102 if (!config_read) 1103 config_read = pci_default_read_config; 1104 if (!config_write) 1105 config_write = pci_default_write_config; 1106 pci_dev->config_read = config_read; 1107 pci_dev->config_write = config_write; 1108 bus->devices[devfn] = pci_dev; 1109 pci_dev->version_id = 2; /* Current pci device vmstate version */ 1110 return pci_dev; 1111 } 1112 1113 static void pci_unregister_io_regions(PCIDevice *pci_dev) 1114 { 1115 PCIIORegion *r; 1116 int i; 1117 1118 for(i = 0; i < PCI_NUM_REGIONS; i++) { 1119 r = &pci_dev->io_regions[i]; 1120 if (!r->size || r->addr == PCI_BAR_UNMAPPED) 1121 continue; 1122 memory_region_del_subregion(r->address_space, r->memory); 1123 } 1124 1125 pci_unregister_vga(pci_dev); 1126 } 1127 1128 static void pci_qdev_unrealize(DeviceState *dev) 1129 { 1130 PCIDevice *pci_dev = PCI_DEVICE(dev); 1131 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 1132 1133 pci_unregister_io_regions(pci_dev); 1134 pci_del_option_rom(pci_dev); 1135 1136 if (pc->exit) { 1137 pc->exit(pci_dev); 1138 } 1139 1140 pci_device_deassert_intx(pci_dev); 1141 do_pci_unregister_device(pci_dev); 1142 } 1143 1144 void pci_register_bar(PCIDevice *pci_dev, int region_num, 1145 uint8_t type, MemoryRegion *memory) 1146 { 1147 PCIIORegion *r; 1148 uint32_t addr; /* offset in pci config space */ 1149 uint64_t wmask; 1150 pcibus_t size = memory_region_size(memory); 1151 uint8_t hdr_type; 1152 1153 assert(region_num >= 0); 1154 assert(region_num < PCI_NUM_REGIONS); 1155 assert(is_power_of_2(size)); 1156 1157 /* A PCI bridge device (with Type 1 header) may only have at most 2 BARs */ 1158 hdr_type = 1159 pci_dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 1160 assert(hdr_type != PCI_HEADER_TYPE_BRIDGE || region_num < 2); 1161 1162 r = &pci_dev->io_regions[region_num]; 1163 r->addr = PCI_BAR_UNMAPPED; 1164 r->size = size; 1165 r->type = type; 1166 r->memory = memory; 1167 r->address_space = type & PCI_BASE_ADDRESS_SPACE_IO 1168 ? pci_get_bus(pci_dev)->address_space_io 1169 : pci_get_bus(pci_dev)->address_space_mem; 1170 1171 wmask = ~(size - 1); 1172 if (region_num == PCI_ROM_SLOT) { 1173 /* ROM enable bit is writable */ 1174 wmask |= PCI_ROM_ADDRESS_ENABLE; 1175 } 1176 1177 addr = pci_bar(pci_dev, region_num); 1178 pci_set_long(pci_dev->config + addr, type); 1179 1180 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) && 1181 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 1182 pci_set_quad(pci_dev->wmask + addr, wmask); 1183 pci_set_quad(pci_dev->cmask + addr, ~0ULL); 1184 } else { 1185 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff); 1186 pci_set_long(pci_dev->cmask + addr, 0xffffffff); 1187 } 1188 } 1189 1190 static void pci_update_vga(PCIDevice *pci_dev) 1191 { 1192 uint16_t cmd; 1193 1194 if (!pci_dev->has_vga) { 1195 return; 1196 } 1197 1198 cmd = pci_get_word(pci_dev->config + PCI_COMMAND); 1199 1200 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_MEM], 1201 cmd & PCI_COMMAND_MEMORY); 1202 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO], 1203 cmd & PCI_COMMAND_IO); 1204 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI], 1205 cmd & PCI_COMMAND_IO); 1206 } 1207 1208 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, 1209 MemoryRegion *io_lo, MemoryRegion *io_hi) 1210 { 1211 PCIBus *bus = pci_get_bus(pci_dev); 1212 1213 assert(!pci_dev->has_vga); 1214 1215 assert(memory_region_size(mem) == QEMU_PCI_VGA_MEM_SIZE); 1216 pci_dev->vga_regions[QEMU_PCI_VGA_MEM] = mem; 1217 memory_region_add_subregion_overlap(bus->address_space_mem, 1218 QEMU_PCI_VGA_MEM_BASE, mem, 1); 1219 1220 assert(memory_region_size(io_lo) == QEMU_PCI_VGA_IO_LO_SIZE); 1221 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO] = io_lo; 1222 memory_region_add_subregion_overlap(bus->address_space_io, 1223 QEMU_PCI_VGA_IO_LO_BASE, io_lo, 1); 1224 1225 assert(memory_region_size(io_hi) == QEMU_PCI_VGA_IO_HI_SIZE); 1226 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI] = io_hi; 1227 memory_region_add_subregion_overlap(bus->address_space_io, 1228 QEMU_PCI_VGA_IO_HI_BASE, io_hi, 1); 1229 pci_dev->has_vga = true; 1230 1231 pci_update_vga(pci_dev); 1232 } 1233 1234 void pci_unregister_vga(PCIDevice *pci_dev) 1235 { 1236 PCIBus *bus = pci_get_bus(pci_dev); 1237 1238 if (!pci_dev->has_vga) { 1239 return; 1240 } 1241 1242 memory_region_del_subregion(bus->address_space_mem, 1243 pci_dev->vga_regions[QEMU_PCI_VGA_MEM]); 1244 memory_region_del_subregion(bus->address_space_io, 1245 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO]); 1246 memory_region_del_subregion(bus->address_space_io, 1247 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI]); 1248 pci_dev->has_vga = false; 1249 } 1250 1251 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num) 1252 { 1253 return pci_dev->io_regions[region_num].addr; 1254 } 1255 1256 static pcibus_t pci_bar_address(PCIDevice *d, 1257 int reg, uint8_t type, pcibus_t size) 1258 { 1259 pcibus_t new_addr, last_addr; 1260 int bar = pci_bar(d, reg); 1261 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND); 1262 Object *machine = qdev_get_machine(); 1263 ObjectClass *oc = object_get_class(machine); 1264 MachineClass *mc = MACHINE_CLASS(oc); 1265 bool allow_0_address = mc->pci_allow_0_address; 1266 1267 if (type & PCI_BASE_ADDRESS_SPACE_IO) { 1268 if (!(cmd & PCI_COMMAND_IO)) { 1269 return PCI_BAR_UNMAPPED; 1270 } 1271 new_addr = pci_get_long(d->config + bar) & ~(size - 1); 1272 last_addr = new_addr + size - 1; 1273 /* Check if 32 bit BAR wraps around explicitly. 1274 * TODO: make priorities correct and remove this work around. 1275 */ 1276 if (last_addr <= new_addr || last_addr >= UINT32_MAX || 1277 (!allow_0_address && new_addr == 0)) { 1278 return PCI_BAR_UNMAPPED; 1279 } 1280 return new_addr; 1281 } 1282 1283 if (!(cmd & PCI_COMMAND_MEMORY)) { 1284 return PCI_BAR_UNMAPPED; 1285 } 1286 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 1287 new_addr = pci_get_quad(d->config + bar); 1288 } else { 1289 new_addr = pci_get_long(d->config + bar); 1290 } 1291 /* the ROM slot has a specific enable bit */ 1292 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) { 1293 return PCI_BAR_UNMAPPED; 1294 } 1295 new_addr &= ~(size - 1); 1296 last_addr = new_addr + size - 1; 1297 /* NOTE: we do not support wrapping */ 1298 /* XXX: as we cannot support really dynamic 1299 mappings, we handle specific values as invalid 1300 mappings. */ 1301 if (last_addr <= new_addr || last_addr == PCI_BAR_UNMAPPED || 1302 (!allow_0_address && new_addr == 0)) { 1303 return PCI_BAR_UNMAPPED; 1304 } 1305 1306 /* Now pcibus_t is 64bit. 1307 * Check if 32 bit BAR wraps around explicitly. 1308 * Without this, PC ide doesn't work well. 1309 * TODO: remove this work around. 1310 */ 1311 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) { 1312 return PCI_BAR_UNMAPPED; 1313 } 1314 1315 /* 1316 * OS is allowed to set BAR beyond its addressable 1317 * bits. For example, 32 bit OS can set 64bit bar 1318 * to >4G. Check it. TODO: we might need to support 1319 * it in the future for e.g. PAE. 1320 */ 1321 if (last_addr >= HWADDR_MAX) { 1322 return PCI_BAR_UNMAPPED; 1323 } 1324 1325 return new_addr; 1326 } 1327 1328 static void pci_update_mappings(PCIDevice *d) 1329 { 1330 PCIIORegion *r; 1331 int i; 1332 pcibus_t new_addr; 1333 1334 for(i = 0; i < PCI_NUM_REGIONS; i++) { 1335 r = &d->io_regions[i]; 1336 1337 /* this region isn't registered */ 1338 if (!r->size) 1339 continue; 1340 1341 new_addr = pci_bar_address(d, i, r->type, r->size); 1342 1343 /* This bar isn't changed */ 1344 if (new_addr == r->addr) 1345 continue; 1346 1347 /* now do the real mapping */ 1348 if (r->addr != PCI_BAR_UNMAPPED) { 1349 trace_pci_update_mappings_del(d, pci_dev_bus_num(d), 1350 PCI_SLOT(d->devfn), 1351 PCI_FUNC(d->devfn), 1352 i, r->addr, r->size); 1353 memory_region_del_subregion(r->address_space, r->memory); 1354 } 1355 r->addr = new_addr; 1356 if (r->addr != PCI_BAR_UNMAPPED) { 1357 trace_pci_update_mappings_add(d, pci_dev_bus_num(d), 1358 PCI_SLOT(d->devfn), 1359 PCI_FUNC(d->devfn), 1360 i, r->addr, r->size); 1361 memory_region_add_subregion_overlap(r->address_space, 1362 r->addr, r->memory, 1); 1363 } 1364 } 1365 1366 pci_update_vga(d); 1367 } 1368 1369 static inline int pci_irq_disabled(PCIDevice *d) 1370 { 1371 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE; 1372 } 1373 1374 /* Called after interrupt disabled field update in config space, 1375 * assert/deassert interrupts if necessary. 1376 * Gets original interrupt disable bit value (before update). */ 1377 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled) 1378 { 1379 int i, disabled = pci_irq_disabled(d); 1380 if (disabled == was_irq_disabled) 1381 return; 1382 for (i = 0; i < PCI_NUM_PINS; ++i) { 1383 int state = pci_irq_state(d, i); 1384 pci_change_irq_level(d, i, disabled ? -state : state); 1385 } 1386 } 1387 1388 uint32_t pci_default_read_config(PCIDevice *d, 1389 uint32_t address, int len) 1390 { 1391 uint32_t val = 0; 1392 1393 assert(address + len <= pci_config_size(d)); 1394 1395 if (pci_is_express_downstream_port(d) && 1396 ranges_overlap(address, len, d->exp.exp_cap + PCI_EXP_LNKSTA, 2)) { 1397 pcie_sync_bridge_lnk(d); 1398 } 1399 memcpy(&val, d->config + address, len); 1400 return le32_to_cpu(val); 1401 } 1402 1403 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val_in, int l) 1404 { 1405 int i, was_irq_disabled = pci_irq_disabled(d); 1406 uint32_t val = val_in; 1407 1408 assert(addr + l <= pci_config_size(d)); 1409 1410 for (i = 0; i < l; val >>= 8, ++i) { 1411 uint8_t wmask = d->wmask[addr + i]; 1412 uint8_t w1cmask = d->w1cmask[addr + i]; 1413 assert(!(wmask & w1cmask)); 1414 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask); 1415 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */ 1416 } 1417 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) || 1418 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) || 1419 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) || 1420 range_covers_byte(addr, l, PCI_COMMAND)) 1421 pci_update_mappings(d); 1422 1423 if (range_covers_byte(addr, l, PCI_COMMAND)) { 1424 pci_update_irq_disabled(d, was_irq_disabled); 1425 memory_region_set_enabled(&d->bus_master_enable_region, 1426 pci_get_word(d->config + PCI_COMMAND) 1427 & PCI_COMMAND_MASTER); 1428 } 1429 1430 msi_write_config(d, addr, val_in, l); 1431 msix_write_config(d, addr, val_in, l); 1432 } 1433 1434 /***********************************************************/ 1435 /* generic PCI irq support */ 1436 1437 /* 0 <= irq_num <= 3. level must be 0 or 1 */ 1438 static void pci_irq_handler(void *opaque, int irq_num, int level) 1439 { 1440 PCIDevice *pci_dev = opaque; 1441 int change; 1442 1443 change = level - pci_irq_state(pci_dev, irq_num); 1444 if (!change) 1445 return; 1446 1447 pci_set_irq_state(pci_dev, irq_num, level); 1448 pci_update_irq_status(pci_dev); 1449 if (pci_irq_disabled(pci_dev)) 1450 return; 1451 pci_change_irq_level(pci_dev, irq_num, change); 1452 } 1453 1454 static inline int pci_intx(PCIDevice *pci_dev) 1455 { 1456 return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1; 1457 } 1458 1459 qemu_irq pci_allocate_irq(PCIDevice *pci_dev) 1460 { 1461 int intx = pci_intx(pci_dev); 1462 1463 return qemu_allocate_irq(pci_irq_handler, pci_dev, intx); 1464 } 1465 1466 void pci_set_irq(PCIDevice *pci_dev, int level) 1467 { 1468 int intx = pci_intx(pci_dev); 1469 pci_irq_handler(pci_dev, intx, level); 1470 } 1471 1472 /* Special hooks used by device assignment */ 1473 void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq) 1474 { 1475 assert(pci_bus_is_root(bus)); 1476 bus->route_intx_to_irq = route_intx_to_irq; 1477 } 1478 1479 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin) 1480 { 1481 PCIBus *bus; 1482 1483 do { 1484 bus = pci_get_bus(dev); 1485 pin = bus->map_irq(dev, pin); 1486 dev = bus->parent_dev; 1487 } while (dev); 1488 1489 if (!bus->route_intx_to_irq) { 1490 error_report("PCI: Bug - unimplemented PCI INTx routing (%s)", 1491 object_get_typename(OBJECT(bus->qbus.parent))); 1492 return (PCIINTxRoute) { PCI_INTX_DISABLED, -1 }; 1493 } 1494 1495 return bus->route_intx_to_irq(bus->irq_opaque, pin); 1496 } 1497 1498 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new) 1499 { 1500 return old->mode != new->mode || old->irq != new->irq; 1501 } 1502 1503 void pci_bus_fire_intx_routing_notifier(PCIBus *bus) 1504 { 1505 PCIDevice *dev; 1506 PCIBus *sec; 1507 int i; 1508 1509 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 1510 dev = bus->devices[i]; 1511 if (dev && dev->intx_routing_notifier) { 1512 dev->intx_routing_notifier(dev); 1513 } 1514 } 1515 1516 QLIST_FOREACH(sec, &bus->child, sibling) { 1517 pci_bus_fire_intx_routing_notifier(sec); 1518 } 1519 } 1520 1521 void pci_device_set_intx_routing_notifier(PCIDevice *dev, 1522 PCIINTxRoutingNotifier notifier) 1523 { 1524 dev->intx_routing_notifier = notifier; 1525 } 1526 1527 /* 1528 * PCI-to-PCI bridge specification 1529 * 9.1: Interrupt routing. Table 9-1 1530 * 1531 * the PCI Express Base Specification, Revision 2.1 1532 * 2.2.8.1: INTx interrutp signaling - Rules 1533 * the Implementation Note 1534 * Table 2-20 1535 */ 1536 /* 1537 * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD 1538 * 0-origin unlike PCI interrupt pin register. 1539 */ 1540 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin) 1541 { 1542 return pci_swizzle(PCI_SLOT(pci_dev->devfn), pin); 1543 } 1544 1545 /***********************************************************/ 1546 /* monitor info on PCI */ 1547 1548 typedef struct { 1549 uint16_t class; 1550 const char *desc; 1551 const char *fw_name; 1552 uint16_t fw_ign_bits; 1553 } pci_class_desc; 1554 1555 static const pci_class_desc pci_class_descriptions[] = 1556 { 1557 { 0x0001, "VGA controller", "display"}, 1558 { 0x0100, "SCSI controller", "scsi"}, 1559 { 0x0101, "IDE controller", "ide"}, 1560 { 0x0102, "Floppy controller", "fdc"}, 1561 { 0x0103, "IPI controller", "ipi"}, 1562 { 0x0104, "RAID controller", "raid"}, 1563 { 0x0106, "SATA controller"}, 1564 { 0x0107, "SAS controller"}, 1565 { 0x0180, "Storage controller"}, 1566 { 0x0200, "Ethernet controller", "ethernet"}, 1567 { 0x0201, "Token Ring controller", "token-ring"}, 1568 { 0x0202, "FDDI controller", "fddi"}, 1569 { 0x0203, "ATM controller", "atm"}, 1570 { 0x0280, "Network controller"}, 1571 { 0x0300, "VGA controller", "display", 0x00ff}, 1572 { 0x0301, "XGA controller"}, 1573 { 0x0302, "3D controller"}, 1574 { 0x0380, "Display controller"}, 1575 { 0x0400, "Video controller", "video"}, 1576 { 0x0401, "Audio controller", "sound"}, 1577 { 0x0402, "Phone"}, 1578 { 0x0403, "Audio controller", "sound"}, 1579 { 0x0480, "Multimedia controller"}, 1580 { 0x0500, "RAM controller", "memory"}, 1581 { 0x0501, "Flash controller", "flash"}, 1582 { 0x0580, "Memory controller"}, 1583 { 0x0600, "Host bridge", "host"}, 1584 { 0x0601, "ISA bridge", "isa"}, 1585 { 0x0602, "EISA bridge", "eisa"}, 1586 { 0x0603, "MC bridge", "mca"}, 1587 { 0x0604, "PCI bridge", "pci-bridge"}, 1588 { 0x0605, "PCMCIA bridge", "pcmcia"}, 1589 { 0x0606, "NUBUS bridge", "nubus"}, 1590 { 0x0607, "CARDBUS bridge", "cardbus"}, 1591 { 0x0608, "RACEWAY bridge"}, 1592 { 0x0680, "Bridge"}, 1593 { 0x0700, "Serial port", "serial"}, 1594 { 0x0701, "Parallel port", "parallel"}, 1595 { 0x0800, "Interrupt controller", "interrupt-controller"}, 1596 { 0x0801, "DMA controller", "dma-controller"}, 1597 { 0x0802, "Timer", "timer"}, 1598 { 0x0803, "RTC", "rtc"}, 1599 { 0x0900, "Keyboard", "keyboard"}, 1600 { 0x0901, "Pen", "pen"}, 1601 { 0x0902, "Mouse", "mouse"}, 1602 { 0x0A00, "Dock station", "dock", 0x00ff}, 1603 { 0x0B00, "i386 cpu", "cpu", 0x00ff}, 1604 { 0x0c00, "Fireware contorller", "fireware"}, 1605 { 0x0c01, "Access bus controller", "access-bus"}, 1606 { 0x0c02, "SSA controller", "ssa"}, 1607 { 0x0c03, "USB controller", "usb"}, 1608 { 0x0c04, "Fibre channel controller", "fibre-channel"}, 1609 { 0x0c05, "SMBus"}, 1610 { 0, NULL} 1611 }; 1612 1613 static void pci_for_each_device_under_bus_reverse(PCIBus *bus, 1614 void (*fn)(PCIBus *b, 1615 PCIDevice *d, 1616 void *opaque), 1617 void *opaque) 1618 { 1619 PCIDevice *d; 1620 int devfn; 1621 1622 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1623 d = bus->devices[ARRAY_SIZE(bus->devices) - 1 - devfn]; 1624 if (d) { 1625 fn(bus, d, opaque); 1626 } 1627 } 1628 } 1629 1630 void pci_for_each_device_reverse(PCIBus *bus, int bus_num, 1631 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque), 1632 void *opaque) 1633 { 1634 bus = pci_find_bus_nr(bus, bus_num); 1635 1636 if (bus) { 1637 pci_for_each_device_under_bus_reverse(bus, fn, opaque); 1638 } 1639 } 1640 1641 static void pci_for_each_device_under_bus(PCIBus *bus, 1642 void (*fn)(PCIBus *b, PCIDevice *d, 1643 void *opaque), 1644 void *opaque) 1645 { 1646 PCIDevice *d; 1647 int devfn; 1648 1649 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1650 d = bus->devices[devfn]; 1651 if (d) { 1652 fn(bus, d, opaque); 1653 } 1654 } 1655 } 1656 1657 void pci_for_each_device(PCIBus *bus, int bus_num, 1658 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque), 1659 void *opaque) 1660 { 1661 bus = pci_find_bus_nr(bus, bus_num); 1662 1663 if (bus) { 1664 pci_for_each_device_under_bus(bus, fn, opaque); 1665 } 1666 } 1667 1668 static const pci_class_desc *get_class_desc(int class) 1669 { 1670 const pci_class_desc *desc; 1671 1672 desc = pci_class_descriptions; 1673 while (desc->desc && class != desc->class) { 1674 desc++; 1675 } 1676 1677 return desc; 1678 } 1679 1680 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num); 1681 1682 static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev) 1683 { 1684 PciMemoryRegionList *head = NULL, *cur_item = NULL; 1685 int i; 1686 1687 for (i = 0; i < PCI_NUM_REGIONS; i++) { 1688 const PCIIORegion *r = &dev->io_regions[i]; 1689 PciMemoryRegionList *region; 1690 1691 if (!r->size) { 1692 continue; 1693 } 1694 1695 region = g_malloc0(sizeof(*region)); 1696 region->value = g_malloc0(sizeof(*region->value)); 1697 1698 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { 1699 region->value->type = g_strdup("io"); 1700 } else { 1701 region->value->type = g_strdup("memory"); 1702 region->value->has_prefetch = true; 1703 region->value->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH); 1704 region->value->has_mem_type_64 = true; 1705 region->value->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64); 1706 } 1707 1708 region->value->bar = i; 1709 region->value->address = r->addr; 1710 region->value->size = r->size; 1711 1712 /* XXX: waiting for the qapi to support GSList */ 1713 if (!cur_item) { 1714 head = cur_item = region; 1715 } else { 1716 cur_item->next = region; 1717 cur_item = region; 1718 } 1719 } 1720 1721 return head; 1722 } 1723 1724 static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus, 1725 int bus_num) 1726 { 1727 PciBridgeInfo *info; 1728 PciMemoryRange *range; 1729 1730 info = g_new0(PciBridgeInfo, 1); 1731 1732 info->bus = g_new0(PciBusInfo, 1); 1733 info->bus->number = dev->config[PCI_PRIMARY_BUS]; 1734 info->bus->secondary = dev->config[PCI_SECONDARY_BUS]; 1735 info->bus->subordinate = dev->config[PCI_SUBORDINATE_BUS]; 1736 1737 range = info->bus->io_range = g_new0(PciMemoryRange, 1); 1738 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO); 1739 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO); 1740 1741 range = info->bus->memory_range = g_new0(PciMemoryRange, 1); 1742 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 1743 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 1744 1745 range = info->bus->prefetchable_range = g_new0(PciMemoryRange, 1); 1746 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 1747 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 1748 1749 if (dev->config[PCI_SECONDARY_BUS] != 0) { 1750 PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]); 1751 if (child_bus) { 1752 info->has_devices = true; 1753 info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]); 1754 } 1755 } 1756 1757 return info; 1758 } 1759 1760 static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus, 1761 int bus_num) 1762 { 1763 const pci_class_desc *desc; 1764 PciDeviceInfo *info; 1765 uint8_t type; 1766 int class; 1767 1768 info = g_new0(PciDeviceInfo, 1); 1769 info->bus = bus_num; 1770 info->slot = PCI_SLOT(dev->devfn); 1771 info->function = PCI_FUNC(dev->devfn); 1772 1773 info->class_info = g_new0(PciDeviceClass, 1); 1774 class = pci_get_word(dev->config + PCI_CLASS_DEVICE); 1775 info->class_info->q_class = class; 1776 desc = get_class_desc(class); 1777 if (desc->desc) { 1778 info->class_info->has_desc = true; 1779 info->class_info->desc = g_strdup(desc->desc); 1780 } 1781 1782 info->id = g_new0(PciDeviceId, 1); 1783 info->id->vendor = pci_get_word(dev->config + PCI_VENDOR_ID); 1784 info->id->device = pci_get_word(dev->config + PCI_DEVICE_ID); 1785 info->regions = qmp_query_pci_regions(dev); 1786 info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : ""); 1787 1788 info->irq_pin = dev->config[PCI_INTERRUPT_PIN]; 1789 if (dev->config[PCI_INTERRUPT_PIN] != 0) { 1790 info->has_irq = true; 1791 info->irq = dev->config[PCI_INTERRUPT_LINE]; 1792 } 1793 1794 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 1795 if (type == PCI_HEADER_TYPE_BRIDGE) { 1796 info->has_pci_bridge = true; 1797 info->pci_bridge = qmp_query_pci_bridge(dev, bus, bus_num); 1798 } else if (type == PCI_HEADER_TYPE_NORMAL) { 1799 info->id->has_subsystem = info->id->has_subsystem_vendor = true; 1800 info->id->subsystem = pci_get_word(dev->config + PCI_SUBSYSTEM_ID); 1801 info->id->subsystem_vendor = 1802 pci_get_word(dev->config + PCI_SUBSYSTEM_VENDOR_ID); 1803 } else if (type == PCI_HEADER_TYPE_CARDBUS) { 1804 info->id->has_subsystem = info->id->has_subsystem_vendor = true; 1805 info->id->subsystem = pci_get_word(dev->config + PCI_CB_SUBSYSTEM_ID); 1806 info->id->subsystem_vendor = 1807 pci_get_word(dev->config + PCI_CB_SUBSYSTEM_VENDOR_ID); 1808 } 1809 1810 return info; 1811 } 1812 1813 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num) 1814 { 1815 PciDeviceInfoList *info, *head = NULL, *cur_item = NULL; 1816 PCIDevice *dev; 1817 int devfn; 1818 1819 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1820 dev = bus->devices[devfn]; 1821 if (dev) { 1822 info = g_malloc0(sizeof(*info)); 1823 info->value = qmp_query_pci_device(dev, bus, bus_num); 1824 1825 /* XXX: waiting for the qapi to support GSList */ 1826 if (!cur_item) { 1827 head = cur_item = info; 1828 } else { 1829 cur_item->next = info; 1830 cur_item = info; 1831 } 1832 } 1833 } 1834 1835 return head; 1836 } 1837 1838 static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num) 1839 { 1840 PciInfo *info = NULL; 1841 1842 bus = pci_find_bus_nr(bus, bus_num); 1843 if (bus) { 1844 info = g_malloc0(sizeof(*info)); 1845 info->bus = bus_num; 1846 info->devices = qmp_query_pci_devices(bus, bus_num); 1847 } 1848 1849 return info; 1850 } 1851 1852 PciInfoList *qmp_query_pci(Error **errp) 1853 { 1854 PciInfoList *info, *head = NULL, *cur_item = NULL; 1855 PCIHostState *host_bridge; 1856 1857 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { 1858 info = g_malloc0(sizeof(*info)); 1859 info->value = qmp_query_pci_bus(host_bridge->bus, 1860 pci_bus_num(host_bridge->bus)); 1861 1862 /* XXX: waiting for the qapi to support GSList */ 1863 if (!cur_item) { 1864 head = cur_item = info; 1865 } else { 1866 cur_item->next = info; 1867 cur_item = info; 1868 } 1869 } 1870 1871 return head; 1872 } 1873 1874 /* Initialize a PCI NIC. */ 1875 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus, 1876 const char *default_model, 1877 const char *default_devaddr) 1878 { 1879 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr; 1880 GSList *list; 1881 GPtrArray *pci_nic_models; 1882 PCIBus *bus; 1883 PCIDevice *pci_dev; 1884 DeviceState *dev; 1885 int devfn; 1886 int i; 1887 int dom, busnr; 1888 unsigned slot; 1889 1890 if (nd->model && !strcmp(nd->model, "virtio")) { 1891 g_free(nd->model); 1892 nd->model = g_strdup("virtio-net-pci"); 1893 } 1894 1895 list = object_class_get_list_sorted(TYPE_PCI_DEVICE, false); 1896 pci_nic_models = g_ptr_array_new(); 1897 while (list) { 1898 DeviceClass *dc = OBJECT_CLASS_CHECK(DeviceClass, list->data, 1899 TYPE_DEVICE); 1900 GSList *next; 1901 if (test_bit(DEVICE_CATEGORY_NETWORK, dc->categories) && 1902 dc->user_creatable) { 1903 const char *name = object_class_get_name(list->data); 1904 /* 1905 * A network device might also be something else than a NIC, see 1906 * e.g. the "rocker" device. Thus we have to look for the "netdev" 1907 * property, too. Unfortunately, some devices like virtio-net only 1908 * create this property during instance_init, so we have to create 1909 * a temporary instance here to be able to check it. 1910 */ 1911 Object *obj = object_new_with_class(OBJECT_CLASS(dc)); 1912 if (object_property_find(obj, "netdev")) { 1913 g_ptr_array_add(pci_nic_models, (gpointer)name); 1914 } 1915 object_unref(obj); 1916 } 1917 next = list->next; 1918 g_slist_free_1(list); 1919 list = next; 1920 } 1921 g_ptr_array_add(pci_nic_models, NULL); 1922 1923 if (qemu_show_nic_models(nd->model, (const char **)pci_nic_models->pdata)) { 1924 exit(0); 1925 } 1926 1927 i = qemu_find_nic_model(nd, (const char **)pci_nic_models->pdata, 1928 default_model); 1929 if (i < 0) { 1930 exit(1); 1931 } 1932 1933 if (!rootbus) { 1934 error_report("No primary PCI bus"); 1935 exit(1); 1936 } 1937 1938 assert(!rootbus->parent_dev); 1939 1940 if (!devaddr) { 1941 devfn = -1; 1942 busnr = 0; 1943 } else { 1944 if (pci_parse_devaddr(devaddr, &dom, &busnr, &slot, NULL) < 0) { 1945 error_report("Invalid PCI device address %s for device %s", 1946 devaddr, nd->model); 1947 exit(1); 1948 } 1949 1950 if (dom != 0) { 1951 error_report("No support for non-zero PCI domains"); 1952 exit(1); 1953 } 1954 1955 devfn = PCI_DEVFN(slot, 0); 1956 } 1957 1958 bus = pci_find_bus_nr(rootbus, busnr); 1959 if (!bus) { 1960 error_report("Invalid PCI device address %s for device %s", 1961 devaddr, nd->model); 1962 exit(1); 1963 } 1964 1965 pci_dev = pci_new(devfn, nd->model); 1966 dev = &pci_dev->qdev; 1967 qdev_set_nic_properties(dev, nd); 1968 pci_realize_and_unref(pci_dev, bus, &error_fatal); 1969 g_ptr_array_free(pci_nic_models, true); 1970 return pci_dev; 1971 } 1972 1973 PCIDevice *pci_vga_init(PCIBus *bus) 1974 { 1975 switch (vga_interface_type) { 1976 case VGA_CIRRUS: 1977 return pci_create_simple(bus, -1, "cirrus-vga"); 1978 case VGA_QXL: 1979 return pci_create_simple(bus, -1, "qxl-vga"); 1980 case VGA_STD: 1981 return pci_create_simple(bus, -1, "VGA"); 1982 case VGA_VMWARE: 1983 return pci_create_simple(bus, -1, "vmware-svga"); 1984 case VGA_VIRTIO: 1985 return pci_create_simple(bus, -1, "virtio-vga"); 1986 case VGA_NONE: 1987 default: /* Other non-PCI types. Checking for unsupported types is already 1988 done in vl.c. */ 1989 return NULL; 1990 } 1991 } 1992 1993 /* Whether a given bus number is in range of the secondary 1994 * bus of the given bridge device. */ 1995 static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num) 1996 { 1997 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) & 1998 PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ && 1999 dev->config[PCI_SECONDARY_BUS] <= bus_num && 2000 bus_num <= dev->config[PCI_SUBORDINATE_BUS]; 2001 } 2002 2003 /* Whether a given bus number is in a range of a root bus */ 2004 static bool pci_root_bus_in_range(PCIBus *bus, int bus_num) 2005 { 2006 int i; 2007 2008 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 2009 PCIDevice *dev = bus->devices[i]; 2010 2011 if (dev && PCI_DEVICE_GET_CLASS(dev)->is_bridge) { 2012 if (pci_secondary_bus_in_range(dev, bus_num)) { 2013 return true; 2014 } 2015 } 2016 } 2017 2018 return false; 2019 } 2020 2021 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num) 2022 { 2023 PCIBus *sec; 2024 2025 if (!bus) { 2026 return NULL; 2027 } 2028 2029 if (pci_bus_num(bus) == bus_num) { 2030 return bus; 2031 } 2032 2033 /* Consider all bus numbers in range for the host pci bridge. */ 2034 if (!pci_bus_is_root(bus) && 2035 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) { 2036 return NULL; 2037 } 2038 2039 /* try child bus */ 2040 for (; bus; bus = sec) { 2041 QLIST_FOREACH(sec, &bus->child, sibling) { 2042 if (pci_bus_num(sec) == bus_num) { 2043 return sec; 2044 } 2045 /* PXB buses assumed to be children of bus 0 */ 2046 if (pci_bus_is_root(sec)) { 2047 if (pci_root_bus_in_range(sec, bus_num)) { 2048 break; 2049 } 2050 } else { 2051 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) { 2052 break; 2053 } 2054 } 2055 } 2056 } 2057 2058 return NULL; 2059 } 2060 2061 void pci_for_each_bus_depth_first(PCIBus *bus, 2062 void *(*begin)(PCIBus *bus, void *parent_state), 2063 void (*end)(PCIBus *bus, void *state), 2064 void *parent_state) 2065 { 2066 PCIBus *sec; 2067 void *state; 2068 2069 if (!bus) { 2070 return; 2071 } 2072 2073 if (begin) { 2074 state = begin(bus, parent_state); 2075 } else { 2076 state = parent_state; 2077 } 2078 2079 QLIST_FOREACH(sec, &bus->child, sibling) { 2080 pci_for_each_bus_depth_first(sec, begin, end, state); 2081 } 2082 2083 if (end) { 2084 end(bus, state); 2085 } 2086 } 2087 2088 2089 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn) 2090 { 2091 bus = pci_find_bus_nr(bus, bus_num); 2092 2093 if (!bus) 2094 return NULL; 2095 2096 return bus->devices[devfn]; 2097 } 2098 2099 static void pci_qdev_realize(DeviceState *qdev, Error **errp) 2100 { 2101 PCIDevice *pci_dev = (PCIDevice *)qdev; 2102 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 2103 ObjectClass *klass = OBJECT_CLASS(pc); 2104 Error *local_err = NULL; 2105 bool is_default_rom; 2106 uint16_t class_id; 2107 2108 /* initialize cap_present for pci_is_express() and pci_config_size(), 2109 * Note that hybrid PCIs are not set automatically and need to manage 2110 * QEMU_PCI_CAP_EXPRESS manually */ 2111 if (object_class_dynamic_cast(klass, INTERFACE_PCIE_DEVICE) && 2112 !object_class_dynamic_cast(klass, INTERFACE_CONVENTIONAL_PCI_DEVICE)) { 2113 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; 2114 } 2115 2116 pci_dev = do_pci_register_device(pci_dev, 2117 object_get_typename(OBJECT(qdev)), 2118 pci_dev->devfn, errp); 2119 if (pci_dev == NULL) 2120 return; 2121 2122 if (pc->realize) { 2123 pc->realize(pci_dev, &local_err); 2124 if (local_err) { 2125 error_propagate(errp, local_err); 2126 do_pci_unregister_device(pci_dev); 2127 return; 2128 } 2129 } 2130 2131 if (pci_dev->failover_pair_id) { 2132 if (!pci_bus_is_express(pci_get_bus(pci_dev))) { 2133 error_setg(errp, "failover primary device must be on " 2134 "PCIExpress bus"); 2135 pci_qdev_unrealize(DEVICE(pci_dev)); 2136 return; 2137 } 2138 class_id = pci_get_word(pci_dev->config + PCI_CLASS_DEVICE); 2139 if (class_id != PCI_CLASS_NETWORK_ETHERNET) { 2140 error_setg(errp, "failover primary device is not an " 2141 "Ethernet device"); 2142 pci_qdev_unrealize(DEVICE(pci_dev)); 2143 return; 2144 } 2145 if (!(pci_dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) 2146 && (PCI_FUNC(pci_dev->devfn) == 0)) { 2147 qdev->allow_unplug_during_migration = true; 2148 } else { 2149 error_setg(errp, "failover: primary device must be in its own " 2150 "PCI slot"); 2151 pci_qdev_unrealize(DEVICE(pci_dev)); 2152 return; 2153 } 2154 qdev->allow_unplug_during_migration = true; 2155 } 2156 2157 /* rom loading */ 2158 is_default_rom = false; 2159 if (pci_dev->romfile == NULL && pc->romfile != NULL) { 2160 pci_dev->romfile = g_strdup(pc->romfile); 2161 is_default_rom = true; 2162 } 2163 2164 pci_add_option_rom(pci_dev, is_default_rom, &local_err); 2165 if (local_err) { 2166 error_propagate(errp, local_err); 2167 pci_qdev_unrealize(DEVICE(pci_dev)); 2168 return; 2169 } 2170 } 2171 2172 PCIDevice *pci_new_multifunction(int devfn, bool multifunction, 2173 const char *name) 2174 { 2175 DeviceState *dev; 2176 2177 dev = qdev_new(name); 2178 qdev_prop_set_int32(dev, "addr", devfn); 2179 qdev_prop_set_bit(dev, "multifunction", multifunction); 2180 return PCI_DEVICE(dev); 2181 } 2182 2183 PCIDevice *pci_new(int devfn, const char *name) 2184 { 2185 return pci_new_multifunction(devfn, false, name); 2186 } 2187 2188 bool pci_realize_and_unref(PCIDevice *dev, PCIBus *bus, Error **errp) 2189 { 2190 return qdev_realize_and_unref(&dev->qdev, &bus->qbus, errp); 2191 } 2192 2193 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, 2194 bool multifunction, 2195 const char *name) 2196 { 2197 PCIDevice *dev = pci_new_multifunction(devfn, multifunction, name); 2198 pci_realize_and_unref(dev, bus, &error_fatal); 2199 return dev; 2200 } 2201 2202 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name) 2203 { 2204 return pci_create_simple_multifunction(bus, devfn, false, name); 2205 } 2206 2207 static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size) 2208 { 2209 int offset = PCI_CONFIG_HEADER_SIZE; 2210 int i; 2211 for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) { 2212 if (pdev->used[i]) 2213 offset = i + 1; 2214 else if (i - offset + 1 == size) 2215 return offset; 2216 } 2217 return 0; 2218 } 2219 2220 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id, 2221 uint8_t *prev_p) 2222 { 2223 uint8_t next, prev; 2224 2225 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST)) 2226 return 0; 2227 2228 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); 2229 prev = next + PCI_CAP_LIST_NEXT) 2230 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id) 2231 break; 2232 2233 if (prev_p) 2234 *prev_p = prev; 2235 return next; 2236 } 2237 2238 static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset) 2239 { 2240 uint8_t next, prev, found = 0; 2241 2242 if (!(pdev->used[offset])) { 2243 return 0; 2244 } 2245 2246 assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST); 2247 2248 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); 2249 prev = next + PCI_CAP_LIST_NEXT) { 2250 if (next <= offset && next > found) { 2251 found = next; 2252 } 2253 } 2254 return found; 2255 } 2256 2257 /* Patch the PCI vendor and device ids in a PCI rom image if necessary. 2258 This is needed for an option rom which is used for more than one device. */ 2259 static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size) 2260 { 2261 uint16_t vendor_id; 2262 uint16_t device_id; 2263 uint16_t rom_vendor_id; 2264 uint16_t rom_device_id; 2265 uint16_t rom_magic; 2266 uint16_t pcir_offset; 2267 uint8_t checksum; 2268 2269 /* Words in rom data are little endian (like in PCI configuration), 2270 so they can be read / written with pci_get_word / pci_set_word. */ 2271 2272 /* Only a valid rom will be patched. */ 2273 rom_magic = pci_get_word(ptr); 2274 if (rom_magic != 0xaa55) { 2275 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic); 2276 return; 2277 } 2278 pcir_offset = pci_get_word(ptr + 0x18); 2279 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) { 2280 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset); 2281 return; 2282 } 2283 2284 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID); 2285 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID); 2286 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4); 2287 rom_device_id = pci_get_word(ptr + pcir_offset + 6); 2288 2289 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile, 2290 vendor_id, device_id, rom_vendor_id, rom_device_id); 2291 2292 checksum = ptr[6]; 2293 2294 if (vendor_id != rom_vendor_id) { 2295 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */ 2296 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8); 2297 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8); 2298 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); 2299 ptr[6] = checksum; 2300 pci_set_word(ptr + pcir_offset + 4, vendor_id); 2301 } 2302 2303 if (device_id != rom_device_id) { 2304 /* Patch device id and checksum (at offset 6 for etherboot roms). */ 2305 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8); 2306 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8); 2307 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); 2308 ptr[6] = checksum; 2309 pci_set_word(ptr + pcir_offset + 6, device_id); 2310 } 2311 } 2312 2313 /* Add an option rom for the device */ 2314 static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, 2315 Error **errp) 2316 { 2317 int size; 2318 char *path; 2319 void *ptr; 2320 char name[32]; 2321 const VMStateDescription *vmsd; 2322 2323 if (!pdev->romfile) 2324 return; 2325 if (strlen(pdev->romfile) == 0) 2326 return; 2327 2328 if (!pdev->rom_bar) { 2329 /* 2330 * Load rom via fw_cfg instead of creating a rom bar, 2331 * for 0.11 compatibility. 2332 */ 2333 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE); 2334 2335 /* 2336 * Hot-plugged devices can't use the option ROM 2337 * if the rom bar is disabled. 2338 */ 2339 if (DEVICE(pdev)->hotplugged) { 2340 error_setg(errp, "Hot-plugged device without ROM bar" 2341 " can't have an option ROM"); 2342 return; 2343 } 2344 2345 if (class == 0x0300) { 2346 rom_add_vga(pdev->romfile); 2347 } else { 2348 rom_add_option(pdev->romfile, -1); 2349 } 2350 return; 2351 } 2352 2353 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile); 2354 if (path == NULL) { 2355 path = g_strdup(pdev->romfile); 2356 } 2357 2358 size = get_image_size(path); 2359 if (size < 0) { 2360 error_setg(errp, "failed to find romfile \"%s\"", pdev->romfile); 2361 g_free(path); 2362 return; 2363 } else if (size == 0) { 2364 error_setg(errp, "romfile \"%s\" is empty", pdev->romfile); 2365 g_free(path); 2366 return; 2367 } 2368 size = pow2ceil(size); 2369 2370 vmsd = qdev_get_vmsd(DEVICE(pdev)); 2371 2372 if (vmsd) { 2373 snprintf(name, sizeof(name), "%s.rom", vmsd->name); 2374 } else { 2375 snprintf(name, sizeof(name), "%s.rom", object_get_typename(OBJECT(pdev))); 2376 } 2377 pdev->has_rom = true; 2378 memory_region_init_rom(&pdev->rom, OBJECT(pdev), name, size, &error_fatal); 2379 ptr = memory_region_get_ram_ptr(&pdev->rom); 2380 if (load_image_size(path, ptr, size) < 0) { 2381 error_setg(errp, "failed to load romfile \"%s\"", pdev->romfile); 2382 g_free(path); 2383 return; 2384 } 2385 g_free(path); 2386 2387 if (is_default_rom) { 2388 /* Only the default rom images will be patched (if needed). */ 2389 pci_patch_ids(pdev, ptr, size); 2390 } 2391 2392 pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom); 2393 } 2394 2395 static void pci_del_option_rom(PCIDevice *pdev) 2396 { 2397 if (!pdev->has_rom) 2398 return; 2399 2400 vmstate_unregister_ram(&pdev->rom, &pdev->qdev); 2401 pdev->has_rom = false; 2402 } 2403 2404 /* 2405 * On success, pci_add_capability() returns a positive value 2406 * that the offset of the pci capability. 2407 * On failure, it sets an error and returns a negative error 2408 * code. 2409 */ 2410 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, 2411 uint8_t offset, uint8_t size, 2412 Error **errp) 2413 { 2414 uint8_t *config; 2415 int i, overlapping_cap; 2416 2417 if (!offset) { 2418 offset = pci_find_space(pdev, size); 2419 /* out of PCI config space is programming error */ 2420 assert(offset); 2421 } else { 2422 /* Verify that capabilities don't overlap. Note: device assignment 2423 * depends on this check to verify that the device is not broken. 2424 * Should never trigger for emulated devices, but it's helpful 2425 * for debugging these. */ 2426 for (i = offset; i < offset + size; i++) { 2427 overlapping_cap = pci_find_capability_at_offset(pdev, i); 2428 if (overlapping_cap) { 2429 error_setg(errp, "%s:%02x:%02x.%x " 2430 "Attempt to add PCI capability %x at offset " 2431 "%x overlaps existing capability %x at offset %x", 2432 pci_root_bus_path(pdev), pci_dev_bus_num(pdev), 2433 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), 2434 cap_id, offset, overlapping_cap, i); 2435 return -EINVAL; 2436 } 2437 } 2438 } 2439 2440 config = pdev->config + offset; 2441 config[PCI_CAP_LIST_ID] = cap_id; 2442 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST]; 2443 pdev->config[PCI_CAPABILITY_LIST] = offset; 2444 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST; 2445 memset(pdev->used + offset, 0xFF, QEMU_ALIGN_UP(size, 4)); 2446 /* Make capability read-only by default */ 2447 memset(pdev->wmask + offset, 0, size); 2448 /* Check capability by default */ 2449 memset(pdev->cmask + offset, 0xFF, size); 2450 return offset; 2451 } 2452 2453 /* Unlink capability from the pci config space. */ 2454 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size) 2455 { 2456 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev); 2457 if (!offset) 2458 return; 2459 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT]; 2460 /* Make capability writable again */ 2461 memset(pdev->wmask + offset, 0xff, size); 2462 memset(pdev->w1cmask + offset, 0, size); 2463 /* Clear cmask as device-specific registers can't be checked */ 2464 memset(pdev->cmask + offset, 0, size); 2465 memset(pdev->used + offset, 0, QEMU_ALIGN_UP(size, 4)); 2466 2467 if (!pdev->config[PCI_CAPABILITY_LIST]) 2468 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST; 2469 } 2470 2471 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id) 2472 { 2473 return pci_find_capability_list(pdev, cap_id, NULL); 2474 } 2475 2476 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent) 2477 { 2478 PCIDevice *d = (PCIDevice *)dev; 2479 const pci_class_desc *desc; 2480 char ctxt[64]; 2481 PCIIORegion *r; 2482 int i, class; 2483 2484 class = pci_get_word(d->config + PCI_CLASS_DEVICE); 2485 desc = pci_class_descriptions; 2486 while (desc->desc && class != desc->class) 2487 desc++; 2488 if (desc->desc) { 2489 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc); 2490 } else { 2491 snprintf(ctxt, sizeof(ctxt), "Class %04x", class); 2492 } 2493 2494 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, " 2495 "pci id %04x:%04x (sub %04x:%04x)\n", 2496 indent, "", ctxt, pci_dev_bus_num(d), 2497 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn), 2498 pci_get_word(d->config + PCI_VENDOR_ID), 2499 pci_get_word(d->config + PCI_DEVICE_ID), 2500 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID), 2501 pci_get_word(d->config + PCI_SUBSYSTEM_ID)); 2502 for (i = 0; i < PCI_NUM_REGIONS; i++) { 2503 r = &d->io_regions[i]; 2504 if (!r->size) 2505 continue; 2506 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS 2507 " [0x%"FMT_PCIBUS"]\n", 2508 indent, "", 2509 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem", 2510 r->addr, r->addr + r->size - 1); 2511 } 2512 } 2513 2514 static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len) 2515 { 2516 PCIDevice *d = (PCIDevice *)dev; 2517 const char *name = NULL; 2518 const pci_class_desc *desc = pci_class_descriptions; 2519 int class = pci_get_word(d->config + PCI_CLASS_DEVICE); 2520 2521 while (desc->desc && 2522 (class & ~desc->fw_ign_bits) != 2523 (desc->class & ~desc->fw_ign_bits)) { 2524 desc++; 2525 } 2526 2527 if (desc->desc) { 2528 name = desc->fw_name; 2529 } 2530 2531 if (name) { 2532 pstrcpy(buf, len, name); 2533 } else { 2534 snprintf(buf, len, "pci%04x,%04x", 2535 pci_get_word(d->config + PCI_VENDOR_ID), 2536 pci_get_word(d->config + PCI_DEVICE_ID)); 2537 } 2538 2539 return buf; 2540 } 2541 2542 static char *pcibus_get_fw_dev_path(DeviceState *dev) 2543 { 2544 PCIDevice *d = (PCIDevice *)dev; 2545 char path[50], name[33]; 2546 int off; 2547 2548 off = snprintf(path, sizeof(path), "%s@%x", 2549 pci_dev_fw_name(dev, name, sizeof name), 2550 PCI_SLOT(d->devfn)); 2551 if (PCI_FUNC(d->devfn)) 2552 snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn)); 2553 return g_strdup(path); 2554 } 2555 2556 static char *pcibus_get_dev_path(DeviceState *dev) 2557 { 2558 PCIDevice *d = container_of(dev, PCIDevice, qdev); 2559 PCIDevice *t; 2560 int slot_depth; 2561 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function. 2562 * 00 is added here to make this format compatible with 2563 * domain:Bus:Slot.Func for systems without nested PCI bridges. 2564 * Slot.Function list specifies the slot and function numbers for all 2565 * devices on the path from root to the specific device. */ 2566 const char *root_bus_path; 2567 int root_bus_len; 2568 char slot[] = ":SS.F"; 2569 int slot_len = sizeof slot - 1 /* For '\0' */; 2570 int path_len; 2571 char *path, *p; 2572 int s; 2573 2574 root_bus_path = pci_root_bus_path(d); 2575 root_bus_len = strlen(root_bus_path); 2576 2577 /* Calculate # of slots on path between device and root. */; 2578 slot_depth = 0; 2579 for (t = d; t; t = pci_get_bus(t)->parent_dev) { 2580 ++slot_depth; 2581 } 2582 2583 path_len = root_bus_len + slot_len * slot_depth; 2584 2585 /* Allocate memory, fill in the terminating null byte. */ 2586 path = g_malloc(path_len + 1 /* For '\0' */); 2587 path[path_len] = '\0'; 2588 2589 memcpy(path, root_bus_path, root_bus_len); 2590 2591 /* Fill in slot numbers. We walk up from device to root, so need to print 2592 * them in the reverse order, last to first. */ 2593 p = path + path_len; 2594 for (t = d; t; t = pci_get_bus(t)->parent_dev) { 2595 p -= slot_len; 2596 s = snprintf(slot, sizeof slot, ":%02x.%x", 2597 PCI_SLOT(t->devfn), PCI_FUNC(t->devfn)); 2598 assert(s == slot_len); 2599 memcpy(p, slot, slot_len); 2600 } 2601 2602 return path; 2603 } 2604 2605 static int pci_qdev_find_recursive(PCIBus *bus, 2606 const char *id, PCIDevice **pdev) 2607 { 2608 DeviceState *qdev = qdev_find_recursive(&bus->qbus, id); 2609 if (!qdev) { 2610 return -ENODEV; 2611 } 2612 2613 /* roughly check if given qdev is pci device */ 2614 if (object_dynamic_cast(OBJECT(qdev), TYPE_PCI_DEVICE)) { 2615 *pdev = PCI_DEVICE(qdev); 2616 return 0; 2617 } 2618 return -EINVAL; 2619 } 2620 2621 int pci_qdev_find_device(const char *id, PCIDevice **pdev) 2622 { 2623 PCIHostState *host_bridge; 2624 int rc = -ENODEV; 2625 2626 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { 2627 int tmp = pci_qdev_find_recursive(host_bridge->bus, id, pdev); 2628 if (!tmp) { 2629 rc = 0; 2630 break; 2631 } 2632 if (tmp != -ENODEV) { 2633 rc = tmp; 2634 } 2635 } 2636 2637 return rc; 2638 } 2639 2640 MemoryRegion *pci_address_space(PCIDevice *dev) 2641 { 2642 return pci_get_bus(dev)->address_space_mem; 2643 } 2644 2645 MemoryRegion *pci_address_space_io(PCIDevice *dev) 2646 { 2647 return pci_get_bus(dev)->address_space_io; 2648 } 2649 2650 static void pci_device_class_init(ObjectClass *klass, void *data) 2651 { 2652 DeviceClass *k = DEVICE_CLASS(klass); 2653 2654 k->realize = pci_qdev_realize; 2655 k->unrealize = pci_qdev_unrealize; 2656 k->bus_type = TYPE_PCI_BUS; 2657 device_class_set_props(k, pci_props); 2658 } 2659 2660 static void pci_device_class_base_init(ObjectClass *klass, void *data) 2661 { 2662 if (!object_class_is_abstract(klass)) { 2663 ObjectClass *conventional = 2664 object_class_dynamic_cast(klass, INTERFACE_CONVENTIONAL_PCI_DEVICE); 2665 ObjectClass *pcie = 2666 object_class_dynamic_cast(klass, INTERFACE_PCIE_DEVICE); 2667 assert(conventional || pcie); 2668 } 2669 } 2670 2671 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev) 2672 { 2673 PCIBus *bus = pci_get_bus(dev); 2674 PCIBus *iommu_bus = bus; 2675 uint8_t devfn = dev->devfn; 2676 2677 while (iommu_bus && !iommu_bus->iommu_fn && iommu_bus->parent_dev) { 2678 PCIBus *parent_bus = pci_get_bus(iommu_bus->parent_dev); 2679 2680 /* 2681 * The requester ID of the provided device may be aliased, as seen from 2682 * the IOMMU, due to topology limitations. The IOMMU relies on a 2683 * requester ID to provide a unique AddressSpace for devices, but 2684 * conventional PCI buses pre-date such concepts. Instead, the PCIe- 2685 * to-PCI bridge creates and accepts transactions on behalf of down- 2686 * stream devices. When doing so, all downstream devices are masked 2687 * (aliased) behind a single requester ID. The requester ID used 2688 * depends on the format of the bridge devices. Proper PCIe-to-PCI 2689 * bridges, with a PCIe capability indicating such, follow the 2690 * guidelines of chapter 2.3 of the PCIe-to-PCI/X bridge specification, 2691 * where the bridge uses the seconary bus as the bridge portion of the 2692 * requester ID and devfn of 00.0. For other bridges, typically those 2693 * found on the root complex such as the dmi-to-pci-bridge, we follow 2694 * the convention of typical bare-metal hardware, which uses the 2695 * requester ID of the bridge itself. There are device specific 2696 * exceptions to these rules, but these are the defaults that the 2697 * Linux kernel uses when determining DMA aliases itself and believed 2698 * to be true for the bare metal equivalents of the devices emulated 2699 * in QEMU. 2700 */ 2701 if (!pci_bus_is_express(iommu_bus)) { 2702 PCIDevice *parent = iommu_bus->parent_dev; 2703 2704 if (pci_is_express(parent) && 2705 pcie_cap_get_type(parent) == PCI_EXP_TYPE_PCI_BRIDGE) { 2706 devfn = PCI_DEVFN(0, 0); 2707 bus = iommu_bus; 2708 } else { 2709 devfn = parent->devfn; 2710 bus = parent_bus; 2711 } 2712 } 2713 2714 iommu_bus = parent_bus; 2715 } 2716 if (iommu_bus && iommu_bus->iommu_fn) { 2717 return iommu_bus->iommu_fn(bus, iommu_bus->iommu_opaque, devfn); 2718 } 2719 return &address_space_memory; 2720 } 2721 2722 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque) 2723 { 2724 bus->iommu_fn = fn; 2725 bus->iommu_opaque = opaque; 2726 } 2727 2728 static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque) 2729 { 2730 Range *range = opaque; 2731 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 2732 uint16_t cmd = pci_get_word(dev->config + PCI_COMMAND); 2733 int i; 2734 2735 if (!(cmd & PCI_COMMAND_MEMORY)) { 2736 return; 2737 } 2738 2739 if (pc->is_bridge) { 2740 pcibus_t base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 2741 pcibus_t limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 2742 2743 base = MAX(base, 0x1ULL << 32); 2744 2745 if (limit >= base) { 2746 Range pref_range; 2747 range_set_bounds(&pref_range, base, limit); 2748 range_extend(range, &pref_range); 2749 } 2750 } 2751 for (i = 0; i < PCI_NUM_REGIONS; ++i) { 2752 PCIIORegion *r = &dev->io_regions[i]; 2753 pcibus_t lob, upb; 2754 Range region_range; 2755 2756 if (!r->size || 2757 (r->type & PCI_BASE_ADDRESS_SPACE_IO) || 2758 !(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64)) { 2759 continue; 2760 } 2761 2762 lob = pci_bar_address(dev, i, r->type, r->size); 2763 upb = lob + r->size - 1; 2764 if (lob == PCI_BAR_UNMAPPED) { 2765 continue; 2766 } 2767 2768 lob = MAX(lob, 0x1ULL << 32); 2769 2770 if (upb >= lob) { 2771 range_set_bounds(®ion_range, lob, upb); 2772 range_extend(range, ®ion_range); 2773 } 2774 } 2775 } 2776 2777 void pci_bus_get_w64_range(PCIBus *bus, Range *range) 2778 { 2779 range_make_empty(range); 2780 pci_for_each_device_under_bus(bus, pci_dev_get_w64, range); 2781 } 2782 2783 static bool pcie_has_upstream_port(PCIDevice *dev) 2784 { 2785 PCIDevice *parent_dev = pci_bridge_get_device(pci_get_bus(dev)); 2786 2787 /* Device associated with an upstream port. 2788 * As there are several types of these, it's easier to check the 2789 * parent device: upstream ports are always connected to 2790 * root or downstream ports. 2791 */ 2792 return parent_dev && 2793 pci_is_express(parent_dev) && 2794 parent_dev->exp.exp_cap && 2795 (pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_ROOT_PORT || 2796 pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_DOWNSTREAM); 2797 } 2798 2799 PCIDevice *pci_get_function_0(PCIDevice *pci_dev) 2800 { 2801 PCIBus *bus = pci_get_bus(pci_dev); 2802 2803 if(pcie_has_upstream_port(pci_dev)) { 2804 /* With an upstream PCIe port, we only support 1 device at slot 0 */ 2805 return bus->devices[0]; 2806 } else { 2807 /* Other bus types might support multiple devices at slots 0-31 */ 2808 return bus->devices[PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 0)]; 2809 } 2810 } 2811 2812 MSIMessage pci_get_msi_message(PCIDevice *dev, int vector) 2813 { 2814 MSIMessage msg; 2815 if (msix_enabled(dev)) { 2816 msg = msix_get_message(dev, vector); 2817 } else if (msi_enabled(dev)) { 2818 msg = msi_get_message(dev, vector); 2819 } else { 2820 /* Should never happen */ 2821 error_report("%s: unknown interrupt type", __func__); 2822 abort(); 2823 } 2824 return msg; 2825 } 2826 2827 static const TypeInfo pci_device_type_info = { 2828 .name = TYPE_PCI_DEVICE, 2829 .parent = TYPE_DEVICE, 2830 .instance_size = sizeof(PCIDevice), 2831 .abstract = true, 2832 .class_size = sizeof(PCIDeviceClass), 2833 .class_init = pci_device_class_init, 2834 .class_base_init = pci_device_class_base_init, 2835 }; 2836 2837 static void pci_register_types(void) 2838 { 2839 type_register_static(&pci_bus_info); 2840 type_register_static(&pcie_bus_info); 2841 type_register_static(&conventional_pci_interface_info); 2842 type_register_static(&pcie_interface_info); 2843 type_register_static(&pci_device_type_info); 2844 } 2845 2846 type_init(pci_register_types) 2847