1 /* 2 * QEMU PCI bus manager 3 * 4 * Copyright (c) 2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu-common.h" 27 #include "qemu/datadir.h" 28 #include "hw/irq.h" 29 #include "hw/pci/pci.h" 30 #include "hw/pci/pci_bridge.h" 31 #include "hw/pci/pci_bus.h" 32 #include "hw/pci/pci_host.h" 33 #include "hw/qdev-properties.h" 34 #include "hw/qdev-properties-system.h" 35 #include "migration/qemu-file-types.h" 36 #include "migration/vmstate.h" 37 #include "monitor/monitor.h" 38 #include "net/net.h" 39 #include "sysemu/numa.h" 40 #include "sysemu/sysemu.h" 41 #include "hw/loader.h" 42 #include "qemu/error-report.h" 43 #include "qemu/range.h" 44 #include "trace.h" 45 #include "hw/pci/msi.h" 46 #include "hw/pci/msix.h" 47 #include "exec/address-spaces.h" 48 #include "hw/hotplug.h" 49 #include "hw/boards.h" 50 #include "qapi/error.h" 51 #include "qapi/qapi-commands-pci.h" 52 #include "qemu/cutils.h" 53 54 //#define DEBUG_PCI 55 #ifdef DEBUG_PCI 56 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) 57 #else 58 # define PCI_DPRINTF(format, ...) do { } while (0) 59 #endif 60 61 bool pci_available = true; 62 63 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent); 64 static char *pcibus_get_dev_path(DeviceState *dev); 65 static char *pcibus_get_fw_dev_path(DeviceState *dev); 66 static void pcibus_reset(BusState *qbus); 67 68 static Property pci_props[] = { 69 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1), 70 DEFINE_PROP_STRING("romfile", PCIDevice, romfile), 71 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1), 72 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present, 73 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false), 74 DEFINE_PROP_BIT("x-pcie-lnksta-dllla", PCIDevice, cap_present, 75 QEMU_PCIE_LNKSTA_DLLLA_BITNR, true), 76 DEFINE_PROP_BIT("x-pcie-extcap-init", PCIDevice, cap_present, 77 QEMU_PCIE_EXTCAP_INIT_BITNR, true), 78 DEFINE_PROP_STRING("failover_pair_id", PCIDevice, 79 failover_pair_id), 80 DEFINE_PROP_END_OF_LIST() 81 }; 82 83 static const VMStateDescription vmstate_pcibus = { 84 .name = "PCIBUS", 85 .version_id = 1, 86 .minimum_version_id = 1, 87 .fields = (VMStateField[]) { 88 VMSTATE_INT32_EQUAL(nirq, PCIBus, NULL), 89 VMSTATE_VARRAY_INT32(irq_count, PCIBus, 90 nirq, 0, vmstate_info_int32, 91 int32_t), 92 VMSTATE_END_OF_LIST() 93 } 94 }; 95 96 static void pci_init_bus_master(PCIDevice *pci_dev) 97 { 98 AddressSpace *dma_as = pci_device_iommu_address_space(pci_dev); 99 100 memory_region_init_alias(&pci_dev->bus_master_enable_region, 101 OBJECT(pci_dev), "bus master", 102 dma_as->root, 0, memory_region_size(dma_as->root)); 103 memory_region_set_enabled(&pci_dev->bus_master_enable_region, false); 104 memory_region_add_subregion(&pci_dev->bus_master_container_region, 0, 105 &pci_dev->bus_master_enable_region); 106 } 107 108 static void pcibus_machine_done(Notifier *notifier, void *data) 109 { 110 PCIBus *bus = container_of(notifier, PCIBus, machine_done); 111 int i; 112 113 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 114 if (bus->devices[i]) { 115 pci_init_bus_master(bus->devices[i]); 116 } 117 } 118 } 119 120 static void pci_bus_realize(BusState *qbus, Error **errp) 121 { 122 PCIBus *bus = PCI_BUS(qbus); 123 124 bus->machine_done.notify = pcibus_machine_done; 125 qemu_add_machine_init_done_notifier(&bus->machine_done); 126 127 vmstate_register(NULL, VMSTATE_INSTANCE_ID_ANY, &vmstate_pcibus, bus); 128 } 129 130 static void pcie_bus_realize(BusState *qbus, Error **errp) 131 { 132 PCIBus *bus = PCI_BUS(qbus); 133 134 pci_bus_realize(qbus, errp); 135 136 /* 137 * A PCI-E bus can support extended config space if it's the root 138 * bus, or if the bus/bridge above it does as well 139 */ 140 if (pci_bus_is_root(bus)) { 141 bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE; 142 } else { 143 PCIBus *parent_bus = pci_get_bus(bus->parent_dev); 144 145 if (pci_bus_allows_extended_config_space(parent_bus)) { 146 bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE; 147 } 148 } 149 } 150 151 static void pci_bus_unrealize(BusState *qbus) 152 { 153 PCIBus *bus = PCI_BUS(qbus); 154 155 qemu_remove_machine_init_done_notifier(&bus->machine_done); 156 157 vmstate_unregister(NULL, &vmstate_pcibus, bus); 158 } 159 160 static int pcibus_num(PCIBus *bus) 161 { 162 if (pci_bus_is_root(bus)) { 163 return 0; /* pci host bridge */ 164 } 165 return bus->parent_dev->config[PCI_SECONDARY_BUS]; 166 } 167 168 static uint16_t pcibus_numa_node(PCIBus *bus) 169 { 170 return NUMA_NODE_UNASSIGNED; 171 } 172 173 static void pci_bus_class_init(ObjectClass *klass, void *data) 174 { 175 BusClass *k = BUS_CLASS(klass); 176 PCIBusClass *pbc = PCI_BUS_CLASS(klass); 177 178 k->print_dev = pcibus_dev_print; 179 k->get_dev_path = pcibus_get_dev_path; 180 k->get_fw_dev_path = pcibus_get_fw_dev_path; 181 k->realize = pci_bus_realize; 182 k->unrealize = pci_bus_unrealize; 183 k->reset = pcibus_reset; 184 185 pbc->bus_num = pcibus_num; 186 pbc->numa_node = pcibus_numa_node; 187 } 188 189 static const TypeInfo pci_bus_info = { 190 .name = TYPE_PCI_BUS, 191 .parent = TYPE_BUS, 192 .instance_size = sizeof(PCIBus), 193 .class_size = sizeof(PCIBusClass), 194 .class_init = pci_bus_class_init, 195 }; 196 197 static const TypeInfo pcie_interface_info = { 198 .name = INTERFACE_PCIE_DEVICE, 199 .parent = TYPE_INTERFACE, 200 }; 201 202 static const TypeInfo conventional_pci_interface_info = { 203 .name = INTERFACE_CONVENTIONAL_PCI_DEVICE, 204 .parent = TYPE_INTERFACE, 205 }; 206 207 static void pcie_bus_class_init(ObjectClass *klass, void *data) 208 { 209 BusClass *k = BUS_CLASS(klass); 210 211 k->realize = pcie_bus_realize; 212 } 213 214 static const TypeInfo pcie_bus_info = { 215 .name = TYPE_PCIE_BUS, 216 .parent = TYPE_PCI_BUS, 217 .class_init = pcie_bus_class_init, 218 }; 219 220 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num); 221 static void pci_update_mappings(PCIDevice *d); 222 static void pci_irq_handler(void *opaque, int irq_num, int level); 223 static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, Error **); 224 static void pci_del_option_rom(PCIDevice *pdev); 225 226 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET; 227 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU; 228 229 static QLIST_HEAD(, PCIHostState) pci_host_bridges; 230 231 int pci_bar(PCIDevice *d, int reg) 232 { 233 uint8_t type; 234 235 if (reg != PCI_ROM_SLOT) 236 return PCI_BASE_ADDRESS_0 + reg * 4; 237 238 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 239 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS; 240 } 241 242 static inline int pci_irq_state(PCIDevice *d, int irq_num) 243 { 244 return (d->irq_state >> irq_num) & 0x1; 245 } 246 247 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level) 248 { 249 d->irq_state &= ~(0x1 << irq_num); 250 d->irq_state |= level << irq_num; 251 } 252 253 static void pci_bus_change_irq_level(PCIBus *bus, int irq_num, int change) 254 { 255 assert(irq_num >= 0); 256 assert(irq_num < bus->nirq); 257 bus->irq_count[irq_num] += change; 258 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0); 259 } 260 261 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change) 262 { 263 PCIBus *bus; 264 for (;;) { 265 bus = pci_get_bus(pci_dev); 266 irq_num = bus->map_irq(pci_dev, irq_num); 267 if (bus->set_irq) 268 break; 269 pci_dev = bus->parent_dev; 270 } 271 pci_bus_change_irq_level(bus, irq_num, change); 272 } 273 274 int pci_bus_get_irq_level(PCIBus *bus, int irq_num) 275 { 276 assert(irq_num >= 0); 277 assert(irq_num < bus->nirq); 278 return !!bus->irq_count[irq_num]; 279 } 280 281 /* Update interrupt status bit in config space on interrupt 282 * state change. */ 283 static void pci_update_irq_status(PCIDevice *dev) 284 { 285 if (dev->irq_state) { 286 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT; 287 } else { 288 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; 289 } 290 } 291 292 void pci_device_deassert_intx(PCIDevice *dev) 293 { 294 int i; 295 for (i = 0; i < PCI_NUM_PINS; ++i) { 296 pci_irq_handler(dev, i, 0); 297 } 298 } 299 300 static void pci_do_device_reset(PCIDevice *dev) 301 { 302 int r; 303 304 pci_device_deassert_intx(dev); 305 assert(dev->irq_state == 0); 306 307 /* Clear all writable bits */ 308 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND, 309 pci_get_word(dev->wmask + PCI_COMMAND) | 310 pci_get_word(dev->w1cmask + PCI_COMMAND)); 311 pci_word_test_and_clear_mask(dev->config + PCI_STATUS, 312 pci_get_word(dev->wmask + PCI_STATUS) | 313 pci_get_word(dev->w1cmask + PCI_STATUS)); 314 /* Some devices make bits of PCI_INTERRUPT_LINE read only */ 315 pci_byte_test_and_clear_mask(dev->config + PCI_INTERRUPT_LINE, 316 pci_get_word(dev->wmask + PCI_INTERRUPT_LINE) | 317 pci_get_word(dev->w1cmask + PCI_INTERRUPT_LINE)); 318 dev->config[PCI_CACHE_LINE_SIZE] = 0x0; 319 for (r = 0; r < PCI_NUM_REGIONS; ++r) { 320 PCIIORegion *region = &dev->io_regions[r]; 321 if (!region->size) { 322 continue; 323 } 324 325 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) && 326 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 327 pci_set_quad(dev->config + pci_bar(dev, r), region->type); 328 } else { 329 pci_set_long(dev->config + pci_bar(dev, r), region->type); 330 } 331 } 332 pci_update_mappings(dev); 333 334 msi_reset(dev); 335 msix_reset(dev); 336 } 337 338 /* 339 * This function is called on #RST and FLR. 340 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set 341 */ 342 void pci_device_reset(PCIDevice *dev) 343 { 344 qdev_reset_all(&dev->qdev); 345 pci_do_device_reset(dev); 346 } 347 348 /* 349 * Trigger pci bus reset under a given bus. 350 * Called via qbus_reset_all on RST# assert, after the devices 351 * have been reset qdev_reset_all-ed already. 352 */ 353 static void pcibus_reset(BusState *qbus) 354 { 355 PCIBus *bus = DO_UPCAST(PCIBus, qbus, qbus); 356 int i; 357 358 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 359 if (bus->devices[i]) { 360 pci_do_device_reset(bus->devices[i]); 361 } 362 } 363 364 for (i = 0; i < bus->nirq; i++) { 365 assert(bus->irq_count[i] == 0); 366 } 367 } 368 369 static void pci_host_bus_register(DeviceState *host) 370 { 371 PCIHostState *host_bridge = PCI_HOST_BRIDGE(host); 372 373 QLIST_INSERT_HEAD(&pci_host_bridges, host_bridge, next); 374 } 375 376 static void pci_host_bus_unregister(DeviceState *host) 377 { 378 PCIHostState *host_bridge = PCI_HOST_BRIDGE(host); 379 380 QLIST_REMOVE(host_bridge, next); 381 } 382 383 PCIBus *pci_device_root_bus(const PCIDevice *d) 384 { 385 PCIBus *bus = pci_get_bus(d); 386 387 while (!pci_bus_is_root(bus)) { 388 d = bus->parent_dev; 389 assert(d != NULL); 390 391 bus = pci_get_bus(d); 392 } 393 394 return bus; 395 } 396 397 const char *pci_root_bus_path(PCIDevice *dev) 398 { 399 PCIBus *rootbus = pci_device_root_bus(dev); 400 PCIHostState *host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent); 401 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_GET_CLASS(host_bridge); 402 403 assert(host_bridge->bus == rootbus); 404 405 if (hc->root_bus_path) { 406 return (*hc->root_bus_path)(host_bridge, rootbus); 407 } 408 409 return rootbus->qbus.name; 410 } 411 412 static void pci_root_bus_init(PCIBus *bus, DeviceState *parent, 413 MemoryRegion *address_space_mem, 414 MemoryRegion *address_space_io, 415 uint8_t devfn_min) 416 { 417 assert(PCI_FUNC(devfn_min) == 0); 418 bus->devfn_min = devfn_min; 419 bus->slot_reserved_mask = 0x0; 420 bus->address_space_mem = address_space_mem; 421 bus->address_space_io = address_space_io; 422 bus->flags |= PCI_BUS_IS_ROOT; 423 424 /* host bridge */ 425 QLIST_INIT(&bus->child); 426 427 pci_host_bus_register(parent); 428 } 429 430 static void pci_bus_uninit(PCIBus *bus) 431 { 432 pci_host_bus_unregister(BUS(bus)->parent); 433 } 434 435 bool pci_bus_is_express(PCIBus *bus) 436 { 437 return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS); 438 } 439 440 void pci_root_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent, 441 const char *name, 442 MemoryRegion *address_space_mem, 443 MemoryRegion *address_space_io, 444 uint8_t devfn_min, const char *typename) 445 { 446 qbus_create_inplace(bus, bus_size, typename, parent, name); 447 pci_root_bus_init(bus, parent, address_space_mem, address_space_io, 448 devfn_min); 449 } 450 451 PCIBus *pci_root_bus_new(DeviceState *parent, const char *name, 452 MemoryRegion *address_space_mem, 453 MemoryRegion *address_space_io, 454 uint8_t devfn_min, const char *typename) 455 { 456 PCIBus *bus; 457 458 bus = PCI_BUS(qbus_create(typename, parent, name)); 459 pci_root_bus_init(bus, parent, address_space_mem, address_space_io, 460 devfn_min); 461 return bus; 462 } 463 464 void pci_root_bus_cleanup(PCIBus *bus) 465 { 466 pci_bus_uninit(bus); 467 /* the caller of the unplug hotplug handler will delete this device */ 468 qbus_unrealize(BUS(bus)); 469 } 470 471 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 472 void *irq_opaque, int nirq) 473 { 474 bus->set_irq = set_irq; 475 bus->map_irq = map_irq; 476 bus->irq_opaque = irq_opaque; 477 bus->nirq = nirq; 478 bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0])); 479 } 480 481 void pci_bus_irqs_cleanup(PCIBus *bus) 482 { 483 bus->set_irq = NULL; 484 bus->map_irq = NULL; 485 bus->irq_opaque = NULL; 486 bus->nirq = 0; 487 g_free(bus->irq_count); 488 } 489 490 PCIBus *pci_register_root_bus(DeviceState *parent, const char *name, 491 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 492 void *irq_opaque, 493 MemoryRegion *address_space_mem, 494 MemoryRegion *address_space_io, 495 uint8_t devfn_min, int nirq, 496 const char *typename) 497 { 498 PCIBus *bus; 499 500 bus = pci_root_bus_new(parent, name, address_space_mem, 501 address_space_io, devfn_min, typename); 502 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq); 503 return bus; 504 } 505 506 void pci_unregister_root_bus(PCIBus *bus) 507 { 508 pci_bus_irqs_cleanup(bus); 509 pci_root_bus_cleanup(bus); 510 } 511 512 int pci_bus_num(PCIBus *s) 513 { 514 return PCI_BUS_GET_CLASS(s)->bus_num(s); 515 } 516 517 int pci_bus_numa_node(PCIBus *bus) 518 { 519 return PCI_BUS_GET_CLASS(bus)->numa_node(bus); 520 } 521 522 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size, 523 const VMStateField *field) 524 { 525 PCIDevice *s = container_of(pv, PCIDevice, config); 526 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(s); 527 uint8_t *config; 528 int i; 529 530 assert(size == pci_config_size(s)); 531 config = g_malloc(size); 532 533 qemu_get_buffer(f, config, size); 534 for (i = 0; i < size; ++i) { 535 if ((config[i] ^ s->config[i]) & 536 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) { 537 error_report("%s: Bad config data: i=0x%x read: %x device: %x " 538 "cmask: %x wmask: %x w1cmask:%x", __func__, 539 i, config[i], s->config[i], 540 s->cmask[i], s->wmask[i], s->w1cmask[i]); 541 g_free(config); 542 return -EINVAL; 543 } 544 } 545 memcpy(s->config, config, size); 546 547 pci_update_mappings(s); 548 if (pc->is_bridge) { 549 PCIBridge *b = PCI_BRIDGE(s); 550 pci_bridge_update_mappings(b); 551 } 552 553 memory_region_set_enabled(&s->bus_master_enable_region, 554 pci_get_word(s->config + PCI_COMMAND) 555 & PCI_COMMAND_MASTER); 556 557 g_free(config); 558 return 0; 559 } 560 561 /* just put buffer */ 562 static int put_pci_config_device(QEMUFile *f, void *pv, size_t size, 563 const VMStateField *field, JSONWriter *vmdesc) 564 { 565 const uint8_t **v = pv; 566 assert(size == pci_config_size(container_of(pv, PCIDevice, config))); 567 qemu_put_buffer(f, *v, size); 568 569 return 0; 570 } 571 572 static VMStateInfo vmstate_info_pci_config = { 573 .name = "pci config", 574 .get = get_pci_config_device, 575 .put = put_pci_config_device, 576 }; 577 578 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size, 579 const VMStateField *field) 580 { 581 PCIDevice *s = container_of(pv, PCIDevice, irq_state); 582 uint32_t irq_state[PCI_NUM_PINS]; 583 int i; 584 for (i = 0; i < PCI_NUM_PINS; ++i) { 585 irq_state[i] = qemu_get_be32(f); 586 if (irq_state[i] != 0x1 && irq_state[i] != 0) { 587 fprintf(stderr, "irq state %d: must be 0 or 1.\n", 588 irq_state[i]); 589 return -EINVAL; 590 } 591 } 592 593 for (i = 0; i < PCI_NUM_PINS; ++i) { 594 pci_set_irq_state(s, i, irq_state[i]); 595 } 596 597 return 0; 598 } 599 600 static int put_pci_irq_state(QEMUFile *f, void *pv, size_t size, 601 const VMStateField *field, JSONWriter *vmdesc) 602 { 603 int i; 604 PCIDevice *s = container_of(pv, PCIDevice, irq_state); 605 606 for (i = 0; i < PCI_NUM_PINS; ++i) { 607 qemu_put_be32(f, pci_irq_state(s, i)); 608 } 609 610 return 0; 611 } 612 613 static VMStateInfo vmstate_info_pci_irq_state = { 614 .name = "pci irq state", 615 .get = get_pci_irq_state, 616 .put = put_pci_irq_state, 617 }; 618 619 static bool migrate_is_pcie(void *opaque, int version_id) 620 { 621 return pci_is_express((PCIDevice *)opaque); 622 } 623 624 static bool migrate_is_not_pcie(void *opaque, int version_id) 625 { 626 return !pci_is_express((PCIDevice *)opaque); 627 } 628 629 const VMStateDescription vmstate_pci_device = { 630 .name = "PCIDevice", 631 .version_id = 2, 632 .minimum_version_id = 1, 633 .fields = (VMStateField[]) { 634 VMSTATE_INT32_POSITIVE_LE(version_id, PCIDevice), 635 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice, 636 migrate_is_not_pcie, 637 0, vmstate_info_pci_config, 638 PCI_CONFIG_SPACE_SIZE), 639 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice, 640 migrate_is_pcie, 641 0, vmstate_info_pci_config, 642 PCIE_CONFIG_SPACE_SIZE), 643 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2, 644 vmstate_info_pci_irq_state, 645 PCI_NUM_PINS * sizeof(int32_t)), 646 VMSTATE_END_OF_LIST() 647 } 648 }; 649 650 651 void pci_device_save(PCIDevice *s, QEMUFile *f) 652 { 653 /* Clear interrupt status bit: it is implicit 654 * in irq_state which we are saving. 655 * This makes us compatible with old devices 656 * which never set or clear this bit. */ 657 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; 658 vmstate_save_state(f, &vmstate_pci_device, s, NULL); 659 /* Restore the interrupt status bit. */ 660 pci_update_irq_status(s); 661 } 662 663 int pci_device_load(PCIDevice *s, QEMUFile *f) 664 { 665 int ret; 666 ret = vmstate_load_state(f, &vmstate_pci_device, s, s->version_id); 667 /* Restore the interrupt status bit. */ 668 pci_update_irq_status(s); 669 return ret; 670 } 671 672 static void pci_set_default_subsystem_id(PCIDevice *pci_dev) 673 { 674 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, 675 pci_default_sub_vendor_id); 676 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 677 pci_default_sub_device_id); 678 } 679 680 /* 681 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL 682 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error 683 */ 684 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, 685 unsigned int *slotp, unsigned int *funcp) 686 { 687 const char *p; 688 char *e; 689 unsigned long val; 690 unsigned long dom = 0, bus = 0; 691 unsigned int slot = 0; 692 unsigned int func = 0; 693 694 p = addr; 695 val = strtoul(p, &e, 16); 696 if (e == p) 697 return -1; 698 if (*e == ':') { 699 bus = val; 700 p = e + 1; 701 val = strtoul(p, &e, 16); 702 if (e == p) 703 return -1; 704 if (*e == ':') { 705 dom = bus; 706 bus = val; 707 p = e + 1; 708 val = strtoul(p, &e, 16); 709 if (e == p) 710 return -1; 711 } 712 } 713 714 slot = val; 715 716 if (funcp != NULL) { 717 if (*e != '.') 718 return -1; 719 720 p = e + 1; 721 val = strtoul(p, &e, 16); 722 if (e == p) 723 return -1; 724 725 func = val; 726 } 727 728 /* if funcp == NULL func is 0 */ 729 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7) 730 return -1; 731 732 if (*e) 733 return -1; 734 735 *domp = dom; 736 *busp = bus; 737 *slotp = slot; 738 if (funcp != NULL) 739 *funcp = func; 740 return 0; 741 } 742 743 static void pci_init_cmask(PCIDevice *dev) 744 { 745 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff); 746 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff); 747 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST; 748 dev->cmask[PCI_REVISION_ID] = 0xff; 749 dev->cmask[PCI_CLASS_PROG] = 0xff; 750 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff); 751 dev->cmask[PCI_HEADER_TYPE] = 0xff; 752 dev->cmask[PCI_CAPABILITY_LIST] = 0xff; 753 } 754 755 static void pci_init_wmask(PCIDevice *dev) 756 { 757 int config_size = pci_config_size(dev); 758 759 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff; 760 dev->wmask[PCI_INTERRUPT_LINE] = 0xff; 761 pci_set_word(dev->wmask + PCI_COMMAND, 762 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | 763 PCI_COMMAND_INTX_DISABLE); 764 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR); 765 766 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff, 767 config_size - PCI_CONFIG_HEADER_SIZE); 768 } 769 770 static void pci_init_w1cmask(PCIDevice *dev) 771 { 772 /* 773 * Note: It's okay to set w1cmask even for readonly bits as 774 * long as their value is hardwired to 0. 775 */ 776 pci_set_word(dev->w1cmask + PCI_STATUS, 777 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT | 778 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT | 779 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY); 780 } 781 782 static void pci_init_mask_bridge(PCIDevice *d) 783 { 784 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and 785 PCI_SEC_LETENCY_TIMER */ 786 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4); 787 788 /* base and limit */ 789 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff; 790 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff; 791 pci_set_word(d->wmask + PCI_MEMORY_BASE, 792 PCI_MEMORY_RANGE_MASK & 0xffff); 793 pci_set_word(d->wmask + PCI_MEMORY_LIMIT, 794 PCI_MEMORY_RANGE_MASK & 0xffff); 795 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE, 796 PCI_PREF_RANGE_MASK & 0xffff); 797 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT, 798 PCI_PREF_RANGE_MASK & 0xffff); 799 800 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */ 801 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8); 802 803 /* Supported memory and i/o types */ 804 d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16; 805 d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16; 806 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE, 807 PCI_PREF_RANGE_TYPE_64); 808 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT, 809 PCI_PREF_RANGE_TYPE_64); 810 811 /* 812 * TODO: Bridges default to 10-bit VGA decoding but we currently only 813 * implement 16-bit decoding (no alias support). 814 */ 815 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 816 PCI_BRIDGE_CTL_PARITY | 817 PCI_BRIDGE_CTL_SERR | 818 PCI_BRIDGE_CTL_ISA | 819 PCI_BRIDGE_CTL_VGA | 820 PCI_BRIDGE_CTL_VGA_16BIT | 821 PCI_BRIDGE_CTL_MASTER_ABORT | 822 PCI_BRIDGE_CTL_BUS_RESET | 823 PCI_BRIDGE_CTL_FAST_BACK | 824 PCI_BRIDGE_CTL_DISCARD | 825 PCI_BRIDGE_CTL_SEC_DISCARD | 826 PCI_BRIDGE_CTL_DISCARD_SERR); 827 /* Below does not do anything as we never set this bit, put here for 828 * completeness. */ 829 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL, 830 PCI_BRIDGE_CTL_DISCARD_STATUS); 831 d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK; 832 d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK; 833 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE, 834 PCI_PREF_RANGE_TYPE_MASK); 835 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT, 836 PCI_PREF_RANGE_TYPE_MASK); 837 } 838 839 static void pci_init_multifunction(PCIBus *bus, PCIDevice *dev, Error **errp) 840 { 841 uint8_t slot = PCI_SLOT(dev->devfn); 842 uint8_t func; 843 844 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 845 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION; 846 } 847 848 /* 849 * multifunction bit is interpreted in two ways as follows. 850 * - all functions must set the bit to 1. 851 * Example: Intel X53 852 * - function 0 must set the bit, but the rest function (> 0) 853 * is allowed to leave the bit to 0. 854 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10, 855 * 856 * So OS (at least Linux) checks the bit of only function 0, 857 * and doesn't see the bit of function > 0. 858 * 859 * The below check allows both interpretation. 860 */ 861 if (PCI_FUNC(dev->devfn)) { 862 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)]; 863 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) { 864 /* function 0 should set multifunction bit */ 865 error_setg(errp, "PCI: single function device can't be populated " 866 "in function %x.%x", slot, PCI_FUNC(dev->devfn)); 867 return; 868 } 869 return; 870 } 871 872 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 873 return; 874 } 875 /* function 0 indicates single function, so function > 0 must be NULL */ 876 for (func = 1; func < PCI_FUNC_MAX; ++func) { 877 if (bus->devices[PCI_DEVFN(slot, func)]) { 878 error_setg(errp, "PCI: %x.0 indicates single function, " 879 "but %x.%x is already populated.", 880 slot, slot, func); 881 return; 882 } 883 } 884 } 885 886 static void pci_config_alloc(PCIDevice *pci_dev) 887 { 888 int config_size = pci_config_size(pci_dev); 889 890 pci_dev->config = g_malloc0(config_size); 891 pci_dev->cmask = g_malloc0(config_size); 892 pci_dev->wmask = g_malloc0(config_size); 893 pci_dev->w1cmask = g_malloc0(config_size); 894 pci_dev->used = g_malloc0(config_size); 895 } 896 897 static void pci_config_free(PCIDevice *pci_dev) 898 { 899 g_free(pci_dev->config); 900 g_free(pci_dev->cmask); 901 g_free(pci_dev->wmask); 902 g_free(pci_dev->w1cmask); 903 g_free(pci_dev->used); 904 } 905 906 static void do_pci_unregister_device(PCIDevice *pci_dev) 907 { 908 pci_get_bus(pci_dev)->devices[pci_dev->devfn] = NULL; 909 pci_config_free(pci_dev); 910 911 if (memory_region_is_mapped(&pci_dev->bus_master_enable_region)) { 912 memory_region_del_subregion(&pci_dev->bus_master_container_region, 913 &pci_dev->bus_master_enable_region); 914 } 915 address_space_destroy(&pci_dev->bus_master_as); 916 } 917 918 /* Extract PCIReqIDCache into BDF format */ 919 static uint16_t pci_req_id_cache_extract(PCIReqIDCache *cache) 920 { 921 uint8_t bus_n; 922 uint16_t result; 923 924 switch (cache->type) { 925 case PCI_REQ_ID_BDF: 926 result = pci_get_bdf(cache->dev); 927 break; 928 case PCI_REQ_ID_SECONDARY_BUS: 929 bus_n = pci_dev_bus_num(cache->dev); 930 result = PCI_BUILD_BDF(bus_n, 0); 931 break; 932 default: 933 error_report("Invalid PCI requester ID cache type: %d", 934 cache->type); 935 exit(1); 936 break; 937 } 938 939 return result; 940 } 941 942 /* Parse bridges up to the root complex and return requester ID 943 * cache for specific device. For full PCIe topology, the cache 944 * result would be exactly the same as getting BDF of the device. 945 * However, several tricks are required when system mixed up with 946 * legacy PCI devices and PCIe-to-PCI bridges. 947 * 948 * Here we cache the proxy device (and type) not requester ID since 949 * bus number might change from time to time. 950 */ 951 static PCIReqIDCache pci_req_id_cache_get(PCIDevice *dev) 952 { 953 PCIDevice *parent; 954 PCIReqIDCache cache = { 955 .dev = dev, 956 .type = PCI_REQ_ID_BDF, 957 }; 958 959 while (!pci_bus_is_root(pci_get_bus(dev))) { 960 /* We are under PCI/PCIe bridges */ 961 parent = pci_get_bus(dev)->parent_dev; 962 if (pci_is_express(parent)) { 963 if (pcie_cap_get_type(parent) == PCI_EXP_TYPE_PCI_BRIDGE) { 964 /* When we pass through PCIe-to-PCI/PCIX bridges, we 965 * override the requester ID using secondary bus 966 * number of parent bridge with zeroed devfn 967 * (pcie-to-pci bridge spec chap 2.3). */ 968 cache.type = PCI_REQ_ID_SECONDARY_BUS; 969 cache.dev = dev; 970 } 971 } else { 972 /* Legacy PCI, override requester ID with the bridge's 973 * BDF upstream. When the root complex connects to 974 * legacy PCI devices (including buses), it can only 975 * obtain requester ID info from directly attached 976 * devices. If devices are attached under bridges, only 977 * the requester ID of the bridge that is directly 978 * attached to the root complex can be recognized. */ 979 cache.type = PCI_REQ_ID_BDF; 980 cache.dev = parent; 981 } 982 dev = parent; 983 } 984 985 return cache; 986 } 987 988 uint16_t pci_requester_id(PCIDevice *dev) 989 { 990 return pci_req_id_cache_extract(&dev->requester_id_cache); 991 } 992 993 static bool pci_bus_devfn_available(PCIBus *bus, int devfn) 994 { 995 return !(bus->devices[devfn]); 996 } 997 998 static bool pci_bus_devfn_reserved(PCIBus *bus, int devfn) 999 { 1000 return bus->slot_reserved_mask & (1UL << PCI_SLOT(devfn)); 1001 } 1002 1003 /* -1 for devfn means auto assign */ 1004 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, 1005 const char *name, int devfn, 1006 Error **errp) 1007 { 1008 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 1009 PCIConfigReadFunc *config_read = pc->config_read; 1010 PCIConfigWriteFunc *config_write = pc->config_write; 1011 Error *local_err = NULL; 1012 DeviceState *dev = DEVICE(pci_dev); 1013 PCIBus *bus = pci_get_bus(pci_dev); 1014 1015 /* Only pci bridges can be attached to extra PCI root buses */ 1016 if (pci_bus_is_root(bus) && bus->parent_dev && !pc->is_bridge) { 1017 error_setg(errp, 1018 "PCI: Only PCI/PCIe bridges can be plugged into %s", 1019 bus->parent_dev->name); 1020 return NULL; 1021 } 1022 1023 if (devfn < 0) { 1024 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices); 1025 devfn += PCI_FUNC_MAX) { 1026 if (pci_bus_devfn_available(bus, devfn) && 1027 !pci_bus_devfn_reserved(bus, devfn)) { 1028 goto found; 1029 } 1030 } 1031 error_setg(errp, "PCI: no slot/function available for %s, all in use " 1032 "or reserved", name); 1033 return NULL; 1034 found: ; 1035 } else if (pci_bus_devfn_reserved(bus, devfn)) { 1036 error_setg(errp, "PCI: slot %d function %d not available for %s," 1037 " reserved", 1038 PCI_SLOT(devfn), PCI_FUNC(devfn), name); 1039 return NULL; 1040 } else if (!pci_bus_devfn_available(bus, devfn)) { 1041 error_setg(errp, "PCI: slot %d function %d not available for %s," 1042 " in use by %s", 1043 PCI_SLOT(devfn), PCI_FUNC(devfn), name, 1044 bus->devices[devfn]->name); 1045 return NULL; 1046 } else if (dev->hotplugged && 1047 pci_get_function_0(pci_dev)) { 1048 error_setg(errp, "PCI: slot %d function 0 already occupied by %s," 1049 " new func %s cannot be exposed to guest.", 1050 PCI_SLOT(pci_get_function_0(pci_dev)->devfn), 1051 pci_get_function_0(pci_dev)->name, 1052 name); 1053 1054 return NULL; 1055 } 1056 1057 pci_dev->devfn = devfn; 1058 pci_dev->requester_id_cache = pci_req_id_cache_get(pci_dev); 1059 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name); 1060 1061 memory_region_init(&pci_dev->bus_master_container_region, OBJECT(pci_dev), 1062 "bus master container", UINT64_MAX); 1063 address_space_init(&pci_dev->bus_master_as, 1064 &pci_dev->bus_master_container_region, pci_dev->name); 1065 1066 if (phase_check(PHASE_MACHINE_READY)) { 1067 pci_init_bus_master(pci_dev); 1068 } 1069 pci_dev->irq_state = 0; 1070 pci_config_alloc(pci_dev); 1071 1072 pci_config_set_vendor_id(pci_dev->config, pc->vendor_id); 1073 pci_config_set_device_id(pci_dev->config, pc->device_id); 1074 pci_config_set_revision(pci_dev->config, pc->revision); 1075 pci_config_set_class(pci_dev->config, pc->class_id); 1076 1077 if (!pc->is_bridge) { 1078 if (pc->subsystem_vendor_id || pc->subsystem_id) { 1079 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, 1080 pc->subsystem_vendor_id); 1081 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 1082 pc->subsystem_id); 1083 } else { 1084 pci_set_default_subsystem_id(pci_dev); 1085 } 1086 } else { 1087 /* subsystem_vendor_id/subsystem_id are only for header type 0 */ 1088 assert(!pc->subsystem_vendor_id); 1089 assert(!pc->subsystem_id); 1090 } 1091 pci_init_cmask(pci_dev); 1092 pci_init_wmask(pci_dev); 1093 pci_init_w1cmask(pci_dev); 1094 if (pc->is_bridge) { 1095 pci_init_mask_bridge(pci_dev); 1096 } 1097 pci_init_multifunction(bus, pci_dev, &local_err); 1098 if (local_err) { 1099 error_propagate(errp, local_err); 1100 do_pci_unregister_device(pci_dev); 1101 return NULL; 1102 } 1103 1104 if (!config_read) 1105 config_read = pci_default_read_config; 1106 if (!config_write) 1107 config_write = pci_default_write_config; 1108 pci_dev->config_read = config_read; 1109 pci_dev->config_write = config_write; 1110 bus->devices[devfn] = pci_dev; 1111 pci_dev->version_id = 2; /* Current pci device vmstate version */ 1112 return pci_dev; 1113 } 1114 1115 static void pci_unregister_io_regions(PCIDevice *pci_dev) 1116 { 1117 PCIIORegion *r; 1118 int i; 1119 1120 for(i = 0; i < PCI_NUM_REGIONS; i++) { 1121 r = &pci_dev->io_regions[i]; 1122 if (!r->size || r->addr == PCI_BAR_UNMAPPED) 1123 continue; 1124 memory_region_del_subregion(r->address_space, r->memory); 1125 } 1126 1127 pci_unregister_vga(pci_dev); 1128 } 1129 1130 static void pci_qdev_unrealize(DeviceState *dev) 1131 { 1132 PCIDevice *pci_dev = PCI_DEVICE(dev); 1133 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 1134 1135 pci_unregister_io_regions(pci_dev); 1136 pci_del_option_rom(pci_dev); 1137 1138 if (pc->exit) { 1139 pc->exit(pci_dev); 1140 } 1141 1142 pci_device_deassert_intx(pci_dev); 1143 do_pci_unregister_device(pci_dev); 1144 } 1145 1146 void pci_register_bar(PCIDevice *pci_dev, int region_num, 1147 uint8_t type, MemoryRegion *memory) 1148 { 1149 PCIIORegion *r; 1150 uint32_t addr; /* offset in pci config space */ 1151 uint64_t wmask; 1152 pcibus_t size = memory_region_size(memory); 1153 uint8_t hdr_type; 1154 1155 assert(region_num >= 0); 1156 assert(region_num < PCI_NUM_REGIONS); 1157 assert(is_power_of_2(size)); 1158 1159 /* A PCI bridge device (with Type 1 header) may only have at most 2 BARs */ 1160 hdr_type = 1161 pci_dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 1162 assert(hdr_type != PCI_HEADER_TYPE_BRIDGE || region_num < 2); 1163 1164 r = &pci_dev->io_regions[region_num]; 1165 r->addr = PCI_BAR_UNMAPPED; 1166 r->size = size; 1167 r->type = type; 1168 r->memory = memory; 1169 r->address_space = type & PCI_BASE_ADDRESS_SPACE_IO 1170 ? pci_get_bus(pci_dev)->address_space_io 1171 : pci_get_bus(pci_dev)->address_space_mem; 1172 1173 wmask = ~(size - 1); 1174 if (region_num == PCI_ROM_SLOT) { 1175 /* ROM enable bit is writable */ 1176 wmask |= PCI_ROM_ADDRESS_ENABLE; 1177 } 1178 1179 addr = pci_bar(pci_dev, region_num); 1180 pci_set_long(pci_dev->config + addr, type); 1181 1182 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) && 1183 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 1184 pci_set_quad(pci_dev->wmask + addr, wmask); 1185 pci_set_quad(pci_dev->cmask + addr, ~0ULL); 1186 } else { 1187 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff); 1188 pci_set_long(pci_dev->cmask + addr, 0xffffffff); 1189 } 1190 } 1191 1192 static void pci_update_vga(PCIDevice *pci_dev) 1193 { 1194 uint16_t cmd; 1195 1196 if (!pci_dev->has_vga) { 1197 return; 1198 } 1199 1200 cmd = pci_get_word(pci_dev->config + PCI_COMMAND); 1201 1202 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_MEM], 1203 cmd & PCI_COMMAND_MEMORY); 1204 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO], 1205 cmd & PCI_COMMAND_IO); 1206 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI], 1207 cmd & PCI_COMMAND_IO); 1208 } 1209 1210 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, 1211 MemoryRegion *io_lo, MemoryRegion *io_hi) 1212 { 1213 PCIBus *bus = pci_get_bus(pci_dev); 1214 1215 assert(!pci_dev->has_vga); 1216 1217 assert(memory_region_size(mem) == QEMU_PCI_VGA_MEM_SIZE); 1218 pci_dev->vga_regions[QEMU_PCI_VGA_MEM] = mem; 1219 memory_region_add_subregion_overlap(bus->address_space_mem, 1220 QEMU_PCI_VGA_MEM_BASE, mem, 1); 1221 1222 assert(memory_region_size(io_lo) == QEMU_PCI_VGA_IO_LO_SIZE); 1223 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO] = io_lo; 1224 memory_region_add_subregion_overlap(bus->address_space_io, 1225 QEMU_PCI_VGA_IO_LO_BASE, io_lo, 1); 1226 1227 assert(memory_region_size(io_hi) == QEMU_PCI_VGA_IO_HI_SIZE); 1228 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI] = io_hi; 1229 memory_region_add_subregion_overlap(bus->address_space_io, 1230 QEMU_PCI_VGA_IO_HI_BASE, io_hi, 1); 1231 pci_dev->has_vga = true; 1232 1233 pci_update_vga(pci_dev); 1234 } 1235 1236 void pci_unregister_vga(PCIDevice *pci_dev) 1237 { 1238 PCIBus *bus = pci_get_bus(pci_dev); 1239 1240 if (!pci_dev->has_vga) { 1241 return; 1242 } 1243 1244 memory_region_del_subregion(bus->address_space_mem, 1245 pci_dev->vga_regions[QEMU_PCI_VGA_MEM]); 1246 memory_region_del_subregion(bus->address_space_io, 1247 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO]); 1248 memory_region_del_subregion(bus->address_space_io, 1249 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI]); 1250 pci_dev->has_vga = false; 1251 } 1252 1253 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num) 1254 { 1255 return pci_dev->io_regions[region_num].addr; 1256 } 1257 1258 static pcibus_t pci_bar_address(PCIDevice *d, 1259 int reg, uint8_t type, pcibus_t size) 1260 { 1261 pcibus_t new_addr, last_addr; 1262 int bar = pci_bar(d, reg); 1263 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND); 1264 Object *machine = qdev_get_machine(); 1265 ObjectClass *oc = object_get_class(machine); 1266 MachineClass *mc = MACHINE_CLASS(oc); 1267 bool allow_0_address = mc->pci_allow_0_address; 1268 1269 if (type & PCI_BASE_ADDRESS_SPACE_IO) { 1270 if (!(cmd & PCI_COMMAND_IO)) { 1271 return PCI_BAR_UNMAPPED; 1272 } 1273 new_addr = pci_get_long(d->config + bar) & ~(size - 1); 1274 last_addr = new_addr + size - 1; 1275 /* Check if 32 bit BAR wraps around explicitly. 1276 * TODO: make priorities correct and remove this work around. 1277 */ 1278 if (last_addr <= new_addr || last_addr >= UINT32_MAX || 1279 (!allow_0_address && new_addr == 0)) { 1280 return PCI_BAR_UNMAPPED; 1281 } 1282 return new_addr; 1283 } 1284 1285 if (!(cmd & PCI_COMMAND_MEMORY)) { 1286 return PCI_BAR_UNMAPPED; 1287 } 1288 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 1289 new_addr = pci_get_quad(d->config + bar); 1290 } else { 1291 new_addr = pci_get_long(d->config + bar); 1292 } 1293 /* the ROM slot has a specific enable bit */ 1294 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) { 1295 return PCI_BAR_UNMAPPED; 1296 } 1297 new_addr &= ~(size - 1); 1298 last_addr = new_addr + size - 1; 1299 /* NOTE: we do not support wrapping */ 1300 /* XXX: as we cannot support really dynamic 1301 mappings, we handle specific values as invalid 1302 mappings. */ 1303 if (last_addr <= new_addr || last_addr == PCI_BAR_UNMAPPED || 1304 (!allow_0_address && new_addr == 0)) { 1305 return PCI_BAR_UNMAPPED; 1306 } 1307 1308 /* Now pcibus_t is 64bit. 1309 * Check if 32 bit BAR wraps around explicitly. 1310 * Without this, PC ide doesn't work well. 1311 * TODO: remove this work around. 1312 */ 1313 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) { 1314 return PCI_BAR_UNMAPPED; 1315 } 1316 1317 /* 1318 * OS is allowed to set BAR beyond its addressable 1319 * bits. For example, 32 bit OS can set 64bit bar 1320 * to >4G. Check it. TODO: we might need to support 1321 * it in the future for e.g. PAE. 1322 */ 1323 if (last_addr >= HWADDR_MAX) { 1324 return PCI_BAR_UNMAPPED; 1325 } 1326 1327 return new_addr; 1328 } 1329 1330 static void pci_update_mappings(PCIDevice *d) 1331 { 1332 PCIIORegion *r; 1333 int i; 1334 pcibus_t new_addr; 1335 1336 for(i = 0; i < PCI_NUM_REGIONS; i++) { 1337 r = &d->io_regions[i]; 1338 1339 /* this region isn't registered */ 1340 if (!r->size) 1341 continue; 1342 1343 new_addr = pci_bar_address(d, i, r->type, r->size); 1344 1345 /* This bar isn't changed */ 1346 if (new_addr == r->addr) 1347 continue; 1348 1349 /* now do the real mapping */ 1350 if (r->addr != PCI_BAR_UNMAPPED) { 1351 trace_pci_update_mappings_del(d, pci_dev_bus_num(d), 1352 PCI_SLOT(d->devfn), 1353 PCI_FUNC(d->devfn), 1354 i, r->addr, r->size); 1355 memory_region_del_subregion(r->address_space, r->memory); 1356 } 1357 r->addr = new_addr; 1358 if (r->addr != PCI_BAR_UNMAPPED) { 1359 trace_pci_update_mappings_add(d, pci_dev_bus_num(d), 1360 PCI_SLOT(d->devfn), 1361 PCI_FUNC(d->devfn), 1362 i, r->addr, r->size); 1363 memory_region_add_subregion_overlap(r->address_space, 1364 r->addr, r->memory, 1); 1365 } 1366 } 1367 1368 pci_update_vga(d); 1369 } 1370 1371 static inline int pci_irq_disabled(PCIDevice *d) 1372 { 1373 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE; 1374 } 1375 1376 /* Called after interrupt disabled field update in config space, 1377 * assert/deassert interrupts if necessary. 1378 * Gets original interrupt disable bit value (before update). */ 1379 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled) 1380 { 1381 int i, disabled = pci_irq_disabled(d); 1382 if (disabled == was_irq_disabled) 1383 return; 1384 for (i = 0; i < PCI_NUM_PINS; ++i) { 1385 int state = pci_irq_state(d, i); 1386 pci_change_irq_level(d, i, disabled ? -state : state); 1387 } 1388 } 1389 1390 uint32_t pci_default_read_config(PCIDevice *d, 1391 uint32_t address, int len) 1392 { 1393 uint32_t val = 0; 1394 1395 assert(address + len <= pci_config_size(d)); 1396 1397 if (pci_is_express_downstream_port(d) && 1398 ranges_overlap(address, len, d->exp.exp_cap + PCI_EXP_LNKSTA, 2)) { 1399 pcie_sync_bridge_lnk(d); 1400 } 1401 memcpy(&val, d->config + address, len); 1402 return le32_to_cpu(val); 1403 } 1404 1405 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val_in, int l) 1406 { 1407 int i, was_irq_disabled = pci_irq_disabled(d); 1408 uint32_t val = val_in; 1409 1410 assert(addr + l <= pci_config_size(d)); 1411 1412 for (i = 0; i < l; val >>= 8, ++i) { 1413 uint8_t wmask = d->wmask[addr + i]; 1414 uint8_t w1cmask = d->w1cmask[addr + i]; 1415 assert(!(wmask & w1cmask)); 1416 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask); 1417 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */ 1418 } 1419 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) || 1420 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) || 1421 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) || 1422 range_covers_byte(addr, l, PCI_COMMAND)) 1423 pci_update_mappings(d); 1424 1425 if (range_covers_byte(addr, l, PCI_COMMAND)) { 1426 pci_update_irq_disabled(d, was_irq_disabled); 1427 memory_region_set_enabled(&d->bus_master_enable_region, 1428 pci_get_word(d->config + PCI_COMMAND) 1429 & PCI_COMMAND_MASTER); 1430 } 1431 1432 msi_write_config(d, addr, val_in, l); 1433 msix_write_config(d, addr, val_in, l); 1434 } 1435 1436 /***********************************************************/ 1437 /* generic PCI irq support */ 1438 1439 /* 0 <= irq_num <= 3. level must be 0 or 1 */ 1440 static void pci_irq_handler(void *opaque, int irq_num, int level) 1441 { 1442 PCIDevice *pci_dev = opaque; 1443 int change; 1444 1445 change = level - pci_irq_state(pci_dev, irq_num); 1446 if (!change) 1447 return; 1448 1449 pci_set_irq_state(pci_dev, irq_num, level); 1450 pci_update_irq_status(pci_dev); 1451 if (pci_irq_disabled(pci_dev)) 1452 return; 1453 pci_change_irq_level(pci_dev, irq_num, change); 1454 } 1455 1456 static inline int pci_intx(PCIDevice *pci_dev) 1457 { 1458 return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1; 1459 } 1460 1461 qemu_irq pci_allocate_irq(PCIDevice *pci_dev) 1462 { 1463 int intx = pci_intx(pci_dev); 1464 1465 return qemu_allocate_irq(pci_irq_handler, pci_dev, intx); 1466 } 1467 1468 void pci_set_irq(PCIDevice *pci_dev, int level) 1469 { 1470 int intx = pci_intx(pci_dev); 1471 pci_irq_handler(pci_dev, intx, level); 1472 } 1473 1474 /* Special hooks used by device assignment */ 1475 void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq) 1476 { 1477 assert(pci_bus_is_root(bus)); 1478 bus->route_intx_to_irq = route_intx_to_irq; 1479 } 1480 1481 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin) 1482 { 1483 PCIBus *bus; 1484 1485 do { 1486 bus = pci_get_bus(dev); 1487 pin = bus->map_irq(dev, pin); 1488 dev = bus->parent_dev; 1489 } while (dev); 1490 1491 if (!bus->route_intx_to_irq) { 1492 error_report("PCI: Bug - unimplemented PCI INTx routing (%s)", 1493 object_get_typename(OBJECT(bus->qbus.parent))); 1494 return (PCIINTxRoute) { PCI_INTX_DISABLED, -1 }; 1495 } 1496 1497 return bus->route_intx_to_irq(bus->irq_opaque, pin); 1498 } 1499 1500 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new) 1501 { 1502 return old->mode != new->mode || old->irq != new->irq; 1503 } 1504 1505 void pci_bus_fire_intx_routing_notifier(PCIBus *bus) 1506 { 1507 PCIDevice *dev; 1508 PCIBus *sec; 1509 int i; 1510 1511 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 1512 dev = bus->devices[i]; 1513 if (dev && dev->intx_routing_notifier) { 1514 dev->intx_routing_notifier(dev); 1515 } 1516 } 1517 1518 QLIST_FOREACH(sec, &bus->child, sibling) { 1519 pci_bus_fire_intx_routing_notifier(sec); 1520 } 1521 } 1522 1523 void pci_device_set_intx_routing_notifier(PCIDevice *dev, 1524 PCIINTxRoutingNotifier notifier) 1525 { 1526 dev->intx_routing_notifier = notifier; 1527 } 1528 1529 /* 1530 * PCI-to-PCI bridge specification 1531 * 9.1: Interrupt routing. Table 9-1 1532 * 1533 * the PCI Express Base Specification, Revision 2.1 1534 * 2.2.8.1: INTx interrutp signaling - Rules 1535 * the Implementation Note 1536 * Table 2-20 1537 */ 1538 /* 1539 * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD 1540 * 0-origin unlike PCI interrupt pin register. 1541 */ 1542 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin) 1543 { 1544 return pci_swizzle(PCI_SLOT(pci_dev->devfn), pin); 1545 } 1546 1547 /***********************************************************/ 1548 /* monitor info on PCI */ 1549 1550 typedef struct { 1551 uint16_t class; 1552 const char *desc; 1553 const char *fw_name; 1554 uint16_t fw_ign_bits; 1555 } pci_class_desc; 1556 1557 static const pci_class_desc pci_class_descriptions[] = 1558 { 1559 { 0x0001, "VGA controller", "display"}, 1560 { 0x0100, "SCSI controller", "scsi"}, 1561 { 0x0101, "IDE controller", "ide"}, 1562 { 0x0102, "Floppy controller", "fdc"}, 1563 { 0x0103, "IPI controller", "ipi"}, 1564 { 0x0104, "RAID controller", "raid"}, 1565 { 0x0106, "SATA controller"}, 1566 { 0x0107, "SAS controller"}, 1567 { 0x0180, "Storage controller"}, 1568 { 0x0200, "Ethernet controller", "ethernet"}, 1569 { 0x0201, "Token Ring controller", "token-ring"}, 1570 { 0x0202, "FDDI controller", "fddi"}, 1571 { 0x0203, "ATM controller", "atm"}, 1572 { 0x0280, "Network controller"}, 1573 { 0x0300, "VGA controller", "display", 0x00ff}, 1574 { 0x0301, "XGA controller"}, 1575 { 0x0302, "3D controller"}, 1576 { 0x0380, "Display controller"}, 1577 { 0x0400, "Video controller", "video"}, 1578 { 0x0401, "Audio controller", "sound"}, 1579 { 0x0402, "Phone"}, 1580 { 0x0403, "Audio controller", "sound"}, 1581 { 0x0480, "Multimedia controller"}, 1582 { 0x0500, "RAM controller", "memory"}, 1583 { 0x0501, "Flash controller", "flash"}, 1584 { 0x0580, "Memory controller"}, 1585 { 0x0600, "Host bridge", "host"}, 1586 { 0x0601, "ISA bridge", "isa"}, 1587 { 0x0602, "EISA bridge", "eisa"}, 1588 { 0x0603, "MC bridge", "mca"}, 1589 { 0x0604, "PCI bridge", "pci-bridge"}, 1590 { 0x0605, "PCMCIA bridge", "pcmcia"}, 1591 { 0x0606, "NUBUS bridge", "nubus"}, 1592 { 0x0607, "CARDBUS bridge", "cardbus"}, 1593 { 0x0608, "RACEWAY bridge"}, 1594 { 0x0680, "Bridge"}, 1595 { 0x0700, "Serial port", "serial"}, 1596 { 0x0701, "Parallel port", "parallel"}, 1597 { 0x0800, "Interrupt controller", "interrupt-controller"}, 1598 { 0x0801, "DMA controller", "dma-controller"}, 1599 { 0x0802, "Timer", "timer"}, 1600 { 0x0803, "RTC", "rtc"}, 1601 { 0x0900, "Keyboard", "keyboard"}, 1602 { 0x0901, "Pen", "pen"}, 1603 { 0x0902, "Mouse", "mouse"}, 1604 { 0x0A00, "Dock station", "dock", 0x00ff}, 1605 { 0x0B00, "i386 cpu", "cpu", 0x00ff}, 1606 { 0x0c00, "Fireware contorller", "fireware"}, 1607 { 0x0c01, "Access bus controller", "access-bus"}, 1608 { 0x0c02, "SSA controller", "ssa"}, 1609 { 0x0c03, "USB controller", "usb"}, 1610 { 0x0c04, "Fibre channel controller", "fibre-channel"}, 1611 { 0x0c05, "SMBus"}, 1612 { 0, NULL} 1613 }; 1614 1615 static void pci_for_each_device_under_bus_reverse(PCIBus *bus, 1616 void (*fn)(PCIBus *b, 1617 PCIDevice *d, 1618 void *opaque), 1619 void *opaque) 1620 { 1621 PCIDevice *d; 1622 int devfn; 1623 1624 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1625 d = bus->devices[ARRAY_SIZE(bus->devices) - 1 - devfn]; 1626 if (d) { 1627 fn(bus, d, opaque); 1628 } 1629 } 1630 } 1631 1632 void pci_for_each_device_reverse(PCIBus *bus, int bus_num, 1633 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque), 1634 void *opaque) 1635 { 1636 bus = pci_find_bus_nr(bus, bus_num); 1637 1638 if (bus) { 1639 pci_for_each_device_under_bus_reverse(bus, fn, opaque); 1640 } 1641 } 1642 1643 static void pci_for_each_device_under_bus(PCIBus *bus, 1644 void (*fn)(PCIBus *b, PCIDevice *d, 1645 void *opaque), 1646 void *opaque) 1647 { 1648 PCIDevice *d; 1649 int devfn; 1650 1651 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1652 d = bus->devices[devfn]; 1653 if (d) { 1654 fn(bus, d, opaque); 1655 } 1656 } 1657 } 1658 1659 void pci_for_each_device(PCIBus *bus, int bus_num, 1660 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque), 1661 void *opaque) 1662 { 1663 bus = pci_find_bus_nr(bus, bus_num); 1664 1665 if (bus) { 1666 pci_for_each_device_under_bus(bus, fn, opaque); 1667 } 1668 } 1669 1670 static const pci_class_desc *get_class_desc(int class) 1671 { 1672 const pci_class_desc *desc; 1673 1674 desc = pci_class_descriptions; 1675 while (desc->desc && class != desc->class) { 1676 desc++; 1677 } 1678 1679 return desc; 1680 } 1681 1682 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num); 1683 1684 static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev) 1685 { 1686 PciMemoryRegionList *head = NULL, **tail = &head; 1687 int i; 1688 1689 for (i = 0; i < PCI_NUM_REGIONS; i++) { 1690 const PCIIORegion *r = &dev->io_regions[i]; 1691 PciMemoryRegion *region; 1692 1693 if (!r->size) { 1694 continue; 1695 } 1696 1697 region = g_malloc0(sizeof(*region)); 1698 1699 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { 1700 region->type = g_strdup("io"); 1701 } else { 1702 region->type = g_strdup("memory"); 1703 region->has_prefetch = true; 1704 region->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH); 1705 region->has_mem_type_64 = true; 1706 region->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64); 1707 } 1708 1709 region->bar = i; 1710 region->address = r->addr; 1711 region->size = r->size; 1712 1713 QAPI_LIST_APPEND(tail, region); 1714 } 1715 1716 return head; 1717 } 1718 1719 static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus, 1720 int bus_num) 1721 { 1722 PciBridgeInfo *info; 1723 PciMemoryRange *range; 1724 1725 info = g_new0(PciBridgeInfo, 1); 1726 1727 info->bus = g_new0(PciBusInfo, 1); 1728 info->bus->number = dev->config[PCI_PRIMARY_BUS]; 1729 info->bus->secondary = dev->config[PCI_SECONDARY_BUS]; 1730 info->bus->subordinate = dev->config[PCI_SUBORDINATE_BUS]; 1731 1732 range = info->bus->io_range = g_new0(PciMemoryRange, 1); 1733 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO); 1734 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO); 1735 1736 range = info->bus->memory_range = g_new0(PciMemoryRange, 1); 1737 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 1738 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 1739 1740 range = info->bus->prefetchable_range = g_new0(PciMemoryRange, 1); 1741 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 1742 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 1743 1744 if (dev->config[PCI_SECONDARY_BUS] != 0) { 1745 PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]); 1746 if (child_bus) { 1747 info->has_devices = true; 1748 info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]); 1749 } 1750 } 1751 1752 return info; 1753 } 1754 1755 static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus, 1756 int bus_num) 1757 { 1758 const pci_class_desc *desc; 1759 PciDeviceInfo *info; 1760 uint8_t type; 1761 int class; 1762 1763 info = g_new0(PciDeviceInfo, 1); 1764 info->bus = bus_num; 1765 info->slot = PCI_SLOT(dev->devfn); 1766 info->function = PCI_FUNC(dev->devfn); 1767 1768 info->class_info = g_new0(PciDeviceClass, 1); 1769 class = pci_get_word(dev->config + PCI_CLASS_DEVICE); 1770 info->class_info->q_class = class; 1771 desc = get_class_desc(class); 1772 if (desc->desc) { 1773 info->class_info->has_desc = true; 1774 info->class_info->desc = g_strdup(desc->desc); 1775 } 1776 1777 info->id = g_new0(PciDeviceId, 1); 1778 info->id->vendor = pci_get_word(dev->config + PCI_VENDOR_ID); 1779 info->id->device = pci_get_word(dev->config + PCI_DEVICE_ID); 1780 info->regions = qmp_query_pci_regions(dev); 1781 info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : ""); 1782 1783 info->irq_pin = dev->config[PCI_INTERRUPT_PIN]; 1784 if (dev->config[PCI_INTERRUPT_PIN] != 0) { 1785 info->has_irq = true; 1786 info->irq = dev->config[PCI_INTERRUPT_LINE]; 1787 } 1788 1789 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 1790 if (type == PCI_HEADER_TYPE_BRIDGE) { 1791 info->has_pci_bridge = true; 1792 info->pci_bridge = qmp_query_pci_bridge(dev, bus, bus_num); 1793 } else if (type == PCI_HEADER_TYPE_NORMAL) { 1794 info->id->has_subsystem = info->id->has_subsystem_vendor = true; 1795 info->id->subsystem = pci_get_word(dev->config + PCI_SUBSYSTEM_ID); 1796 info->id->subsystem_vendor = 1797 pci_get_word(dev->config + PCI_SUBSYSTEM_VENDOR_ID); 1798 } else if (type == PCI_HEADER_TYPE_CARDBUS) { 1799 info->id->has_subsystem = info->id->has_subsystem_vendor = true; 1800 info->id->subsystem = pci_get_word(dev->config + PCI_CB_SUBSYSTEM_ID); 1801 info->id->subsystem_vendor = 1802 pci_get_word(dev->config + PCI_CB_SUBSYSTEM_VENDOR_ID); 1803 } 1804 1805 return info; 1806 } 1807 1808 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num) 1809 { 1810 PciDeviceInfoList *head = NULL, **tail = &head; 1811 PCIDevice *dev; 1812 int devfn; 1813 1814 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1815 dev = bus->devices[devfn]; 1816 if (dev) { 1817 QAPI_LIST_APPEND(tail, qmp_query_pci_device(dev, bus, bus_num)); 1818 } 1819 } 1820 1821 return head; 1822 } 1823 1824 static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num) 1825 { 1826 PciInfo *info = NULL; 1827 1828 bus = pci_find_bus_nr(bus, bus_num); 1829 if (bus) { 1830 info = g_malloc0(sizeof(*info)); 1831 info->bus = bus_num; 1832 info->devices = qmp_query_pci_devices(bus, bus_num); 1833 } 1834 1835 return info; 1836 } 1837 1838 PciInfoList *qmp_query_pci(Error **errp) 1839 { 1840 PciInfoList *head = NULL, **tail = &head; 1841 PCIHostState *host_bridge; 1842 1843 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { 1844 QAPI_LIST_APPEND(tail, 1845 qmp_query_pci_bus(host_bridge->bus, 1846 pci_bus_num(host_bridge->bus))); 1847 } 1848 1849 return head; 1850 } 1851 1852 /* Initialize a PCI NIC. */ 1853 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus, 1854 const char *default_model, 1855 const char *default_devaddr) 1856 { 1857 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr; 1858 GSList *list; 1859 GPtrArray *pci_nic_models; 1860 PCIBus *bus; 1861 PCIDevice *pci_dev; 1862 DeviceState *dev; 1863 int devfn; 1864 int i; 1865 int dom, busnr; 1866 unsigned slot; 1867 1868 if (nd->model && !strcmp(nd->model, "virtio")) { 1869 g_free(nd->model); 1870 nd->model = g_strdup("virtio-net-pci"); 1871 } 1872 1873 list = object_class_get_list_sorted(TYPE_PCI_DEVICE, false); 1874 pci_nic_models = g_ptr_array_new(); 1875 while (list) { 1876 DeviceClass *dc = OBJECT_CLASS_CHECK(DeviceClass, list->data, 1877 TYPE_DEVICE); 1878 GSList *next; 1879 if (test_bit(DEVICE_CATEGORY_NETWORK, dc->categories) && 1880 dc->user_creatable) { 1881 const char *name = object_class_get_name(list->data); 1882 /* 1883 * A network device might also be something else than a NIC, see 1884 * e.g. the "rocker" device. Thus we have to look for the "netdev" 1885 * property, too. Unfortunately, some devices like virtio-net only 1886 * create this property during instance_init, so we have to create 1887 * a temporary instance here to be able to check it. 1888 */ 1889 Object *obj = object_new_with_class(OBJECT_CLASS(dc)); 1890 if (object_property_find(obj, "netdev")) { 1891 g_ptr_array_add(pci_nic_models, (gpointer)name); 1892 } 1893 object_unref(obj); 1894 } 1895 next = list->next; 1896 g_slist_free_1(list); 1897 list = next; 1898 } 1899 g_ptr_array_add(pci_nic_models, NULL); 1900 1901 if (qemu_show_nic_models(nd->model, (const char **)pci_nic_models->pdata)) { 1902 exit(0); 1903 } 1904 1905 i = qemu_find_nic_model(nd, (const char **)pci_nic_models->pdata, 1906 default_model); 1907 if (i < 0) { 1908 exit(1); 1909 } 1910 1911 if (!rootbus) { 1912 error_report("No primary PCI bus"); 1913 exit(1); 1914 } 1915 1916 assert(!rootbus->parent_dev); 1917 1918 if (!devaddr) { 1919 devfn = -1; 1920 busnr = 0; 1921 } else { 1922 if (pci_parse_devaddr(devaddr, &dom, &busnr, &slot, NULL) < 0) { 1923 error_report("Invalid PCI device address %s for device %s", 1924 devaddr, nd->model); 1925 exit(1); 1926 } 1927 1928 if (dom != 0) { 1929 error_report("No support for non-zero PCI domains"); 1930 exit(1); 1931 } 1932 1933 devfn = PCI_DEVFN(slot, 0); 1934 } 1935 1936 bus = pci_find_bus_nr(rootbus, busnr); 1937 if (!bus) { 1938 error_report("Invalid PCI device address %s for device %s", 1939 devaddr, nd->model); 1940 exit(1); 1941 } 1942 1943 pci_dev = pci_new(devfn, nd->model); 1944 dev = &pci_dev->qdev; 1945 qdev_set_nic_properties(dev, nd); 1946 pci_realize_and_unref(pci_dev, bus, &error_fatal); 1947 g_ptr_array_free(pci_nic_models, true); 1948 return pci_dev; 1949 } 1950 1951 PCIDevice *pci_vga_init(PCIBus *bus) 1952 { 1953 switch (vga_interface_type) { 1954 case VGA_CIRRUS: 1955 return pci_create_simple(bus, -1, "cirrus-vga"); 1956 case VGA_QXL: 1957 return pci_create_simple(bus, -1, "qxl-vga"); 1958 case VGA_STD: 1959 return pci_create_simple(bus, -1, "VGA"); 1960 case VGA_VMWARE: 1961 return pci_create_simple(bus, -1, "vmware-svga"); 1962 case VGA_VIRTIO: 1963 return pci_create_simple(bus, -1, "virtio-vga"); 1964 case VGA_NONE: 1965 default: /* Other non-PCI types. Checking for unsupported types is already 1966 done in vl.c. */ 1967 return NULL; 1968 } 1969 } 1970 1971 /* Whether a given bus number is in range of the secondary 1972 * bus of the given bridge device. */ 1973 static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num) 1974 { 1975 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) & 1976 PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ && 1977 dev->config[PCI_SECONDARY_BUS] <= bus_num && 1978 bus_num <= dev->config[PCI_SUBORDINATE_BUS]; 1979 } 1980 1981 /* Whether a given bus number is in a range of a root bus */ 1982 static bool pci_root_bus_in_range(PCIBus *bus, int bus_num) 1983 { 1984 int i; 1985 1986 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 1987 PCIDevice *dev = bus->devices[i]; 1988 1989 if (dev && PCI_DEVICE_GET_CLASS(dev)->is_bridge) { 1990 if (pci_secondary_bus_in_range(dev, bus_num)) { 1991 return true; 1992 } 1993 } 1994 } 1995 1996 return false; 1997 } 1998 1999 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num) 2000 { 2001 PCIBus *sec; 2002 2003 if (!bus) { 2004 return NULL; 2005 } 2006 2007 if (pci_bus_num(bus) == bus_num) { 2008 return bus; 2009 } 2010 2011 /* Consider all bus numbers in range for the host pci bridge. */ 2012 if (!pci_bus_is_root(bus) && 2013 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) { 2014 return NULL; 2015 } 2016 2017 /* try child bus */ 2018 for (; bus; bus = sec) { 2019 QLIST_FOREACH(sec, &bus->child, sibling) { 2020 if (pci_bus_num(sec) == bus_num) { 2021 return sec; 2022 } 2023 /* PXB buses assumed to be children of bus 0 */ 2024 if (pci_bus_is_root(sec)) { 2025 if (pci_root_bus_in_range(sec, bus_num)) { 2026 break; 2027 } 2028 } else { 2029 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) { 2030 break; 2031 } 2032 } 2033 } 2034 } 2035 2036 return NULL; 2037 } 2038 2039 void pci_for_each_bus_depth_first(PCIBus *bus, 2040 void *(*begin)(PCIBus *bus, void *parent_state), 2041 void (*end)(PCIBus *bus, void *state), 2042 void *parent_state) 2043 { 2044 PCIBus *sec; 2045 void *state; 2046 2047 if (!bus) { 2048 return; 2049 } 2050 2051 if (begin) { 2052 state = begin(bus, parent_state); 2053 } else { 2054 state = parent_state; 2055 } 2056 2057 QLIST_FOREACH(sec, &bus->child, sibling) { 2058 pci_for_each_bus_depth_first(sec, begin, end, state); 2059 } 2060 2061 if (end) { 2062 end(bus, state); 2063 } 2064 } 2065 2066 2067 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn) 2068 { 2069 bus = pci_find_bus_nr(bus, bus_num); 2070 2071 if (!bus) 2072 return NULL; 2073 2074 return bus->devices[devfn]; 2075 } 2076 2077 static void pci_qdev_realize(DeviceState *qdev, Error **errp) 2078 { 2079 PCIDevice *pci_dev = (PCIDevice *)qdev; 2080 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 2081 ObjectClass *klass = OBJECT_CLASS(pc); 2082 Error *local_err = NULL; 2083 bool is_default_rom; 2084 uint16_t class_id; 2085 2086 /* initialize cap_present for pci_is_express() and pci_config_size(), 2087 * Note that hybrid PCIs are not set automatically and need to manage 2088 * QEMU_PCI_CAP_EXPRESS manually */ 2089 if (object_class_dynamic_cast(klass, INTERFACE_PCIE_DEVICE) && 2090 !object_class_dynamic_cast(klass, INTERFACE_CONVENTIONAL_PCI_DEVICE)) { 2091 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; 2092 } 2093 2094 pci_dev = do_pci_register_device(pci_dev, 2095 object_get_typename(OBJECT(qdev)), 2096 pci_dev->devfn, errp); 2097 if (pci_dev == NULL) 2098 return; 2099 2100 if (pc->realize) { 2101 pc->realize(pci_dev, &local_err); 2102 if (local_err) { 2103 error_propagate(errp, local_err); 2104 do_pci_unregister_device(pci_dev); 2105 return; 2106 } 2107 } 2108 2109 if (pci_dev->failover_pair_id) { 2110 if (!pci_bus_is_express(pci_get_bus(pci_dev))) { 2111 error_setg(errp, "failover primary device must be on " 2112 "PCIExpress bus"); 2113 pci_qdev_unrealize(DEVICE(pci_dev)); 2114 return; 2115 } 2116 class_id = pci_get_word(pci_dev->config + PCI_CLASS_DEVICE); 2117 if (class_id != PCI_CLASS_NETWORK_ETHERNET) { 2118 error_setg(errp, "failover primary device is not an " 2119 "Ethernet device"); 2120 pci_qdev_unrealize(DEVICE(pci_dev)); 2121 return; 2122 } 2123 if (!(pci_dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) 2124 && (PCI_FUNC(pci_dev->devfn) == 0)) { 2125 qdev->allow_unplug_during_migration = true; 2126 } else { 2127 error_setg(errp, "failover: primary device must be in its own " 2128 "PCI slot"); 2129 pci_qdev_unrealize(DEVICE(pci_dev)); 2130 return; 2131 } 2132 qdev->allow_unplug_during_migration = true; 2133 } 2134 2135 /* rom loading */ 2136 is_default_rom = false; 2137 if (pci_dev->romfile == NULL && pc->romfile != NULL) { 2138 pci_dev->romfile = g_strdup(pc->romfile); 2139 is_default_rom = true; 2140 } 2141 2142 pci_add_option_rom(pci_dev, is_default_rom, &local_err); 2143 if (local_err) { 2144 error_propagate(errp, local_err); 2145 pci_qdev_unrealize(DEVICE(pci_dev)); 2146 return; 2147 } 2148 } 2149 2150 PCIDevice *pci_new_multifunction(int devfn, bool multifunction, 2151 const char *name) 2152 { 2153 DeviceState *dev; 2154 2155 dev = qdev_new(name); 2156 qdev_prop_set_int32(dev, "addr", devfn); 2157 qdev_prop_set_bit(dev, "multifunction", multifunction); 2158 return PCI_DEVICE(dev); 2159 } 2160 2161 PCIDevice *pci_new(int devfn, const char *name) 2162 { 2163 return pci_new_multifunction(devfn, false, name); 2164 } 2165 2166 bool pci_realize_and_unref(PCIDevice *dev, PCIBus *bus, Error **errp) 2167 { 2168 return qdev_realize_and_unref(&dev->qdev, &bus->qbus, errp); 2169 } 2170 2171 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, 2172 bool multifunction, 2173 const char *name) 2174 { 2175 PCIDevice *dev = pci_new_multifunction(devfn, multifunction, name); 2176 pci_realize_and_unref(dev, bus, &error_fatal); 2177 return dev; 2178 } 2179 2180 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name) 2181 { 2182 return pci_create_simple_multifunction(bus, devfn, false, name); 2183 } 2184 2185 static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size) 2186 { 2187 int offset = PCI_CONFIG_HEADER_SIZE; 2188 int i; 2189 for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) { 2190 if (pdev->used[i]) 2191 offset = i + 1; 2192 else if (i - offset + 1 == size) 2193 return offset; 2194 } 2195 return 0; 2196 } 2197 2198 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id, 2199 uint8_t *prev_p) 2200 { 2201 uint8_t next, prev; 2202 2203 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST)) 2204 return 0; 2205 2206 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); 2207 prev = next + PCI_CAP_LIST_NEXT) 2208 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id) 2209 break; 2210 2211 if (prev_p) 2212 *prev_p = prev; 2213 return next; 2214 } 2215 2216 static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset) 2217 { 2218 uint8_t next, prev, found = 0; 2219 2220 if (!(pdev->used[offset])) { 2221 return 0; 2222 } 2223 2224 assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST); 2225 2226 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); 2227 prev = next + PCI_CAP_LIST_NEXT) { 2228 if (next <= offset && next > found) { 2229 found = next; 2230 } 2231 } 2232 return found; 2233 } 2234 2235 /* Patch the PCI vendor and device ids in a PCI rom image if necessary. 2236 This is needed for an option rom which is used for more than one device. */ 2237 static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size) 2238 { 2239 uint16_t vendor_id; 2240 uint16_t device_id; 2241 uint16_t rom_vendor_id; 2242 uint16_t rom_device_id; 2243 uint16_t rom_magic; 2244 uint16_t pcir_offset; 2245 uint8_t checksum; 2246 2247 /* Words in rom data are little endian (like in PCI configuration), 2248 so they can be read / written with pci_get_word / pci_set_word. */ 2249 2250 /* Only a valid rom will be patched. */ 2251 rom_magic = pci_get_word(ptr); 2252 if (rom_magic != 0xaa55) { 2253 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic); 2254 return; 2255 } 2256 pcir_offset = pci_get_word(ptr + 0x18); 2257 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) { 2258 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset); 2259 return; 2260 } 2261 2262 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID); 2263 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID); 2264 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4); 2265 rom_device_id = pci_get_word(ptr + pcir_offset + 6); 2266 2267 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile, 2268 vendor_id, device_id, rom_vendor_id, rom_device_id); 2269 2270 checksum = ptr[6]; 2271 2272 if (vendor_id != rom_vendor_id) { 2273 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */ 2274 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8); 2275 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8); 2276 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); 2277 ptr[6] = checksum; 2278 pci_set_word(ptr + pcir_offset + 4, vendor_id); 2279 } 2280 2281 if (device_id != rom_device_id) { 2282 /* Patch device id and checksum (at offset 6 for etherboot roms). */ 2283 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8); 2284 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8); 2285 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); 2286 ptr[6] = checksum; 2287 pci_set_word(ptr + pcir_offset + 6, device_id); 2288 } 2289 } 2290 2291 /* Add an option rom for the device */ 2292 static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, 2293 Error **errp) 2294 { 2295 int size; 2296 char *path; 2297 void *ptr; 2298 char name[32]; 2299 const VMStateDescription *vmsd; 2300 2301 if (!pdev->romfile) 2302 return; 2303 if (strlen(pdev->romfile) == 0) 2304 return; 2305 2306 if (!pdev->rom_bar) { 2307 /* 2308 * Load rom via fw_cfg instead of creating a rom bar, 2309 * for 0.11 compatibility. 2310 */ 2311 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE); 2312 2313 /* 2314 * Hot-plugged devices can't use the option ROM 2315 * if the rom bar is disabled. 2316 */ 2317 if (DEVICE(pdev)->hotplugged) { 2318 error_setg(errp, "Hot-plugged device without ROM bar" 2319 " can't have an option ROM"); 2320 return; 2321 } 2322 2323 if (class == 0x0300) { 2324 rom_add_vga(pdev->romfile); 2325 } else { 2326 rom_add_option(pdev->romfile, -1); 2327 } 2328 return; 2329 } 2330 2331 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile); 2332 if (path == NULL) { 2333 path = g_strdup(pdev->romfile); 2334 } 2335 2336 size = get_image_size(path); 2337 if (size < 0) { 2338 error_setg(errp, "failed to find romfile \"%s\"", pdev->romfile); 2339 g_free(path); 2340 return; 2341 } else if (size == 0) { 2342 error_setg(errp, "romfile \"%s\" is empty", pdev->romfile); 2343 g_free(path); 2344 return; 2345 } 2346 size = pow2ceil(size); 2347 2348 vmsd = qdev_get_vmsd(DEVICE(pdev)); 2349 2350 if (vmsd) { 2351 snprintf(name, sizeof(name), "%s.rom", vmsd->name); 2352 } else { 2353 snprintf(name, sizeof(name), "%s.rom", object_get_typename(OBJECT(pdev))); 2354 } 2355 pdev->has_rom = true; 2356 memory_region_init_rom(&pdev->rom, OBJECT(pdev), name, size, &error_fatal); 2357 ptr = memory_region_get_ram_ptr(&pdev->rom); 2358 if (load_image_size(path, ptr, size) < 0) { 2359 error_setg(errp, "failed to load romfile \"%s\"", pdev->romfile); 2360 g_free(path); 2361 return; 2362 } 2363 g_free(path); 2364 2365 if (is_default_rom) { 2366 /* Only the default rom images will be patched (if needed). */ 2367 pci_patch_ids(pdev, ptr, size); 2368 } 2369 2370 pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom); 2371 } 2372 2373 static void pci_del_option_rom(PCIDevice *pdev) 2374 { 2375 if (!pdev->has_rom) 2376 return; 2377 2378 vmstate_unregister_ram(&pdev->rom, &pdev->qdev); 2379 pdev->has_rom = false; 2380 } 2381 2382 /* 2383 * On success, pci_add_capability() returns a positive value 2384 * that the offset of the pci capability. 2385 * On failure, it sets an error and returns a negative error 2386 * code. 2387 */ 2388 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, 2389 uint8_t offset, uint8_t size, 2390 Error **errp) 2391 { 2392 uint8_t *config; 2393 int i, overlapping_cap; 2394 2395 if (!offset) { 2396 offset = pci_find_space(pdev, size); 2397 /* out of PCI config space is programming error */ 2398 assert(offset); 2399 } else { 2400 /* Verify that capabilities don't overlap. Note: device assignment 2401 * depends on this check to verify that the device is not broken. 2402 * Should never trigger for emulated devices, but it's helpful 2403 * for debugging these. */ 2404 for (i = offset; i < offset + size; i++) { 2405 overlapping_cap = pci_find_capability_at_offset(pdev, i); 2406 if (overlapping_cap) { 2407 error_setg(errp, "%s:%02x:%02x.%x " 2408 "Attempt to add PCI capability %x at offset " 2409 "%x overlaps existing capability %x at offset %x", 2410 pci_root_bus_path(pdev), pci_dev_bus_num(pdev), 2411 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), 2412 cap_id, offset, overlapping_cap, i); 2413 return -EINVAL; 2414 } 2415 } 2416 } 2417 2418 config = pdev->config + offset; 2419 config[PCI_CAP_LIST_ID] = cap_id; 2420 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST]; 2421 pdev->config[PCI_CAPABILITY_LIST] = offset; 2422 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST; 2423 memset(pdev->used + offset, 0xFF, QEMU_ALIGN_UP(size, 4)); 2424 /* Make capability read-only by default */ 2425 memset(pdev->wmask + offset, 0, size); 2426 /* Check capability by default */ 2427 memset(pdev->cmask + offset, 0xFF, size); 2428 return offset; 2429 } 2430 2431 /* Unlink capability from the pci config space. */ 2432 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size) 2433 { 2434 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev); 2435 if (!offset) 2436 return; 2437 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT]; 2438 /* Make capability writable again */ 2439 memset(pdev->wmask + offset, 0xff, size); 2440 memset(pdev->w1cmask + offset, 0, size); 2441 /* Clear cmask as device-specific registers can't be checked */ 2442 memset(pdev->cmask + offset, 0, size); 2443 memset(pdev->used + offset, 0, QEMU_ALIGN_UP(size, 4)); 2444 2445 if (!pdev->config[PCI_CAPABILITY_LIST]) 2446 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST; 2447 } 2448 2449 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id) 2450 { 2451 return pci_find_capability_list(pdev, cap_id, NULL); 2452 } 2453 2454 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent) 2455 { 2456 PCIDevice *d = (PCIDevice *)dev; 2457 const pci_class_desc *desc; 2458 char ctxt[64]; 2459 PCIIORegion *r; 2460 int i, class; 2461 2462 class = pci_get_word(d->config + PCI_CLASS_DEVICE); 2463 desc = pci_class_descriptions; 2464 while (desc->desc && class != desc->class) 2465 desc++; 2466 if (desc->desc) { 2467 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc); 2468 } else { 2469 snprintf(ctxt, sizeof(ctxt), "Class %04x", class); 2470 } 2471 2472 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, " 2473 "pci id %04x:%04x (sub %04x:%04x)\n", 2474 indent, "", ctxt, pci_dev_bus_num(d), 2475 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn), 2476 pci_get_word(d->config + PCI_VENDOR_ID), 2477 pci_get_word(d->config + PCI_DEVICE_ID), 2478 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID), 2479 pci_get_word(d->config + PCI_SUBSYSTEM_ID)); 2480 for (i = 0; i < PCI_NUM_REGIONS; i++) { 2481 r = &d->io_regions[i]; 2482 if (!r->size) 2483 continue; 2484 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS 2485 " [0x%"FMT_PCIBUS"]\n", 2486 indent, "", 2487 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem", 2488 r->addr, r->addr + r->size - 1); 2489 } 2490 } 2491 2492 static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len) 2493 { 2494 PCIDevice *d = (PCIDevice *)dev; 2495 const char *name = NULL; 2496 const pci_class_desc *desc = pci_class_descriptions; 2497 int class = pci_get_word(d->config + PCI_CLASS_DEVICE); 2498 2499 while (desc->desc && 2500 (class & ~desc->fw_ign_bits) != 2501 (desc->class & ~desc->fw_ign_bits)) { 2502 desc++; 2503 } 2504 2505 if (desc->desc) { 2506 name = desc->fw_name; 2507 } 2508 2509 if (name) { 2510 pstrcpy(buf, len, name); 2511 } else { 2512 snprintf(buf, len, "pci%04x,%04x", 2513 pci_get_word(d->config + PCI_VENDOR_ID), 2514 pci_get_word(d->config + PCI_DEVICE_ID)); 2515 } 2516 2517 return buf; 2518 } 2519 2520 static char *pcibus_get_fw_dev_path(DeviceState *dev) 2521 { 2522 PCIDevice *d = (PCIDevice *)dev; 2523 char path[50], name[33]; 2524 int off; 2525 2526 off = snprintf(path, sizeof(path), "%s@%x", 2527 pci_dev_fw_name(dev, name, sizeof name), 2528 PCI_SLOT(d->devfn)); 2529 if (PCI_FUNC(d->devfn)) 2530 snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn)); 2531 return g_strdup(path); 2532 } 2533 2534 static char *pcibus_get_dev_path(DeviceState *dev) 2535 { 2536 PCIDevice *d = container_of(dev, PCIDevice, qdev); 2537 PCIDevice *t; 2538 int slot_depth; 2539 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function. 2540 * 00 is added here to make this format compatible with 2541 * domain:Bus:Slot.Func for systems without nested PCI bridges. 2542 * Slot.Function list specifies the slot and function numbers for all 2543 * devices on the path from root to the specific device. */ 2544 const char *root_bus_path; 2545 int root_bus_len; 2546 char slot[] = ":SS.F"; 2547 int slot_len = sizeof slot - 1 /* For '\0' */; 2548 int path_len; 2549 char *path, *p; 2550 int s; 2551 2552 root_bus_path = pci_root_bus_path(d); 2553 root_bus_len = strlen(root_bus_path); 2554 2555 /* Calculate # of slots on path between device and root. */; 2556 slot_depth = 0; 2557 for (t = d; t; t = pci_get_bus(t)->parent_dev) { 2558 ++slot_depth; 2559 } 2560 2561 path_len = root_bus_len + slot_len * slot_depth; 2562 2563 /* Allocate memory, fill in the terminating null byte. */ 2564 path = g_malloc(path_len + 1 /* For '\0' */); 2565 path[path_len] = '\0'; 2566 2567 memcpy(path, root_bus_path, root_bus_len); 2568 2569 /* Fill in slot numbers. We walk up from device to root, so need to print 2570 * them in the reverse order, last to first. */ 2571 p = path + path_len; 2572 for (t = d; t; t = pci_get_bus(t)->parent_dev) { 2573 p -= slot_len; 2574 s = snprintf(slot, sizeof slot, ":%02x.%x", 2575 PCI_SLOT(t->devfn), PCI_FUNC(t->devfn)); 2576 assert(s == slot_len); 2577 memcpy(p, slot, slot_len); 2578 } 2579 2580 return path; 2581 } 2582 2583 static int pci_qdev_find_recursive(PCIBus *bus, 2584 const char *id, PCIDevice **pdev) 2585 { 2586 DeviceState *qdev = qdev_find_recursive(&bus->qbus, id); 2587 if (!qdev) { 2588 return -ENODEV; 2589 } 2590 2591 /* roughly check if given qdev is pci device */ 2592 if (object_dynamic_cast(OBJECT(qdev), TYPE_PCI_DEVICE)) { 2593 *pdev = PCI_DEVICE(qdev); 2594 return 0; 2595 } 2596 return -EINVAL; 2597 } 2598 2599 int pci_qdev_find_device(const char *id, PCIDevice **pdev) 2600 { 2601 PCIHostState *host_bridge; 2602 int rc = -ENODEV; 2603 2604 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { 2605 int tmp = pci_qdev_find_recursive(host_bridge->bus, id, pdev); 2606 if (!tmp) { 2607 rc = 0; 2608 break; 2609 } 2610 if (tmp != -ENODEV) { 2611 rc = tmp; 2612 } 2613 } 2614 2615 return rc; 2616 } 2617 2618 MemoryRegion *pci_address_space(PCIDevice *dev) 2619 { 2620 return pci_get_bus(dev)->address_space_mem; 2621 } 2622 2623 MemoryRegion *pci_address_space_io(PCIDevice *dev) 2624 { 2625 return pci_get_bus(dev)->address_space_io; 2626 } 2627 2628 static void pci_device_class_init(ObjectClass *klass, void *data) 2629 { 2630 DeviceClass *k = DEVICE_CLASS(klass); 2631 2632 k->realize = pci_qdev_realize; 2633 k->unrealize = pci_qdev_unrealize; 2634 k->bus_type = TYPE_PCI_BUS; 2635 device_class_set_props(k, pci_props); 2636 } 2637 2638 static void pci_device_class_base_init(ObjectClass *klass, void *data) 2639 { 2640 if (!object_class_is_abstract(klass)) { 2641 ObjectClass *conventional = 2642 object_class_dynamic_cast(klass, INTERFACE_CONVENTIONAL_PCI_DEVICE); 2643 ObjectClass *pcie = 2644 object_class_dynamic_cast(klass, INTERFACE_PCIE_DEVICE); 2645 assert(conventional || pcie); 2646 } 2647 } 2648 2649 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev) 2650 { 2651 PCIBus *bus = pci_get_bus(dev); 2652 PCIBus *iommu_bus = bus; 2653 uint8_t devfn = dev->devfn; 2654 2655 while (iommu_bus && !iommu_bus->iommu_fn && iommu_bus->parent_dev) { 2656 PCIBus *parent_bus = pci_get_bus(iommu_bus->parent_dev); 2657 2658 /* 2659 * The requester ID of the provided device may be aliased, as seen from 2660 * the IOMMU, due to topology limitations. The IOMMU relies on a 2661 * requester ID to provide a unique AddressSpace for devices, but 2662 * conventional PCI buses pre-date such concepts. Instead, the PCIe- 2663 * to-PCI bridge creates and accepts transactions on behalf of down- 2664 * stream devices. When doing so, all downstream devices are masked 2665 * (aliased) behind a single requester ID. The requester ID used 2666 * depends on the format of the bridge devices. Proper PCIe-to-PCI 2667 * bridges, with a PCIe capability indicating such, follow the 2668 * guidelines of chapter 2.3 of the PCIe-to-PCI/X bridge specification, 2669 * where the bridge uses the seconary bus as the bridge portion of the 2670 * requester ID and devfn of 00.0. For other bridges, typically those 2671 * found on the root complex such as the dmi-to-pci-bridge, we follow 2672 * the convention of typical bare-metal hardware, which uses the 2673 * requester ID of the bridge itself. There are device specific 2674 * exceptions to these rules, but these are the defaults that the 2675 * Linux kernel uses when determining DMA aliases itself and believed 2676 * to be true for the bare metal equivalents of the devices emulated 2677 * in QEMU. 2678 */ 2679 if (!pci_bus_is_express(iommu_bus)) { 2680 PCIDevice *parent = iommu_bus->parent_dev; 2681 2682 if (pci_is_express(parent) && 2683 pcie_cap_get_type(parent) == PCI_EXP_TYPE_PCI_BRIDGE) { 2684 devfn = PCI_DEVFN(0, 0); 2685 bus = iommu_bus; 2686 } else { 2687 devfn = parent->devfn; 2688 bus = parent_bus; 2689 } 2690 } 2691 2692 iommu_bus = parent_bus; 2693 } 2694 if (iommu_bus && iommu_bus->iommu_fn) { 2695 return iommu_bus->iommu_fn(bus, iommu_bus->iommu_opaque, devfn); 2696 } 2697 return &address_space_memory; 2698 } 2699 2700 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque) 2701 { 2702 bus->iommu_fn = fn; 2703 bus->iommu_opaque = opaque; 2704 } 2705 2706 static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque) 2707 { 2708 Range *range = opaque; 2709 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 2710 uint16_t cmd = pci_get_word(dev->config + PCI_COMMAND); 2711 int i; 2712 2713 if (!(cmd & PCI_COMMAND_MEMORY)) { 2714 return; 2715 } 2716 2717 if (pc->is_bridge) { 2718 pcibus_t base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 2719 pcibus_t limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 2720 2721 base = MAX(base, 0x1ULL << 32); 2722 2723 if (limit >= base) { 2724 Range pref_range; 2725 range_set_bounds(&pref_range, base, limit); 2726 range_extend(range, &pref_range); 2727 } 2728 } 2729 for (i = 0; i < PCI_NUM_REGIONS; ++i) { 2730 PCIIORegion *r = &dev->io_regions[i]; 2731 pcibus_t lob, upb; 2732 Range region_range; 2733 2734 if (!r->size || 2735 (r->type & PCI_BASE_ADDRESS_SPACE_IO) || 2736 !(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64)) { 2737 continue; 2738 } 2739 2740 lob = pci_bar_address(dev, i, r->type, r->size); 2741 upb = lob + r->size - 1; 2742 if (lob == PCI_BAR_UNMAPPED) { 2743 continue; 2744 } 2745 2746 lob = MAX(lob, 0x1ULL << 32); 2747 2748 if (upb >= lob) { 2749 range_set_bounds(®ion_range, lob, upb); 2750 range_extend(range, ®ion_range); 2751 } 2752 } 2753 } 2754 2755 void pci_bus_get_w64_range(PCIBus *bus, Range *range) 2756 { 2757 range_make_empty(range); 2758 pci_for_each_device_under_bus(bus, pci_dev_get_w64, range); 2759 } 2760 2761 static bool pcie_has_upstream_port(PCIDevice *dev) 2762 { 2763 PCIDevice *parent_dev = pci_bridge_get_device(pci_get_bus(dev)); 2764 2765 /* Device associated with an upstream port. 2766 * As there are several types of these, it's easier to check the 2767 * parent device: upstream ports are always connected to 2768 * root or downstream ports. 2769 */ 2770 return parent_dev && 2771 pci_is_express(parent_dev) && 2772 parent_dev->exp.exp_cap && 2773 (pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_ROOT_PORT || 2774 pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_DOWNSTREAM); 2775 } 2776 2777 PCIDevice *pci_get_function_0(PCIDevice *pci_dev) 2778 { 2779 PCIBus *bus = pci_get_bus(pci_dev); 2780 2781 if(pcie_has_upstream_port(pci_dev)) { 2782 /* With an upstream PCIe port, we only support 1 device at slot 0 */ 2783 return bus->devices[0]; 2784 } else { 2785 /* Other bus types might support multiple devices at slots 0-31 */ 2786 return bus->devices[PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 0)]; 2787 } 2788 } 2789 2790 MSIMessage pci_get_msi_message(PCIDevice *dev, int vector) 2791 { 2792 MSIMessage msg; 2793 if (msix_enabled(dev)) { 2794 msg = msix_get_message(dev, vector); 2795 } else if (msi_enabled(dev)) { 2796 msg = msi_get_message(dev, vector); 2797 } else { 2798 /* Should never happen */ 2799 error_report("%s: unknown interrupt type", __func__); 2800 abort(); 2801 } 2802 return msg; 2803 } 2804 2805 static const TypeInfo pci_device_type_info = { 2806 .name = TYPE_PCI_DEVICE, 2807 .parent = TYPE_DEVICE, 2808 .instance_size = sizeof(PCIDevice), 2809 .abstract = true, 2810 .class_size = sizeof(PCIDeviceClass), 2811 .class_init = pci_device_class_init, 2812 .class_base_init = pci_device_class_base_init, 2813 }; 2814 2815 static void pci_register_types(void) 2816 { 2817 type_register_static(&pci_bus_info); 2818 type_register_static(&pcie_bus_info); 2819 type_register_static(&conventional_pci_interface_info); 2820 type_register_static(&pcie_interface_info); 2821 type_register_static(&pci_device_type_info); 2822 } 2823 2824 type_init(pci_register_types) 2825