1 /* 2 * QEMU PCI bus manager 3 * 4 * Copyright (c) 2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/hw.h" 25 #include "hw/pci/pci.h" 26 #include "hw/pci/pci_bridge.h" 27 #include "hw/pci/pci_bus.h" 28 #include "hw/pci/pci_host.h" 29 #include "monitor/monitor.h" 30 #include "net/net.h" 31 #include "sysemu/sysemu.h" 32 #include "hw/loader.h" 33 #include "qemu/range.h" 34 #include "qmp-commands.h" 35 #include "hw/pci/msi.h" 36 #include "hw/pci/msix.h" 37 #include "exec/address-spaces.h" 38 39 //#define DEBUG_PCI 40 #ifdef DEBUG_PCI 41 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) 42 #else 43 # define PCI_DPRINTF(format, ...) do { } while (0) 44 #endif 45 46 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent); 47 static char *pcibus_get_dev_path(DeviceState *dev); 48 static char *pcibus_get_fw_dev_path(DeviceState *dev); 49 static int pcibus_reset(BusState *qbus); 50 static void pci_bus_finalize(Object *obj); 51 52 static Property pci_props[] = { 53 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1), 54 DEFINE_PROP_STRING("romfile", PCIDevice, romfile), 55 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1), 56 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present, 57 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false), 58 DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present, 59 QEMU_PCI_CAP_SERR_BITNR, true), 60 DEFINE_PROP_END_OF_LIST() 61 }; 62 63 static void pci_bus_class_init(ObjectClass *klass, void *data) 64 { 65 BusClass *k = BUS_CLASS(klass); 66 67 k->print_dev = pcibus_dev_print; 68 k->get_dev_path = pcibus_get_dev_path; 69 k->get_fw_dev_path = pcibus_get_fw_dev_path; 70 k->reset = pcibus_reset; 71 } 72 73 static const TypeInfo pci_bus_info = { 74 .name = TYPE_PCI_BUS, 75 .parent = TYPE_BUS, 76 .instance_size = sizeof(PCIBus), 77 .instance_finalize = pci_bus_finalize, 78 .class_init = pci_bus_class_init, 79 }; 80 81 static const TypeInfo pcie_bus_info = { 82 .name = TYPE_PCIE_BUS, 83 .parent = TYPE_PCI_BUS, 84 }; 85 86 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num); 87 static void pci_update_mappings(PCIDevice *d); 88 static void pci_irq_handler(void *opaque, int irq_num, int level); 89 static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom); 90 static void pci_del_option_rom(PCIDevice *pdev); 91 92 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET; 93 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU; 94 95 static QLIST_HEAD(, PCIHostState) pci_host_bridges; 96 97 static const VMStateDescription vmstate_pcibus = { 98 .name = "PCIBUS", 99 .version_id = 1, 100 .minimum_version_id = 1, 101 .minimum_version_id_old = 1, 102 .fields = (VMStateField []) { 103 VMSTATE_INT32_EQUAL(nirq, PCIBus), 104 VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t), 105 VMSTATE_END_OF_LIST() 106 } 107 }; 108 static int pci_bar(PCIDevice *d, int reg) 109 { 110 uint8_t type; 111 112 if (reg != PCI_ROM_SLOT) 113 return PCI_BASE_ADDRESS_0 + reg * 4; 114 115 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 116 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS; 117 } 118 119 static inline int pci_irq_state(PCIDevice *d, int irq_num) 120 { 121 return (d->irq_state >> irq_num) & 0x1; 122 } 123 124 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level) 125 { 126 d->irq_state &= ~(0x1 << irq_num); 127 d->irq_state |= level << irq_num; 128 } 129 130 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change) 131 { 132 PCIBus *bus; 133 for (;;) { 134 bus = pci_dev->bus; 135 irq_num = bus->map_irq(pci_dev, irq_num); 136 if (bus->set_irq) 137 break; 138 pci_dev = bus->parent_dev; 139 } 140 bus->irq_count[irq_num] += change; 141 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0); 142 } 143 144 int pci_bus_get_irq_level(PCIBus *bus, int irq_num) 145 { 146 assert(irq_num >= 0); 147 assert(irq_num < bus->nirq); 148 return !!bus->irq_count[irq_num]; 149 } 150 151 /* Update interrupt status bit in config space on interrupt 152 * state change. */ 153 static void pci_update_irq_status(PCIDevice *dev) 154 { 155 if (dev->irq_state) { 156 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT; 157 } else { 158 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; 159 } 160 } 161 162 void pci_device_deassert_intx(PCIDevice *dev) 163 { 164 int i; 165 for (i = 0; i < PCI_NUM_PINS; ++i) { 166 pci_irq_handler(dev, i, 0); 167 } 168 } 169 170 /* 171 * This function is called on #RST and FLR. 172 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set 173 */ 174 void pci_device_reset(PCIDevice *dev) 175 { 176 int r; 177 178 qdev_reset_all(&dev->qdev); 179 180 dev->irq_state = 0; 181 pci_update_irq_status(dev); 182 pci_device_deassert_intx(dev); 183 /* Clear all writable bits */ 184 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND, 185 pci_get_word(dev->wmask + PCI_COMMAND) | 186 pci_get_word(dev->w1cmask + PCI_COMMAND)); 187 pci_word_test_and_clear_mask(dev->config + PCI_STATUS, 188 pci_get_word(dev->wmask + PCI_STATUS) | 189 pci_get_word(dev->w1cmask + PCI_STATUS)); 190 dev->config[PCI_CACHE_LINE_SIZE] = 0x0; 191 dev->config[PCI_INTERRUPT_LINE] = 0x0; 192 for (r = 0; r < PCI_NUM_REGIONS; ++r) { 193 PCIIORegion *region = &dev->io_regions[r]; 194 if (!region->size) { 195 continue; 196 } 197 198 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) && 199 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 200 pci_set_quad(dev->config + pci_bar(dev, r), region->type); 201 } else { 202 pci_set_long(dev->config + pci_bar(dev, r), region->type); 203 } 204 } 205 pci_update_mappings(dev); 206 207 msi_reset(dev); 208 msix_reset(dev); 209 } 210 211 /* 212 * Trigger pci bus reset under a given bus. 213 * To be called on RST# assert. 214 */ 215 void pci_bus_reset(PCIBus *bus) 216 { 217 int i; 218 219 for (i = 0; i < bus->nirq; i++) { 220 bus->irq_count[i] = 0; 221 } 222 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 223 if (bus->devices[i]) { 224 pci_device_reset(bus->devices[i]); 225 } 226 } 227 } 228 229 static int pcibus_reset(BusState *qbus) 230 { 231 pci_bus_reset(DO_UPCAST(PCIBus, qbus, qbus)); 232 233 /* topology traverse is done by pci_bus_reset(). 234 Tell qbus/qdev walker not to traverse the tree */ 235 return 1; 236 } 237 238 static void pci_host_bus_register(PCIBus *bus, DeviceState *parent) 239 { 240 PCIHostState *host_bridge = PCI_HOST_BRIDGE(parent); 241 242 QLIST_INSERT_HEAD(&pci_host_bridges, host_bridge, next); 243 } 244 245 PCIBus *pci_find_primary_bus(void) 246 { 247 PCIBus *primary_bus = NULL; 248 PCIHostState *host; 249 250 QLIST_FOREACH(host, &pci_host_bridges, next) { 251 if (primary_bus) { 252 /* We have multiple root buses, refuse to select a primary */ 253 return NULL; 254 } 255 primary_bus = host->bus; 256 } 257 258 return primary_bus; 259 } 260 261 PCIBus *pci_device_root_bus(const PCIDevice *d) 262 { 263 PCIBus *bus = d->bus; 264 265 while ((d = bus->parent_dev) != NULL) { 266 bus = d->bus; 267 } 268 269 return bus; 270 } 271 272 const char *pci_root_bus_path(PCIDevice *dev) 273 { 274 PCIBus *rootbus = pci_device_root_bus(dev); 275 PCIHostState *host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent); 276 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_GET_CLASS(host_bridge); 277 278 assert(!rootbus->parent_dev); 279 assert(host_bridge->bus == rootbus); 280 281 if (hc->root_bus_path) { 282 return (*hc->root_bus_path)(host_bridge, rootbus); 283 } 284 285 return rootbus->qbus.name; 286 } 287 288 static void pci_bus_init(PCIBus *bus, DeviceState *parent, 289 const char *name, 290 MemoryRegion *address_space_mem, 291 MemoryRegion *address_space_io, 292 uint8_t devfn_min) 293 { 294 assert(PCI_FUNC(devfn_min) == 0); 295 bus->devfn_min = devfn_min; 296 bus->address_space_mem = address_space_mem; 297 bus->address_space_io = address_space_io; 298 299 /* host bridge */ 300 QLIST_INIT(&bus->child); 301 302 pci_host_bus_register(bus, parent); 303 304 vmstate_register(NULL, -1, &vmstate_pcibus, bus); 305 } 306 307 bool pci_bus_is_express(PCIBus *bus) 308 { 309 return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS); 310 } 311 312 bool pci_bus_is_root(PCIBus *bus) 313 { 314 return !bus->parent_dev; 315 } 316 317 void pci_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent, 318 const char *name, 319 MemoryRegion *address_space_mem, 320 MemoryRegion *address_space_io, 321 uint8_t devfn_min, const char *typename) 322 { 323 qbus_create_inplace(bus, bus_size, typename, parent, name); 324 pci_bus_init(bus, parent, name, address_space_mem, 325 address_space_io, devfn_min); 326 } 327 328 PCIBus *pci_bus_new(DeviceState *parent, const char *name, 329 MemoryRegion *address_space_mem, 330 MemoryRegion *address_space_io, 331 uint8_t devfn_min, const char *typename) 332 { 333 PCIBus *bus; 334 335 bus = PCI_BUS(qbus_create(typename, parent, name)); 336 pci_bus_init(bus, parent, name, address_space_mem, 337 address_space_io, devfn_min); 338 return bus; 339 } 340 341 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 342 void *irq_opaque, int nirq) 343 { 344 bus->set_irq = set_irq; 345 bus->map_irq = map_irq; 346 bus->irq_opaque = irq_opaque; 347 bus->nirq = nirq; 348 bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0])); 349 } 350 351 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *qdev) 352 { 353 bus->qbus.allow_hotplug = 1; 354 bus->hotplug = hotplug; 355 bus->hotplug_qdev = qdev; 356 } 357 358 PCIBus *pci_register_bus(DeviceState *parent, const char *name, 359 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 360 void *irq_opaque, 361 MemoryRegion *address_space_mem, 362 MemoryRegion *address_space_io, 363 uint8_t devfn_min, int nirq, const char *typename) 364 { 365 PCIBus *bus; 366 367 bus = pci_bus_new(parent, name, address_space_mem, 368 address_space_io, devfn_min, typename); 369 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq); 370 return bus; 371 } 372 373 int pci_bus_num(PCIBus *s) 374 { 375 if (pci_bus_is_root(s)) 376 return 0; /* pci host bridge */ 377 return s->parent_dev->config[PCI_SECONDARY_BUS]; 378 } 379 380 static void pci_bus_finalize(Object *obj) 381 { 382 PCIBus *bus = PCI_BUS(obj); 383 vmstate_unregister(NULL, &vmstate_pcibus, bus); 384 } 385 386 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size) 387 { 388 PCIDevice *s = container_of(pv, PCIDevice, config); 389 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(s); 390 uint8_t *config; 391 int i; 392 393 assert(size == pci_config_size(s)); 394 config = g_malloc(size); 395 396 qemu_get_buffer(f, config, size); 397 for (i = 0; i < size; ++i) { 398 if ((config[i] ^ s->config[i]) & 399 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) { 400 g_free(config); 401 return -EINVAL; 402 } 403 } 404 memcpy(s->config, config, size); 405 406 pci_update_mappings(s); 407 if (pc->is_bridge) { 408 PCIBridge *b = PCI_BRIDGE(s); 409 pci_bridge_update_mappings(b); 410 } 411 412 memory_region_set_enabled(&s->bus_master_enable_region, 413 pci_get_word(s->config + PCI_COMMAND) 414 & PCI_COMMAND_MASTER); 415 416 g_free(config); 417 return 0; 418 } 419 420 /* just put buffer */ 421 static void put_pci_config_device(QEMUFile *f, void *pv, size_t size) 422 { 423 const uint8_t **v = pv; 424 assert(size == pci_config_size(container_of(pv, PCIDevice, config))); 425 qemu_put_buffer(f, *v, size); 426 } 427 428 static VMStateInfo vmstate_info_pci_config = { 429 .name = "pci config", 430 .get = get_pci_config_device, 431 .put = put_pci_config_device, 432 }; 433 434 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size) 435 { 436 PCIDevice *s = container_of(pv, PCIDevice, irq_state); 437 uint32_t irq_state[PCI_NUM_PINS]; 438 int i; 439 for (i = 0; i < PCI_NUM_PINS; ++i) { 440 irq_state[i] = qemu_get_be32(f); 441 if (irq_state[i] != 0x1 && irq_state[i] != 0) { 442 fprintf(stderr, "irq state %d: must be 0 or 1.\n", 443 irq_state[i]); 444 return -EINVAL; 445 } 446 } 447 448 for (i = 0; i < PCI_NUM_PINS; ++i) { 449 pci_set_irq_state(s, i, irq_state[i]); 450 } 451 452 return 0; 453 } 454 455 static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size) 456 { 457 int i; 458 PCIDevice *s = container_of(pv, PCIDevice, irq_state); 459 460 for (i = 0; i < PCI_NUM_PINS; ++i) { 461 qemu_put_be32(f, pci_irq_state(s, i)); 462 } 463 } 464 465 static VMStateInfo vmstate_info_pci_irq_state = { 466 .name = "pci irq state", 467 .get = get_pci_irq_state, 468 .put = put_pci_irq_state, 469 }; 470 471 const VMStateDescription vmstate_pci_device = { 472 .name = "PCIDevice", 473 .version_id = 2, 474 .minimum_version_id = 1, 475 .minimum_version_id_old = 1, 476 .fields = (VMStateField []) { 477 VMSTATE_INT32_LE(version_id, PCIDevice), 478 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0, 479 vmstate_info_pci_config, 480 PCI_CONFIG_SPACE_SIZE), 481 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2, 482 vmstate_info_pci_irq_state, 483 PCI_NUM_PINS * sizeof(int32_t)), 484 VMSTATE_END_OF_LIST() 485 } 486 }; 487 488 const VMStateDescription vmstate_pcie_device = { 489 .name = "PCIEDevice", 490 .version_id = 2, 491 .minimum_version_id = 1, 492 .minimum_version_id_old = 1, 493 .fields = (VMStateField []) { 494 VMSTATE_INT32_LE(version_id, PCIDevice), 495 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0, 496 vmstate_info_pci_config, 497 PCIE_CONFIG_SPACE_SIZE), 498 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2, 499 vmstate_info_pci_irq_state, 500 PCI_NUM_PINS * sizeof(int32_t)), 501 VMSTATE_END_OF_LIST() 502 } 503 }; 504 505 static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s) 506 { 507 return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device; 508 } 509 510 void pci_device_save(PCIDevice *s, QEMUFile *f) 511 { 512 /* Clear interrupt status bit: it is implicit 513 * in irq_state which we are saving. 514 * This makes us compatible with old devices 515 * which never set or clear this bit. */ 516 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; 517 vmstate_save_state(f, pci_get_vmstate(s), s); 518 /* Restore the interrupt status bit. */ 519 pci_update_irq_status(s); 520 } 521 522 int pci_device_load(PCIDevice *s, QEMUFile *f) 523 { 524 int ret; 525 ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id); 526 /* Restore the interrupt status bit. */ 527 pci_update_irq_status(s); 528 return ret; 529 } 530 531 static void pci_set_default_subsystem_id(PCIDevice *pci_dev) 532 { 533 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, 534 pci_default_sub_vendor_id); 535 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 536 pci_default_sub_device_id); 537 } 538 539 /* 540 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL 541 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error 542 */ 543 int pci_parse_devaddr(const char *addr, int *domp, int *busp, 544 unsigned int *slotp, unsigned int *funcp) 545 { 546 const char *p; 547 char *e; 548 unsigned long val; 549 unsigned long dom = 0, bus = 0; 550 unsigned int slot = 0; 551 unsigned int func = 0; 552 553 p = addr; 554 val = strtoul(p, &e, 16); 555 if (e == p) 556 return -1; 557 if (*e == ':') { 558 bus = val; 559 p = e + 1; 560 val = strtoul(p, &e, 16); 561 if (e == p) 562 return -1; 563 if (*e == ':') { 564 dom = bus; 565 bus = val; 566 p = e + 1; 567 val = strtoul(p, &e, 16); 568 if (e == p) 569 return -1; 570 } 571 } 572 573 slot = val; 574 575 if (funcp != NULL) { 576 if (*e != '.') 577 return -1; 578 579 p = e + 1; 580 val = strtoul(p, &e, 16); 581 if (e == p) 582 return -1; 583 584 func = val; 585 } 586 587 /* if funcp == NULL func is 0 */ 588 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7) 589 return -1; 590 591 if (*e) 592 return -1; 593 594 *domp = dom; 595 *busp = bus; 596 *slotp = slot; 597 if (funcp != NULL) 598 *funcp = func; 599 return 0; 600 } 601 602 PCIBus *pci_get_bus_devfn(int *devfnp, PCIBus *root, const char *devaddr) 603 { 604 int dom, bus; 605 unsigned slot; 606 607 assert(!root->parent_dev); 608 609 if (!root) { 610 fprintf(stderr, "No primary PCI bus\n"); 611 return NULL; 612 } 613 614 if (!devaddr) { 615 *devfnp = -1; 616 return pci_find_bus_nr(root, 0); 617 } 618 619 if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) { 620 return NULL; 621 } 622 623 if (dom != 0) { 624 fprintf(stderr, "No support for non-zero PCI domains\n"); 625 return NULL; 626 } 627 628 *devfnp = PCI_DEVFN(slot, 0); 629 return pci_find_bus_nr(root, bus); 630 } 631 632 static void pci_init_cmask(PCIDevice *dev) 633 { 634 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff); 635 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff); 636 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST; 637 dev->cmask[PCI_REVISION_ID] = 0xff; 638 dev->cmask[PCI_CLASS_PROG] = 0xff; 639 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff); 640 dev->cmask[PCI_HEADER_TYPE] = 0xff; 641 dev->cmask[PCI_CAPABILITY_LIST] = 0xff; 642 } 643 644 static void pci_init_wmask(PCIDevice *dev) 645 { 646 int config_size = pci_config_size(dev); 647 648 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff; 649 dev->wmask[PCI_INTERRUPT_LINE] = 0xff; 650 pci_set_word(dev->wmask + PCI_COMMAND, 651 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | 652 PCI_COMMAND_INTX_DISABLE); 653 if (dev->cap_present & QEMU_PCI_CAP_SERR) { 654 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR); 655 } 656 657 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff, 658 config_size - PCI_CONFIG_HEADER_SIZE); 659 } 660 661 static void pci_init_w1cmask(PCIDevice *dev) 662 { 663 /* 664 * Note: It's okay to set w1cmask even for readonly bits as 665 * long as their value is hardwired to 0. 666 */ 667 pci_set_word(dev->w1cmask + PCI_STATUS, 668 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT | 669 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT | 670 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY); 671 } 672 673 static void pci_init_mask_bridge(PCIDevice *d) 674 { 675 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and 676 PCI_SEC_LETENCY_TIMER */ 677 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4); 678 679 /* base and limit */ 680 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff; 681 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff; 682 pci_set_word(d->wmask + PCI_MEMORY_BASE, 683 PCI_MEMORY_RANGE_MASK & 0xffff); 684 pci_set_word(d->wmask + PCI_MEMORY_LIMIT, 685 PCI_MEMORY_RANGE_MASK & 0xffff); 686 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE, 687 PCI_PREF_RANGE_MASK & 0xffff); 688 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT, 689 PCI_PREF_RANGE_MASK & 0xffff); 690 691 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */ 692 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8); 693 694 /* Supported memory and i/o types */ 695 d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16; 696 d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16; 697 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE, 698 PCI_PREF_RANGE_TYPE_64); 699 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT, 700 PCI_PREF_RANGE_TYPE_64); 701 702 /* 703 * TODO: Bridges default to 10-bit VGA decoding but we currently only 704 * implement 16-bit decoding (no alias support). 705 */ 706 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 707 PCI_BRIDGE_CTL_PARITY | 708 PCI_BRIDGE_CTL_SERR | 709 PCI_BRIDGE_CTL_ISA | 710 PCI_BRIDGE_CTL_VGA | 711 PCI_BRIDGE_CTL_VGA_16BIT | 712 PCI_BRIDGE_CTL_MASTER_ABORT | 713 PCI_BRIDGE_CTL_BUS_RESET | 714 PCI_BRIDGE_CTL_FAST_BACK | 715 PCI_BRIDGE_CTL_DISCARD | 716 PCI_BRIDGE_CTL_SEC_DISCARD | 717 PCI_BRIDGE_CTL_DISCARD_SERR); 718 /* Below does not do anything as we never set this bit, put here for 719 * completeness. */ 720 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL, 721 PCI_BRIDGE_CTL_DISCARD_STATUS); 722 d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK; 723 d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK; 724 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE, 725 PCI_PREF_RANGE_TYPE_MASK); 726 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT, 727 PCI_PREF_RANGE_TYPE_MASK); 728 } 729 730 static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev) 731 { 732 uint8_t slot = PCI_SLOT(dev->devfn); 733 uint8_t func; 734 735 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 736 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION; 737 } 738 739 /* 740 * multifunction bit is interpreted in two ways as follows. 741 * - all functions must set the bit to 1. 742 * Example: Intel X53 743 * - function 0 must set the bit, but the rest function (> 0) 744 * is allowed to leave the bit to 0. 745 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10, 746 * 747 * So OS (at least Linux) checks the bit of only function 0, 748 * and doesn't see the bit of function > 0. 749 * 750 * The below check allows both interpretation. 751 */ 752 if (PCI_FUNC(dev->devfn)) { 753 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)]; 754 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) { 755 /* function 0 should set multifunction bit */ 756 error_report("PCI: single function device can't be populated " 757 "in function %x.%x", slot, PCI_FUNC(dev->devfn)); 758 return -1; 759 } 760 return 0; 761 } 762 763 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 764 return 0; 765 } 766 /* function 0 indicates single function, so function > 0 must be NULL */ 767 for (func = 1; func < PCI_FUNC_MAX; ++func) { 768 if (bus->devices[PCI_DEVFN(slot, func)]) { 769 error_report("PCI: %x.0 indicates single function, " 770 "but %x.%x is already populated.", 771 slot, slot, func); 772 return -1; 773 } 774 } 775 return 0; 776 } 777 778 static void pci_config_alloc(PCIDevice *pci_dev) 779 { 780 int config_size = pci_config_size(pci_dev); 781 782 pci_dev->config = g_malloc0(config_size); 783 pci_dev->cmask = g_malloc0(config_size); 784 pci_dev->wmask = g_malloc0(config_size); 785 pci_dev->w1cmask = g_malloc0(config_size); 786 pci_dev->used = g_malloc0(config_size); 787 } 788 789 static void pci_config_free(PCIDevice *pci_dev) 790 { 791 g_free(pci_dev->config); 792 g_free(pci_dev->cmask); 793 g_free(pci_dev->wmask); 794 g_free(pci_dev->w1cmask); 795 g_free(pci_dev->used); 796 } 797 798 /* -1 for devfn means auto assign */ 799 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus, 800 const char *name, int devfn) 801 { 802 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 803 PCIConfigReadFunc *config_read = pc->config_read; 804 PCIConfigWriteFunc *config_write = pc->config_write; 805 AddressSpace *dma_as; 806 807 if (devfn < 0) { 808 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices); 809 devfn += PCI_FUNC_MAX) { 810 if (!bus->devices[devfn]) 811 goto found; 812 } 813 error_report("PCI: no slot/function available for %s, all in use", name); 814 return NULL; 815 found: ; 816 } else if (bus->devices[devfn]) { 817 error_report("PCI: slot %d function %d not available for %s, in use by %s", 818 PCI_SLOT(devfn), PCI_FUNC(devfn), name, bus->devices[devfn]->name); 819 return NULL; 820 } 821 822 pci_dev->bus = bus; 823 dma_as = pci_device_iommu_address_space(pci_dev); 824 825 memory_region_init_alias(&pci_dev->bus_master_enable_region, 826 OBJECT(pci_dev), "bus master", 827 dma_as->root, 0, memory_region_size(dma_as->root)); 828 memory_region_set_enabled(&pci_dev->bus_master_enable_region, false); 829 address_space_init(&pci_dev->bus_master_as, &pci_dev->bus_master_enable_region, 830 name); 831 832 pci_dev->devfn = devfn; 833 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name); 834 pci_dev->irq_state = 0; 835 pci_config_alloc(pci_dev); 836 837 pci_config_set_vendor_id(pci_dev->config, pc->vendor_id); 838 pci_config_set_device_id(pci_dev->config, pc->device_id); 839 pci_config_set_revision(pci_dev->config, pc->revision); 840 pci_config_set_class(pci_dev->config, pc->class_id); 841 842 if (!pc->is_bridge) { 843 if (pc->subsystem_vendor_id || pc->subsystem_id) { 844 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, 845 pc->subsystem_vendor_id); 846 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 847 pc->subsystem_id); 848 } else { 849 pci_set_default_subsystem_id(pci_dev); 850 } 851 } else { 852 /* subsystem_vendor_id/subsystem_id are only for header type 0 */ 853 assert(!pc->subsystem_vendor_id); 854 assert(!pc->subsystem_id); 855 } 856 pci_init_cmask(pci_dev); 857 pci_init_wmask(pci_dev); 858 pci_init_w1cmask(pci_dev); 859 if (pc->is_bridge) { 860 pci_init_mask_bridge(pci_dev); 861 } 862 if (pci_init_multifunction(bus, pci_dev)) { 863 pci_config_free(pci_dev); 864 return NULL; 865 } 866 867 if (!config_read) 868 config_read = pci_default_read_config; 869 if (!config_write) 870 config_write = pci_default_write_config; 871 pci_dev->config_read = config_read; 872 pci_dev->config_write = config_write; 873 bus->devices[devfn] = pci_dev; 874 pci_dev->version_id = 2; /* Current pci device vmstate version */ 875 return pci_dev; 876 } 877 878 static void do_pci_unregister_device(PCIDevice *pci_dev) 879 { 880 pci_dev->bus->devices[pci_dev->devfn] = NULL; 881 pci_config_free(pci_dev); 882 883 address_space_destroy(&pci_dev->bus_master_as); 884 memory_region_destroy(&pci_dev->bus_master_enable_region); 885 } 886 887 static void pci_unregister_io_regions(PCIDevice *pci_dev) 888 { 889 PCIIORegion *r; 890 int i; 891 892 for(i = 0; i < PCI_NUM_REGIONS; i++) { 893 r = &pci_dev->io_regions[i]; 894 if (!r->size || r->addr == PCI_BAR_UNMAPPED) 895 continue; 896 memory_region_del_subregion(r->address_space, r->memory); 897 } 898 899 pci_unregister_vga(pci_dev); 900 } 901 902 static int pci_unregister_device(DeviceState *dev) 903 { 904 PCIDevice *pci_dev = PCI_DEVICE(dev); 905 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 906 907 pci_unregister_io_regions(pci_dev); 908 pci_del_option_rom(pci_dev); 909 910 if (pc->exit) { 911 pc->exit(pci_dev); 912 } 913 914 do_pci_unregister_device(pci_dev); 915 return 0; 916 } 917 918 void pci_register_bar(PCIDevice *pci_dev, int region_num, 919 uint8_t type, MemoryRegion *memory) 920 { 921 PCIIORegion *r; 922 uint32_t addr; 923 uint64_t wmask; 924 pcibus_t size = memory_region_size(memory); 925 926 assert(region_num >= 0); 927 assert(region_num < PCI_NUM_REGIONS); 928 if (size & (size-1)) { 929 fprintf(stderr, "ERROR: PCI region size must be pow2 " 930 "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size); 931 exit(1); 932 } 933 934 r = &pci_dev->io_regions[region_num]; 935 r->addr = PCI_BAR_UNMAPPED; 936 r->size = size; 937 r->type = type; 938 r->memory = NULL; 939 940 wmask = ~(size - 1); 941 addr = pci_bar(pci_dev, region_num); 942 if (region_num == PCI_ROM_SLOT) { 943 /* ROM enable bit is writable */ 944 wmask |= PCI_ROM_ADDRESS_ENABLE; 945 } 946 pci_set_long(pci_dev->config + addr, type); 947 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) && 948 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 949 pci_set_quad(pci_dev->wmask + addr, wmask); 950 pci_set_quad(pci_dev->cmask + addr, ~0ULL); 951 } else { 952 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff); 953 pci_set_long(pci_dev->cmask + addr, 0xffffffff); 954 } 955 pci_dev->io_regions[region_num].memory = memory; 956 pci_dev->io_regions[region_num].address_space 957 = type & PCI_BASE_ADDRESS_SPACE_IO 958 ? pci_dev->bus->address_space_io 959 : pci_dev->bus->address_space_mem; 960 } 961 962 static void pci_update_vga(PCIDevice *pci_dev) 963 { 964 uint16_t cmd; 965 966 if (!pci_dev->has_vga) { 967 return; 968 } 969 970 cmd = pci_get_word(pci_dev->config + PCI_COMMAND); 971 972 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_MEM], 973 cmd & PCI_COMMAND_MEMORY); 974 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO], 975 cmd & PCI_COMMAND_IO); 976 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI], 977 cmd & PCI_COMMAND_IO); 978 } 979 980 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, 981 MemoryRegion *io_lo, MemoryRegion *io_hi) 982 { 983 assert(!pci_dev->has_vga); 984 985 assert(memory_region_size(mem) == QEMU_PCI_VGA_MEM_SIZE); 986 pci_dev->vga_regions[QEMU_PCI_VGA_MEM] = mem; 987 memory_region_add_subregion_overlap(pci_dev->bus->address_space_mem, 988 QEMU_PCI_VGA_MEM_BASE, mem, 1); 989 990 assert(memory_region_size(io_lo) == QEMU_PCI_VGA_IO_LO_SIZE); 991 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO] = io_lo; 992 memory_region_add_subregion_overlap(pci_dev->bus->address_space_io, 993 QEMU_PCI_VGA_IO_LO_BASE, io_lo, 1); 994 995 assert(memory_region_size(io_hi) == QEMU_PCI_VGA_IO_HI_SIZE); 996 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI] = io_hi; 997 memory_region_add_subregion_overlap(pci_dev->bus->address_space_io, 998 QEMU_PCI_VGA_IO_HI_BASE, io_hi, 1); 999 pci_dev->has_vga = true; 1000 1001 pci_update_vga(pci_dev); 1002 } 1003 1004 void pci_unregister_vga(PCIDevice *pci_dev) 1005 { 1006 if (!pci_dev->has_vga) { 1007 return; 1008 } 1009 1010 memory_region_del_subregion(pci_dev->bus->address_space_mem, 1011 pci_dev->vga_regions[QEMU_PCI_VGA_MEM]); 1012 memory_region_del_subregion(pci_dev->bus->address_space_io, 1013 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO]); 1014 memory_region_del_subregion(pci_dev->bus->address_space_io, 1015 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI]); 1016 pci_dev->has_vga = false; 1017 } 1018 1019 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num) 1020 { 1021 return pci_dev->io_regions[region_num].addr; 1022 } 1023 1024 static pcibus_t pci_bar_address(PCIDevice *d, 1025 int reg, uint8_t type, pcibus_t size) 1026 { 1027 pcibus_t new_addr, last_addr; 1028 int bar = pci_bar(d, reg); 1029 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND); 1030 1031 if (type & PCI_BASE_ADDRESS_SPACE_IO) { 1032 if (!(cmd & PCI_COMMAND_IO)) { 1033 return PCI_BAR_UNMAPPED; 1034 } 1035 new_addr = pci_get_long(d->config + bar) & ~(size - 1); 1036 last_addr = new_addr + size - 1; 1037 /* Check if 32 bit BAR wraps around explicitly. 1038 * TODO: make priorities correct and remove this work around. 1039 */ 1040 if (last_addr <= new_addr || new_addr == 0 || last_addr >= UINT32_MAX) { 1041 return PCI_BAR_UNMAPPED; 1042 } 1043 return new_addr; 1044 } 1045 1046 if (!(cmd & PCI_COMMAND_MEMORY)) { 1047 return PCI_BAR_UNMAPPED; 1048 } 1049 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 1050 new_addr = pci_get_quad(d->config + bar); 1051 } else { 1052 new_addr = pci_get_long(d->config + bar); 1053 } 1054 /* the ROM slot has a specific enable bit */ 1055 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) { 1056 return PCI_BAR_UNMAPPED; 1057 } 1058 new_addr &= ~(size - 1); 1059 last_addr = new_addr + size - 1; 1060 /* NOTE: we do not support wrapping */ 1061 /* XXX: as we cannot support really dynamic 1062 mappings, we handle specific values as invalid 1063 mappings. */ 1064 if (last_addr <= new_addr || new_addr == 0 || 1065 last_addr == PCI_BAR_UNMAPPED) { 1066 return PCI_BAR_UNMAPPED; 1067 } 1068 1069 /* Now pcibus_t is 64bit. 1070 * Check if 32 bit BAR wraps around explicitly. 1071 * Without this, PC ide doesn't work well. 1072 * TODO: remove this work around. 1073 */ 1074 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) { 1075 return PCI_BAR_UNMAPPED; 1076 } 1077 1078 /* 1079 * OS is allowed to set BAR beyond its addressable 1080 * bits. For example, 32 bit OS can set 64bit bar 1081 * to >4G. Check it. TODO: we might need to support 1082 * it in the future for e.g. PAE. 1083 */ 1084 if (last_addr >= HWADDR_MAX) { 1085 return PCI_BAR_UNMAPPED; 1086 } 1087 1088 return new_addr; 1089 } 1090 1091 static void pci_update_mappings(PCIDevice *d) 1092 { 1093 PCIIORegion *r; 1094 int i; 1095 pcibus_t new_addr; 1096 1097 for(i = 0; i < PCI_NUM_REGIONS; i++) { 1098 r = &d->io_regions[i]; 1099 1100 /* this region isn't registered */ 1101 if (!r->size) 1102 continue; 1103 1104 new_addr = pci_bar_address(d, i, r->type, r->size); 1105 1106 /* This bar isn't changed */ 1107 if (new_addr == r->addr) 1108 continue; 1109 1110 /* now do the real mapping */ 1111 if (r->addr != PCI_BAR_UNMAPPED) { 1112 memory_region_del_subregion(r->address_space, r->memory); 1113 } 1114 r->addr = new_addr; 1115 if (r->addr != PCI_BAR_UNMAPPED) { 1116 memory_region_add_subregion_overlap(r->address_space, 1117 r->addr, r->memory, 1); 1118 } 1119 } 1120 1121 pci_update_vga(d); 1122 } 1123 1124 static inline int pci_irq_disabled(PCIDevice *d) 1125 { 1126 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE; 1127 } 1128 1129 /* Called after interrupt disabled field update in config space, 1130 * assert/deassert interrupts if necessary. 1131 * Gets original interrupt disable bit value (before update). */ 1132 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled) 1133 { 1134 int i, disabled = pci_irq_disabled(d); 1135 if (disabled == was_irq_disabled) 1136 return; 1137 for (i = 0; i < PCI_NUM_PINS; ++i) { 1138 int state = pci_irq_state(d, i); 1139 pci_change_irq_level(d, i, disabled ? -state : state); 1140 } 1141 } 1142 1143 uint32_t pci_default_read_config(PCIDevice *d, 1144 uint32_t address, int len) 1145 { 1146 uint32_t val = 0; 1147 1148 memcpy(&val, d->config + address, len); 1149 return le32_to_cpu(val); 1150 } 1151 1152 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l) 1153 { 1154 int i, was_irq_disabled = pci_irq_disabled(d); 1155 1156 for (i = 0; i < l; val >>= 8, ++i) { 1157 uint8_t wmask = d->wmask[addr + i]; 1158 uint8_t w1cmask = d->w1cmask[addr + i]; 1159 assert(!(wmask & w1cmask)); 1160 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask); 1161 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */ 1162 } 1163 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) || 1164 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) || 1165 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) || 1166 range_covers_byte(addr, l, PCI_COMMAND)) 1167 pci_update_mappings(d); 1168 1169 if (range_covers_byte(addr, l, PCI_COMMAND)) { 1170 pci_update_irq_disabled(d, was_irq_disabled); 1171 memory_region_set_enabled(&d->bus_master_enable_region, 1172 pci_get_word(d->config + PCI_COMMAND) 1173 & PCI_COMMAND_MASTER); 1174 } 1175 1176 msi_write_config(d, addr, val, l); 1177 msix_write_config(d, addr, val, l); 1178 } 1179 1180 /***********************************************************/ 1181 /* generic PCI irq support */ 1182 1183 /* 0 <= irq_num <= 3. level must be 0 or 1 */ 1184 static void pci_irq_handler(void *opaque, int irq_num, int level) 1185 { 1186 PCIDevice *pci_dev = opaque; 1187 int change; 1188 1189 change = level - pci_irq_state(pci_dev, irq_num); 1190 if (!change) 1191 return; 1192 1193 pci_set_irq_state(pci_dev, irq_num, level); 1194 pci_update_irq_status(pci_dev); 1195 if (pci_irq_disabled(pci_dev)) 1196 return; 1197 pci_change_irq_level(pci_dev, irq_num, change); 1198 } 1199 1200 static inline int pci_intx(PCIDevice *pci_dev) 1201 { 1202 return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1; 1203 } 1204 1205 qemu_irq pci_allocate_irq(PCIDevice *pci_dev) 1206 { 1207 int intx = pci_intx(pci_dev); 1208 1209 return qemu_allocate_irq(pci_irq_handler, pci_dev, intx); 1210 } 1211 1212 void pci_set_irq(PCIDevice *pci_dev, int level) 1213 { 1214 int intx = pci_intx(pci_dev); 1215 pci_irq_handler(pci_dev, intx, level); 1216 } 1217 1218 /* Special hooks used by device assignment */ 1219 void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq) 1220 { 1221 assert(pci_bus_is_root(bus)); 1222 bus->route_intx_to_irq = route_intx_to_irq; 1223 } 1224 1225 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin) 1226 { 1227 PCIBus *bus; 1228 1229 do { 1230 bus = dev->bus; 1231 pin = bus->map_irq(dev, pin); 1232 dev = bus->parent_dev; 1233 } while (dev); 1234 1235 if (!bus->route_intx_to_irq) { 1236 error_report("PCI: Bug - unimplemented PCI INTx routing (%s)", 1237 object_get_typename(OBJECT(bus->qbus.parent))); 1238 return (PCIINTxRoute) { PCI_INTX_DISABLED, -1 }; 1239 } 1240 1241 return bus->route_intx_to_irq(bus->irq_opaque, pin); 1242 } 1243 1244 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new) 1245 { 1246 return old->mode != new->mode || old->irq != new->irq; 1247 } 1248 1249 void pci_bus_fire_intx_routing_notifier(PCIBus *bus) 1250 { 1251 PCIDevice *dev; 1252 PCIBus *sec; 1253 int i; 1254 1255 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 1256 dev = bus->devices[i]; 1257 if (dev && dev->intx_routing_notifier) { 1258 dev->intx_routing_notifier(dev); 1259 } 1260 } 1261 1262 QLIST_FOREACH(sec, &bus->child, sibling) { 1263 pci_bus_fire_intx_routing_notifier(sec); 1264 } 1265 } 1266 1267 void pci_device_set_intx_routing_notifier(PCIDevice *dev, 1268 PCIINTxRoutingNotifier notifier) 1269 { 1270 dev->intx_routing_notifier = notifier; 1271 } 1272 1273 /* 1274 * PCI-to-PCI bridge specification 1275 * 9.1: Interrupt routing. Table 9-1 1276 * 1277 * the PCI Express Base Specification, Revision 2.1 1278 * 2.2.8.1: INTx interrutp signaling - Rules 1279 * the Implementation Note 1280 * Table 2-20 1281 */ 1282 /* 1283 * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD 1284 * 0-origin unlike PCI interrupt pin register. 1285 */ 1286 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin) 1287 { 1288 return (pin + PCI_SLOT(pci_dev->devfn)) % PCI_NUM_PINS; 1289 } 1290 1291 /***********************************************************/ 1292 /* monitor info on PCI */ 1293 1294 typedef struct { 1295 uint16_t class; 1296 const char *desc; 1297 const char *fw_name; 1298 uint16_t fw_ign_bits; 1299 } pci_class_desc; 1300 1301 static const pci_class_desc pci_class_descriptions[] = 1302 { 1303 { 0x0001, "VGA controller", "display"}, 1304 { 0x0100, "SCSI controller", "scsi"}, 1305 { 0x0101, "IDE controller", "ide"}, 1306 { 0x0102, "Floppy controller", "fdc"}, 1307 { 0x0103, "IPI controller", "ipi"}, 1308 { 0x0104, "RAID controller", "raid"}, 1309 { 0x0106, "SATA controller"}, 1310 { 0x0107, "SAS controller"}, 1311 { 0x0180, "Storage controller"}, 1312 { 0x0200, "Ethernet controller", "ethernet"}, 1313 { 0x0201, "Token Ring controller", "token-ring"}, 1314 { 0x0202, "FDDI controller", "fddi"}, 1315 { 0x0203, "ATM controller", "atm"}, 1316 { 0x0280, "Network controller"}, 1317 { 0x0300, "VGA controller", "display", 0x00ff}, 1318 { 0x0301, "XGA controller"}, 1319 { 0x0302, "3D controller"}, 1320 { 0x0380, "Display controller"}, 1321 { 0x0400, "Video controller", "video"}, 1322 { 0x0401, "Audio controller", "sound"}, 1323 { 0x0402, "Phone"}, 1324 { 0x0403, "Audio controller", "sound"}, 1325 { 0x0480, "Multimedia controller"}, 1326 { 0x0500, "RAM controller", "memory"}, 1327 { 0x0501, "Flash controller", "flash"}, 1328 { 0x0580, "Memory controller"}, 1329 { 0x0600, "Host bridge", "host"}, 1330 { 0x0601, "ISA bridge", "isa"}, 1331 { 0x0602, "EISA bridge", "eisa"}, 1332 { 0x0603, "MC bridge", "mca"}, 1333 { 0x0604, "PCI bridge", "pci-bridge"}, 1334 { 0x0605, "PCMCIA bridge", "pcmcia"}, 1335 { 0x0606, "NUBUS bridge", "nubus"}, 1336 { 0x0607, "CARDBUS bridge", "cardbus"}, 1337 { 0x0608, "RACEWAY bridge"}, 1338 { 0x0680, "Bridge"}, 1339 { 0x0700, "Serial port", "serial"}, 1340 { 0x0701, "Parallel port", "parallel"}, 1341 { 0x0800, "Interrupt controller", "interrupt-controller"}, 1342 { 0x0801, "DMA controller", "dma-controller"}, 1343 { 0x0802, "Timer", "timer"}, 1344 { 0x0803, "RTC", "rtc"}, 1345 { 0x0900, "Keyboard", "keyboard"}, 1346 { 0x0901, "Pen", "pen"}, 1347 { 0x0902, "Mouse", "mouse"}, 1348 { 0x0A00, "Dock station", "dock", 0x00ff}, 1349 { 0x0B00, "i386 cpu", "cpu", 0x00ff}, 1350 { 0x0c00, "Fireware contorller", "fireware"}, 1351 { 0x0c01, "Access bus controller", "access-bus"}, 1352 { 0x0c02, "SSA controller", "ssa"}, 1353 { 0x0c03, "USB controller", "usb"}, 1354 { 0x0c04, "Fibre channel controller", "fibre-channel"}, 1355 { 0x0c05, "SMBus"}, 1356 { 0, NULL} 1357 }; 1358 1359 static void pci_for_each_device_under_bus(PCIBus *bus, 1360 void (*fn)(PCIBus *b, PCIDevice *d, 1361 void *opaque), 1362 void *opaque) 1363 { 1364 PCIDevice *d; 1365 int devfn; 1366 1367 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1368 d = bus->devices[devfn]; 1369 if (d) { 1370 fn(bus, d, opaque); 1371 } 1372 } 1373 } 1374 1375 void pci_for_each_device(PCIBus *bus, int bus_num, 1376 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque), 1377 void *opaque) 1378 { 1379 bus = pci_find_bus_nr(bus, bus_num); 1380 1381 if (bus) { 1382 pci_for_each_device_under_bus(bus, fn, opaque); 1383 } 1384 } 1385 1386 static const pci_class_desc *get_class_desc(int class) 1387 { 1388 const pci_class_desc *desc; 1389 1390 desc = pci_class_descriptions; 1391 while (desc->desc && class != desc->class) { 1392 desc++; 1393 } 1394 1395 return desc; 1396 } 1397 1398 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num); 1399 1400 static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev) 1401 { 1402 PciMemoryRegionList *head = NULL, *cur_item = NULL; 1403 int i; 1404 1405 for (i = 0; i < PCI_NUM_REGIONS; i++) { 1406 const PCIIORegion *r = &dev->io_regions[i]; 1407 PciMemoryRegionList *region; 1408 1409 if (!r->size) { 1410 continue; 1411 } 1412 1413 region = g_malloc0(sizeof(*region)); 1414 region->value = g_malloc0(sizeof(*region->value)); 1415 1416 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { 1417 region->value->type = g_strdup("io"); 1418 } else { 1419 region->value->type = g_strdup("memory"); 1420 region->value->has_prefetch = true; 1421 region->value->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH); 1422 region->value->has_mem_type_64 = true; 1423 region->value->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64); 1424 } 1425 1426 region->value->bar = i; 1427 region->value->address = r->addr; 1428 region->value->size = r->size; 1429 1430 /* XXX: waiting for the qapi to support GSList */ 1431 if (!cur_item) { 1432 head = cur_item = region; 1433 } else { 1434 cur_item->next = region; 1435 cur_item = region; 1436 } 1437 } 1438 1439 return head; 1440 } 1441 1442 static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus, 1443 int bus_num) 1444 { 1445 PciBridgeInfo *info; 1446 1447 info = g_malloc0(sizeof(*info)); 1448 1449 info->bus.number = dev->config[PCI_PRIMARY_BUS]; 1450 info->bus.secondary = dev->config[PCI_SECONDARY_BUS]; 1451 info->bus.subordinate = dev->config[PCI_SUBORDINATE_BUS]; 1452 1453 info->bus.io_range = g_malloc0(sizeof(*info->bus.io_range)); 1454 info->bus.io_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO); 1455 info->bus.io_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO); 1456 1457 info->bus.memory_range = g_malloc0(sizeof(*info->bus.memory_range)); 1458 info->bus.memory_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 1459 info->bus.memory_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 1460 1461 info->bus.prefetchable_range = g_malloc0(sizeof(*info->bus.prefetchable_range)); 1462 info->bus.prefetchable_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 1463 info->bus.prefetchable_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 1464 1465 if (dev->config[PCI_SECONDARY_BUS] != 0) { 1466 PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]); 1467 if (child_bus) { 1468 info->has_devices = true; 1469 info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]); 1470 } 1471 } 1472 1473 return info; 1474 } 1475 1476 static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus, 1477 int bus_num) 1478 { 1479 const pci_class_desc *desc; 1480 PciDeviceInfo *info; 1481 uint8_t type; 1482 int class; 1483 1484 info = g_malloc0(sizeof(*info)); 1485 info->bus = bus_num; 1486 info->slot = PCI_SLOT(dev->devfn); 1487 info->function = PCI_FUNC(dev->devfn); 1488 1489 class = pci_get_word(dev->config + PCI_CLASS_DEVICE); 1490 info->class_info.q_class = class; 1491 desc = get_class_desc(class); 1492 if (desc->desc) { 1493 info->class_info.has_desc = true; 1494 info->class_info.desc = g_strdup(desc->desc); 1495 } 1496 1497 info->id.vendor = pci_get_word(dev->config + PCI_VENDOR_ID); 1498 info->id.device = pci_get_word(dev->config + PCI_DEVICE_ID); 1499 info->regions = qmp_query_pci_regions(dev); 1500 info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : ""); 1501 1502 if (dev->config[PCI_INTERRUPT_PIN] != 0) { 1503 info->has_irq = true; 1504 info->irq = dev->config[PCI_INTERRUPT_LINE]; 1505 } 1506 1507 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 1508 if (type == PCI_HEADER_TYPE_BRIDGE) { 1509 info->has_pci_bridge = true; 1510 info->pci_bridge = qmp_query_pci_bridge(dev, bus, bus_num); 1511 } 1512 1513 return info; 1514 } 1515 1516 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num) 1517 { 1518 PciDeviceInfoList *info, *head = NULL, *cur_item = NULL; 1519 PCIDevice *dev; 1520 int devfn; 1521 1522 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1523 dev = bus->devices[devfn]; 1524 if (dev) { 1525 info = g_malloc0(sizeof(*info)); 1526 info->value = qmp_query_pci_device(dev, bus, bus_num); 1527 1528 /* XXX: waiting for the qapi to support GSList */ 1529 if (!cur_item) { 1530 head = cur_item = info; 1531 } else { 1532 cur_item->next = info; 1533 cur_item = info; 1534 } 1535 } 1536 } 1537 1538 return head; 1539 } 1540 1541 static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num) 1542 { 1543 PciInfo *info = NULL; 1544 1545 bus = pci_find_bus_nr(bus, bus_num); 1546 if (bus) { 1547 info = g_malloc0(sizeof(*info)); 1548 info->bus = bus_num; 1549 info->devices = qmp_query_pci_devices(bus, bus_num); 1550 } 1551 1552 return info; 1553 } 1554 1555 PciInfoList *qmp_query_pci(Error **errp) 1556 { 1557 PciInfoList *info, *head = NULL, *cur_item = NULL; 1558 PCIHostState *host_bridge; 1559 1560 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { 1561 info = g_malloc0(sizeof(*info)); 1562 info->value = qmp_query_pci_bus(host_bridge->bus, 0); 1563 1564 /* XXX: waiting for the qapi to support GSList */ 1565 if (!cur_item) { 1566 head = cur_item = info; 1567 } else { 1568 cur_item->next = info; 1569 cur_item = info; 1570 } 1571 } 1572 1573 return head; 1574 } 1575 1576 static const char * const pci_nic_models[] = { 1577 "ne2k_pci", 1578 "i82551", 1579 "i82557b", 1580 "i82559er", 1581 "rtl8139", 1582 "e1000", 1583 "pcnet", 1584 "virtio", 1585 NULL 1586 }; 1587 1588 static const char * const pci_nic_names[] = { 1589 "ne2k_pci", 1590 "i82551", 1591 "i82557b", 1592 "i82559er", 1593 "rtl8139", 1594 "e1000", 1595 "pcnet", 1596 "virtio-net-pci", 1597 NULL 1598 }; 1599 1600 /* Initialize a PCI NIC. */ 1601 /* FIXME callers should check for failure, but don't */ 1602 PCIDevice *pci_nic_init(NICInfo *nd, PCIBus *rootbus, 1603 const char *default_model, 1604 const char *default_devaddr) 1605 { 1606 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr; 1607 PCIBus *bus; 1608 int devfn; 1609 PCIDevice *pci_dev; 1610 DeviceState *dev; 1611 int i; 1612 1613 i = qemu_find_nic_model(nd, pci_nic_models, default_model); 1614 if (i < 0) 1615 return NULL; 1616 1617 bus = pci_get_bus_devfn(&devfn, rootbus, devaddr); 1618 if (!bus) { 1619 error_report("Invalid PCI device address %s for device %s", 1620 devaddr, pci_nic_names[i]); 1621 return NULL; 1622 } 1623 1624 pci_dev = pci_create(bus, devfn, pci_nic_names[i]); 1625 dev = &pci_dev->qdev; 1626 qdev_set_nic_properties(dev, nd); 1627 if (qdev_init(dev) < 0) 1628 return NULL; 1629 return pci_dev; 1630 } 1631 1632 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus, 1633 const char *default_model, 1634 const char *default_devaddr) 1635 { 1636 PCIDevice *res; 1637 1638 if (qemu_show_nic_models(nd->model, pci_nic_models)) 1639 exit(0); 1640 1641 res = pci_nic_init(nd, rootbus, default_model, default_devaddr); 1642 if (!res) 1643 exit(1); 1644 return res; 1645 } 1646 1647 PCIDevice *pci_vga_init(PCIBus *bus) 1648 { 1649 switch (vga_interface_type) { 1650 case VGA_CIRRUS: 1651 return pci_create_simple(bus, -1, "cirrus-vga"); 1652 case VGA_QXL: 1653 return pci_create_simple(bus, -1, "qxl-vga"); 1654 case VGA_STD: 1655 return pci_create_simple(bus, -1, "VGA"); 1656 case VGA_VMWARE: 1657 return pci_create_simple(bus, -1, "vmware-svga"); 1658 case VGA_NONE: 1659 default: /* Other non-PCI types. Checking for unsupported types is already 1660 done in vl.c. */ 1661 return NULL; 1662 } 1663 } 1664 1665 /* Whether a given bus number is in range of the secondary 1666 * bus of the given bridge device. */ 1667 static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num) 1668 { 1669 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) & 1670 PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ && 1671 dev->config[PCI_SECONDARY_BUS] < bus_num && 1672 bus_num <= dev->config[PCI_SUBORDINATE_BUS]; 1673 } 1674 1675 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num) 1676 { 1677 PCIBus *sec; 1678 1679 if (!bus) { 1680 return NULL; 1681 } 1682 1683 if (pci_bus_num(bus) == bus_num) { 1684 return bus; 1685 } 1686 1687 /* Consider all bus numbers in range for the host pci bridge. */ 1688 if (!pci_bus_is_root(bus) && 1689 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) { 1690 return NULL; 1691 } 1692 1693 /* try child bus */ 1694 for (; bus; bus = sec) { 1695 QLIST_FOREACH(sec, &bus->child, sibling) { 1696 assert(!pci_bus_is_root(sec)); 1697 if (sec->parent_dev->config[PCI_SECONDARY_BUS] == bus_num) { 1698 return sec; 1699 } 1700 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) { 1701 break; 1702 } 1703 } 1704 } 1705 1706 return NULL; 1707 } 1708 1709 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn) 1710 { 1711 bus = pci_find_bus_nr(bus, bus_num); 1712 1713 if (!bus) 1714 return NULL; 1715 1716 return bus->devices[devfn]; 1717 } 1718 1719 static int pci_qdev_init(DeviceState *qdev) 1720 { 1721 PCIDevice *pci_dev = (PCIDevice *)qdev; 1722 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 1723 PCIBus *bus; 1724 int rc; 1725 bool is_default_rom; 1726 1727 /* initialize cap_present for pci_is_express() and pci_config_size() */ 1728 if (pc->is_express) { 1729 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; 1730 } 1731 1732 bus = PCI_BUS(qdev_get_parent_bus(qdev)); 1733 pci_dev = do_pci_register_device(pci_dev, bus, 1734 object_get_typename(OBJECT(qdev)), 1735 pci_dev->devfn); 1736 if (pci_dev == NULL) 1737 return -1; 1738 if (qdev->hotplugged && pc->no_hotplug) { 1739 qerror_report(QERR_DEVICE_NO_HOTPLUG, object_get_typename(OBJECT(pci_dev))); 1740 do_pci_unregister_device(pci_dev); 1741 return -1; 1742 } 1743 if (pc->init) { 1744 rc = pc->init(pci_dev); 1745 if (rc != 0) { 1746 do_pci_unregister_device(pci_dev); 1747 return rc; 1748 } 1749 } 1750 1751 /* rom loading */ 1752 is_default_rom = false; 1753 if (pci_dev->romfile == NULL && pc->romfile != NULL) { 1754 pci_dev->romfile = g_strdup(pc->romfile); 1755 is_default_rom = true; 1756 } 1757 pci_add_option_rom(pci_dev, is_default_rom); 1758 1759 if (bus->hotplug) { 1760 /* Let buses differentiate between hotplug and when device is 1761 * enabled during qemu machine creation. */ 1762 rc = bus->hotplug(bus->hotplug_qdev, pci_dev, 1763 qdev->hotplugged ? PCI_HOTPLUG_ENABLED: 1764 PCI_COLDPLUG_ENABLED); 1765 if (rc != 0) { 1766 int r = pci_unregister_device(&pci_dev->qdev); 1767 assert(!r); 1768 return rc; 1769 } 1770 } 1771 return 0; 1772 } 1773 1774 static int pci_unplug_device(DeviceState *qdev) 1775 { 1776 PCIDevice *dev = PCI_DEVICE(qdev); 1777 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 1778 1779 if (pc->no_hotplug) { 1780 qerror_report(QERR_DEVICE_NO_HOTPLUG, object_get_typename(OBJECT(dev))); 1781 return -1; 1782 } 1783 return dev->bus->hotplug(dev->bus->hotplug_qdev, dev, 1784 PCI_HOTPLUG_DISABLED); 1785 } 1786 1787 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction, 1788 const char *name) 1789 { 1790 DeviceState *dev; 1791 1792 dev = qdev_create(&bus->qbus, name); 1793 qdev_prop_set_int32(dev, "addr", devfn); 1794 qdev_prop_set_bit(dev, "multifunction", multifunction); 1795 return PCI_DEVICE(dev); 1796 } 1797 1798 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, 1799 bool multifunction, 1800 const char *name) 1801 { 1802 PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name); 1803 qdev_init_nofail(&dev->qdev); 1804 return dev; 1805 } 1806 1807 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name) 1808 { 1809 return pci_create_multifunction(bus, devfn, false, name); 1810 } 1811 1812 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name) 1813 { 1814 return pci_create_simple_multifunction(bus, devfn, false, name); 1815 } 1816 1817 static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size) 1818 { 1819 int offset = PCI_CONFIG_HEADER_SIZE; 1820 int i; 1821 for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) { 1822 if (pdev->used[i]) 1823 offset = i + 1; 1824 else if (i - offset + 1 == size) 1825 return offset; 1826 } 1827 return 0; 1828 } 1829 1830 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id, 1831 uint8_t *prev_p) 1832 { 1833 uint8_t next, prev; 1834 1835 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST)) 1836 return 0; 1837 1838 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); 1839 prev = next + PCI_CAP_LIST_NEXT) 1840 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id) 1841 break; 1842 1843 if (prev_p) 1844 *prev_p = prev; 1845 return next; 1846 } 1847 1848 static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset) 1849 { 1850 uint8_t next, prev, found = 0; 1851 1852 if (!(pdev->used[offset])) { 1853 return 0; 1854 } 1855 1856 assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST); 1857 1858 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); 1859 prev = next + PCI_CAP_LIST_NEXT) { 1860 if (next <= offset && next > found) { 1861 found = next; 1862 } 1863 } 1864 return found; 1865 } 1866 1867 /* Patch the PCI vendor and device ids in a PCI rom image if necessary. 1868 This is needed for an option rom which is used for more than one device. */ 1869 static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size) 1870 { 1871 uint16_t vendor_id; 1872 uint16_t device_id; 1873 uint16_t rom_vendor_id; 1874 uint16_t rom_device_id; 1875 uint16_t rom_magic; 1876 uint16_t pcir_offset; 1877 uint8_t checksum; 1878 1879 /* Words in rom data are little endian (like in PCI configuration), 1880 so they can be read / written with pci_get_word / pci_set_word. */ 1881 1882 /* Only a valid rom will be patched. */ 1883 rom_magic = pci_get_word(ptr); 1884 if (rom_magic != 0xaa55) { 1885 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic); 1886 return; 1887 } 1888 pcir_offset = pci_get_word(ptr + 0x18); 1889 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) { 1890 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset); 1891 return; 1892 } 1893 1894 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID); 1895 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID); 1896 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4); 1897 rom_device_id = pci_get_word(ptr + pcir_offset + 6); 1898 1899 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile, 1900 vendor_id, device_id, rom_vendor_id, rom_device_id); 1901 1902 checksum = ptr[6]; 1903 1904 if (vendor_id != rom_vendor_id) { 1905 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */ 1906 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8); 1907 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8); 1908 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); 1909 ptr[6] = checksum; 1910 pci_set_word(ptr + pcir_offset + 4, vendor_id); 1911 } 1912 1913 if (device_id != rom_device_id) { 1914 /* Patch device id and checksum (at offset 6 for etherboot roms). */ 1915 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8); 1916 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8); 1917 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); 1918 ptr[6] = checksum; 1919 pci_set_word(ptr + pcir_offset + 6, device_id); 1920 } 1921 } 1922 1923 /* Add an option rom for the device */ 1924 static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom) 1925 { 1926 int size; 1927 char *path; 1928 void *ptr; 1929 char name[32]; 1930 const VMStateDescription *vmsd; 1931 1932 if (!pdev->romfile) 1933 return 0; 1934 if (strlen(pdev->romfile) == 0) 1935 return 0; 1936 1937 if (!pdev->rom_bar) { 1938 /* 1939 * Load rom via fw_cfg instead of creating a rom bar, 1940 * for 0.11 compatibility. 1941 */ 1942 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE); 1943 if (class == 0x0300) { 1944 rom_add_vga(pdev->romfile); 1945 } else { 1946 rom_add_option(pdev->romfile, -1); 1947 } 1948 return 0; 1949 } 1950 1951 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile); 1952 if (path == NULL) { 1953 path = g_strdup(pdev->romfile); 1954 } 1955 1956 size = get_image_size(path); 1957 if (size < 0) { 1958 error_report("%s: failed to find romfile \"%s\"", 1959 __func__, pdev->romfile); 1960 g_free(path); 1961 return -1; 1962 } else if (size == 0) { 1963 error_report("%s: ignoring empty romfile \"%s\"", 1964 __func__, pdev->romfile); 1965 g_free(path); 1966 return -1; 1967 } 1968 if (size & (size - 1)) { 1969 size = 1 << qemu_fls(size); 1970 } 1971 1972 vmsd = qdev_get_vmsd(DEVICE(pdev)); 1973 1974 if (vmsd) { 1975 snprintf(name, sizeof(name), "%s.rom", vmsd->name); 1976 } else { 1977 snprintf(name, sizeof(name), "%s.rom", object_get_typename(OBJECT(pdev))); 1978 } 1979 pdev->has_rom = true; 1980 memory_region_init_ram(&pdev->rom, OBJECT(pdev), name, size); 1981 vmstate_register_ram(&pdev->rom, &pdev->qdev); 1982 ptr = memory_region_get_ram_ptr(&pdev->rom); 1983 load_image(path, ptr); 1984 g_free(path); 1985 1986 if (is_default_rom) { 1987 /* Only the default rom images will be patched (if needed). */ 1988 pci_patch_ids(pdev, ptr, size); 1989 } 1990 1991 pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom); 1992 1993 return 0; 1994 } 1995 1996 static void pci_del_option_rom(PCIDevice *pdev) 1997 { 1998 if (!pdev->has_rom) 1999 return; 2000 2001 vmstate_unregister_ram(&pdev->rom, &pdev->qdev); 2002 memory_region_destroy(&pdev->rom); 2003 pdev->has_rom = false; 2004 } 2005 2006 /* 2007 * if !offset 2008 * Reserve space and add capability to the linked list in pci config space 2009 * 2010 * if offset = 0, 2011 * Find and reserve space and add capability to the linked list 2012 * in pci config space */ 2013 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, 2014 uint8_t offset, uint8_t size) 2015 { 2016 uint8_t *config; 2017 int i, overlapping_cap; 2018 2019 if (!offset) { 2020 offset = pci_find_space(pdev, size); 2021 if (!offset) { 2022 return -ENOSPC; 2023 } 2024 } else { 2025 /* Verify that capabilities don't overlap. Note: device assignment 2026 * depends on this check to verify that the device is not broken. 2027 * Should never trigger for emulated devices, but it's helpful 2028 * for debugging these. */ 2029 for (i = offset; i < offset + size; i++) { 2030 overlapping_cap = pci_find_capability_at_offset(pdev, i); 2031 if (overlapping_cap) { 2032 fprintf(stderr, "ERROR: %s:%02x:%02x.%x " 2033 "Attempt to add PCI capability %x at offset " 2034 "%x overlaps existing capability %x at offset %x\n", 2035 pci_root_bus_path(pdev), pci_bus_num(pdev->bus), 2036 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), 2037 cap_id, offset, overlapping_cap, i); 2038 return -EINVAL; 2039 } 2040 } 2041 } 2042 2043 config = pdev->config + offset; 2044 config[PCI_CAP_LIST_ID] = cap_id; 2045 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST]; 2046 pdev->config[PCI_CAPABILITY_LIST] = offset; 2047 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST; 2048 memset(pdev->used + offset, 0xFF, QEMU_ALIGN_UP(size, 4)); 2049 /* Make capability read-only by default */ 2050 memset(pdev->wmask + offset, 0, size); 2051 /* Check capability by default */ 2052 memset(pdev->cmask + offset, 0xFF, size); 2053 return offset; 2054 } 2055 2056 /* Unlink capability from the pci config space. */ 2057 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size) 2058 { 2059 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev); 2060 if (!offset) 2061 return; 2062 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT]; 2063 /* Make capability writable again */ 2064 memset(pdev->wmask + offset, 0xff, size); 2065 memset(pdev->w1cmask + offset, 0, size); 2066 /* Clear cmask as device-specific registers can't be checked */ 2067 memset(pdev->cmask + offset, 0, size); 2068 memset(pdev->used + offset, 0, QEMU_ALIGN_UP(size, 4)); 2069 2070 if (!pdev->config[PCI_CAPABILITY_LIST]) 2071 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST; 2072 } 2073 2074 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id) 2075 { 2076 return pci_find_capability_list(pdev, cap_id, NULL); 2077 } 2078 2079 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent) 2080 { 2081 PCIDevice *d = (PCIDevice *)dev; 2082 const pci_class_desc *desc; 2083 char ctxt[64]; 2084 PCIIORegion *r; 2085 int i, class; 2086 2087 class = pci_get_word(d->config + PCI_CLASS_DEVICE); 2088 desc = pci_class_descriptions; 2089 while (desc->desc && class != desc->class) 2090 desc++; 2091 if (desc->desc) { 2092 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc); 2093 } else { 2094 snprintf(ctxt, sizeof(ctxt), "Class %04x", class); 2095 } 2096 2097 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, " 2098 "pci id %04x:%04x (sub %04x:%04x)\n", 2099 indent, "", ctxt, pci_bus_num(d->bus), 2100 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn), 2101 pci_get_word(d->config + PCI_VENDOR_ID), 2102 pci_get_word(d->config + PCI_DEVICE_ID), 2103 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID), 2104 pci_get_word(d->config + PCI_SUBSYSTEM_ID)); 2105 for (i = 0; i < PCI_NUM_REGIONS; i++) { 2106 r = &d->io_regions[i]; 2107 if (!r->size) 2108 continue; 2109 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS 2110 " [0x%"FMT_PCIBUS"]\n", 2111 indent, "", 2112 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem", 2113 r->addr, r->addr + r->size - 1); 2114 } 2115 } 2116 2117 static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len) 2118 { 2119 PCIDevice *d = (PCIDevice *)dev; 2120 const char *name = NULL; 2121 const pci_class_desc *desc = pci_class_descriptions; 2122 int class = pci_get_word(d->config + PCI_CLASS_DEVICE); 2123 2124 while (desc->desc && 2125 (class & ~desc->fw_ign_bits) != 2126 (desc->class & ~desc->fw_ign_bits)) { 2127 desc++; 2128 } 2129 2130 if (desc->desc) { 2131 name = desc->fw_name; 2132 } 2133 2134 if (name) { 2135 pstrcpy(buf, len, name); 2136 } else { 2137 snprintf(buf, len, "pci%04x,%04x", 2138 pci_get_word(d->config + PCI_VENDOR_ID), 2139 pci_get_word(d->config + PCI_DEVICE_ID)); 2140 } 2141 2142 return buf; 2143 } 2144 2145 static char *pcibus_get_fw_dev_path(DeviceState *dev) 2146 { 2147 PCIDevice *d = (PCIDevice *)dev; 2148 char path[50], name[33]; 2149 int off; 2150 2151 off = snprintf(path, sizeof(path), "%s@%x", 2152 pci_dev_fw_name(dev, name, sizeof name), 2153 PCI_SLOT(d->devfn)); 2154 if (PCI_FUNC(d->devfn)) 2155 snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn)); 2156 return g_strdup(path); 2157 } 2158 2159 static char *pcibus_get_dev_path(DeviceState *dev) 2160 { 2161 PCIDevice *d = container_of(dev, PCIDevice, qdev); 2162 PCIDevice *t; 2163 int slot_depth; 2164 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function. 2165 * 00 is added here to make this format compatible with 2166 * domain:Bus:Slot.Func for systems without nested PCI bridges. 2167 * Slot.Function list specifies the slot and function numbers for all 2168 * devices on the path from root to the specific device. */ 2169 const char *root_bus_path; 2170 int root_bus_len; 2171 char slot[] = ":SS.F"; 2172 int slot_len = sizeof slot - 1 /* For '\0' */; 2173 int path_len; 2174 char *path, *p; 2175 int s; 2176 2177 root_bus_path = pci_root_bus_path(d); 2178 root_bus_len = strlen(root_bus_path); 2179 2180 /* Calculate # of slots on path between device and root. */; 2181 slot_depth = 0; 2182 for (t = d; t; t = t->bus->parent_dev) { 2183 ++slot_depth; 2184 } 2185 2186 path_len = root_bus_len + slot_len * slot_depth; 2187 2188 /* Allocate memory, fill in the terminating null byte. */ 2189 path = g_malloc(path_len + 1 /* For '\0' */); 2190 path[path_len] = '\0'; 2191 2192 memcpy(path, root_bus_path, root_bus_len); 2193 2194 /* Fill in slot numbers. We walk up from device to root, so need to print 2195 * them in the reverse order, last to first. */ 2196 p = path + path_len; 2197 for (t = d; t; t = t->bus->parent_dev) { 2198 p -= slot_len; 2199 s = snprintf(slot, sizeof slot, ":%02x.%x", 2200 PCI_SLOT(t->devfn), PCI_FUNC(t->devfn)); 2201 assert(s == slot_len); 2202 memcpy(p, slot, slot_len); 2203 } 2204 2205 return path; 2206 } 2207 2208 static int pci_qdev_find_recursive(PCIBus *bus, 2209 const char *id, PCIDevice **pdev) 2210 { 2211 DeviceState *qdev = qdev_find_recursive(&bus->qbus, id); 2212 if (!qdev) { 2213 return -ENODEV; 2214 } 2215 2216 /* roughly check if given qdev is pci device */ 2217 if (object_dynamic_cast(OBJECT(qdev), TYPE_PCI_DEVICE)) { 2218 *pdev = PCI_DEVICE(qdev); 2219 return 0; 2220 } 2221 return -EINVAL; 2222 } 2223 2224 int pci_qdev_find_device(const char *id, PCIDevice **pdev) 2225 { 2226 PCIHostState *host_bridge; 2227 int rc = -ENODEV; 2228 2229 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { 2230 int tmp = pci_qdev_find_recursive(host_bridge->bus, id, pdev); 2231 if (!tmp) { 2232 rc = 0; 2233 break; 2234 } 2235 if (tmp != -ENODEV) { 2236 rc = tmp; 2237 } 2238 } 2239 2240 return rc; 2241 } 2242 2243 MemoryRegion *pci_address_space(PCIDevice *dev) 2244 { 2245 return dev->bus->address_space_mem; 2246 } 2247 2248 MemoryRegion *pci_address_space_io(PCIDevice *dev) 2249 { 2250 return dev->bus->address_space_io; 2251 } 2252 2253 static void pci_device_class_init(ObjectClass *klass, void *data) 2254 { 2255 DeviceClass *k = DEVICE_CLASS(klass); 2256 k->init = pci_qdev_init; 2257 k->unplug = pci_unplug_device; 2258 k->exit = pci_unregister_device; 2259 k->bus_type = TYPE_PCI_BUS; 2260 k->props = pci_props; 2261 } 2262 2263 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev) 2264 { 2265 PCIBus *bus = PCI_BUS(dev->bus); 2266 2267 if (bus->iommu_fn) { 2268 return bus->iommu_fn(bus, bus->iommu_opaque, dev->devfn); 2269 } 2270 2271 if (bus->parent_dev) { 2272 /** We are ignoring the bus master DMA bit of the bridge 2273 * as it would complicate things such as VFIO for no good reason */ 2274 return pci_device_iommu_address_space(bus->parent_dev); 2275 } 2276 2277 return &address_space_memory; 2278 } 2279 2280 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque) 2281 { 2282 bus->iommu_fn = fn; 2283 bus->iommu_opaque = opaque; 2284 } 2285 2286 static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque) 2287 { 2288 Range *range = opaque; 2289 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 2290 uint16_t cmd = pci_get_word(dev->config + PCI_COMMAND); 2291 int i; 2292 2293 if (!(cmd & PCI_COMMAND_MEMORY)) { 2294 return; 2295 } 2296 2297 if (pc->is_bridge) { 2298 pcibus_t base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 2299 pcibus_t limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 2300 2301 base = MAX(base, 0x1ULL << 32); 2302 2303 if (limit >= base) { 2304 Range pref_range; 2305 pref_range.begin = base; 2306 pref_range.end = limit + 1; 2307 range_extend(range, &pref_range); 2308 } 2309 } 2310 for (i = 0; i < PCI_NUM_REGIONS; ++i) { 2311 PCIIORegion *r = &dev->io_regions[i]; 2312 Range region_range; 2313 2314 if (!r->size || 2315 (r->type & PCI_BASE_ADDRESS_SPACE_IO) || 2316 !(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64)) { 2317 continue; 2318 } 2319 region_range.begin = pci_bar_address(dev, i, r->type, r->size); 2320 region_range.end = region_range.begin + r->size; 2321 2322 if (region_range.begin == PCI_BAR_UNMAPPED) { 2323 continue; 2324 } 2325 2326 region_range.begin = MAX(region_range.begin, 0x1ULL << 32); 2327 2328 if (region_range.end - 1 >= region_range.begin) { 2329 range_extend(range, ®ion_range); 2330 } 2331 } 2332 } 2333 2334 void pci_bus_get_w64_range(PCIBus *bus, Range *range) 2335 { 2336 range->begin = range->end = 0; 2337 pci_for_each_device_under_bus(bus, pci_dev_get_w64, range); 2338 } 2339 2340 static const TypeInfo pci_device_type_info = { 2341 .name = TYPE_PCI_DEVICE, 2342 .parent = TYPE_DEVICE, 2343 .instance_size = sizeof(PCIDevice), 2344 .abstract = true, 2345 .class_size = sizeof(PCIDeviceClass), 2346 .class_init = pci_device_class_init, 2347 }; 2348 2349 static void pci_register_types(void) 2350 { 2351 type_register_static(&pci_bus_info); 2352 type_register_static(&pcie_bus_info); 2353 type_register_static(&pci_device_type_info); 2354 } 2355 2356 type_init(pci_register_types) 2357