1 /* 2 * QEMU PCI bus manager 3 * 4 * Copyright (c) 2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/hw.h" 27 #include "hw/pci/pci.h" 28 #include "hw/pci/pci_bridge.h" 29 #include "hw/pci/pci_bus.h" 30 #include "hw/pci/pci_host.h" 31 #include "monitor/monitor.h" 32 #include "net/net.h" 33 #include "sysemu/sysemu.h" 34 #include "hw/loader.h" 35 #include "qemu/error-report.h" 36 #include "qemu/range.h" 37 #include "trace.h" 38 #include "hw/pci/msi.h" 39 #include "hw/pci/msix.h" 40 #include "exec/address-spaces.h" 41 #include "hw/hotplug.h" 42 #include "hw/boards.h" 43 #include "qapi/error.h" 44 #include "qapi/qapi-commands-misc.h" 45 #include "qemu/cutils.h" 46 47 //#define DEBUG_PCI 48 #ifdef DEBUG_PCI 49 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) 50 #else 51 # define PCI_DPRINTF(format, ...) do { } while (0) 52 #endif 53 54 bool pci_available = true; 55 56 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent); 57 static char *pcibus_get_dev_path(DeviceState *dev); 58 static char *pcibus_get_fw_dev_path(DeviceState *dev); 59 static void pcibus_reset(BusState *qbus); 60 61 static Property pci_props[] = { 62 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1), 63 DEFINE_PROP_STRING("romfile", PCIDevice, romfile), 64 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1), 65 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present, 66 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false), 67 DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present, 68 QEMU_PCI_CAP_SERR_BITNR, true), 69 DEFINE_PROP_BIT("x-pcie-lnksta-dllla", PCIDevice, cap_present, 70 QEMU_PCIE_LNKSTA_DLLLA_BITNR, true), 71 DEFINE_PROP_BIT("x-pcie-extcap-init", PCIDevice, cap_present, 72 QEMU_PCIE_EXTCAP_INIT_BITNR, true), 73 DEFINE_PROP_END_OF_LIST() 74 }; 75 76 static const VMStateDescription vmstate_pcibus = { 77 .name = "PCIBUS", 78 .version_id = 1, 79 .minimum_version_id = 1, 80 .fields = (VMStateField[]) { 81 VMSTATE_INT32_EQUAL(nirq, PCIBus, NULL), 82 VMSTATE_VARRAY_INT32(irq_count, PCIBus, 83 nirq, 0, vmstate_info_int32, 84 int32_t), 85 VMSTATE_END_OF_LIST() 86 } 87 }; 88 89 static void pci_init_bus_master(PCIDevice *pci_dev) 90 { 91 AddressSpace *dma_as = pci_device_iommu_address_space(pci_dev); 92 93 memory_region_init_alias(&pci_dev->bus_master_enable_region, 94 OBJECT(pci_dev), "bus master", 95 dma_as->root, 0, memory_region_size(dma_as->root)); 96 memory_region_set_enabled(&pci_dev->bus_master_enable_region, false); 97 memory_region_add_subregion(&pci_dev->bus_master_container_region, 0, 98 &pci_dev->bus_master_enable_region); 99 } 100 101 static void pcibus_machine_done(Notifier *notifier, void *data) 102 { 103 PCIBus *bus = container_of(notifier, PCIBus, machine_done); 104 int i; 105 106 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 107 if (bus->devices[i]) { 108 pci_init_bus_master(bus->devices[i]); 109 } 110 } 111 } 112 113 static void pci_bus_realize(BusState *qbus, Error **errp) 114 { 115 PCIBus *bus = PCI_BUS(qbus); 116 117 bus->machine_done.notify = pcibus_machine_done; 118 qemu_add_machine_init_done_notifier(&bus->machine_done); 119 120 vmstate_register(NULL, -1, &vmstate_pcibus, bus); 121 } 122 123 static void pci_bus_unrealize(BusState *qbus, Error **errp) 124 { 125 PCIBus *bus = PCI_BUS(qbus); 126 127 qemu_remove_machine_init_done_notifier(&bus->machine_done); 128 129 vmstate_unregister(NULL, &vmstate_pcibus, bus); 130 } 131 132 static bool pcibus_is_root(PCIBus *bus) 133 { 134 return !bus->parent_dev; 135 } 136 137 static int pcibus_num(PCIBus *bus) 138 { 139 if (pcibus_is_root(bus)) { 140 return 0; /* pci host bridge */ 141 } 142 return bus->parent_dev->config[PCI_SECONDARY_BUS]; 143 } 144 145 static uint16_t pcibus_numa_node(PCIBus *bus) 146 { 147 return NUMA_NODE_UNASSIGNED; 148 } 149 150 static void pci_bus_class_init(ObjectClass *klass, void *data) 151 { 152 BusClass *k = BUS_CLASS(klass); 153 PCIBusClass *pbc = PCI_BUS_CLASS(klass); 154 155 k->print_dev = pcibus_dev_print; 156 k->get_dev_path = pcibus_get_dev_path; 157 k->get_fw_dev_path = pcibus_get_fw_dev_path; 158 k->realize = pci_bus_realize; 159 k->unrealize = pci_bus_unrealize; 160 k->reset = pcibus_reset; 161 162 pbc->is_root = pcibus_is_root; 163 pbc->bus_num = pcibus_num; 164 pbc->numa_node = pcibus_numa_node; 165 } 166 167 static const TypeInfo pci_bus_info = { 168 .name = TYPE_PCI_BUS, 169 .parent = TYPE_BUS, 170 .instance_size = sizeof(PCIBus), 171 .class_size = sizeof(PCIBusClass), 172 .class_init = pci_bus_class_init, 173 }; 174 175 static const TypeInfo pcie_interface_info = { 176 .name = INTERFACE_PCIE_DEVICE, 177 .parent = TYPE_INTERFACE, 178 }; 179 180 static const TypeInfo conventional_pci_interface_info = { 181 .name = INTERFACE_CONVENTIONAL_PCI_DEVICE, 182 .parent = TYPE_INTERFACE, 183 }; 184 185 static const TypeInfo pcie_bus_info = { 186 .name = TYPE_PCIE_BUS, 187 .parent = TYPE_PCI_BUS, 188 }; 189 190 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num); 191 static void pci_update_mappings(PCIDevice *d); 192 static void pci_irq_handler(void *opaque, int irq_num, int level); 193 static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, Error **); 194 static void pci_del_option_rom(PCIDevice *pdev); 195 196 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET; 197 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU; 198 199 static QLIST_HEAD(, PCIHostState) pci_host_bridges; 200 201 int pci_bar(PCIDevice *d, int reg) 202 { 203 uint8_t type; 204 205 if (reg != PCI_ROM_SLOT) 206 return PCI_BASE_ADDRESS_0 + reg * 4; 207 208 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 209 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS; 210 } 211 212 static inline int pci_irq_state(PCIDevice *d, int irq_num) 213 { 214 return (d->irq_state >> irq_num) & 0x1; 215 } 216 217 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level) 218 { 219 d->irq_state &= ~(0x1 << irq_num); 220 d->irq_state |= level << irq_num; 221 } 222 223 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change) 224 { 225 PCIBus *bus; 226 for (;;) { 227 bus = pci_get_bus(pci_dev); 228 irq_num = bus->map_irq(pci_dev, irq_num); 229 if (bus->set_irq) 230 break; 231 pci_dev = bus->parent_dev; 232 } 233 bus->irq_count[irq_num] += change; 234 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0); 235 } 236 237 int pci_bus_get_irq_level(PCIBus *bus, int irq_num) 238 { 239 assert(irq_num >= 0); 240 assert(irq_num < bus->nirq); 241 return !!bus->irq_count[irq_num]; 242 } 243 244 /* Update interrupt status bit in config space on interrupt 245 * state change. */ 246 static void pci_update_irq_status(PCIDevice *dev) 247 { 248 if (dev->irq_state) { 249 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT; 250 } else { 251 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; 252 } 253 } 254 255 void pci_device_deassert_intx(PCIDevice *dev) 256 { 257 int i; 258 for (i = 0; i < PCI_NUM_PINS; ++i) { 259 pci_irq_handler(dev, i, 0); 260 } 261 } 262 263 static void pci_do_device_reset(PCIDevice *dev) 264 { 265 int r; 266 267 pci_device_deassert_intx(dev); 268 assert(dev->irq_state == 0); 269 270 /* Clear all writable bits */ 271 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND, 272 pci_get_word(dev->wmask + PCI_COMMAND) | 273 pci_get_word(dev->w1cmask + PCI_COMMAND)); 274 pci_word_test_and_clear_mask(dev->config + PCI_STATUS, 275 pci_get_word(dev->wmask + PCI_STATUS) | 276 pci_get_word(dev->w1cmask + PCI_STATUS)); 277 dev->config[PCI_CACHE_LINE_SIZE] = 0x0; 278 dev->config[PCI_INTERRUPT_LINE] = 0x0; 279 for (r = 0; r < PCI_NUM_REGIONS; ++r) { 280 PCIIORegion *region = &dev->io_regions[r]; 281 if (!region->size) { 282 continue; 283 } 284 285 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) && 286 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 287 pci_set_quad(dev->config + pci_bar(dev, r), region->type); 288 } else { 289 pci_set_long(dev->config + pci_bar(dev, r), region->type); 290 } 291 } 292 pci_update_mappings(dev); 293 294 msi_reset(dev); 295 msix_reset(dev); 296 } 297 298 /* 299 * This function is called on #RST and FLR. 300 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set 301 */ 302 void pci_device_reset(PCIDevice *dev) 303 { 304 qdev_reset_all(&dev->qdev); 305 pci_do_device_reset(dev); 306 } 307 308 /* 309 * Trigger pci bus reset under a given bus. 310 * Called via qbus_reset_all on RST# assert, after the devices 311 * have been reset qdev_reset_all-ed already. 312 */ 313 static void pcibus_reset(BusState *qbus) 314 { 315 PCIBus *bus = DO_UPCAST(PCIBus, qbus, qbus); 316 int i; 317 318 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 319 if (bus->devices[i]) { 320 pci_do_device_reset(bus->devices[i]); 321 } 322 } 323 324 for (i = 0; i < bus->nirq; i++) { 325 assert(bus->irq_count[i] == 0); 326 } 327 } 328 329 static void pci_host_bus_register(DeviceState *host) 330 { 331 PCIHostState *host_bridge = PCI_HOST_BRIDGE(host); 332 333 QLIST_INSERT_HEAD(&pci_host_bridges, host_bridge, next); 334 } 335 336 PCIBus *pci_device_root_bus(const PCIDevice *d) 337 { 338 PCIBus *bus = pci_get_bus(d); 339 340 while (!pci_bus_is_root(bus)) { 341 d = bus->parent_dev; 342 assert(d != NULL); 343 344 bus = pci_get_bus(d); 345 } 346 347 return bus; 348 } 349 350 const char *pci_root_bus_path(PCIDevice *dev) 351 { 352 PCIBus *rootbus = pci_device_root_bus(dev); 353 PCIHostState *host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent); 354 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_GET_CLASS(host_bridge); 355 356 assert(host_bridge->bus == rootbus); 357 358 if (hc->root_bus_path) { 359 return (*hc->root_bus_path)(host_bridge, rootbus); 360 } 361 362 return rootbus->qbus.name; 363 } 364 365 static void pci_root_bus_init(PCIBus *bus, DeviceState *parent, 366 MemoryRegion *address_space_mem, 367 MemoryRegion *address_space_io, 368 uint8_t devfn_min) 369 { 370 assert(PCI_FUNC(devfn_min) == 0); 371 bus->devfn_min = devfn_min; 372 bus->slot_reserved_mask = 0x0; 373 bus->address_space_mem = address_space_mem; 374 bus->address_space_io = address_space_io; 375 376 /* host bridge */ 377 QLIST_INIT(&bus->child); 378 379 pci_host_bus_register(parent); 380 } 381 382 bool pci_bus_is_express(PCIBus *bus) 383 { 384 return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS); 385 } 386 387 bool pci_bus_is_root(PCIBus *bus) 388 { 389 return PCI_BUS_GET_CLASS(bus)->is_root(bus); 390 } 391 392 void pci_root_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent, 393 const char *name, 394 MemoryRegion *address_space_mem, 395 MemoryRegion *address_space_io, 396 uint8_t devfn_min, const char *typename) 397 { 398 qbus_create_inplace(bus, bus_size, typename, parent, name); 399 pci_root_bus_init(bus, parent, address_space_mem, address_space_io, 400 devfn_min); 401 } 402 403 PCIBus *pci_root_bus_new(DeviceState *parent, const char *name, 404 MemoryRegion *address_space_mem, 405 MemoryRegion *address_space_io, 406 uint8_t devfn_min, const char *typename) 407 { 408 PCIBus *bus; 409 410 bus = PCI_BUS(qbus_create(typename, parent, name)); 411 pci_root_bus_init(bus, parent, address_space_mem, address_space_io, 412 devfn_min); 413 return bus; 414 } 415 416 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 417 void *irq_opaque, int nirq) 418 { 419 bus->set_irq = set_irq; 420 bus->map_irq = map_irq; 421 bus->irq_opaque = irq_opaque; 422 bus->nirq = nirq; 423 bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0])); 424 } 425 426 PCIBus *pci_register_root_bus(DeviceState *parent, const char *name, 427 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 428 void *irq_opaque, 429 MemoryRegion *address_space_mem, 430 MemoryRegion *address_space_io, 431 uint8_t devfn_min, int nirq, 432 const char *typename) 433 { 434 PCIBus *bus; 435 436 bus = pci_root_bus_new(parent, name, address_space_mem, 437 address_space_io, devfn_min, typename); 438 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq); 439 return bus; 440 } 441 442 int pci_bus_num(PCIBus *s) 443 { 444 return PCI_BUS_GET_CLASS(s)->bus_num(s); 445 } 446 447 int pci_bus_numa_node(PCIBus *bus) 448 { 449 return PCI_BUS_GET_CLASS(bus)->numa_node(bus); 450 } 451 452 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size, 453 VMStateField *field) 454 { 455 PCIDevice *s = container_of(pv, PCIDevice, config); 456 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(s); 457 uint8_t *config; 458 int i; 459 460 assert(size == pci_config_size(s)); 461 config = g_malloc(size); 462 463 qemu_get_buffer(f, config, size); 464 for (i = 0; i < size; ++i) { 465 if ((config[i] ^ s->config[i]) & 466 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) { 467 error_report("%s: Bad config data: i=0x%x read: %x device: %x " 468 "cmask: %x wmask: %x w1cmask:%x", __func__, 469 i, config[i], s->config[i], 470 s->cmask[i], s->wmask[i], s->w1cmask[i]); 471 g_free(config); 472 return -EINVAL; 473 } 474 } 475 memcpy(s->config, config, size); 476 477 pci_update_mappings(s); 478 if (pc->is_bridge) { 479 PCIBridge *b = PCI_BRIDGE(s); 480 pci_bridge_update_mappings(b); 481 } 482 483 memory_region_set_enabled(&s->bus_master_enable_region, 484 pci_get_word(s->config + PCI_COMMAND) 485 & PCI_COMMAND_MASTER); 486 487 g_free(config); 488 return 0; 489 } 490 491 /* just put buffer */ 492 static int put_pci_config_device(QEMUFile *f, void *pv, size_t size, 493 VMStateField *field, QJSON *vmdesc) 494 { 495 const uint8_t **v = pv; 496 assert(size == pci_config_size(container_of(pv, PCIDevice, config))); 497 qemu_put_buffer(f, *v, size); 498 499 return 0; 500 } 501 502 static VMStateInfo vmstate_info_pci_config = { 503 .name = "pci config", 504 .get = get_pci_config_device, 505 .put = put_pci_config_device, 506 }; 507 508 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size, 509 VMStateField *field) 510 { 511 PCIDevice *s = container_of(pv, PCIDevice, irq_state); 512 uint32_t irq_state[PCI_NUM_PINS]; 513 int i; 514 for (i = 0; i < PCI_NUM_PINS; ++i) { 515 irq_state[i] = qemu_get_be32(f); 516 if (irq_state[i] != 0x1 && irq_state[i] != 0) { 517 fprintf(stderr, "irq state %d: must be 0 or 1.\n", 518 irq_state[i]); 519 return -EINVAL; 520 } 521 } 522 523 for (i = 0; i < PCI_NUM_PINS; ++i) { 524 pci_set_irq_state(s, i, irq_state[i]); 525 } 526 527 return 0; 528 } 529 530 static int put_pci_irq_state(QEMUFile *f, void *pv, size_t size, 531 VMStateField *field, QJSON *vmdesc) 532 { 533 int i; 534 PCIDevice *s = container_of(pv, PCIDevice, irq_state); 535 536 for (i = 0; i < PCI_NUM_PINS; ++i) { 537 qemu_put_be32(f, pci_irq_state(s, i)); 538 } 539 540 return 0; 541 } 542 543 static VMStateInfo vmstate_info_pci_irq_state = { 544 .name = "pci irq state", 545 .get = get_pci_irq_state, 546 .put = put_pci_irq_state, 547 }; 548 549 static bool migrate_is_pcie(void *opaque, int version_id) 550 { 551 return pci_is_express((PCIDevice *)opaque); 552 } 553 554 static bool migrate_is_not_pcie(void *opaque, int version_id) 555 { 556 return !pci_is_express((PCIDevice *)opaque); 557 } 558 559 const VMStateDescription vmstate_pci_device = { 560 .name = "PCIDevice", 561 .version_id = 2, 562 .minimum_version_id = 1, 563 .fields = (VMStateField[]) { 564 VMSTATE_INT32_POSITIVE_LE(version_id, PCIDevice), 565 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice, 566 migrate_is_not_pcie, 567 0, vmstate_info_pci_config, 568 PCI_CONFIG_SPACE_SIZE), 569 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice, 570 migrate_is_pcie, 571 0, vmstate_info_pci_config, 572 PCIE_CONFIG_SPACE_SIZE), 573 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2, 574 vmstate_info_pci_irq_state, 575 PCI_NUM_PINS * sizeof(int32_t)), 576 VMSTATE_END_OF_LIST() 577 } 578 }; 579 580 581 void pci_device_save(PCIDevice *s, QEMUFile *f) 582 { 583 /* Clear interrupt status bit: it is implicit 584 * in irq_state which we are saving. 585 * This makes us compatible with old devices 586 * which never set or clear this bit. */ 587 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; 588 vmstate_save_state(f, &vmstate_pci_device, s, NULL); 589 /* Restore the interrupt status bit. */ 590 pci_update_irq_status(s); 591 } 592 593 int pci_device_load(PCIDevice *s, QEMUFile *f) 594 { 595 int ret; 596 ret = vmstate_load_state(f, &vmstate_pci_device, s, s->version_id); 597 /* Restore the interrupt status bit. */ 598 pci_update_irq_status(s); 599 return ret; 600 } 601 602 static void pci_set_default_subsystem_id(PCIDevice *pci_dev) 603 { 604 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, 605 pci_default_sub_vendor_id); 606 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 607 pci_default_sub_device_id); 608 } 609 610 /* 611 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL 612 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error 613 */ 614 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, 615 unsigned int *slotp, unsigned int *funcp) 616 { 617 const char *p; 618 char *e; 619 unsigned long val; 620 unsigned long dom = 0, bus = 0; 621 unsigned int slot = 0; 622 unsigned int func = 0; 623 624 p = addr; 625 val = strtoul(p, &e, 16); 626 if (e == p) 627 return -1; 628 if (*e == ':') { 629 bus = val; 630 p = e + 1; 631 val = strtoul(p, &e, 16); 632 if (e == p) 633 return -1; 634 if (*e == ':') { 635 dom = bus; 636 bus = val; 637 p = e + 1; 638 val = strtoul(p, &e, 16); 639 if (e == p) 640 return -1; 641 } 642 } 643 644 slot = val; 645 646 if (funcp != NULL) { 647 if (*e != '.') 648 return -1; 649 650 p = e + 1; 651 val = strtoul(p, &e, 16); 652 if (e == p) 653 return -1; 654 655 func = val; 656 } 657 658 /* if funcp == NULL func is 0 */ 659 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7) 660 return -1; 661 662 if (*e) 663 return -1; 664 665 *domp = dom; 666 *busp = bus; 667 *slotp = slot; 668 if (funcp != NULL) 669 *funcp = func; 670 return 0; 671 } 672 673 static PCIBus *pci_get_bus_devfn(int *devfnp, PCIBus *root, 674 const char *devaddr) 675 { 676 int dom, bus; 677 unsigned slot; 678 679 if (!root) { 680 fprintf(stderr, "No primary PCI bus\n"); 681 return NULL; 682 } 683 684 assert(!root->parent_dev); 685 686 if (!devaddr) { 687 *devfnp = -1; 688 return pci_find_bus_nr(root, 0); 689 } 690 691 if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) { 692 return NULL; 693 } 694 695 if (dom != 0) { 696 fprintf(stderr, "No support for non-zero PCI domains\n"); 697 return NULL; 698 } 699 700 *devfnp = PCI_DEVFN(slot, 0); 701 return pci_find_bus_nr(root, bus); 702 } 703 704 static void pci_init_cmask(PCIDevice *dev) 705 { 706 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff); 707 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff); 708 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST; 709 dev->cmask[PCI_REVISION_ID] = 0xff; 710 dev->cmask[PCI_CLASS_PROG] = 0xff; 711 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff); 712 dev->cmask[PCI_HEADER_TYPE] = 0xff; 713 dev->cmask[PCI_CAPABILITY_LIST] = 0xff; 714 } 715 716 static void pci_init_wmask(PCIDevice *dev) 717 { 718 int config_size = pci_config_size(dev); 719 720 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff; 721 dev->wmask[PCI_INTERRUPT_LINE] = 0xff; 722 pci_set_word(dev->wmask + PCI_COMMAND, 723 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | 724 PCI_COMMAND_INTX_DISABLE); 725 if (dev->cap_present & QEMU_PCI_CAP_SERR) { 726 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR); 727 } 728 729 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff, 730 config_size - PCI_CONFIG_HEADER_SIZE); 731 } 732 733 static void pci_init_w1cmask(PCIDevice *dev) 734 { 735 /* 736 * Note: It's okay to set w1cmask even for readonly bits as 737 * long as their value is hardwired to 0. 738 */ 739 pci_set_word(dev->w1cmask + PCI_STATUS, 740 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT | 741 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT | 742 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY); 743 } 744 745 static void pci_init_mask_bridge(PCIDevice *d) 746 { 747 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and 748 PCI_SEC_LETENCY_TIMER */ 749 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4); 750 751 /* base and limit */ 752 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff; 753 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff; 754 pci_set_word(d->wmask + PCI_MEMORY_BASE, 755 PCI_MEMORY_RANGE_MASK & 0xffff); 756 pci_set_word(d->wmask + PCI_MEMORY_LIMIT, 757 PCI_MEMORY_RANGE_MASK & 0xffff); 758 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE, 759 PCI_PREF_RANGE_MASK & 0xffff); 760 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT, 761 PCI_PREF_RANGE_MASK & 0xffff); 762 763 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */ 764 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8); 765 766 /* Supported memory and i/o types */ 767 d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16; 768 d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16; 769 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE, 770 PCI_PREF_RANGE_TYPE_64); 771 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT, 772 PCI_PREF_RANGE_TYPE_64); 773 774 /* 775 * TODO: Bridges default to 10-bit VGA decoding but we currently only 776 * implement 16-bit decoding (no alias support). 777 */ 778 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 779 PCI_BRIDGE_CTL_PARITY | 780 PCI_BRIDGE_CTL_SERR | 781 PCI_BRIDGE_CTL_ISA | 782 PCI_BRIDGE_CTL_VGA | 783 PCI_BRIDGE_CTL_VGA_16BIT | 784 PCI_BRIDGE_CTL_MASTER_ABORT | 785 PCI_BRIDGE_CTL_BUS_RESET | 786 PCI_BRIDGE_CTL_FAST_BACK | 787 PCI_BRIDGE_CTL_DISCARD | 788 PCI_BRIDGE_CTL_SEC_DISCARD | 789 PCI_BRIDGE_CTL_DISCARD_SERR); 790 /* Below does not do anything as we never set this bit, put here for 791 * completeness. */ 792 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL, 793 PCI_BRIDGE_CTL_DISCARD_STATUS); 794 d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK; 795 d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK; 796 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE, 797 PCI_PREF_RANGE_TYPE_MASK); 798 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT, 799 PCI_PREF_RANGE_TYPE_MASK); 800 } 801 802 static void pci_init_multifunction(PCIBus *bus, PCIDevice *dev, Error **errp) 803 { 804 uint8_t slot = PCI_SLOT(dev->devfn); 805 uint8_t func; 806 807 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 808 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION; 809 } 810 811 /* 812 * multifunction bit is interpreted in two ways as follows. 813 * - all functions must set the bit to 1. 814 * Example: Intel X53 815 * - function 0 must set the bit, but the rest function (> 0) 816 * is allowed to leave the bit to 0. 817 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10, 818 * 819 * So OS (at least Linux) checks the bit of only function 0, 820 * and doesn't see the bit of function > 0. 821 * 822 * The below check allows both interpretation. 823 */ 824 if (PCI_FUNC(dev->devfn)) { 825 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)]; 826 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) { 827 /* function 0 should set multifunction bit */ 828 error_setg(errp, "PCI: single function device can't be populated " 829 "in function %x.%x", slot, PCI_FUNC(dev->devfn)); 830 return; 831 } 832 return; 833 } 834 835 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 836 return; 837 } 838 /* function 0 indicates single function, so function > 0 must be NULL */ 839 for (func = 1; func < PCI_FUNC_MAX; ++func) { 840 if (bus->devices[PCI_DEVFN(slot, func)]) { 841 error_setg(errp, "PCI: %x.0 indicates single function, " 842 "but %x.%x is already populated.", 843 slot, slot, func); 844 return; 845 } 846 } 847 } 848 849 static void pci_config_alloc(PCIDevice *pci_dev) 850 { 851 int config_size = pci_config_size(pci_dev); 852 853 pci_dev->config = g_malloc0(config_size); 854 pci_dev->cmask = g_malloc0(config_size); 855 pci_dev->wmask = g_malloc0(config_size); 856 pci_dev->w1cmask = g_malloc0(config_size); 857 pci_dev->used = g_malloc0(config_size); 858 } 859 860 static void pci_config_free(PCIDevice *pci_dev) 861 { 862 g_free(pci_dev->config); 863 g_free(pci_dev->cmask); 864 g_free(pci_dev->wmask); 865 g_free(pci_dev->w1cmask); 866 g_free(pci_dev->used); 867 } 868 869 static void do_pci_unregister_device(PCIDevice *pci_dev) 870 { 871 pci_get_bus(pci_dev)->devices[pci_dev->devfn] = NULL; 872 pci_config_free(pci_dev); 873 874 if (memory_region_is_mapped(&pci_dev->bus_master_enable_region)) { 875 memory_region_del_subregion(&pci_dev->bus_master_container_region, 876 &pci_dev->bus_master_enable_region); 877 } 878 address_space_destroy(&pci_dev->bus_master_as); 879 } 880 881 /* Extract PCIReqIDCache into BDF format */ 882 static uint16_t pci_req_id_cache_extract(PCIReqIDCache *cache) 883 { 884 uint8_t bus_n; 885 uint16_t result; 886 887 switch (cache->type) { 888 case PCI_REQ_ID_BDF: 889 result = pci_get_bdf(cache->dev); 890 break; 891 case PCI_REQ_ID_SECONDARY_BUS: 892 bus_n = pci_dev_bus_num(cache->dev); 893 result = PCI_BUILD_BDF(bus_n, 0); 894 break; 895 default: 896 error_printf("Invalid PCI requester ID cache type: %d\n", 897 cache->type); 898 exit(1); 899 break; 900 } 901 902 return result; 903 } 904 905 /* Parse bridges up to the root complex and return requester ID 906 * cache for specific device. For full PCIe topology, the cache 907 * result would be exactly the same as getting BDF of the device. 908 * However, several tricks are required when system mixed up with 909 * legacy PCI devices and PCIe-to-PCI bridges. 910 * 911 * Here we cache the proxy device (and type) not requester ID since 912 * bus number might change from time to time. 913 */ 914 static PCIReqIDCache pci_req_id_cache_get(PCIDevice *dev) 915 { 916 PCIDevice *parent; 917 PCIReqIDCache cache = { 918 .dev = dev, 919 .type = PCI_REQ_ID_BDF, 920 }; 921 922 while (!pci_bus_is_root(pci_get_bus(dev))) { 923 /* We are under PCI/PCIe bridges */ 924 parent = pci_get_bus(dev)->parent_dev; 925 if (pci_is_express(parent)) { 926 if (pcie_cap_get_type(parent) == PCI_EXP_TYPE_PCI_BRIDGE) { 927 /* When we pass through PCIe-to-PCI/PCIX bridges, we 928 * override the requester ID using secondary bus 929 * number of parent bridge with zeroed devfn 930 * (pcie-to-pci bridge spec chap 2.3). */ 931 cache.type = PCI_REQ_ID_SECONDARY_BUS; 932 cache.dev = dev; 933 } 934 } else { 935 /* Legacy PCI, override requester ID with the bridge's 936 * BDF upstream. When the root complex connects to 937 * legacy PCI devices (including buses), it can only 938 * obtain requester ID info from directly attached 939 * devices. If devices are attached under bridges, only 940 * the requester ID of the bridge that is directly 941 * attached to the root complex can be recognized. */ 942 cache.type = PCI_REQ_ID_BDF; 943 cache.dev = parent; 944 } 945 dev = parent; 946 } 947 948 return cache; 949 } 950 951 uint16_t pci_requester_id(PCIDevice *dev) 952 { 953 return pci_req_id_cache_extract(&dev->requester_id_cache); 954 } 955 956 static bool pci_bus_devfn_available(PCIBus *bus, int devfn) 957 { 958 return !(bus->devices[devfn]); 959 } 960 961 static bool pci_bus_devfn_reserved(PCIBus *bus, int devfn) 962 { 963 return bus->slot_reserved_mask & (1UL << PCI_SLOT(devfn)); 964 } 965 966 /* -1 for devfn means auto assign */ 967 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, 968 const char *name, int devfn, 969 Error **errp) 970 { 971 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 972 PCIConfigReadFunc *config_read = pc->config_read; 973 PCIConfigWriteFunc *config_write = pc->config_write; 974 Error *local_err = NULL; 975 DeviceState *dev = DEVICE(pci_dev); 976 PCIBus *bus = pci_get_bus(pci_dev); 977 978 /* Only pci bridges can be attached to extra PCI root buses */ 979 if (pci_bus_is_root(bus) && bus->parent_dev && !pc->is_bridge) { 980 error_setg(errp, 981 "PCI: Only PCI/PCIe bridges can be plugged into %s", 982 bus->parent_dev->name); 983 return NULL; 984 } 985 986 if (devfn < 0) { 987 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices); 988 devfn += PCI_FUNC_MAX) { 989 if (pci_bus_devfn_available(bus, devfn) && 990 !pci_bus_devfn_reserved(bus, devfn)) { 991 goto found; 992 } 993 } 994 error_setg(errp, "PCI: no slot/function available for %s, all in use " 995 "or reserved", name); 996 return NULL; 997 found: ; 998 } else if (pci_bus_devfn_reserved(bus, devfn)) { 999 error_setg(errp, "PCI: slot %d function %d not available for %s," 1000 " reserved", 1001 PCI_SLOT(devfn), PCI_FUNC(devfn), name); 1002 return NULL; 1003 } else if (!pci_bus_devfn_available(bus, devfn)) { 1004 error_setg(errp, "PCI: slot %d function %d not available for %s," 1005 " in use by %s", 1006 PCI_SLOT(devfn), PCI_FUNC(devfn), name, 1007 bus->devices[devfn]->name); 1008 return NULL; 1009 } else if (dev->hotplugged && 1010 pci_get_function_0(pci_dev)) { 1011 error_setg(errp, "PCI: slot %d function 0 already ocuppied by %s," 1012 " new func %s cannot be exposed to guest.", 1013 PCI_SLOT(pci_get_function_0(pci_dev)->devfn), 1014 pci_get_function_0(pci_dev)->name, 1015 name); 1016 1017 return NULL; 1018 } 1019 1020 pci_dev->devfn = devfn; 1021 pci_dev->requester_id_cache = pci_req_id_cache_get(pci_dev); 1022 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name); 1023 1024 memory_region_init(&pci_dev->bus_master_container_region, OBJECT(pci_dev), 1025 "bus master container", UINT64_MAX); 1026 address_space_init(&pci_dev->bus_master_as, 1027 &pci_dev->bus_master_container_region, pci_dev->name); 1028 1029 if (qdev_hotplug) { 1030 pci_init_bus_master(pci_dev); 1031 } 1032 pci_dev->irq_state = 0; 1033 pci_config_alloc(pci_dev); 1034 1035 pci_config_set_vendor_id(pci_dev->config, pc->vendor_id); 1036 pci_config_set_device_id(pci_dev->config, pc->device_id); 1037 pci_config_set_revision(pci_dev->config, pc->revision); 1038 pci_config_set_class(pci_dev->config, pc->class_id); 1039 1040 if (!pc->is_bridge) { 1041 if (pc->subsystem_vendor_id || pc->subsystem_id) { 1042 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, 1043 pc->subsystem_vendor_id); 1044 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 1045 pc->subsystem_id); 1046 } else { 1047 pci_set_default_subsystem_id(pci_dev); 1048 } 1049 } else { 1050 /* subsystem_vendor_id/subsystem_id are only for header type 0 */ 1051 assert(!pc->subsystem_vendor_id); 1052 assert(!pc->subsystem_id); 1053 } 1054 pci_init_cmask(pci_dev); 1055 pci_init_wmask(pci_dev); 1056 pci_init_w1cmask(pci_dev); 1057 if (pc->is_bridge) { 1058 pci_init_mask_bridge(pci_dev); 1059 } 1060 pci_init_multifunction(bus, pci_dev, &local_err); 1061 if (local_err) { 1062 error_propagate(errp, local_err); 1063 do_pci_unregister_device(pci_dev); 1064 return NULL; 1065 } 1066 1067 if (!config_read) 1068 config_read = pci_default_read_config; 1069 if (!config_write) 1070 config_write = pci_default_write_config; 1071 pci_dev->config_read = config_read; 1072 pci_dev->config_write = config_write; 1073 bus->devices[devfn] = pci_dev; 1074 pci_dev->version_id = 2; /* Current pci device vmstate version */ 1075 return pci_dev; 1076 } 1077 1078 static void pci_unregister_io_regions(PCIDevice *pci_dev) 1079 { 1080 PCIIORegion *r; 1081 int i; 1082 1083 for(i = 0; i < PCI_NUM_REGIONS; i++) { 1084 r = &pci_dev->io_regions[i]; 1085 if (!r->size || r->addr == PCI_BAR_UNMAPPED) 1086 continue; 1087 memory_region_del_subregion(r->address_space, r->memory); 1088 } 1089 1090 pci_unregister_vga(pci_dev); 1091 } 1092 1093 static void pci_qdev_unrealize(DeviceState *dev, Error **errp) 1094 { 1095 PCIDevice *pci_dev = PCI_DEVICE(dev); 1096 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 1097 1098 pci_unregister_io_regions(pci_dev); 1099 pci_del_option_rom(pci_dev); 1100 1101 if (pc->exit) { 1102 pc->exit(pci_dev); 1103 } 1104 1105 pci_device_deassert_intx(pci_dev); 1106 do_pci_unregister_device(pci_dev); 1107 } 1108 1109 void pci_register_bar(PCIDevice *pci_dev, int region_num, 1110 uint8_t type, MemoryRegion *memory) 1111 { 1112 PCIIORegion *r; 1113 uint32_t addr; /* offset in pci config space */ 1114 uint64_t wmask; 1115 pcibus_t size = memory_region_size(memory); 1116 1117 assert(region_num >= 0); 1118 assert(region_num < PCI_NUM_REGIONS); 1119 if (size & (size-1)) { 1120 error_report("ERROR: PCI region size must be pow2 " 1121 "type=0x%x, size=0x%"FMT_PCIBUS"", type, size); 1122 exit(1); 1123 } 1124 1125 r = &pci_dev->io_regions[region_num]; 1126 r->addr = PCI_BAR_UNMAPPED; 1127 r->size = size; 1128 r->type = type; 1129 r->memory = memory; 1130 r->address_space = type & PCI_BASE_ADDRESS_SPACE_IO 1131 ? pci_get_bus(pci_dev)->address_space_io 1132 : pci_get_bus(pci_dev)->address_space_mem; 1133 1134 wmask = ~(size - 1); 1135 if (region_num == PCI_ROM_SLOT) { 1136 /* ROM enable bit is writable */ 1137 wmask |= PCI_ROM_ADDRESS_ENABLE; 1138 } 1139 1140 addr = pci_bar(pci_dev, region_num); 1141 pci_set_long(pci_dev->config + addr, type); 1142 1143 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) && 1144 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 1145 pci_set_quad(pci_dev->wmask + addr, wmask); 1146 pci_set_quad(pci_dev->cmask + addr, ~0ULL); 1147 } else { 1148 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff); 1149 pci_set_long(pci_dev->cmask + addr, 0xffffffff); 1150 } 1151 } 1152 1153 static void pci_update_vga(PCIDevice *pci_dev) 1154 { 1155 uint16_t cmd; 1156 1157 if (!pci_dev->has_vga) { 1158 return; 1159 } 1160 1161 cmd = pci_get_word(pci_dev->config + PCI_COMMAND); 1162 1163 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_MEM], 1164 cmd & PCI_COMMAND_MEMORY); 1165 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO], 1166 cmd & PCI_COMMAND_IO); 1167 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI], 1168 cmd & PCI_COMMAND_IO); 1169 } 1170 1171 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, 1172 MemoryRegion *io_lo, MemoryRegion *io_hi) 1173 { 1174 PCIBus *bus = pci_get_bus(pci_dev); 1175 1176 assert(!pci_dev->has_vga); 1177 1178 assert(memory_region_size(mem) == QEMU_PCI_VGA_MEM_SIZE); 1179 pci_dev->vga_regions[QEMU_PCI_VGA_MEM] = mem; 1180 memory_region_add_subregion_overlap(bus->address_space_mem, 1181 QEMU_PCI_VGA_MEM_BASE, mem, 1); 1182 1183 assert(memory_region_size(io_lo) == QEMU_PCI_VGA_IO_LO_SIZE); 1184 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO] = io_lo; 1185 memory_region_add_subregion_overlap(bus->address_space_io, 1186 QEMU_PCI_VGA_IO_LO_BASE, io_lo, 1); 1187 1188 assert(memory_region_size(io_hi) == QEMU_PCI_VGA_IO_HI_SIZE); 1189 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI] = io_hi; 1190 memory_region_add_subregion_overlap(bus->address_space_io, 1191 QEMU_PCI_VGA_IO_HI_BASE, io_hi, 1); 1192 pci_dev->has_vga = true; 1193 1194 pci_update_vga(pci_dev); 1195 } 1196 1197 void pci_unregister_vga(PCIDevice *pci_dev) 1198 { 1199 PCIBus *bus = pci_get_bus(pci_dev); 1200 1201 if (!pci_dev->has_vga) { 1202 return; 1203 } 1204 1205 memory_region_del_subregion(bus->address_space_mem, 1206 pci_dev->vga_regions[QEMU_PCI_VGA_MEM]); 1207 memory_region_del_subregion(bus->address_space_io, 1208 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO]); 1209 memory_region_del_subregion(bus->address_space_io, 1210 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI]); 1211 pci_dev->has_vga = false; 1212 } 1213 1214 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num) 1215 { 1216 return pci_dev->io_regions[region_num].addr; 1217 } 1218 1219 static pcibus_t pci_bar_address(PCIDevice *d, 1220 int reg, uint8_t type, pcibus_t size) 1221 { 1222 pcibus_t new_addr, last_addr; 1223 int bar = pci_bar(d, reg); 1224 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND); 1225 Object *machine = qdev_get_machine(); 1226 ObjectClass *oc = object_get_class(machine); 1227 MachineClass *mc = MACHINE_CLASS(oc); 1228 bool allow_0_address = mc->pci_allow_0_address; 1229 1230 if (type & PCI_BASE_ADDRESS_SPACE_IO) { 1231 if (!(cmd & PCI_COMMAND_IO)) { 1232 return PCI_BAR_UNMAPPED; 1233 } 1234 new_addr = pci_get_long(d->config + bar) & ~(size - 1); 1235 last_addr = new_addr + size - 1; 1236 /* Check if 32 bit BAR wraps around explicitly. 1237 * TODO: make priorities correct and remove this work around. 1238 */ 1239 if (last_addr <= new_addr || last_addr >= UINT32_MAX || 1240 (!allow_0_address && new_addr == 0)) { 1241 return PCI_BAR_UNMAPPED; 1242 } 1243 return new_addr; 1244 } 1245 1246 if (!(cmd & PCI_COMMAND_MEMORY)) { 1247 return PCI_BAR_UNMAPPED; 1248 } 1249 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 1250 new_addr = pci_get_quad(d->config + bar); 1251 } else { 1252 new_addr = pci_get_long(d->config + bar); 1253 } 1254 /* the ROM slot has a specific enable bit */ 1255 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) { 1256 return PCI_BAR_UNMAPPED; 1257 } 1258 new_addr &= ~(size - 1); 1259 last_addr = new_addr + size - 1; 1260 /* NOTE: we do not support wrapping */ 1261 /* XXX: as we cannot support really dynamic 1262 mappings, we handle specific values as invalid 1263 mappings. */ 1264 if (last_addr <= new_addr || last_addr == PCI_BAR_UNMAPPED || 1265 (!allow_0_address && new_addr == 0)) { 1266 return PCI_BAR_UNMAPPED; 1267 } 1268 1269 /* Now pcibus_t is 64bit. 1270 * Check if 32 bit BAR wraps around explicitly. 1271 * Without this, PC ide doesn't work well. 1272 * TODO: remove this work around. 1273 */ 1274 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) { 1275 return PCI_BAR_UNMAPPED; 1276 } 1277 1278 /* 1279 * OS is allowed to set BAR beyond its addressable 1280 * bits. For example, 32 bit OS can set 64bit bar 1281 * to >4G. Check it. TODO: we might need to support 1282 * it in the future for e.g. PAE. 1283 */ 1284 if (last_addr >= HWADDR_MAX) { 1285 return PCI_BAR_UNMAPPED; 1286 } 1287 1288 return new_addr; 1289 } 1290 1291 static void pci_update_mappings(PCIDevice *d) 1292 { 1293 PCIIORegion *r; 1294 int i; 1295 pcibus_t new_addr; 1296 1297 for(i = 0; i < PCI_NUM_REGIONS; i++) { 1298 r = &d->io_regions[i]; 1299 1300 /* this region isn't registered */ 1301 if (!r->size) 1302 continue; 1303 1304 new_addr = pci_bar_address(d, i, r->type, r->size); 1305 1306 /* This bar isn't changed */ 1307 if (new_addr == r->addr) 1308 continue; 1309 1310 /* now do the real mapping */ 1311 if (r->addr != PCI_BAR_UNMAPPED) { 1312 trace_pci_update_mappings_del(d, pci_dev_bus_num(d), 1313 PCI_SLOT(d->devfn), 1314 PCI_FUNC(d->devfn), 1315 i, r->addr, r->size); 1316 memory_region_del_subregion(r->address_space, r->memory); 1317 } 1318 r->addr = new_addr; 1319 if (r->addr != PCI_BAR_UNMAPPED) { 1320 trace_pci_update_mappings_add(d, pci_dev_bus_num(d), 1321 PCI_SLOT(d->devfn), 1322 PCI_FUNC(d->devfn), 1323 i, r->addr, r->size); 1324 memory_region_add_subregion_overlap(r->address_space, 1325 r->addr, r->memory, 1); 1326 } 1327 } 1328 1329 pci_update_vga(d); 1330 } 1331 1332 static inline int pci_irq_disabled(PCIDevice *d) 1333 { 1334 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE; 1335 } 1336 1337 /* Called after interrupt disabled field update in config space, 1338 * assert/deassert interrupts if necessary. 1339 * Gets original interrupt disable bit value (before update). */ 1340 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled) 1341 { 1342 int i, disabled = pci_irq_disabled(d); 1343 if (disabled == was_irq_disabled) 1344 return; 1345 for (i = 0; i < PCI_NUM_PINS; ++i) { 1346 int state = pci_irq_state(d, i); 1347 pci_change_irq_level(d, i, disabled ? -state : state); 1348 } 1349 } 1350 1351 uint32_t pci_default_read_config(PCIDevice *d, 1352 uint32_t address, int len) 1353 { 1354 uint32_t val = 0; 1355 1356 memcpy(&val, d->config + address, len); 1357 return le32_to_cpu(val); 1358 } 1359 1360 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val_in, int l) 1361 { 1362 int i, was_irq_disabled = pci_irq_disabled(d); 1363 uint32_t val = val_in; 1364 1365 for (i = 0; i < l; val >>= 8, ++i) { 1366 uint8_t wmask = d->wmask[addr + i]; 1367 uint8_t w1cmask = d->w1cmask[addr + i]; 1368 assert(!(wmask & w1cmask)); 1369 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask); 1370 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */ 1371 } 1372 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) || 1373 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) || 1374 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) || 1375 range_covers_byte(addr, l, PCI_COMMAND)) 1376 pci_update_mappings(d); 1377 1378 if (range_covers_byte(addr, l, PCI_COMMAND)) { 1379 pci_update_irq_disabled(d, was_irq_disabled); 1380 memory_region_set_enabled(&d->bus_master_enable_region, 1381 pci_get_word(d->config + PCI_COMMAND) 1382 & PCI_COMMAND_MASTER); 1383 } 1384 1385 msi_write_config(d, addr, val_in, l); 1386 msix_write_config(d, addr, val_in, l); 1387 } 1388 1389 /***********************************************************/ 1390 /* generic PCI irq support */ 1391 1392 /* 0 <= irq_num <= 3. level must be 0 or 1 */ 1393 static void pci_irq_handler(void *opaque, int irq_num, int level) 1394 { 1395 PCIDevice *pci_dev = opaque; 1396 int change; 1397 1398 change = level - pci_irq_state(pci_dev, irq_num); 1399 if (!change) 1400 return; 1401 1402 pci_set_irq_state(pci_dev, irq_num, level); 1403 pci_update_irq_status(pci_dev); 1404 if (pci_irq_disabled(pci_dev)) 1405 return; 1406 pci_change_irq_level(pci_dev, irq_num, change); 1407 } 1408 1409 static inline int pci_intx(PCIDevice *pci_dev) 1410 { 1411 return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1; 1412 } 1413 1414 qemu_irq pci_allocate_irq(PCIDevice *pci_dev) 1415 { 1416 int intx = pci_intx(pci_dev); 1417 1418 return qemu_allocate_irq(pci_irq_handler, pci_dev, intx); 1419 } 1420 1421 void pci_set_irq(PCIDevice *pci_dev, int level) 1422 { 1423 int intx = pci_intx(pci_dev); 1424 pci_irq_handler(pci_dev, intx, level); 1425 } 1426 1427 /* Special hooks used by device assignment */ 1428 void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq) 1429 { 1430 assert(pci_bus_is_root(bus)); 1431 bus->route_intx_to_irq = route_intx_to_irq; 1432 } 1433 1434 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin) 1435 { 1436 PCIBus *bus; 1437 1438 do { 1439 bus = pci_get_bus(dev); 1440 pin = bus->map_irq(dev, pin); 1441 dev = bus->parent_dev; 1442 } while (dev); 1443 1444 if (!bus->route_intx_to_irq) { 1445 error_report("PCI: Bug - unimplemented PCI INTx routing (%s)", 1446 object_get_typename(OBJECT(bus->qbus.parent))); 1447 return (PCIINTxRoute) { PCI_INTX_DISABLED, -1 }; 1448 } 1449 1450 return bus->route_intx_to_irq(bus->irq_opaque, pin); 1451 } 1452 1453 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new) 1454 { 1455 return old->mode != new->mode || old->irq != new->irq; 1456 } 1457 1458 void pci_bus_fire_intx_routing_notifier(PCIBus *bus) 1459 { 1460 PCIDevice *dev; 1461 PCIBus *sec; 1462 int i; 1463 1464 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 1465 dev = bus->devices[i]; 1466 if (dev && dev->intx_routing_notifier) { 1467 dev->intx_routing_notifier(dev); 1468 } 1469 } 1470 1471 QLIST_FOREACH(sec, &bus->child, sibling) { 1472 pci_bus_fire_intx_routing_notifier(sec); 1473 } 1474 } 1475 1476 void pci_device_set_intx_routing_notifier(PCIDevice *dev, 1477 PCIINTxRoutingNotifier notifier) 1478 { 1479 dev->intx_routing_notifier = notifier; 1480 } 1481 1482 /* 1483 * PCI-to-PCI bridge specification 1484 * 9.1: Interrupt routing. Table 9-1 1485 * 1486 * the PCI Express Base Specification, Revision 2.1 1487 * 2.2.8.1: INTx interrutp signaling - Rules 1488 * the Implementation Note 1489 * Table 2-20 1490 */ 1491 /* 1492 * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD 1493 * 0-origin unlike PCI interrupt pin register. 1494 */ 1495 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin) 1496 { 1497 return (pin + PCI_SLOT(pci_dev->devfn)) % PCI_NUM_PINS; 1498 } 1499 1500 /***********************************************************/ 1501 /* monitor info on PCI */ 1502 1503 typedef struct { 1504 uint16_t class; 1505 const char *desc; 1506 const char *fw_name; 1507 uint16_t fw_ign_bits; 1508 } pci_class_desc; 1509 1510 static const pci_class_desc pci_class_descriptions[] = 1511 { 1512 { 0x0001, "VGA controller", "display"}, 1513 { 0x0100, "SCSI controller", "scsi"}, 1514 { 0x0101, "IDE controller", "ide"}, 1515 { 0x0102, "Floppy controller", "fdc"}, 1516 { 0x0103, "IPI controller", "ipi"}, 1517 { 0x0104, "RAID controller", "raid"}, 1518 { 0x0106, "SATA controller"}, 1519 { 0x0107, "SAS controller"}, 1520 { 0x0180, "Storage controller"}, 1521 { 0x0200, "Ethernet controller", "ethernet"}, 1522 { 0x0201, "Token Ring controller", "token-ring"}, 1523 { 0x0202, "FDDI controller", "fddi"}, 1524 { 0x0203, "ATM controller", "atm"}, 1525 { 0x0280, "Network controller"}, 1526 { 0x0300, "VGA controller", "display", 0x00ff}, 1527 { 0x0301, "XGA controller"}, 1528 { 0x0302, "3D controller"}, 1529 { 0x0380, "Display controller"}, 1530 { 0x0400, "Video controller", "video"}, 1531 { 0x0401, "Audio controller", "sound"}, 1532 { 0x0402, "Phone"}, 1533 { 0x0403, "Audio controller", "sound"}, 1534 { 0x0480, "Multimedia controller"}, 1535 { 0x0500, "RAM controller", "memory"}, 1536 { 0x0501, "Flash controller", "flash"}, 1537 { 0x0580, "Memory controller"}, 1538 { 0x0600, "Host bridge", "host"}, 1539 { 0x0601, "ISA bridge", "isa"}, 1540 { 0x0602, "EISA bridge", "eisa"}, 1541 { 0x0603, "MC bridge", "mca"}, 1542 { 0x0604, "PCI bridge", "pci-bridge"}, 1543 { 0x0605, "PCMCIA bridge", "pcmcia"}, 1544 { 0x0606, "NUBUS bridge", "nubus"}, 1545 { 0x0607, "CARDBUS bridge", "cardbus"}, 1546 { 0x0608, "RACEWAY bridge"}, 1547 { 0x0680, "Bridge"}, 1548 { 0x0700, "Serial port", "serial"}, 1549 { 0x0701, "Parallel port", "parallel"}, 1550 { 0x0800, "Interrupt controller", "interrupt-controller"}, 1551 { 0x0801, "DMA controller", "dma-controller"}, 1552 { 0x0802, "Timer", "timer"}, 1553 { 0x0803, "RTC", "rtc"}, 1554 { 0x0900, "Keyboard", "keyboard"}, 1555 { 0x0901, "Pen", "pen"}, 1556 { 0x0902, "Mouse", "mouse"}, 1557 { 0x0A00, "Dock station", "dock", 0x00ff}, 1558 { 0x0B00, "i386 cpu", "cpu", 0x00ff}, 1559 { 0x0c00, "Fireware contorller", "fireware"}, 1560 { 0x0c01, "Access bus controller", "access-bus"}, 1561 { 0x0c02, "SSA controller", "ssa"}, 1562 { 0x0c03, "USB controller", "usb"}, 1563 { 0x0c04, "Fibre channel controller", "fibre-channel"}, 1564 { 0x0c05, "SMBus"}, 1565 { 0, NULL} 1566 }; 1567 1568 static void pci_for_each_device_under_bus_reverse(PCIBus *bus, 1569 void (*fn)(PCIBus *b, 1570 PCIDevice *d, 1571 void *opaque), 1572 void *opaque) 1573 { 1574 PCIDevice *d; 1575 int devfn; 1576 1577 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1578 d = bus->devices[ARRAY_SIZE(bus->devices) - 1 - devfn]; 1579 if (d) { 1580 fn(bus, d, opaque); 1581 } 1582 } 1583 } 1584 1585 void pci_for_each_device_reverse(PCIBus *bus, int bus_num, 1586 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque), 1587 void *opaque) 1588 { 1589 bus = pci_find_bus_nr(bus, bus_num); 1590 1591 if (bus) { 1592 pci_for_each_device_under_bus_reverse(bus, fn, opaque); 1593 } 1594 } 1595 1596 static void pci_for_each_device_under_bus(PCIBus *bus, 1597 void (*fn)(PCIBus *b, PCIDevice *d, 1598 void *opaque), 1599 void *opaque) 1600 { 1601 PCIDevice *d; 1602 int devfn; 1603 1604 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1605 d = bus->devices[devfn]; 1606 if (d) { 1607 fn(bus, d, opaque); 1608 } 1609 } 1610 } 1611 1612 void pci_for_each_device(PCIBus *bus, int bus_num, 1613 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque), 1614 void *opaque) 1615 { 1616 bus = pci_find_bus_nr(bus, bus_num); 1617 1618 if (bus) { 1619 pci_for_each_device_under_bus(bus, fn, opaque); 1620 } 1621 } 1622 1623 static const pci_class_desc *get_class_desc(int class) 1624 { 1625 const pci_class_desc *desc; 1626 1627 desc = pci_class_descriptions; 1628 while (desc->desc && class != desc->class) { 1629 desc++; 1630 } 1631 1632 return desc; 1633 } 1634 1635 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num); 1636 1637 static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev) 1638 { 1639 PciMemoryRegionList *head = NULL, *cur_item = NULL; 1640 int i; 1641 1642 for (i = 0; i < PCI_NUM_REGIONS; i++) { 1643 const PCIIORegion *r = &dev->io_regions[i]; 1644 PciMemoryRegionList *region; 1645 1646 if (!r->size) { 1647 continue; 1648 } 1649 1650 region = g_malloc0(sizeof(*region)); 1651 region->value = g_malloc0(sizeof(*region->value)); 1652 1653 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { 1654 region->value->type = g_strdup("io"); 1655 } else { 1656 region->value->type = g_strdup("memory"); 1657 region->value->has_prefetch = true; 1658 region->value->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH); 1659 region->value->has_mem_type_64 = true; 1660 region->value->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64); 1661 } 1662 1663 region->value->bar = i; 1664 region->value->address = r->addr; 1665 region->value->size = r->size; 1666 1667 /* XXX: waiting for the qapi to support GSList */ 1668 if (!cur_item) { 1669 head = cur_item = region; 1670 } else { 1671 cur_item->next = region; 1672 cur_item = region; 1673 } 1674 } 1675 1676 return head; 1677 } 1678 1679 static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus, 1680 int bus_num) 1681 { 1682 PciBridgeInfo *info; 1683 PciMemoryRange *range; 1684 1685 info = g_new0(PciBridgeInfo, 1); 1686 1687 info->bus = g_new0(PciBusInfo, 1); 1688 info->bus->number = dev->config[PCI_PRIMARY_BUS]; 1689 info->bus->secondary = dev->config[PCI_SECONDARY_BUS]; 1690 info->bus->subordinate = dev->config[PCI_SUBORDINATE_BUS]; 1691 1692 range = info->bus->io_range = g_new0(PciMemoryRange, 1); 1693 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO); 1694 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO); 1695 1696 range = info->bus->memory_range = g_new0(PciMemoryRange, 1); 1697 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 1698 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 1699 1700 range = info->bus->prefetchable_range = g_new0(PciMemoryRange, 1); 1701 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 1702 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 1703 1704 if (dev->config[PCI_SECONDARY_BUS] != 0) { 1705 PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]); 1706 if (child_bus) { 1707 info->has_devices = true; 1708 info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]); 1709 } 1710 } 1711 1712 return info; 1713 } 1714 1715 static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus, 1716 int bus_num) 1717 { 1718 const pci_class_desc *desc; 1719 PciDeviceInfo *info; 1720 uint8_t type; 1721 int class; 1722 1723 info = g_new0(PciDeviceInfo, 1); 1724 info->bus = bus_num; 1725 info->slot = PCI_SLOT(dev->devfn); 1726 info->function = PCI_FUNC(dev->devfn); 1727 1728 info->class_info = g_new0(PciDeviceClass, 1); 1729 class = pci_get_word(dev->config + PCI_CLASS_DEVICE); 1730 info->class_info->q_class = class; 1731 desc = get_class_desc(class); 1732 if (desc->desc) { 1733 info->class_info->has_desc = true; 1734 info->class_info->desc = g_strdup(desc->desc); 1735 } 1736 1737 info->id = g_new0(PciDeviceId, 1); 1738 info->id->vendor = pci_get_word(dev->config + PCI_VENDOR_ID); 1739 info->id->device = pci_get_word(dev->config + PCI_DEVICE_ID); 1740 info->regions = qmp_query_pci_regions(dev); 1741 info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : ""); 1742 1743 if (dev->config[PCI_INTERRUPT_PIN] != 0) { 1744 info->has_irq = true; 1745 info->irq = dev->config[PCI_INTERRUPT_LINE]; 1746 } 1747 1748 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 1749 if (type == PCI_HEADER_TYPE_BRIDGE) { 1750 info->has_pci_bridge = true; 1751 info->pci_bridge = qmp_query_pci_bridge(dev, bus, bus_num); 1752 } else if (type == PCI_HEADER_TYPE_NORMAL) { 1753 info->id->has_subsystem = info->id->has_subsystem_vendor = true; 1754 info->id->subsystem = pci_get_word(dev->config + PCI_SUBSYSTEM_ID); 1755 info->id->subsystem_vendor = 1756 pci_get_word(dev->config + PCI_SUBSYSTEM_VENDOR_ID); 1757 } else if (type == PCI_HEADER_TYPE_CARDBUS) { 1758 info->id->has_subsystem = info->id->has_subsystem_vendor = true; 1759 info->id->subsystem = pci_get_word(dev->config + PCI_CB_SUBSYSTEM_ID); 1760 info->id->subsystem_vendor = 1761 pci_get_word(dev->config + PCI_CB_SUBSYSTEM_VENDOR_ID); 1762 } 1763 1764 return info; 1765 } 1766 1767 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num) 1768 { 1769 PciDeviceInfoList *info, *head = NULL, *cur_item = NULL; 1770 PCIDevice *dev; 1771 int devfn; 1772 1773 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1774 dev = bus->devices[devfn]; 1775 if (dev) { 1776 info = g_malloc0(sizeof(*info)); 1777 info->value = qmp_query_pci_device(dev, bus, bus_num); 1778 1779 /* XXX: waiting for the qapi to support GSList */ 1780 if (!cur_item) { 1781 head = cur_item = info; 1782 } else { 1783 cur_item->next = info; 1784 cur_item = info; 1785 } 1786 } 1787 } 1788 1789 return head; 1790 } 1791 1792 static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num) 1793 { 1794 PciInfo *info = NULL; 1795 1796 bus = pci_find_bus_nr(bus, bus_num); 1797 if (bus) { 1798 info = g_malloc0(sizeof(*info)); 1799 info->bus = bus_num; 1800 info->devices = qmp_query_pci_devices(bus, bus_num); 1801 } 1802 1803 return info; 1804 } 1805 1806 PciInfoList *qmp_query_pci(Error **errp) 1807 { 1808 PciInfoList *info, *head = NULL, *cur_item = NULL; 1809 PCIHostState *host_bridge; 1810 1811 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { 1812 info = g_malloc0(sizeof(*info)); 1813 info->value = qmp_query_pci_bus(host_bridge->bus, 1814 pci_bus_num(host_bridge->bus)); 1815 1816 /* XXX: waiting for the qapi to support GSList */ 1817 if (!cur_item) { 1818 head = cur_item = info; 1819 } else { 1820 cur_item->next = info; 1821 cur_item = info; 1822 } 1823 } 1824 1825 return head; 1826 } 1827 1828 /* Initialize a PCI NIC. */ 1829 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus, 1830 const char *default_model, 1831 const char *default_devaddr) 1832 { 1833 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr; 1834 GSList *list; 1835 GPtrArray *pci_nic_models; 1836 PCIBus *bus; 1837 PCIDevice *pci_dev; 1838 DeviceState *dev; 1839 int devfn; 1840 int i; 1841 1842 if (nd->model && !strcmp(nd->model, "virtio")) { 1843 g_free(nd->model); 1844 nd->model = g_strdup("virtio-net-pci"); 1845 } 1846 1847 list = object_class_get_list_sorted(TYPE_PCI_DEVICE, false); 1848 pci_nic_models = g_ptr_array_new(); 1849 while (list) { 1850 DeviceClass *dc = OBJECT_CLASS_CHECK(DeviceClass, list->data, 1851 TYPE_DEVICE); 1852 GSList *next; 1853 if (test_bit(DEVICE_CATEGORY_NETWORK, dc->categories) && 1854 dc->user_creatable) { 1855 const char *name = object_class_get_name(list->data); 1856 g_ptr_array_add(pci_nic_models, (gpointer)name); 1857 } 1858 next = list->next; 1859 g_slist_free_1(list); 1860 list = next; 1861 } 1862 g_ptr_array_add(pci_nic_models, NULL); 1863 1864 if (qemu_show_nic_models(nd->model, (const char **)pci_nic_models->pdata)) { 1865 exit(0); 1866 } 1867 1868 i = qemu_find_nic_model(nd, (const char **)pci_nic_models->pdata, 1869 default_model); 1870 if (i < 0) { 1871 exit(1); 1872 } 1873 1874 bus = pci_get_bus_devfn(&devfn, rootbus, devaddr); 1875 if (!bus) { 1876 error_report("Invalid PCI device address %s for device %s", 1877 devaddr, nd->model); 1878 exit(1); 1879 } 1880 1881 pci_dev = pci_create(bus, devfn, nd->model); 1882 dev = &pci_dev->qdev; 1883 qdev_set_nic_properties(dev, nd); 1884 qdev_init_nofail(dev); 1885 g_ptr_array_free(pci_nic_models, true); 1886 return pci_dev; 1887 } 1888 1889 PCIDevice *pci_vga_init(PCIBus *bus) 1890 { 1891 switch (vga_interface_type) { 1892 case VGA_CIRRUS: 1893 return pci_create_simple(bus, -1, "cirrus-vga"); 1894 case VGA_QXL: 1895 return pci_create_simple(bus, -1, "qxl-vga"); 1896 case VGA_STD: 1897 return pci_create_simple(bus, -1, "VGA"); 1898 case VGA_VMWARE: 1899 return pci_create_simple(bus, -1, "vmware-svga"); 1900 case VGA_VIRTIO: 1901 return pci_create_simple(bus, -1, "virtio-vga"); 1902 case VGA_NONE: 1903 default: /* Other non-PCI types. Checking for unsupported types is already 1904 done in vl.c. */ 1905 return NULL; 1906 } 1907 } 1908 1909 /* Whether a given bus number is in range of the secondary 1910 * bus of the given bridge device. */ 1911 static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num) 1912 { 1913 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) & 1914 PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ && 1915 dev->config[PCI_SECONDARY_BUS] <= bus_num && 1916 bus_num <= dev->config[PCI_SUBORDINATE_BUS]; 1917 } 1918 1919 /* Whether a given bus number is in a range of a root bus */ 1920 static bool pci_root_bus_in_range(PCIBus *bus, int bus_num) 1921 { 1922 int i; 1923 1924 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 1925 PCIDevice *dev = bus->devices[i]; 1926 1927 if (dev && PCI_DEVICE_GET_CLASS(dev)->is_bridge) { 1928 if (pci_secondary_bus_in_range(dev, bus_num)) { 1929 return true; 1930 } 1931 } 1932 } 1933 1934 return false; 1935 } 1936 1937 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num) 1938 { 1939 PCIBus *sec; 1940 1941 if (!bus) { 1942 return NULL; 1943 } 1944 1945 if (pci_bus_num(bus) == bus_num) { 1946 return bus; 1947 } 1948 1949 /* Consider all bus numbers in range for the host pci bridge. */ 1950 if (!pci_bus_is_root(bus) && 1951 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) { 1952 return NULL; 1953 } 1954 1955 /* try child bus */ 1956 for (; bus; bus = sec) { 1957 QLIST_FOREACH(sec, &bus->child, sibling) { 1958 if (pci_bus_num(sec) == bus_num) { 1959 return sec; 1960 } 1961 /* PXB buses assumed to be children of bus 0 */ 1962 if (pci_bus_is_root(sec)) { 1963 if (pci_root_bus_in_range(sec, bus_num)) { 1964 break; 1965 } 1966 } else { 1967 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) { 1968 break; 1969 } 1970 } 1971 } 1972 } 1973 1974 return NULL; 1975 } 1976 1977 void pci_for_each_bus_depth_first(PCIBus *bus, 1978 void *(*begin)(PCIBus *bus, void *parent_state), 1979 void (*end)(PCIBus *bus, void *state), 1980 void *parent_state) 1981 { 1982 PCIBus *sec; 1983 void *state; 1984 1985 if (!bus) { 1986 return; 1987 } 1988 1989 if (begin) { 1990 state = begin(bus, parent_state); 1991 } else { 1992 state = parent_state; 1993 } 1994 1995 QLIST_FOREACH(sec, &bus->child, sibling) { 1996 pci_for_each_bus_depth_first(sec, begin, end, state); 1997 } 1998 1999 if (end) { 2000 end(bus, state); 2001 } 2002 } 2003 2004 2005 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn) 2006 { 2007 bus = pci_find_bus_nr(bus, bus_num); 2008 2009 if (!bus) 2010 return NULL; 2011 2012 return bus->devices[devfn]; 2013 } 2014 2015 static void pci_qdev_realize(DeviceState *qdev, Error **errp) 2016 { 2017 PCIDevice *pci_dev = (PCIDevice *)qdev; 2018 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 2019 ObjectClass *klass = OBJECT_CLASS(pc); 2020 Error *local_err = NULL; 2021 bool is_default_rom; 2022 2023 /* initialize cap_present for pci_is_express() and pci_config_size(), 2024 * Note that hybrid PCIs are not set automatically and need to manage 2025 * QEMU_PCI_CAP_EXPRESS manually */ 2026 if (object_class_dynamic_cast(klass, INTERFACE_PCIE_DEVICE) && 2027 !object_class_dynamic_cast(klass, INTERFACE_CONVENTIONAL_PCI_DEVICE)) { 2028 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; 2029 } 2030 2031 pci_dev = do_pci_register_device(pci_dev, 2032 object_get_typename(OBJECT(qdev)), 2033 pci_dev->devfn, errp); 2034 if (pci_dev == NULL) 2035 return; 2036 2037 if (pc->realize) { 2038 pc->realize(pci_dev, &local_err); 2039 if (local_err) { 2040 error_propagate(errp, local_err); 2041 do_pci_unregister_device(pci_dev); 2042 return; 2043 } 2044 } 2045 2046 /* rom loading */ 2047 is_default_rom = false; 2048 if (pci_dev->romfile == NULL && pc->romfile != NULL) { 2049 pci_dev->romfile = g_strdup(pc->romfile); 2050 is_default_rom = true; 2051 } 2052 2053 pci_add_option_rom(pci_dev, is_default_rom, &local_err); 2054 if (local_err) { 2055 error_propagate(errp, local_err); 2056 pci_qdev_unrealize(DEVICE(pci_dev), NULL); 2057 return; 2058 } 2059 } 2060 2061 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction, 2062 const char *name) 2063 { 2064 DeviceState *dev; 2065 2066 dev = qdev_create(&bus->qbus, name); 2067 qdev_prop_set_int32(dev, "addr", devfn); 2068 qdev_prop_set_bit(dev, "multifunction", multifunction); 2069 return PCI_DEVICE(dev); 2070 } 2071 2072 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, 2073 bool multifunction, 2074 const char *name) 2075 { 2076 PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name); 2077 qdev_init_nofail(&dev->qdev); 2078 return dev; 2079 } 2080 2081 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name) 2082 { 2083 return pci_create_multifunction(bus, devfn, false, name); 2084 } 2085 2086 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name) 2087 { 2088 return pci_create_simple_multifunction(bus, devfn, false, name); 2089 } 2090 2091 static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size) 2092 { 2093 int offset = PCI_CONFIG_HEADER_SIZE; 2094 int i; 2095 for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) { 2096 if (pdev->used[i]) 2097 offset = i + 1; 2098 else if (i - offset + 1 == size) 2099 return offset; 2100 } 2101 return 0; 2102 } 2103 2104 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id, 2105 uint8_t *prev_p) 2106 { 2107 uint8_t next, prev; 2108 2109 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST)) 2110 return 0; 2111 2112 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); 2113 prev = next + PCI_CAP_LIST_NEXT) 2114 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id) 2115 break; 2116 2117 if (prev_p) 2118 *prev_p = prev; 2119 return next; 2120 } 2121 2122 static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset) 2123 { 2124 uint8_t next, prev, found = 0; 2125 2126 if (!(pdev->used[offset])) { 2127 return 0; 2128 } 2129 2130 assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST); 2131 2132 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); 2133 prev = next + PCI_CAP_LIST_NEXT) { 2134 if (next <= offset && next > found) { 2135 found = next; 2136 } 2137 } 2138 return found; 2139 } 2140 2141 /* Patch the PCI vendor and device ids in a PCI rom image if necessary. 2142 This is needed for an option rom which is used for more than one device. */ 2143 static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size) 2144 { 2145 uint16_t vendor_id; 2146 uint16_t device_id; 2147 uint16_t rom_vendor_id; 2148 uint16_t rom_device_id; 2149 uint16_t rom_magic; 2150 uint16_t pcir_offset; 2151 uint8_t checksum; 2152 2153 /* Words in rom data are little endian (like in PCI configuration), 2154 so they can be read / written with pci_get_word / pci_set_word. */ 2155 2156 /* Only a valid rom will be patched. */ 2157 rom_magic = pci_get_word(ptr); 2158 if (rom_magic != 0xaa55) { 2159 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic); 2160 return; 2161 } 2162 pcir_offset = pci_get_word(ptr + 0x18); 2163 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) { 2164 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset); 2165 return; 2166 } 2167 2168 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID); 2169 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID); 2170 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4); 2171 rom_device_id = pci_get_word(ptr + pcir_offset + 6); 2172 2173 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile, 2174 vendor_id, device_id, rom_vendor_id, rom_device_id); 2175 2176 checksum = ptr[6]; 2177 2178 if (vendor_id != rom_vendor_id) { 2179 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */ 2180 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8); 2181 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8); 2182 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); 2183 ptr[6] = checksum; 2184 pci_set_word(ptr + pcir_offset + 4, vendor_id); 2185 } 2186 2187 if (device_id != rom_device_id) { 2188 /* Patch device id and checksum (at offset 6 for etherboot roms). */ 2189 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8); 2190 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8); 2191 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); 2192 ptr[6] = checksum; 2193 pci_set_word(ptr + pcir_offset + 6, device_id); 2194 } 2195 } 2196 2197 /* Add an option rom for the device */ 2198 static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, 2199 Error **errp) 2200 { 2201 int size; 2202 char *path; 2203 void *ptr; 2204 char name[32]; 2205 const VMStateDescription *vmsd; 2206 2207 if (!pdev->romfile) 2208 return; 2209 if (strlen(pdev->romfile) == 0) 2210 return; 2211 2212 if (!pdev->rom_bar) { 2213 /* 2214 * Load rom via fw_cfg instead of creating a rom bar, 2215 * for 0.11 compatibility. 2216 */ 2217 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE); 2218 2219 /* 2220 * Hot-plugged devices can't use the option ROM 2221 * if the rom bar is disabled. 2222 */ 2223 if (DEVICE(pdev)->hotplugged) { 2224 error_setg(errp, "Hot-plugged device without ROM bar" 2225 " can't have an option ROM"); 2226 return; 2227 } 2228 2229 if (class == 0x0300) { 2230 rom_add_vga(pdev->romfile); 2231 } else { 2232 rom_add_option(pdev->romfile, -1); 2233 } 2234 return; 2235 } 2236 2237 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile); 2238 if (path == NULL) { 2239 path = g_strdup(pdev->romfile); 2240 } 2241 2242 size = get_image_size(path); 2243 if (size < 0) { 2244 error_setg(errp, "failed to find romfile \"%s\"", pdev->romfile); 2245 g_free(path); 2246 return; 2247 } else if (size == 0) { 2248 error_setg(errp, "romfile \"%s\" is empty", pdev->romfile); 2249 g_free(path); 2250 return; 2251 } 2252 size = pow2ceil(size); 2253 2254 vmsd = qdev_get_vmsd(DEVICE(pdev)); 2255 2256 if (vmsd) { 2257 snprintf(name, sizeof(name), "%s.rom", vmsd->name); 2258 } else { 2259 snprintf(name, sizeof(name), "%s.rom", object_get_typename(OBJECT(pdev))); 2260 } 2261 pdev->has_rom = true; 2262 memory_region_init_rom(&pdev->rom, OBJECT(pdev), name, size, &error_fatal); 2263 ptr = memory_region_get_ram_ptr(&pdev->rom); 2264 load_image(path, ptr); 2265 g_free(path); 2266 2267 if (is_default_rom) { 2268 /* Only the default rom images will be patched (if needed). */ 2269 pci_patch_ids(pdev, ptr, size); 2270 } 2271 2272 pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom); 2273 } 2274 2275 static void pci_del_option_rom(PCIDevice *pdev) 2276 { 2277 if (!pdev->has_rom) 2278 return; 2279 2280 vmstate_unregister_ram(&pdev->rom, &pdev->qdev); 2281 pdev->has_rom = false; 2282 } 2283 2284 /* 2285 * On success, pci_add_capability() returns a positive value 2286 * that the offset of the pci capability. 2287 * On failure, it sets an error and returns a negative error 2288 * code. 2289 */ 2290 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, 2291 uint8_t offset, uint8_t size, 2292 Error **errp) 2293 { 2294 uint8_t *config; 2295 int i, overlapping_cap; 2296 2297 if (!offset) { 2298 offset = pci_find_space(pdev, size); 2299 /* out of PCI config space is programming error */ 2300 assert(offset); 2301 } else { 2302 /* Verify that capabilities don't overlap. Note: device assignment 2303 * depends on this check to verify that the device is not broken. 2304 * Should never trigger for emulated devices, but it's helpful 2305 * for debugging these. */ 2306 for (i = offset; i < offset + size; i++) { 2307 overlapping_cap = pci_find_capability_at_offset(pdev, i); 2308 if (overlapping_cap) { 2309 error_setg(errp, "%s:%02x:%02x.%x " 2310 "Attempt to add PCI capability %x at offset " 2311 "%x overlaps existing capability %x at offset %x", 2312 pci_root_bus_path(pdev), pci_dev_bus_num(pdev), 2313 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), 2314 cap_id, offset, overlapping_cap, i); 2315 return -EINVAL; 2316 } 2317 } 2318 } 2319 2320 config = pdev->config + offset; 2321 config[PCI_CAP_LIST_ID] = cap_id; 2322 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST]; 2323 pdev->config[PCI_CAPABILITY_LIST] = offset; 2324 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST; 2325 memset(pdev->used + offset, 0xFF, QEMU_ALIGN_UP(size, 4)); 2326 /* Make capability read-only by default */ 2327 memset(pdev->wmask + offset, 0, size); 2328 /* Check capability by default */ 2329 memset(pdev->cmask + offset, 0xFF, size); 2330 return offset; 2331 } 2332 2333 /* Unlink capability from the pci config space. */ 2334 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size) 2335 { 2336 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev); 2337 if (!offset) 2338 return; 2339 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT]; 2340 /* Make capability writable again */ 2341 memset(pdev->wmask + offset, 0xff, size); 2342 memset(pdev->w1cmask + offset, 0, size); 2343 /* Clear cmask as device-specific registers can't be checked */ 2344 memset(pdev->cmask + offset, 0, size); 2345 memset(pdev->used + offset, 0, QEMU_ALIGN_UP(size, 4)); 2346 2347 if (!pdev->config[PCI_CAPABILITY_LIST]) 2348 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST; 2349 } 2350 2351 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id) 2352 { 2353 return pci_find_capability_list(pdev, cap_id, NULL); 2354 } 2355 2356 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent) 2357 { 2358 PCIDevice *d = (PCIDevice *)dev; 2359 const pci_class_desc *desc; 2360 char ctxt[64]; 2361 PCIIORegion *r; 2362 int i, class; 2363 2364 class = pci_get_word(d->config + PCI_CLASS_DEVICE); 2365 desc = pci_class_descriptions; 2366 while (desc->desc && class != desc->class) 2367 desc++; 2368 if (desc->desc) { 2369 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc); 2370 } else { 2371 snprintf(ctxt, sizeof(ctxt), "Class %04x", class); 2372 } 2373 2374 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, " 2375 "pci id %04x:%04x (sub %04x:%04x)\n", 2376 indent, "", ctxt, pci_dev_bus_num(d), 2377 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn), 2378 pci_get_word(d->config + PCI_VENDOR_ID), 2379 pci_get_word(d->config + PCI_DEVICE_ID), 2380 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID), 2381 pci_get_word(d->config + PCI_SUBSYSTEM_ID)); 2382 for (i = 0; i < PCI_NUM_REGIONS; i++) { 2383 r = &d->io_regions[i]; 2384 if (!r->size) 2385 continue; 2386 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS 2387 " [0x%"FMT_PCIBUS"]\n", 2388 indent, "", 2389 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem", 2390 r->addr, r->addr + r->size - 1); 2391 } 2392 } 2393 2394 static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len) 2395 { 2396 PCIDevice *d = (PCIDevice *)dev; 2397 const char *name = NULL; 2398 const pci_class_desc *desc = pci_class_descriptions; 2399 int class = pci_get_word(d->config + PCI_CLASS_DEVICE); 2400 2401 while (desc->desc && 2402 (class & ~desc->fw_ign_bits) != 2403 (desc->class & ~desc->fw_ign_bits)) { 2404 desc++; 2405 } 2406 2407 if (desc->desc) { 2408 name = desc->fw_name; 2409 } 2410 2411 if (name) { 2412 pstrcpy(buf, len, name); 2413 } else { 2414 snprintf(buf, len, "pci%04x,%04x", 2415 pci_get_word(d->config + PCI_VENDOR_ID), 2416 pci_get_word(d->config + PCI_DEVICE_ID)); 2417 } 2418 2419 return buf; 2420 } 2421 2422 static char *pcibus_get_fw_dev_path(DeviceState *dev) 2423 { 2424 PCIDevice *d = (PCIDevice *)dev; 2425 char path[50], name[33]; 2426 int off; 2427 2428 off = snprintf(path, sizeof(path), "%s@%x", 2429 pci_dev_fw_name(dev, name, sizeof name), 2430 PCI_SLOT(d->devfn)); 2431 if (PCI_FUNC(d->devfn)) 2432 snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn)); 2433 return g_strdup(path); 2434 } 2435 2436 static char *pcibus_get_dev_path(DeviceState *dev) 2437 { 2438 PCIDevice *d = container_of(dev, PCIDevice, qdev); 2439 PCIDevice *t; 2440 int slot_depth; 2441 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function. 2442 * 00 is added here to make this format compatible with 2443 * domain:Bus:Slot.Func for systems without nested PCI bridges. 2444 * Slot.Function list specifies the slot and function numbers for all 2445 * devices on the path from root to the specific device. */ 2446 const char *root_bus_path; 2447 int root_bus_len; 2448 char slot[] = ":SS.F"; 2449 int slot_len = sizeof slot - 1 /* For '\0' */; 2450 int path_len; 2451 char *path, *p; 2452 int s; 2453 2454 root_bus_path = pci_root_bus_path(d); 2455 root_bus_len = strlen(root_bus_path); 2456 2457 /* Calculate # of slots on path between device and root. */; 2458 slot_depth = 0; 2459 for (t = d; t; t = pci_get_bus(t)->parent_dev) { 2460 ++slot_depth; 2461 } 2462 2463 path_len = root_bus_len + slot_len * slot_depth; 2464 2465 /* Allocate memory, fill in the terminating null byte. */ 2466 path = g_malloc(path_len + 1 /* For '\0' */); 2467 path[path_len] = '\0'; 2468 2469 memcpy(path, root_bus_path, root_bus_len); 2470 2471 /* Fill in slot numbers. We walk up from device to root, so need to print 2472 * them in the reverse order, last to first. */ 2473 p = path + path_len; 2474 for (t = d; t; t = pci_get_bus(t)->parent_dev) { 2475 p -= slot_len; 2476 s = snprintf(slot, sizeof slot, ":%02x.%x", 2477 PCI_SLOT(t->devfn), PCI_FUNC(t->devfn)); 2478 assert(s == slot_len); 2479 memcpy(p, slot, slot_len); 2480 } 2481 2482 return path; 2483 } 2484 2485 static int pci_qdev_find_recursive(PCIBus *bus, 2486 const char *id, PCIDevice **pdev) 2487 { 2488 DeviceState *qdev = qdev_find_recursive(&bus->qbus, id); 2489 if (!qdev) { 2490 return -ENODEV; 2491 } 2492 2493 /* roughly check if given qdev is pci device */ 2494 if (object_dynamic_cast(OBJECT(qdev), TYPE_PCI_DEVICE)) { 2495 *pdev = PCI_DEVICE(qdev); 2496 return 0; 2497 } 2498 return -EINVAL; 2499 } 2500 2501 int pci_qdev_find_device(const char *id, PCIDevice **pdev) 2502 { 2503 PCIHostState *host_bridge; 2504 int rc = -ENODEV; 2505 2506 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { 2507 int tmp = pci_qdev_find_recursive(host_bridge->bus, id, pdev); 2508 if (!tmp) { 2509 rc = 0; 2510 break; 2511 } 2512 if (tmp != -ENODEV) { 2513 rc = tmp; 2514 } 2515 } 2516 2517 return rc; 2518 } 2519 2520 MemoryRegion *pci_address_space(PCIDevice *dev) 2521 { 2522 return pci_get_bus(dev)->address_space_mem; 2523 } 2524 2525 MemoryRegion *pci_address_space_io(PCIDevice *dev) 2526 { 2527 return pci_get_bus(dev)->address_space_io; 2528 } 2529 2530 static void pci_device_class_init(ObjectClass *klass, void *data) 2531 { 2532 DeviceClass *k = DEVICE_CLASS(klass); 2533 2534 k->realize = pci_qdev_realize; 2535 k->unrealize = pci_qdev_unrealize; 2536 k->bus_type = TYPE_PCI_BUS; 2537 k->props = pci_props; 2538 } 2539 2540 static void pci_device_class_base_init(ObjectClass *klass, void *data) 2541 { 2542 if (!object_class_is_abstract(klass)) { 2543 ObjectClass *conventional = 2544 object_class_dynamic_cast(klass, INTERFACE_CONVENTIONAL_PCI_DEVICE); 2545 ObjectClass *pcie = 2546 object_class_dynamic_cast(klass, INTERFACE_PCIE_DEVICE); 2547 assert(conventional || pcie); 2548 } 2549 } 2550 2551 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev) 2552 { 2553 PCIBus *bus = pci_get_bus(dev); 2554 PCIBus *iommu_bus = bus; 2555 2556 while(iommu_bus && !iommu_bus->iommu_fn && iommu_bus->parent_dev) { 2557 iommu_bus = pci_get_bus(iommu_bus->parent_dev); 2558 } 2559 if (iommu_bus && iommu_bus->iommu_fn) { 2560 return iommu_bus->iommu_fn(bus, iommu_bus->iommu_opaque, dev->devfn); 2561 } 2562 return &address_space_memory; 2563 } 2564 2565 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque) 2566 { 2567 bus->iommu_fn = fn; 2568 bus->iommu_opaque = opaque; 2569 } 2570 2571 static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque) 2572 { 2573 Range *range = opaque; 2574 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 2575 uint16_t cmd = pci_get_word(dev->config + PCI_COMMAND); 2576 int i; 2577 2578 if (!(cmd & PCI_COMMAND_MEMORY)) { 2579 return; 2580 } 2581 2582 if (pc->is_bridge) { 2583 pcibus_t base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 2584 pcibus_t limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 2585 2586 base = MAX(base, 0x1ULL << 32); 2587 2588 if (limit >= base) { 2589 Range pref_range; 2590 range_set_bounds(&pref_range, base, limit); 2591 range_extend(range, &pref_range); 2592 } 2593 } 2594 for (i = 0; i < PCI_NUM_REGIONS; ++i) { 2595 PCIIORegion *r = &dev->io_regions[i]; 2596 pcibus_t lob, upb; 2597 Range region_range; 2598 2599 if (!r->size || 2600 (r->type & PCI_BASE_ADDRESS_SPACE_IO) || 2601 !(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64)) { 2602 continue; 2603 } 2604 2605 lob = pci_bar_address(dev, i, r->type, r->size); 2606 upb = lob + r->size - 1; 2607 if (lob == PCI_BAR_UNMAPPED) { 2608 continue; 2609 } 2610 2611 lob = MAX(lob, 0x1ULL << 32); 2612 2613 if (upb >= lob) { 2614 range_set_bounds(®ion_range, lob, upb); 2615 range_extend(range, ®ion_range); 2616 } 2617 } 2618 } 2619 2620 void pci_bus_get_w64_range(PCIBus *bus, Range *range) 2621 { 2622 range_make_empty(range); 2623 pci_for_each_device_under_bus(bus, pci_dev_get_w64, range); 2624 } 2625 2626 static bool pcie_has_upstream_port(PCIDevice *dev) 2627 { 2628 PCIDevice *parent_dev = pci_bridge_get_device(pci_get_bus(dev)); 2629 2630 /* Device associated with an upstream port. 2631 * As there are several types of these, it's easier to check the 2632 * parent device: upstream ports are always connected to 2633 * root or downstream ports. 2634 */ 2635 return parent_dev && 2636 pci_is_express(parent_dev) && 2637 parent_dev->exp.exp_cap && 2638 (pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_ROOT_PORT || 2639 pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_DOWNSTREAM); 2640 } 2641 2642 PCIDevice *pci_get_function_0(PCIDevice *pci_dev) 2643 { 2644 PCIBus *bus = pci_get_bus(pci_dev); 2645 2646 if(pcie_has_upstream_port(pci_dev)) { 2647 /* With an upstream PCIe port, we only support 1 device at slot 0 */ 2648 return bus->devices[0]; 2649 } else { 2650 /* Other bus types might support multiple devices at slots 0-31 */ 2651 return bus->devices[PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 0)]; 2652 } 2653 } 2654 2655 MSIMessage pci_get_msi_message(PCIDevice *dev, int vector) 2656 { 2657 MSIMessage msg; 2658 if (msix_enabled(dev)) { 2659 msg = msix_get_message(dev, vector); 2660 } else if (msi_enabled(dev)) { 2661 msg = msi_get_message(dev, vector); 2662 } else { 2663 /* Should never happen */ 2664 error_report("%s: unknown interrupt type", __func__); 2665 abort(); 2666 } 2667 return msg; 2668 } 2669 2670 static const TypeInfo pci_device_type_info = { 2671 .name = TYPE_PCI_DEVICE, 2672 .parent = TYPE_DEVICE, 2673 .instance_size = sizeof(PCIDevice), 2674 .abstract = true, 2675 .class_size = sizeof(PCIDeviceClass), 2676 .class_init = pci_device_class_init, 2677 .class_base_init = pci_device_class_base_init, 2678 }; 2679 2680 static void pci_register_types(void) 2681 { 2682 type_register_static(&pci_bus_info); 2683 type_register_static(&pcie_bus_info); 2684 type_register_static(&conventional_pci_interface_info); 2685 type_register_static(&pcie_interface_info); 2686 type_register_static(&pci_device_type_info); 2687 } 2688 2689 type_init(pci_register_types) 2690