1 /*
2 * HMP commands related to PCI
3 *
4 * Copyright IBM, Corp. 2011
5 *
6 * Authors:
7 * Anthony Liguori <aliguori@us.ibm.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
11 *
12 * Contributions after 2012-01-13 are licensed under the terms of the
13 * GNU GPL, version 2 or (at your option) any later version.
14 */
15
16 #include "qemu/osdep.h"
17 #include "hw/pci/pci.h"
18 #include "hw/pci/pci_device.h"
19 #include "monitor/hmp.h"
20 #include "monitor/monitor.h"
21 #include "pci-internal.h"
22 #include "qapi/error.h"
23 #include "qapi/qmp/qdict.h"
24 #include "qapi/qapi-commands-pci.h"
25 #include "qemu/cutils.h"
26
hmp_info_pci_device(Monitor * mon,const PciDeviceInfo * dev)27 static void hmp_info_pci_device(Monitor *mon, const PciDeviceInfo *dev)
28 {
29 PciMemoryRegionList *region;
30
31 monitor_printf(mon, " Bus %2" PRId64 ", ", dev->bus);
32 monitor_printf(mon, "device %3" PRId64 ", function %" PRId64 ":\n",
33 dev->slot, dev->function);
34 monitor_printf(mon, " ");
35
36 if (dev->class_info->desc) {
37 monitor_puts(mon, dev->class_info->desc);
38 } else {
39 monitor_printf(mon, "Class %04" PRId64, dev->class_info->q_class);
40 }
41
42 monitor_printf(mon, ": PCI device %04" PRIx64 ":%04" PRIx64 "\n",
43 dev->id->vendor, dev->id->device);
44 if (dev->id->has_subsystem_vendor && dev->id->has_subsystem) {
45 monitor_printf(mon, " PCI subsystem %04" PRIx64 ":%04" PRIx64 "\n",
46 dev->id->subsystem_vendor, dev->id->subsystem);
47 }
48
49 if (dev->has_irq) {
50 monitor_printf(mon, " IRQ %" PRId64 ", pin %c\n",
51 dev->irq, (char)('A' + dev->irq_pin - 1));
52 }
53
54 if (dev->pci_bridge) {
55 monitor_printf(mon, " BUS %" PRId64 ".\n",
56 dev->pci_bridge->bus->number);
57 monitor_printf(mon, " secondary bus %" PRId64 ".\n",
58 dev->pci_bridge->bus->secondary);
59 monitor_printf(mon, " subordinate bus %" PRId64 ".\n",
60 dev->pci_bridge->bus->subordinate);
61
62 monitor_printf(mon, " IO range [0x%04"PRIx64", 0x%04"PRIx64"]\n",
63 dev->pci_bridge->bus->io_range->base,
64 dev->pci_bridge->bus->io_range->limit);
65
66 monitor_printf(mon,
67 " memory range [0x%08"PRIx64", 0x%08"PRIx64"]\n",
68 dev->pci_bridge->bus->memory_range->base,
69 dev->pci_bridge->bus->memory_range->limit);
70
71 monitor_printf(mon, " prefetchable memory range "
72 "[0x%08"PRIx64", 0x%08"PRIx64"]\n",
73 dev->pci_bridge->bus->prefetchable_range->base,
74 dev->pci_bridge->bus->prefetchable_range->limit);
75 }
76
77 for (region = dev->regions; region; region = region->next) {
78 uint64_t addr, size;
79
80 addr = region->value->address;
81 size = region->value->size;
82
83 monitor_printf(mon, " BAR%" PRId64 ": ", region->value->bar);
84
85 if (!strcmp(region->value->type, "io")) {
86 if (addr != PCI_BAR_UNMAPPED) {
87 monitor_printf(mon, "I/O at 0x%04" PRIx64
88 " [0x%04" PRIx64 "]\n",
89 addr, addr + size - 1);
90 } else {
91 monitor_printf(mon, "I/O (not mapped)\n");
92 }
93 } else {
94 if (addr != PCI_BAR_UNMAPPED) {
95 monitor_printf(mon, "%d bit%s memory at 0x%08" PRIx64
96 " [0x%08" PRIx64 "]\n",
97 region->value->mem_type_64 ? 64 : 32,
98 region->value->prefetch ? " prefetchable" : "",
99 addr, addr + size - 1);
100 } else {
101 monitor_printf(mon, "%d bit%s memory (not mapped)\n",
102 region->value->mem_type_64 ? 64 : 32,
103 region->value->prefetch ? " prefetchable" : "");
104 }
105 }
106 }
107
108 monitor_printf(mon, " id \"%s\"\n", dev->qdev_id);
109
110 if (dev->pci_bridge) {
111 if (dev->pci_bridge->has_devices) {
112 PciDeviceInfoList *cdev;
113 for (cdev = dev->pci_bridge->devices; cdev; cdev = cdev->next) {
114 hmp_info_pci_device(mon, cdev->value);
115 }
116 }
117 }
118 }
119
hmp_info_pci(Monitor * mon,const QDict * qdict)120 void hmp_info_pci(Monitor *mon, const QDict *qdict)
121 {
122 PciInfoList *info_list, *info;
123
124 info_list = qmp_query_pci(&error_abort);
125
126 for (info = info_list; info; info = info->next) {
127 PciDeviceInfoList *dev;
128
129 for (dev = info->value->devices; dev; dev = dev->next) {
130 hmp_info_pci_device(mon, dev->value);
131 }
132 }
133
134 qapi_free_PciInfoList(info_list);
135 }
136
pcibus_dev_print(Monitor * mon,DeviceState * dev,int indent)137 void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
138 {
139 PCIDevice *d = (PCIDevice *)dev;
140 int class = pci_get_word(d->config + PCI_CLASS_DEVICE);
141 const pci_class_desc *desc = get_class_desc(class);
142 char ctxt[64];
143 PCIIORegion *r;
144 int i;
145
146 if (desc->desc) {
147 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
148 } else {
149 snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
150 }
151
152 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
153 "pci id %04x:%04x (sub %04x:%04x)\n",
154 indent, "", ctxt, pci_dev_bus_num(d),
155 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
156 pci_get_word(d->config + PCI_VENDOR_ID),
157 pci_get_word(d->config + PCI_DEVICE_ID),
158 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
159 pci_get_word(d->config + PCI_SUBSYSTEM_ID));
160 for (i = 0; i < PCI_NUM_REGIONS; i++) {
161 r = &d->io_regions[i];
162 if (!r->size) {
163 continue;
164 }
165 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
166 " [0x%"FMT_PCIBUS"]\n",
167 indent, "",
168 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
169 r->addr, r->addr + r->size - 1);
170 }
171 }
172
hmp_pcie_aer_inject_error(Monitor * mon,const QDict * qdict)173 void hmp_pcie_aer_inject_error(Monitor *mon, const QDict *qdict)
174 {
175 Error *err = NULL;
176 const char *id = qdict_get_str(qdict, "id");
177 const char *error_name;
178 uint32_t error_status;
179 unsigned int num;
180 bool correctable;
181 PCIDevice *dev;
182 PCIEAERErr aer_err;
183 int ret;
184
185 ret = pci_qdev_find_device(id, &dev);
186 if (ret == -ENODEV) {
187 error_setg(&err, "device '%s' not found", id);
188 goto out;
189 }
190 if (ret < 0 || !pci_is_express(dev)) {
191 error_setg(&err, "device '%s' is not a PCIe device", id);
192 goto out;
193 }
194
195 error_name = qdict_get_str(qdict, "error_status");
196 if (pcie_aer_parse_error_string(error_name, &error_status, &correctable)) {
197 if (qemu_strtoui(error_name, NULL, 0, &num) < 0) {
198 error_setg(&err, "invalid error status value '%s'", error_name);
199 goto out;
200 }
201 error_status = num;
202 correctable = qdict_get_try_bool(qdict, "correctable", false);
203 } else {
204 if (qdict_haskey(qdict, "correctable")) {
205 error_setg(&err, "-c is only valid with numeric error status");
206 goto out;
207 }
208 }
209 aer_err.status = error_status;
210 aer_err.source_id = pci_requester_id(dev);
211
212 aer_err.flags = 0;
213 if (correctable) {
214 aer_err.flags |= PCIE_AER_ERR_IS_CORRECTABLE;
215 }
216 if (qdict_get_try_bool(qdict, "advisory_non_fatal", false)) {
217 aer_err.flags |= PCIE_AER_ERR_MAYBE_ADVISORY;
218 }
219 if (qdict_haskey(qdict, "header0")) {
220 aer_err.flags |= PCIE_AER_ERR_HEADER_VALID;
221 }
222 if (qdict_haskey(qdict, "prefix0")) {
223 aer_err.flags |= PCIE_AER_ERR_TLP_PREFIX_PRESENT;
224 }
225
226 aer_err.header[0] = qdict_get_try_int(qdict, "header0", 0);
227 aer_err.header[1] = qdict_get_try_int(qdict, "header1", 0);
228 aer_err.header[2] = qdict_get_try_int(qdict, "header2", 0);
229 aer_err.header[3] = qdict_get_try_int(qdict, "header3", 0);
230
231 aer_err.prefix[0] = qdict_get_try_int(qdict, "prefix0", 0);
232 aer_err.prefix[1] = qdict_get_try_int(qdict, "prefix1", 0);
233 aer_err.prefix[2] = qdict_get_try_int(qdict, "prefix2", 0);
234 aer_err.prefix[3] = qdict_get_try_int(qdict, "prefix3", 0);
235
236 ret = pcie_aer_inject_error(dev, &aer_err);
237 if (ret < 0) {
238 error_setg_errno(&err, -ret, "failed to inject error");
239 goto out;
240 }
241
242
243 monitor_printf(mon, "OK id: %s root bus: %s, bus: %x devfn: %x.%x\n",
244 id, pci_root_bus_path(dev), pci_dev_bus_num(dev),
245 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
246
247 out:
248 hmp_handle_error(mon, err);
249 }
250