1 /* 2 * Xilinx PCIe host controller emulation. 3 * 4 * Copyright (c) 2016 Imagination Technologies 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/units.h" 22 #include "qapi/error.h" 23 #include "hw/pci/pci_bridge.h" 24 #include "hw/pci-host/xilinx-pcie.h" 25 26 enum root_cfg_reg { 27 /* Interrupt Decode Register */ 28 ROOTCFG_INTDEC = 0x138, 29 30 /* Interrupt Mask Register */ 31 ROOTCFG_INTMASK = 0x13c, 32 /* INTx Interrupt Received */ 33 #define ROOTCFG_INTMASK_INTX (1 << 16) 34 /* MSI Interrupt Received */ 35 #define ROOTCFG_INTMASK_MSI (1 << 17) 36 37 /* PHY Status/Control Register */ 38 ROOTCFG_PSCR = 0x144, 39 /* Link Up */ 40 #define ROOTCFG_PSCR_LINK_UP (1 << 11) 41 42 /* Root Port Status/Control Register */ 43 ROOTCFG_RPSCR = 0x148, 44 /* Bridge Enable */ 45 #define ROOTCFG_RPSCR_BRIDGEEN (1 << 0) 46 /* Interrupt FIFO Not Empty */ 47 #define ROOTCFG_RPSCR_INTNEMPTY (1 << 18) 48 /* Interrupt FIFO Overflow */ 49 #define ROOTCFG_RPSCR_INTOVF (1 << 19) 50 51 /* Root Port Interrupt FIFO Read Register 1 */ 52 ROOTCFG_RPIFR1 = 0x158, 53 #define ROOTCFG_RPIFR1_INT_LANE_SHIFT 27 54 #define ROOTCFG_RPIFR1_INT_ASSERT_SHIFT 29 55 #define ROOTCFG_RPIFR1_INT_VALID_SHIFT 31 56 /* Root Port Interrupt FIFO Read Register 2 */ 57 ROOTCFG_RPIFR2 = 0x15c, 58 }; 59 60 static void xilinx_pcie_update_intr(XilinxPCIEHost *s, 61 uint32_t set, uint32_t clear) 62 { 63 int level; 64 65 s->intr |= set; 66 s->intr &= ~clear; 67 68 if (s->intr_fifo_r != s->intr_fifo_w) { 69 s->intr |= ROOTCFG_INTMASK_INTX; 70 } 71 72 level = !!(s->intr & s->intr_mask); 73 qemu_set_irq(s->irq, level); 74 } 75 76 static void xilinx_pcie_queue_intr(XilinxPCIEHost *s, 77 uint32_t fifo_reg1, uint32_t fifo_reg2) 78 { 79 XilinxPCIEInt *intr; 80 unsigned int new_w; 81 82 new_w = (s->intr_fifo_w + 1) % ARRAY_SIZE(s->intr_fifo); 83 if (new_w == s->intr_fifo_r) { 84 s->rpscr |= ROOTCFG_RPSCR_INTOVF; 85 return; 86 } 87 88 intr = &s->intr_fifo[s->intr_fifo_w]; 89 s->intr_fifo_w = new_w; 90 91 intr->fifo_reg1 = fifo_reg1; 92 intr->fifo_reg2 = fifo_reg2; 93 94 xilinx_pcie_update_intr(s, ROOTCFG_INTMASK_INTX, 0); 95 } 96 97 static void xilinx_pcie_set_irq(void *opaque, int irq_num, int level) 98 { 99 XilinxPCIEHost *s = XILINX_PCIE_HOST(opaque); 100 101 xilinx_pcie_queue_intr(s, 102 (irq_num << ROOTCFG_RPIFR1_INT_LANE_SHIFT) | 103 (level << ROOTCFG_RPIFR1_INT_ASSERT_SHIFT) | 104 (1 << ROOTCFG_RPIFR1_INT_VALID_SHIFT), 105 0); 106 } 107 108 static void xilinx_pcie_host_realize(DeviceState *dev, Error **errp) 109 { 110 PCIHostState *pci = PCI_HOST_BRIDGE(dev); 111 XilinxPCIEHost *s = XILINX_PCIE_HOST(dev); 112 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 113 PCIExpressHost *pex = PCIE_HOST_BRIDGE(dev); 114 115 snprintf(s->name, sizeof(s->name), "pcie%u", s->bus_nr); 116 117 /* PCI configuration space */ 118 pcie_host_mmcfg_init(pex, s->cfg_size); 119 120 /* MMIO region */ 121 memory_region_init(&s->mmio, OBJECT(s), "mmio", UINT64_MAX); 122 memory_region_set_enabled(&s->mmio, false); 123 124 /* dummy PCI I/O region (not visible to the CPU) */ 125 memory_region_init(&s->io, OBJECT(s), "io", 16); 126 127 /* interrupt out */ 128 qdev_init_gpio_out_named(dev, &s->irq, "interrupt_out", 1); 129 130 sysbus_init_mmio(sbd, &pex->mmio); 131 sysbus_init_mmio(sbd, &s->mmio); 132 133 pci->bus = pci_register_root_bus(dev, s->name, xilinx_pcie_set_irq, 134 pci_swizzle_map_irq_fn, s, &s->mmio, 135 &s->io, 0, 4, TYPE_PCIE_BUS); 136 137 qdev_set_parent_bus(DEVICE(&s->root), BUS(pci->bus)); 138 qdev_init_nofail(DEVICE(&s->root)); 139 } 140 141 static const char *xilinx_pcie_host_root_bus_path(PCIHostState *host_bridge, 142 PCIBus *rootbus) 143 { 144 return "0000:00"; 145 } 146 147 static void xilinx_pcie_host_init(Object *obj) 148 { 149 XilinxPCIEHost *s = XILINX_PCIE_HOST(obj); 150 XilinxPCIERoot *root = &s->root; 151 152 object_initialize(root, sizeof(*root), TYPE_XILINX_PCIE_ROOT); 153 object_property_add_child(obj, "root", OBJECT(root), NULL); 154 qdev_prop_set_int32(DEVICE(root), "addr", PCI_DEVFN(0, 0)); 155 qdev_prop_set_bit(DEVICE(root), "multifunction", false); 156 } 157 158 static Property xilinx_pcie_host_props[] = { 159 DEFINE_PROP_UINT32("bus_nr", XilinxPCIEHost, bus_nr, 0), 160 DEFINE_PROP_SIZE("cfg_base", XilinxPCIEHost, cfg_base, 0), 161 DEFINE_PROP_SIZE("cfg_size", XilinxPCIEHost, cfg_size, 32 * MiB), 162 DEFINE_PROP_SIZE("mmio_base", XilinxPCIEHost, mmio_base, 0), 163 DEFINE_PROP_SIZE("mmio_size", XilinxPCIEHost, mmio_size, 1 * MiB), 164 DEFINE_PROP_BOOL("link_up", XilinxPCIEHost, link_up, true), 165 DEFINE_PROP_END_OF_LIST(), 166 }; 167 168 static void xilinx_pcie_host_class_init(ObjectClass *klass, void *data) 169 { 170 DeviceClass *dc = DEVICE_CLASS(klass); 171 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); 172 173 hc->root_bus_path = xilinx_pcie_host_root_bus_path; 174 dc->realize = xilinx_pcie_host_realize; 175 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 176 dc->fw_name = "pci"; 177 dc->props = xilinx_pcie_host_props; 178 } 179 180 static const TypeInfo xilinx_pcie_host_info = { 181 .name = TYPE_XILINX_PCIE_HOST, 182 .parent = TYPE_PCIE_HOST_BRIDGE, 183 .instance_size = sizeof(XilinxPCIEHost), 184 .instance_init = xilinx_pcie_host_init, 185 .class_init = xilinx_pcie_host_class_init, 186 }; 187 188 static uint32_t xilinx_pcie_root_config_read(PCIDevice *d, 189 uint32_t address, int len) 190 { 191 XilinxPCIEHost *s = XILINX_PCIE_HOST(OBJECT(d)->parent); 192 uint32_t val; 193 194 switch (address) { 195 case ROOTCFG_INTDEC: 196 val = s->intr; 197 break; 198 case ROOTCFG_INTMASK: 199 val = s->intr_mask; 200 break; 201 case ROOTCFG_PSCR: 202 val = s->link_up ? ROOTCFG_PSCR_LINK_UP : 0; 203 break; 204 case ROOTCFG_RPSCR: 205 if (s->intr_fifo_r != s->intr_fifo_w) { 206 s->rpscr &= ~ROOTCFG_RPSCR_INTNEMPTY; 207 } else { 208 s->rpscr |= ROOTCFG_RPSCR_INTNEMPTY; 209 } 210 val = s->rpscr; 211 break; 212 case ROOTCFG_RPIFR1: 213 if (s->intr_fifo_w == s->intr_fifo_r) { 214 /* FIFO empty */ 215 val = 0; 216 } else { 217 val = s->intr_fifo[s->intr_fifo_r].fifo_reg1; 218 } 219 break; 220 case ROOTCFG_RPIFR2: 221 if (s->intr_fifo_w == s->intr_fifo_r) { 222 /* FIFO empty */ 223 val = 0; 224 } else { 225 val = s->intr_fifo[s->intr_fifo_r].fifo_reg2; 226 } 227 break; 228 default: 229 val = pci_default_read_config(d, address, len); 230 break; 231 } 232 return val; 233 } 234 235 static void xilinx_pcie_root_config_write(PCIDevice *d, uint32_t address, 236 uint32_t val, int len) 237 { 238 XilinxPCIEHost *s = XILINX_PCIE_HOST(OBJECT(d)->parent); 239 switch (address) { 240 case ROOTCFG_INTDEC: 241 xilinx_pcie_update_intr(s, 0, val); 242 break; 243 case ROOTCFG_INTMASK: 244 s->intr_mask = val; 245 xilinx_pcie_update_intr(s, 0, 0); 246 break; 247 case ROOTCFG_RPSCR: 248 s->rpscr &= ~ROOTCFG_RPSCR_BRIDGEEN; 249 s->rpscr |= val & ROOTCFG_RPSCR_BRIDGEEN; 250 memory_region_set_enabled(&s->mmio, val & ROOTCFG_RPSCR_BRIDGEEN); 251 252 if (val & ROOTCFG_INTMASK_INTX) { 253 s->rpscr &= ~ROOTCFG_INTMASK_INTX; 254 } 255 break; 256 case ROOTCFG_RPIFR1: 257 case ROOTCFG_RPIFR2: 258 if (s->intr_fifo_w == s->intr_fifo_r) { 259 /* FIFO empty */ 260 return; 261 } else { 262 s->intr_fifo_r = (s->intr_fifo_r + 1) % ARRAY_SIZE(s->intr_fifo); 263 } 264 break; 265 default: 266 pci_default_write_config(d, address, val, len); 267 break; 268 } 269 } 270 271 static void xilinx_pcie_root_realize(PCIDevice *pci_dev, Error **errp) 272 { 273 BusState *bus = qdev_get_parent_bus(DEVICE(pci_dev)); 274 XilinxPCIEHost *s = XILINX_PCIE_HOST(bus->parent); 275 276 pci_set_word(pci_dev->config + PCI_COMMAND, 277 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 278 pci_set_word(pci_dev->config + PCI_MEMORY_BASE, s->mmio_base >> 16); 279 pci_set_word(pci_dev->config + PCI_MEMORY_LIMIT, 280 ((s->mmio_base + s->mmio_size - 1) >> 16) & 0xfff0); 281 282 pci_bridge_initfn(pci_dev, TYPE_PCI_BUS); 283 284 if (pcie_endpoint_cap_v1_init(pci_dev, 0x80) < 0) { 285 error_setg(errp, "Failed to initialize PCIe capability"); 286 } 287 } 288 289 static void xilinx_pcie_root_class_init(ObjectClass *klass, void *data) 290 { 291 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 292 DeviceClass *dc = DEVICE_CLASS(klass); 293 294 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 295 dc->desc = "Xilinx AXI-PCIe Host Bridge"; 296 k->vendor_id = PCI_VENDOR_ID_XILINX; 297 k->device_id = 0x7021; 298 k->revision = 0; 299 k->class_id = PCI_CLASS_BRIDGE_HOST; 300 k->is_bridge = true; 301 k->realize = xilinx_pcie_root_realize; 302 k->exit = pci_bridge_exitfn; 303 dc->reset = pci_bridge_reset; 304 k->config_read = xilinx_pcie_root_config_read; 305 k->config_write = xilinx_pcie_root_config_write; 306 /* 307 * PCI-facing part of the host bridge, not usable without the 308 * host-facing part, which can't be device_add'ed, yet. 309 */ 310 dc->user_creatable = false; 311 } 312 313 static const TypeInfo xilinx_pcie_root_info = { 314 .name = TYPE_XILINX_PCIE_ROOT, 315 .parent = TYPE_PCI_BRIDGE, 316 .instance_size = sizeof(XilinxPCIERoot), 317 .class_init = xilinx_pcie_root_class_init, 318 .interfaces = (InterfaceInfo[]) { 319 { INTERFACE_PCIE_DEVICE }, 320 { } 321 }, 322 }; 323 324 static void xilinx_pcie_register(void) 325 { 326 type_register_static(&xilinx_pcie_root_info); 327 type_register_static(&xilinx_pcie_host_info); 328 } 329 330 type_init(xilinx_pcie_register) 331