1 /* 2 * Xilinx PCIe host controller emulation. 3 * 4 * Copyright (c) 2016 Imagination Technologies 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/module.h" 22 #include "qemu/units.h" 23 #include "qapi/error.h" 24 #include "hw/pci/pci_bridge.h" 25 #include "hw/irq.h" 26 #include "hw/pci-host/xilinx-pcie.h" 27 28 enum root_cfg_reg { 29 /* Interrupt Decode Register */ 30 ROOTCFG_INTDEC = 0x138, 31 32 /* Interrupt Mask Register */ 33 ROOTCFG_INTMASK = 0x13c, 34 /* INTx Interrupt Received */ 35 #define ROOTCFG_INTMASK_INTX (1 << 16) 36 /* MSI Interrupt Received */ 37 #define ROOTCFG_INTMASK_MSI (1 << 17) 38 39 /* PHY Status/Control Register */ 40 ROOTCFG_PSCR = 0x144, 41 /* Link Up */ 42 #define ROOTCFG_PSCR_LINK_UP (1 << 11) 43 44 /* Root Port Status/Control Register */ 45 ROOTCFG_RPSCR = 0x148, 46 /* Bridge Enable */ 47 #define ROOTCFG_RPSCR_BRIDGEEN (1 << 0) 48 /* Interrupt FIFO Not Empty */ 49 #define ROOTCFG_RPSCR_INTNEMPTY (1 << 18) 50 /* Interrupt FIFO Overflow */ 51 #define ROOTCFG_RPSCR_INTOVF (1 << 19) 52 53 /* Root Port Interrupt FIFO Read Register 1 */ 54 ROOTCFG_RPIFR1 = 0x158, 55 #define ROOTCFG_RPIFR1_INT_LANE_SHIFT 27 56 #define ROOTCFG_RPIFR1_INT_ASSERT_SHIFT 29 57 #define ROOTCFG_RPIFR1_INT_VALID_SHIFT 31 58 /* Root Port Interrupt FIFO Read Register 2 */ 59 ROOTCFG_RPIFR2 = 0x15c, 60 }; 61 62 static void xilinx_pcie_update_intr(XilinxPCIEHost *s, 63 uint32_t set, uint32_t clear) 64 { 65 int level; 66 67 s->intr |= set; 68 s->intr &= ~clear; 69 70 if (s->intr_fifo_r != s->intr_fifo_w) { 71 s->intr |= ROOTCFG_INTMASK_INTX; 72 } 73 74 level = !!(s->intr & s->intr_mask); 75 qemu_set_irq(s->irq, level); 76 } 77 78 static void xilinx_pcie_queue_intr(XilinxPCIEHost *s, 79 uint32_t fifo_reg1, uint32_t fifo_reg2) 80 { 81 XilinxPCIEInt *intr; 82 unsigned int new_w; 83 84 new_w = (s->intr_fifo_w + 1) % ARRAY_SIZE(s->intr_fifo); 85 if (new_w == s->intr_fifo_r) { 86 s->rpscr |= ROOTCFG_RPSCR_INTOVF; 87 return; 88 } 89 90 intr = &s->intr_fifo[s->intr_fifo_w]; 91 s->intr_fifo_w = new_w; 92 93 intr->fifo_reg1 = fifo_reg1; 94 intr->fifo_reg2 = fifo_reg2; 95 96 xilinx_pcie_update_intr(s, ROOTCFG_INTMASK_INTX, 0); 97 } 98 99 static void xilinx_pcie_set_irq(void *opaque, int irq_num, int level) 100 { 101 XilinxPCIEHost *s = XILINX_PCIE_HOST(opaque); 102 103 xilinx_pcie_queue_intr(s, 104 (irq_num << ROOTCFG_RPIFR1_INT_LANE_SHIFT) | 105 (level << ROOTCFG_RPIFR1_INT_ASSERT_SHIFT) | 106 (1 << ROOTCFG_RPIFR1_INT_VALID_SHIFT), 107 0); 108 } 109 110 static void xilinx_pcie_host_realize(DeviceState *dev, Error **errp) 111 { 112 PCIHostState *pci = PCI_HOST_BRIDGE(dev); 113 XilinxPCIEHost *s = XILINX_PCIE_HOST(dev); 114 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 115 PCIExpressHost *pex = PCIE_HOST_BRIDGE(dev); 116 117 snprintf(s->name, sizeof(s->name), "pcie%u", s->bus_nr); 118 119 /* PCI configuration space */ 120 pcie_host_mmcfg_init(pex, s->cfg_size); 121 122 /* MMIO region */ 123 memory_region_init(&s->mmio, OBJECT(s), "mmio", UINT64_MAX); 124 memory_region_set_enabled(&s->mmio, false); 125 126 /* dummy PCI I/O region (not visible to the CPU) */ 127 memory_region_init(&s->io, OBJECT(s), "io", 16); 128 129 /* interrupt out */ 130 qdev_init_gpio_out_named(dev, &s->irq, "interrupt_out", 1); 131 132 sysbus_init_mmio(sbd, &pex->mmio); 133 sysbus_init_mmio(sbd, &s->mmio); 134 135 pci->bus = pci_register_root_bus(dev, s->name, xilinx_pcie_set_irq, 136 pci_swizzle_map_irq_fn, s, &s->mmio, 137 &s->io, 0, 4, TYPE_PCIE_BUS); 138 139 qdev_set_parent_bus(DEVICE(&s->root), BUS(pci->bus)); 140 qdev_init_nofail(DEVICE(&s->root)); 141 } 142 143 static const char *xilinx_pcie_host_root_bus_path(PCIHostState *host_bridge, 144 PCIBus *rootbus) 145 { 146 return "0000:00"; 147 } 148 149 static void xilinx_pcie_host_init(Object *obj) 150 { 151 XilinxPCIEHost *s = XILINX_PCIE_HOST(obj); 152 XilinxPCIERoot *root = &s->root; 153 154 object_initialize_child(obj, "root", root, sizeof(*root), 155 TYPE_XILINX_PCIE_ROOT, &error_abort, NULL); 156 qdev_prop_set_int32(DEVICE(root), "addr", PCI_DEVFN(0, 0)); 157 qdev_prop_set_bit(DEVICE(root), "multifunction", false); 158 } 159 160 static Property xilinx_pcie_host_props[] = { 161 DEFINE_PROP_UINT32("bus_nr", XilinxPCIEHost, bus_nr, 0), 162 DEFINE_PROP_SIZE("cfg_base", XilinxPCIEHost, cfg_base, 0), 163 DEFINE_PROP_SIZE("cfg_size", XilinxPCIEHost, cfg_size, 32 * MiB), 164 DEFINE_PROP_SIZE("mmio_base", XilinxPCIEHost, mmio_base, 0), 165 DEFINE_PROP_SIZE("mmio_size", XilinxPCIEHost, mmio_size, 1 * MiB), 166 DEFINE_PROP_BOOL("link_up", XilinxPCIEHost, link_up, true), 167 DEFINE_PROP_END_OF_LIST(), 168 }; 169 170 static void xilinx_pcie_host_class_init(ObjectClass *klass, void *data) 171 { 172 DeviceClass *dc = DEVICE_CLASS(klass); 173 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); 174 175 hc->root_bus_path = xilinx_pcie_host_root_bus_path; 176 dc->realize = xilinx_pcie_host_realize; 177 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 178 dc->fw_name = "pci"; 179 dc->props = xilinx_pcie_host_props; 180 } 181 182 static const TypeInfo xilinx_pcie_host_info = { 183 .name = TYPE_XILINX_PCIE_HOST, 184 .parent = TYPE_PCIE_HOST_BRIDGE, 185 .instance_size = sizeof(XilinxPCIEHost), 186 .instance_init = xilinx_pcie_host_init, 187 .class_init = xilinx_pcie_host_class_init, 188 }; 189 190 static uint32_t xilinx_pcie_root_config_read(PCIDevice *d, 191 uint32_t address, int len) 192 { 193 XilinxPCIEHost *s = XILINX_PCIE_HOST(OBJECT(d)->parent); 194 uint32_t val; 195 196 switch (address) { 197 case ROOTCFG_INTDEC: 198 val = s->intr; 199 break; 200 case ROOTCFG_INTMASK: 201 val = s->intr_mask; 202 break; 203 case ROOTCFG_PSCR: 204 val = s->link_up ? ROOTCFG_PSCR_LINK_UP : 0; 205 break; 206 case ROOTCFG_RPSCR: 207 if (s->intr_fifo_r != s->intr_fifo_w) { 208 s->rpscr &= ~ROOTCFG_RPSCR_INTNEMPTY; 209 } else { 210 s->rpscr |= ROOTCFG_RPSCR_INTNEMPTY; 211 } 212 val = s->rpscr; 213 break; 214 case ROOTCFG_RPIFR1: 215 if (s->intr_fifo_w == s->intr_fifo_r) { 216 /* FIFO empty */ 217 val = 0; 218 } else { 219 val = s->intr_fifo[s->intr_fifo_r].fifo_reg1; 220 } 221 break; 222 case ROOTCFG_RPIFR2: 223 if (s->intr_fifo_w == s->intr_fifo_r) { 224 /* FIFO empty */ 225 val = 0; 226 } else { 227 val = s->intr_fifo[s->intr_fifo_r].fifo_reg2; 228 } 229 break; 230 default: 231 val = pci_default_read_config(d, address, len); 232 break; 233 } 234 return val; 235 } 236 237 static void xilinx_pcie_root_config_write(PCIDevice *d, uint32_t address, 238 uint32_t val, int len) 239 { 240 XilinxPCIEHost *s = XILINX_PCIE_HOST(OBJECT(d)->parent); 241 switch (address) { 242 case ROOTCFG_INTDEC: 243 xilinx_pcie_update_intr(s, 0, val); 244 break; 245 case ROOTCFG_INTMASK: 246 s->intr_mask = val; 247 xilinx_pcie_update_intr(s, 0, 0); 248 break; 249 case ROOTCFG_RPSCR: 250 s->rpscr &= ~ROOTCFG_RPSCR_BRIDGEEN; 251 s->rpscr |= val & ROOTCFG_RPSCR_BRIDGEEN; 252 memory_region_set_enabled(&s->mmio, val & ROOTCFG_RPSCR_BRIDGEEN); 253 254 if (val & ROOTCFG_INTMASK_INTX) { 255 s->rpscr &= ~ROOTCFG_INTMASK_INTX; 256 } 257 break; 258 case ROOTCFG_RPIFR1: 259 case ROOTCFG_RPIFR2: 260 if (s->intr_fifo_w == s->intr_fifo_r) { 261 /* FIFO empty */ 262 return; 263 } else { 264 s->intr_fifo_r = (s->intr_fifo_r + 1) % ARRAY_SIZE(s->intr_fifo); 265 } 266 break; 267 default: 268 pci_default_write_config(d, address, val, len); 269 break; 270 } 271 } 272 273 static void xilinx_pcie_root_realize(PCIDevice *pci_dev, Error **errp) 274 { 275 BusState *bus = qdev_get_parent_bus(DEVICE(pci_dev)); 276 XilinxPCIEHost *s = XILINX_PCIE_HOST(bus->parent); 277 278 pci_set_word(pci_dev->config + PCI_COMMAND, 279 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 280 pci_set_word(pci_dev->config + PCI_MEMORY_BASE, s->mmio_base >> 16); 281 pci_set_word(pci_dev->config + PCI_MEMORY_LIMIT, 282 ((s->mmio_base + s->mmio_size - 1) >> 16) & 0xfff0); 283 284 pci_bridge_initfn(pci_dev, TYPE_PCI_BUS); 285 286 if (pcie_endpoint_cap_v1_init(pci_dev, 0x80) < 0) { 287 error_setg(errp, "Failed to initialize PCIe capability"); 288 } 289 } 290 291 static void xilinx_pcie_root_class_init(ObjectClass *klass, void *data) 292 { 293 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 294 DeviceClass *dc = DEVICE_CLASS(klass); 295 296 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 297 dc->desc = "Xilinx AXI-PCIe Host Bridge"; 298 k->vendor_id = PCI_VENDOR_ID_XILINX; 299 k->device_id = 0x7021; 300 k->revision = 0; 301 k->class_id = PCI_CLASS_BRIDGE_HOST; 302 k->is_bridge = true; 303 k->realize = xilinx_pcie_root_realize; 304 k->exit = pci_bridge_exitfn; 305 dc->reset = pci_bridge_reset; 306 k->config_read = xilinx_pcie_root_config_read; 307 k->config_write = xilinx_pcie_root_config_write; 308 /* 309 * PCI-facing part of the host bridge, not usable without the 310 * host-facing part, which can't be device_add'ed, yet. 311 */ 312 dc->user_creatable = false; 313 } 314 315 static const TypeInfo xilinx_pcie_root_info = { 316 .name = TYPE_XILINX_PCIE_ROOT, 317 .parent = TYPE_PCI_BRIDGE, 318 .instance_size = sizeof(XilinxPCIERoot), 319 .class_init = xilinx_pcie_root_class_init, 320 .interfaces = (InterfaceInfo[]) { 321 { INTERFACE_PCIE_DEVICE }, 322 { } 323 }, 324 }; 325 326 static void xilinx_pcie_register(void) 327 { 328 type_register_static(&xilinx_pcie_root_info); 329 type_register_static(&xilinx_pcie_host_info); 330 } 331 332 type_init(xilinx_pcie_register) 333