1 /* 2 * Xilinx PCIe host controller emulation. 3 * 4 * Copyright (c) 2016 Imagination Technologies 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/module.h" 22 #include "qemu/units.h" 23 #include "qapi/error.h" 24 #include "hw/pci/pci_bridge.h" 25 #include "hw/qdev-properties.h" 26 #include "hw/irq.h" 27 #include "hw/pci-host/xilinx-pcie.h" 28 29 enum root_cfg_reg { 30 /* Interrupt Decode Register */ 31 ROOTCFG_INTDEC = 0x138, 32 33 /* Interrupt Mask Register */ 34 ROOTCFG_INTMASK = 0x13c, 35 /* INTx Interrupt Received */ 36 #define ROOTCFG_INTMASK_INTX (1 << 16) 37 /* MSI Interrupt Received */ 38 #define ROOTCFG_INTMASK_MSI (1 << 17) 39 40 /* PHY Status/Control Register */ 41 ROOTCFG_PSCR = 0x144, 42 /* Link Up */ 43 #define ROOTCFG_PSCR_LINK_UP (1 << 11) 44 45 /* Root Port Status/Control Register */ 46 ROOTCFG_RPSCR = 0x148, 47 /* Bridge Enable */ 48 #define ROOTCFG_RPSCR_BRIDGEEN (1 << 0) 49 /* Interrupt FIFO Not Empty */ 50 #define ROOTCFG_RPSCR_INTNEMPTY (1 << 18) 51 /* Interrupt FIFO Overflow */ 52 #define ROOTCFG_RPSCR_INTOVF (1 << 19) 53 54 /* Root Port Interrupt FIFO Read Register 1 */ 55 ROOTCFG_RPIFR1 = 0x158, 56 #define ROOTCFG_RPIFR1_INT_LANE_SHIFT 27 57 #define ROOTCFG_RPIFR1_INT_ASSERT_SHIFT 29 58 #define ROOTCFG_RPIFR1_INT_VALID_SHIFT 31 59 /* Root Port Interrupt FIFO Read Register 2 */ 60 ROOTCFG_RPIFR2 = 0x15c, 61 }; 62 63 static void xilinx_pcie_update_intr(XilinxPCIEHost *s, 64 uint32_t set, uint32_t clear) 65 { 66 int level; 67 68 s->intr |= set; 69 s->intr &= ~clear; 70 71 if (s->intr_fifo_r != s->intr_fifo_w) { 72 s->intr |= ROOTCFG_INTMASK_INTX; 73 } 74 75 level = !!(s->intr & s->intr_mask); 76 qemu_set_irq(s->irq, level); 77 } 78 79 static void xilinx_pcie_queue_intr(XilinxPCIEHost *s, 80 uint32_t fifo_reg1, uint32_t fifo_reg2) 81 { 82 XilinxPCIEInt *intr; 83 unsigned int new_w; 84 85 new_w = (s->intr_fifo_w + 1) % ARRAY_SIZE(s->intr_fifo); 86 if (new_w == s->intr_fifo_r) { 87 s->rpscr |= ROOTCFG_RPSCR_INTOVF; 88 return; 89 } 90 91 intr = &s->intr_fifo[s->intr_fifo_w]; 92 s->intr_fifo_w = new_w; 93 94 intr->fifo_reg1 = fifo_reg1; 95 intr->fifo_reg2 = fifo_reg2; 96 97 xilinx_pcie_update_intr(s, ROOTCFG_INTMASK_INTX, 0); 98 } 99 100 static void xilinx_pcie_set_irq(void *opaque, int irq_num, int level) 101 { 102 XilinxPCIEHost *s = XILINX_PCIE_HOST(opaque); 103 104 xilinx_pcie_queue_intr(s, 105 (irq_num << ROOTCFG_RPIFR1_INT_LANE_SHIFT) | 106 (level << ROOTCFG_RPIFR1_INT_ASSERT_SHIFT) | 107 (1 << ROOTCFG_RPIFR1_INT_VALID_SHIFT), 108 0); 109 } 110 111 static void xilinx_pcie_host_realize(DeviceState *dev, Error **errp) 112 { 113 PCIHostState *pci = PCI_HOST_BRIDGE(dev); 114 XilinxPCIEHost *s = XILINX_PCIE_HOST(dev); 115 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 116 PCIExpressHost *pex = PCIE_HOST_BRIDGE(dev); 117 118 snprintf(s->name, sizeof(s->name), "pcie%u", s->bus_nr); 119 120 /* PCI configuration space */ 121 pcie_host_mmcfg_init(pex, s->cfg_size); 122 123 /* MMIO region */ 124 memory_region_init(&s->mmio, OBJECT(s), "mmio", UINT64_MAX); 125 memory_region_set_enabled(&s->mmio, false); 126 127 /* dummy PCI I/O region (not visible to the CPU) */ 128 memory_region_init(&s->io, OBJECT(s), "io", 16); 129 130 /* interrupt out */ 131 qdev_init_gpio_out_named(dev, &s->irq, "interrupt_out", 1); 132 133 sysbus_init_mmio(sbd, &pex->mmio); 134 sysbus_init_mmio(sbd, &s->mmio); 135 136 pci->bus = pci_register_root_bus(dev, s->name, xilinx_pcie_set_irq, 137 pci_swizzle_map_irq_fn, s, &s->mmio, 138 &s->io, 0, 4, TYPE_PCIE_BUS); 139 140 qdev_set_parent_bus(DEVICE(&s->root), BUS(pci->bus)); 141 qdev_init_nofail(DEVICE(&s->root)); 142 } 143 144 static const char *xilinx_pcie_host_root_bus_path(PCIHostState *host_bridge, 145 PCIBus *rootbus) 146 { 147 return "0000:00"; 148 } 149 150 static void xilinx_pcie_host_init(Object *obj) 151 { 152 XilinxPCIEHost *s = XILINX_PCIE_HOST(obj); 153 XilinxPCIERoot *root = &s->root; 154 155 object_initialize_child(obj, "root", root, sizeof(*root), 156 TYPE_XILINX_PCIE_ROOT, &error_abort, NULL); 157 qdev_prop_set_int32(DEVICE(root), "addr", PCI_DEVFN(0, 0)); 158 qdev_prop_set_bit(DEVICE(root), "multifunction", false); 159 } 160 161 static Property xilinx_pcie_host_props[] = { 162 DEFINE_PROP_UINT32("bus_nr", XilinxPCIEHost, bus_nr, 0), 163 DEFINE_PROP_SIZE("cfg_base", XilinxPCIEHost, cfg_base, 0), 164 DEFINE_PROP_SIZE("cfg_size", XilinxPCIEHost, cfg_size, 32 * MiB), 165 DEFINE_PROP_SIZE("mmio_base", XilinxPCIEHost, mmio_base, 0), 166 DEFINE_PROP_SIZE("mmio_size", XilinxPCIEHost, mmio_size, 1 * MiB), 167 DEFINE_PROP_BOOL("link_up", XilinxPCIEHost, link_up, true), 168 DEFINE_PROP_END_OF_LIST(), 169 }; 170 171 static void xilinx_pcie_host_class_init(ObjectClass *klass, void *data) 172 { 173 DeviceClass *dc = DEVICE_CLASS(klass); 174 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); 175 176 hc->root_bus_path = xilinx_pcie_host_root_bus_path; 177 dc->realize = xilinx_pcie_host_realize; 178 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 179 dc->fw_name = "pci"; 180 dc->props = xilinx_pcie_host_props; 181 } 182 183 static const TypeInfo xilinx_pcie_host_info = { 184 .name = TYPE_XILINX_PCIE_HOST, 185 .parent = TYPE_PCIE_HOST_BRIDGE, 186 .instance_size = sizeof(XilinxPCIEHost), 187 .instance_init = xilinx_pcie_host_init, 188 .class_init = xilinx_pcie_host_class_init, 189 }; 190 191 static uint32_t xilinx_pcie_root_config_read(PCIDevice *d, 192 uint32_t address, int len) 193 { 194 XilinxPCIEHost *s = XILINX_PCIE_HOST(OBJECT(d)->parent); 195 uint32_t val; 196 197 switch (address) { 198 case ROOTCFG_INTDEC: 199 val = s->intr; 200 break; 201 case ROOTCFG_INTMASK: 202 val = s->intr_mask; 203 break; 204 case ROOTCFG_PSCR: 205 val = s->link_up ? ROOTCFG_PSCR_LINK_UP : 0; 206 break; 207 case ROOTCFG_RPSCR: 208 if (s->intr_fifo_r != s->intr_fifo_w) { 209 s->rpscr &= ~ROOTCFG_RPSCR_INTNEMPTY; 210 } else { 211 s->rpscr |= ROOTCFG_RPSCR_INTNEMPTY; 212 } 213 val = s->rpscr; 214 break; 215 case ROOTCFG_RPIFR1: 216 if (s->intr_fifo_w == s->intr_fifo_r) { 217 /* FIFO empty */ 218 val = 0; 219 } else { 220 val = s->intr_fifo[s->intr_fifo_r].fifo_reg1; 221 } 222 break; 223 case ROOTCFG_RPIFR2: 224 if (s->intr_fifo_w == s->intr_fifo_r) { 225 /* FIFO empty */ 226 val = 0; 227 } else { 228 val = s->intr_fifo[s->intr_fifo_r].fifo_reg2; 229 } 230 break; 231 default: 232 val = pci_default_read_config(d, address, len); 233 break; 234 } 235 return val; 236 } 237 238 static void xilinx_pcie_root_config_write(PCIDevice *d, uint32_t address, 239 uint32_t val, int len) 240 { 241 XilinxPCIEHost *s = XILINX_PCIE_HOST(OBJECT(d)->parent); 242 switch (address) { 243 case ROOTCFG_INTDEC: 244 xilinx_pcie_update_intr(s, 0, val); 245 break; 246 case ROOTCFG_INTMASK: 247 s->intr_mask = val; 248 xilinx_pcie_update_intr(s, 0, 0); 249 break; 250 case ROOTCFG_RPSCR: 251 s->rpscr &= ~ROOTCFG_RPSCR_BRIDGEEN; 252 s->rpscr |= val & ROOTCFG_RPSCR_BRIDGEEN; 253 memory_region_set_enabled(&s->mmio, val & ROOTCFG_RPSCR_BRIDGEEN); 254 255 if (val & ROOTCFG_INTMASK_INTX) { 256 s->rpscr &= ~ROOTCFG_INTMASK_INTX; 257 } 258 break; 259 case ROOTCFG_RPIFR1: 260 case ROOTCFG_RPIFR2: 261 if (s->intr_fifo_w == s->intr_fifo_r) { 262 /* FIFO empty */ 263 return; 264 } else { 265 s->intr_fifo_r = (s->intr_fifo_r + 1) % ARRAY_SIZE(s->intr_fifo); 266 } 267 break; 268 default: 269 pci_default_write_config(d, address, val, len); 270 break; 271 } 272 } 273 274 static void xilinx_pcie_root_realize(PCIDevice *pci_dev, Error **errp) 275 { 276 BusState *bus = qdev_get_parent_bus(DEVICE(pci_dev)); 277 XilinxPCIEHost *s = XILINX_PCIE_HOST(bus->parent); 278 279 pci_set_word(pci_dev->config + PCI_COMMAND, 280 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 281 pci_set_word(pci_dev->config + PCI_MEMORY_BASE, s->mmio_base >> 16); 282 pci_set_word(pci_dev->config + PCI_MEMORY_LIMIT, 283 ((s->mmio_base + s->mmio_size - 1) >> 16) & 0xfff0); 284 285 pci_bridge_initfn(pci_dev, TYPE_PCI_BUS); 286 287 if (pcie_endpoint_cap_v1_init(pci_dev, 0x80) < 0) { 288 error_setg(errp, "Failed to initialize PCIe capability"); 289 } 290 } 291 292 static void xilinx_pcie_root_class_init(ObjectClass *klass, void *data) 293 { 294 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 295 DeviceClass *dc = DEVICE_CLASS(klass); 296 297 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 298 dc->desc = "Xilinx AXI-PCIe Host Bridge"; 299 k->vendor_id = PCI_VENDOR_ID_XILINX; 300 k->device_id = 0x7021; 301 k->revision = 0; 302 k->class_id = PCI_CLASS_BRIDGE_HOST; 303 k->is_bridge = true; 304 k->realize = xilinx_pcie_root_realize; 305 k->exit = pci_bridge_exitfn; 306 dc->reset = pci_bridge_reset; 307 k->config_read = xilinx_pcie_root_config_read; 308 k->config_write = xilinx_pcie_root_config_write; 309 /* 310 * PCI-facing part of the host bridge, not usable without the 311 * host-facing part, which can't be device_add'ed, yet. 312 */ 313 dc->user_creatable = false; 314 } 315 316 static const TypeInfo xilinx_pcie_root_info = { 317 .name = TYPE_XILINX_PCIE_ROOT, 318 .parent = TYPE_PCI_BRIDGE, 319 .instance_size = sizeof(XilinxPCIERoot), 320 .class_init = xilinx_pcie_root_class_init, 321 .interfaces = (InterfaceInfo[]) { 322 { INTERFACE_PCIE_DEVICE }, 323 { } 324 }, 325 }; 326 327 static void xilinx_pcie_register(void) 328 { 329 type_register_static(&xilinx_pcie_root_info); 330 type_register_static(&xilinx_pcie_host_info); 331 } 332 333 type_init(xilinx_pcie_register) 334