1 /* 2 * ARM Versatile/PB PCI host controller 3 * 4 * Copyright (c) 2006-2009 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the LGPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "hw/sysbus.h" 12 #include "migration/vmstate.h" 13 #include "hw/irq.h" 14 #include "hw/pci/pci.h" 15 #include "hw/pci/pci_bus.h" 16 #include "hw/pci/pci_host.h" 17 #include "qemu/log.h" 18 #include "qemu/module.h" 19 20 /* Old and buggy versions of QEMU used the wrong mapping from 21 * PCI IRQs to system interrupt lines. Unfortunately the Linux 22 * kernel also had the corresponding bug in setting up interrupts 23 * (so older kernels work on QEMU and not on real hardware). 24 * We automatically detect these broken kernels and flip back 25 * to the broken irq mapping by spotting guest writes to the 26 * PCI_INTERRUPT_LINE register to see where the guest thinks 27 * interrupts are going to be routed. So we start in state 28 * ASSUME_OK on reset, and transition to either BROKEN or 29 * FORCE_OK at the first write to an INTERRUPT_LINE register for 30 * a slot where broken and correct interrupt mapping would differ. 31 * Once in either BROKEN or FORCE_OK we never transition again; 32 * this allows a newer kernel to use the INTERRUPT_LINE 33 * registers arbitrarily once it has indicated that it isn't 34 * broken in its init code somewhere. 35 * 36 * Unfortunately we have to cope with multiple different 37 * variants on the broken kernel behaviour: 38 * phase I (before kernel commit 1bc39ac5d) kernels assume old 39 * QEMU behaviour, so they use IRQ 27 for all slots 40 * phase II (1bc39ac5d and later, but before e3e92a7be6) kernels 41 * swizzle IRQs between slots, but do it wrongly, so they 42 * work only for every fourth PCI card, and only if (like old 43 * QEMU) the PCI host device is at slot 0 rather than where 44 * the h/w actually puts it 45 * phase III (e3e92a7be6 and later) kernels still swizzle IRQs between 46 * slots wrongly, but add a fixed offset of 64 to everything 47 * they write to PCI_INTERRUPT_LINE. 48 * 49 * We live in hope of a mythical phase IV kernel which might 50 * actually behave in ways that work on the hardware. Such a 51 * kernel should probably start off by writing some value neither 52 * 27 nor 91 to slot zero's PCI_INTERRUPT_LINE register to 53 * disable the autodetection. After that it can do what it likes. 54 * 55 * Slot % 4 | hw | I | II | III 56 * ------------------------------- 57 * 0 | 29 | 27 | 27 | 91 58 * 1 | 30 | 27 | 28 | 92 59 * 2 | 27 | 27 | 29 | 93 60 * 3 | 28 | 27 | 30 | 94 61 * 62 * Since our autodetection is not perfect we also provide a 63 * property so the user can make us start in BROKEN or FORCE_OK 64 * on reset if they know they have a bad or good kernel. 65 */ 66 enum { 67 PCI_VPB_IRQMAP_ASSUME_OK, 68 PCI_VPB_IRQMAP_BROKEN, 69 PCI_VPB_IRQMAP_FORCE_OK, 70 }; 71 72 typedef struct { 73 PCIHostState parent_obj; 74 75 qemu_irq irq[4]; 76 MemoryRegion controlregs; 77 MemoryRegion mem_config; 78 MemoryRegion mem_config2; 79 /* Containers representing the PCI address spaces */ 80 MemoryRegion pci_io_space; 81 MemoryRegion pci_mem_space; 82 /* Alias regions into PCI address spaces which we expose as sysbus regions. 83 * The offsets into pci_mem_space are controlled by the imap registers. 84 */ 85 MemoryRegion pci_io_window; 86 MemoryRegion pci_mem_window[3]; 87 PCIBus pci_bus; 88 PCIDevice pci_dev; 89 90 /* Constant for life of device: */ 91 int realview; 92 uint32_t mem_win_size[3]; 93 uint8_t irq_mapping_prop; 94 95 /* Variable state: */ 96 uint32_t imap[3]; 97 uint32_t smap[3]; 98 uint32_t selfid; 99 uint32_t flags; 100 uint8_t irq_mapping; 101 } PCIVPBState; 102 103 static void pci_vpb_update_window(PCIVPBState *s, int i) 104 { 105 /* Adjust the offset of the alias region we use for 106 * the memory window i to account for a change in the 107 * value of the corresponding IMAP register. 108 * Note that the semantics of the IMAP register differ 109 * for realview and versatile variants of the controller. 110 */ 111 hwaddr offset; 112 if (s->realview) { 113 /* Top bits of register (masked according to window size) provide 114 * top bits of PCI address. 115 */ 116 offset = s->imap[i] & ~(s->mem_win_size[i] - 1); 117 } else { 118 /* Bottom 4 bits of register provide top 4 bits of PCI address */ 119 offset = s->imap[i] << 28; 120 } 121 memory_region_set_alias_offset(&s->pci_mem_window[i], offset); 122 } 123 124 static void pci_vpb_update_all_windows(PCIVPBState *s) 125 { 126 /* Update all alias windows based on the current register state */ 127 int i; 128 129 for (i = 0; i < 3; i++) { 130 pci_vpb_update_window(s, i); 131 } 132 } 133 134 static int pci_vpb_post_load(void *opaque, int version_id) 135 { 136 PCIVPBState *s = opaque; 137 pci_vpb_update_all_windows(s); 138 return 0; 139 } 140 141 static const VMStateDescription pci_vpb_vmstate = { 142 .name = "versatile-pci", 143 .version_id = 1, 144 .minimum_version_id = 1, 145 .post_load = pci_vpb_post_load, 146 .fields = (VMStateField[]) { 147 VMSTATE_UINT32_ARRAY(imap, PCIVPBState, 3), 148 VMSTATE_UINT32_ARRAY(smap, PCIVPBState, 3), 149 VMSTATE_UINT32(selfid, PCIVPBState), 150 VMSTATE_UINT32(flags, PCIVPBState), 151 VMSTATE_UINT8(irq_mapping, PCIVPBState), 152 VMSTATE_END_OF_LIST() 153 } 154 }; 155 156 #define TYPE_VERSATILE_PCI "versatile_pci" 157 #define PCI_VPB(obj) \ 158 OBJECT_CHECK(PCIVPBState, (obj), TYPE_VERSATILE_PCI) 159 160 #define TYPE_VERSATILE_PCI_HOST "versatile_pci_host" 161 #define PCI_VPB_HOST(obj) \ 162 OBJECT_CHECK(PCIDevice, (obj), TYPE_VERSATILE_PCIHOST) 163 164 typedef enum { 165 PCI_IMAP0 = 0x0, 166 PCI_IMAP1 = 0x4, 167 PCI_IMAP2 = 0x8, 168 PCI_SELFID = 0xc, 169 PCI_FLAGS = 0x10, 170 PCI_SMAP0 = 0x14, 171 PCI_SMAP1 = 0x18, 172 PCI_SMAP2 = 0x1c, 173 } PCIVPBControlRegs; 174 175 static void pci_vpb_reg_write(void *opaque, hwaddr addr, 176 uint64_t val, unsigned size) 177 { 178 PCIVPBState *s = opaque; 179 180 switch (addr) { 181 case PCI_IMAP0: 182 case PCI_IMAP1: 183 case PCI_IMAP2: 184 { 185 int win = (addr - PCI_IMAP0) >> 2; 186 s->imap[win] = val; 187 pci_vpb_update_window(s, win); 188 break; 189 } 190 case PCI_SELFID: 191 s->selfid = val; 192 break; 193 case PCI_FLAGS: 194 s->flags = val; 195 break; 196 case PCI_SMAP0: 197 case PCI_SMAP1: 198 case PCI_SMAP2: 199 { 200 int win = (addr - PCI_SMAP0) >> 2; 201 s->smap[win] = val; 202 break; 203 } 204 default: 205 qemu_log_mask(LOG_GUEST_ERROR, 206 "pci_vpb_reg_write: Bad offset %x\n", (int)addr); 207 break; 208 } 209 } 210 211 static uint64_t pci_vpb_reg_read(void *opaque, hwaddr addr, 212 unsigned size) 213 { 214 PCIVPBState *s = opaque; 215 216 switch (addr) { 217 case PCI_IMAP0: 218 case PCI_IMAP1: 219 case PCI_IMAP2: 220 { 221 int win = (addr - PCI_IMAP0) >> 2; 222 return s->imap[win]; 223 } 224 case PCI_SELFID: 225 return s->selfid; 226 case PCI_FLAGS: 227 return s->flags; 228 case PCI_SMAP0: 229 case PCI_SMAP1: 230 case PCI_SMAP2: 231 { 232 int win = (addr - PCI_SMAP0) >> 2; 233 return s->smap[win]; 234 } 235 default: 236 qemu_log_mask(LOG_GUEST_ERROR, 237 "pci_vpb_reg_read: Bad offset %x\n", (int)addr); 238 return 0; 239 } 240 } 241 242 static const MemoryRegionOps pci_vpb_reg_ops = { 243 .read = pci_vpb_reg_read, 244 .write = pci_vpb_reg_write, 245 .endianness = DEVICE_NATIVE_ENDIAN, 246 .valid = { 247 .min_access_size = 4, 248 .max_access_size = 4, 249 }, 250 }; 251 252 static int pci_vpb_broken_irq(int slot, int irq) 253 { 254 /* Determine whether this IRQ value for this slot represents a 255 * known broken Linux kernel behaviour for this slot. 256 * Return one of the PCI_VPB_IRQMAP_ constants: 257 * BROKEN : if this definitely looks like a broken kernel 258 * FORCE_OK : if this definitely looks good 259 * ASSUME_OK : if we can't tell 260 */ 261 slot %= PCI_NUM_PINS; 262 263 if (irq == 27) { 264 if (slot == 2) { 265 /* Might be a Phase I kernel, or might be a fixed kernel, 266 * since slot 2 is where we expect this IRQ. 267 */ 268 return PCI_VPB_IRQMAP_ASSUME_OK; 269 } 270 /* Phase I kernel */ 271 return PCI_VPB_IRQMAP_BROKEN; 272 } 273 if (irq == slot + 27) { 274 /* Phase II kernel */ 275 return PCI_VPB_IRQMAP_BROKEN; 276 } 277 if (irq == slot + 27 + 64) { 278 /* Phase III kernel */ 279 return PCI_VPB_IRQMAP_BROKEN; 280 } 281 /* Anything else must be a fixed kernel, possibly using an 282 * arbitrary irq map. 283 */ 284 return PCI_VPB_IRQMAP_FORCE_OK; 285 } 286 287 static void pci_vpb_config_write(void *opaque, hwaddr addr, 288 uint64_t val, unsigned size) 289 { 290 PCIVPBState *s = opaque; 291 if (!s->realview && (addr & 0xff) == PCI_INTERRUPT_LINE 292 && s->irq_mapping == PCI_VPB_IRQMAP_ASSUME_OK) { 293 uint8_t devfn = addr >> 8; 294 s->irq_mapping = pci_vpb_broken_irq(PCI_SLOT(devfn), val); 295 } 296 pci_data_write(&s->pci_bus, addr, val, size); 297 } 298 299 static uint64_t pci_vpb_config_read(void *opaque, hwaddr addr, 300 unsigned size) 301 { 302 PCIVPBState *s = opaque; 303 uint32_t val; 304 val = pci_data_read(&s->pci_bus, addr, size); 305 return val; 306 } 307 308 static const MemoryRegionOps pci_vpb_config_ops = { 309 .read = pci_vpb_config_read, 310 .write = pci_vpb_config_write, 311 .endianness = DEVICE_NATIVE_ENDIAN, 312 }; 313 314 static int pci_vpb_map_irq(PCIDevice *d, int irq_num) 315 { 316 PCIVPBState *s = container_of(pci_get_bus(d), PCIVPBState, pci_bus); 317 318 if (s->irq_mapping == PCI_VPB_IRQMAP_BROKEN) { 319 /* Legacy broken IRQ mapping for compatibility with old and 320 * buggy Linux guests 321 */ 322 return irq_num; 323 } 324 325 /* Slot to IRQ mapping for RealView Platform Baseboard 926 backplane 326 * name slot IntA IntB IntC IntD 327 * A 31 IRQ28 IRQ29 IRQ30 IRQ27 328 * B 30 IRQ27 IRQ28 IRQ29 IRQ30 329 * C 29 IRQ30 IRQ27 IRQ28 IRQ29 330 * Slot C is for the host bridge; A and B the peripherals. 331 * Our output irqs 0..3 correspond to the baseboard's 27..30. 332 * 333 * This mapping function takes account of an oddity in the PB926 334 * board wiring, where the FPGA's P_nINTA input is connected to 335 * the INTB connection on the board PCI edge connector, P_nINTB 336 * is connected to INTC, and so on, so everything is one number 337 * further round from where you might expect. 338 */ 339 return pci_swizzle_map_irq_fn(d, irq_num + 2); 340 } 341 342 static int pci_vpb_rv_map_irq(PCIDevice *d, int irq_num) 343 { 344 /* Slot to IRQ mapping for RealView EB and PB1176 backplane 345 * name slot IntA IntB IntC IntD 346 * A 31 IRQ50 IRQ51 IRQ48 IRQ49 347 * B 30 IRQ49 IRQ50 IRQ51 IRQ48 348 * C 29 IRQ48 IRQ49 IRQ50 IRQ51 349 * Slot C is for the host bridge; A and B the peripherals. 350 * Our output irqs 0..3 correspond to the baseboard's 48..51. 351 * 352 * The PB1176 and EB boards don't have the PB926 wiring oddity 353 * described above; P_nINTA connects to INTA, P_nINTB to INTB 354 * and so on, which is why this mapping function is different. 355 */ 356 return pci_swizzle_map_irq_fn(d, irq_num + 3); 357 } 358 359 static void pci_vpb_set_irq(void *opaque, int irq_num, int level) 360 { 361 qemu_irq *pic = opaque; 362 363 qemu_set_irq(pic[irq_num], level); 364 } 365 366 static void pci_vpb_reset(DeviceState *d) 367 { 368 PCIVPBState *s = PCI_VPB(d); 369 370 s->imap[0] = 0; 371 s->imap[1] = 0; 372 s->imap[2] = 0; 373 s->smap[0] = 0; 374 s->smap[1] = 0; 375 s->smap[2] = 0; 376 s->selfid = 0; 377 s->flags = 0; 378 s->irq_mapping = s->irq_mapping_prop; 379 380 pci_vpb_update_all_windows(s); 381 } 382 383 static void pci_vpb_init(Object *obj) 384 { 385 PCIVPBState *s = PCI_VPB(obj); 386 387 /* Window sizes for VersatilePB; realview_pci's init will override */ 388 s->mem_win_size[0] = 0x0c000000; 389 s->mem_win_size[1] = 0x10000000; 390 s->mem_win_size[2] = 0x10000000; 391 } 392 393 static void pci_vpb_realize(DeviceState *dev, Error **errp) 394 { 395 PCIVPBState *s = PCI_VPB(dev); 396 PCIHostState *h = PCI_HOST_BRIDGE(dev); 397 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 398 pci_map_irq_fn mapfn; 399 int i; 400 401 memory_region_init(&s->pci_io_space, OBJECT(s), "pci_io", 1ULL << 32); 402 memory_region_init(&s->pci_mem_space, OBJECT(s), "pci_mem", 1ULL << 32); 403 404 pci_root_bus_new_inplace(&s->pci_bus, sizeof(s->pci_bus), dev, "pci", 405 &s->pci_mem_space, &s->pci_io_space, 406 PCI_DEVFN(11, 0), TYPE_PCI_BUS); 407 h->bus = &s->pci_bus; 408 409 object_initialize(&s->pci_dev, sizeof(s->pci_dev), TYPE_VERSATILE_PCI_HOST); 410 qdev_set_parent_bus(DEVICE(&s->pci_dev), BUS(&s->pci_bus)); 411 412 for (i = 0; i < 4; i++) { 413 sysbus_init_irq(sbd, &s->irq[i]); 414 } 415 416 if (s->realview) { 417 mapfn = pci_vpb_rv_map_irq; 418 } else { 419 mapfn = pci_vpb_map_irq; 420 } 421 422 pci_bus_irqs(&s->pci_bus, pci_vpb_set_irq, mapfn, s->irq, 4); 423 424 /* Our memory regions are: 425 * 0 : our control registers 426 * 1 : PCI self config window 427 * 2 : PCI config window 428 * 3 : PCI IO window 429 * 4..6 : PCI memory windows 430 */ 431 memory_region_init_io(&s->controlregs, OBJECT(s), &pci_vpb_reg_ops, s, 432 "pci-vpb-regs", 0x1000); 433 sysbus_init_mmio(sbd, &s->controlregs); 434 memory_region_init_io(&s->mem_config, OBJECT(s), &pci_vpb_config_ops, s, 435 "pci-vpb-selfconfig", 0x1000000); 436 sysbus_init_mmio(sbd, &s->mem_config); 437 memory_region_init_io(&s->mem_config2, OBJECT(s), &pci_vpb_config_ops, s, 438 "pci-vpb-config", 0x1000000); 439 sysbus_init_mmio(sbd, &s->mem_config2); 440 441 /* The window into I/O space is always into a fixed base address; 442 * its size is the same for both realview and versatile. 443 */ 444 memory_region_init_alias(&s->pci_io_window, OBJECT(s), "pci-vbp-io-window", 445 &s->pci_io_space, 0, 0x100000); 446 447 sysbus_init_mmio(sbd, &s->pci_io_space); 448 449 /* Create the alias regions corresponding to our three windows onto 450 * PCI memory space. The sizes vary from board to board; the base 451 * offsets are guest controllable via the IMAP registers. 452 */ 453 for (i = 0; i < 3; i++) { 454 memory_region_init_alias(&s->pci_mem_window[i], OBJECT(s), "pci-vbp-window", 455 &s->pci_mem_space, 0, s->mem_win_size[i]); 456 sysbus_init_mmio(sbd, &s->pci_mem_window[i]); 457 } 458 459 /* TODO Remove once realize propagates to child devices. */ 460 object_property_set_bool(OBJECT(&s->pci_bus), true, "realized", errp); 461 object_property_set_bool(OBJECT(&s->pci_dev), true, "realized", errp); 462 } 463 464 static void versatile_pci_host_realize(PCIDevice *d, Error **errp) 465 { 466 pci_set_word(d->config + PCI_STATUS, 467 PCI_STATUS_66MHZ | PCI_STATUS_DEVSEL_MEDIUM); 468 pci_set_byte(d->config + PCI_LATENCY_TIMER, 0x10); 469 } 470 471 static void versatile_pci_host_class_init(ObjectClass *klass, void *data) 472 { 473 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 474 DeviceClass *dc = DEVICE_CLASS(klass); 475 476 k->realize = versatile_pci_host_realize; 477 k->vendor_id = PCI_VENDOR_ID_XILINX; 478 k->device_id = PCI_DEVICE_ID_XILINX_XC2VP30; 479 k->class_id = PCI_CLASS_PROCESSOR_CO; 480 /* 481 * PCI-facing part of the host bridge, not usable without the 482 * host-facing part, which can't be device_add'ed, yet. 483 */ 484 dc->user_creatable = false; 485 } 486 487 static const TypeInfo versatile_pci_host_info = { 488 .name = TYPE_VERSATILE_PCI_HOST, 489 .parent = TYPE_PCI_DEVICE, 490 .instance_size = sizeof(PCIDevice), 491 .class_init = versatile_pci_host_class_init, 492 .interfaces = (InterfaceInfo[]) { 493 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 494 { }, 495 }, 496 }; 497 498 static Property pci_vpb_properties[] = { 499 DEFINE_PROP_UINT8("broken-irq-mapping", PCIVPBState, irq_mapping_prop, 500 PCI_VPB_IRQMAP_ASSUME_OK), 501 DEFINE_PROP_END_OF_LIST() 502 }; 503 504 static void pci_vpb_class_init(ObjectClass *klass, void *data) 505 { 506 DeviceClass *dc = DEVICE_CLASS(klass); 507 508 dc->realize = pci_vpb_realize; 509 dc->reset = pci_vpb_reset; 510 dc->vmsd = &pci_vpb_vmstate; 511 dc->props = pci_vpb_properties; 512 } 513 514 static const TypeInfo pci_vpb_info = { 515 .name = TYPE_VERSATILE_PCI, 516 .parent = TYPE_PCI_HOST_BRIDGE, 517 .instance_size = sizeof(PCIVPBState), 518 .instance_init = pci_vpb_init, 519 .class_init = pci_vpb_class_init, 520 }; 521 522 static void pci_realview_init(Object *obj) 523 { 524 PCIVPBState *s = PCI_VPB(obj); 525 526 s->realview = 1; 527 /* The PCI window sizes are different on Realview boards */ 528 s->mem_win_size[0] = 0x01000000; 529 s->mem_win_size[1] = 0x04000000; 530 s->mem_win_size[2] = 0x08000000; 531 } 532 533 static const TypeInfo pci_realview_info = { 534 .name = "realview_pci", 535 .parent = TYPE_VERSATILE_PCI, 536 .instance_init = pci_realview_init, 537 }; 538 539 static void versatile_pci_register_types(void) 540 { 541 type_register_static(&pci_vpb_info); 542 type_register_static(&pci_realview_info); 543 type_register_static(&versatile_pci_host_info); 544 } 545 546 type_init(versatile_pci_register_types) 547