xref: /openbmc/qemu/hw/pci-host/versatile.c (revision 64552b6b)
1 /*
2  * ARM Versatile/PB PCI host controller
3  *
4  * Copyright (c) 2006-2009 CodeSourcery.
5  * Written by Paul Brook
6  *
7  * This code is licensed under the LGPL.
8  */
9 
10 #include "qemu/osdep.h"
11 #include "hw/sysbus.h"
12 #include "hw/irq.h"
13 #include "hw/pci/pci.h"
14 #include "hw/pci/pci_bus.h"
15 #include "hw/pci/pci_host.h"
16 #include "qemu/log.h"
17 #include "qemu/module.h"
18 
19 /* Old and buggy versions of QEMU used the wrong mapping from
20  * PCI IRQs to system interrupt lines. Unfortunately the Linux
21  * kernel also had the corresponding bug in setting up interrupts
22  * (so older kernels work on QEMU and not on real hardware).
23  * We automatically detect these broken kernels and flip back
24  * to the broken irq mapping by spotting guest writes to the
25  * PCI_INTERRUPT_LINE register to see where the guest thinks
26  * interrupts are going to be routed. So we start in state
27  * ASSUME_OK on reset, and transition to either BROKEN or
28  * FORCE_OK at the first write to an INTERRUPT_LINE register for
29  * a slot where broken and correct interrupt mapping would differ.
30  * Once in either BROKEN or FORCE_OK we never transition again;
31  * this allows a newer kernel to use the INTERRUPT_LINE
32  * registers arbitrarily once it has indicated that it isn't
33  * broken in its init code somewhere.
34  *
35  * Unfortunately we have to cope with multiple different
36  * variants on the broken kernel behaviour:
37  *  phase I (before kernel commit 1bc39ac5d) kernels assume old
38  *   QEMU behaviour, so they use IRQ 27 for all slots
39  *  phase II (1bc39ac5d and later, but before e3e92a7be6) kernels
40  *   swizzle IRQs between slots, but do it wrongly, so they
41  *   work only for every fourth PCI card, and only if (like old
42  *   QEMU) the PCI host device is at slot 0 rather than where
43  *   the h/w actually puts it
44  *  phase III (e3e92a7be6 and later) kernels still swizzle IRQs between
45  *   slots wrongly, but add a fixed offset of 64 to everything
46  *   they write to PCI_INTERRUPT_LINE.
47  *
48  * We live in hope of a mythical phase IV kernel which might
49  * actually behave in ways that work on the hardware. Such a
50  * kernel should probably start off by writing some value neither
51  * 27 nor 91 to slot zero's PCI_INTERRUPT_LINE register to
52  * disable the autodetection. After that it can do what it likes.
53  *
54  * Slot % 4 | hw | I  | II | III
55  * -------------------------------
56  *   0      | 29 | 27 | 27 | 91
57  *   1      | 30 | 27 | 28 | 92
58  *   2      | 27 | 27 | 29 | 93
59  *   3      | 28 | 27 | 30 | 94
60  *
61  * Since our autodetection is not perfect we also provide a
62  * property so the user can make us start in BROKEN or FORCE_OK
63  * on reset if they know they have a bad or good kernel.
64  */
65 enum {
66     PCI_VPB_IRQMAP_ASSUME_OK,
67     PCI_VPB_IRQMAP_BROKEN,
68     PCI_VPB_IRQMAP_FORCE_OK,
69 };
70 
71 typedef struct {
72     PCIHostState parent_obj;
73 
74     qemu_irq irq[4];
75     MemoryRegion controlregs;
76     MemoryRegion mem_config;
77     MemoryRegion mem_config2;
78     /* Containers representing the PCI address spaces */
79     MemoryRegion pci_io_space;
80     MemoryRegion pci_mem_space;
81     /* Alias regions into PCI address spaces which we expose as sysbus regions.
82      * The offsets into pci_mem_space are controlled by the imap registers.
83      */
84     MemoryRegion pci_io_window;
85     MemoryRegion pci_mem_window[3];
86     PCIBus pci_bus;
87     PCIDevice pci_dev;
88 
89     /* Constant for life of device: */
90     int realview;
91     uint32_t mem_win_size[3];
92     uint8_t irq_mapping_prop;
93 
94     /* Variable state: */
95     uint32_t imap[3];
96     uint32_t smap[3];
97     uint32_t selfid;
98     uint32_t flags;
99     uint8_t irq_mapping;
100 } PCIVPBState;
101 
102 static void pci_vpb_update_window(PCIVPBState *s, int i)
103 {
104     /* Adjust the offset of the alias region we use for
105      * the memory window i to account for a change in the
106      * value of the corresponding IMAP register.
107      * Note that the semantics of the IMAP register differ
108      * for realview and versatile variants of the controller.
109      */
110     hwaddr offset;
111     if (s->realview) {
112         /* Top bits of register (masked according to window size) provide
113          * top bits of PCI address.
114          */
115         offset = s->imap[i] & ~(s->mem_win_size[i] - 1);
116     } else {
117         /* Bottom 4 bits of register provide top 4 bits of PCI address */
118         offset = s->imap[i] << 28;
119     }
120     memory_region_set_alias_offset(&s->pci_mem_window[i], offset);
121 }
122 
123 static void pci_vpb_update_all_windows(PCIVPBState *s)
124 {
125     /* Update all alias windows based on the current register state */
126     int i;
127 
128     for (i = 0; i < 3; i++) {
129         pci_vpb_update_window(s, i);
130     }
131 }
132 
133 static int pci_vpb_post_load(void *opaque, int version_id)
134 {
135     PCIVPBState *s = opaque;
136     pci_vpb_update_all_windows(s);
137     return 0;
138 }
139 
140 static const VMStateDescription pci_vpb_vmstate = {
141     .name = "versatile-pci",
142     .version_id = 1,
143     .minimum_version_id = 1,
144     .post_load = pci_vpb_post_load,
145     .fields = (VMStateField[]) {
146         VMSTATE_UINT32_ARRAY(imap, PCIVPBState, 3),
147         VMSTATE_UINT32_ARRAY(smap, PCIVPBState, 3),
148         VMSTATE_UINT32(selfid, PCIVPBState),
149         VMSTATE_UINT32(flags, PCIVPBState),
150         VMSTATE_UINT8(irq_mapping, PCIVPBState),
151         VMSTATE_END_OF_LIST()
152     }
153 };
154 
155 #define TYPE_VERSATILE_PCI "versatile_pci"
156 #define PCI_VPB(obj) \
157     OBJECT_CHECK(PCIVPBState, (obj), TYPE_VERSATILE_PCI)
158 
159 #define TYPE_VERSATILE_PCI_HOST "versatile_pci_host"
160 #define PCI_VPB_HOST(obj) \
161     OBJECT_CHECK(PCIDevice, (obj), TYPE_VERSATILE_PCIHOST)
162 
163 typedef enum {
164     PCI_IMAP0 = 0x0,
165     PCI_IMAP1 = 0x4,
166     PCI_IMAP2 = 0x8,
167     PCI_SELFID = 0xc,
168     PCI_FLAGS = 0x10,
169     PCI_SMAP0 = 0x14,
170     PCI_SMAP1 = 0x18,
171     PCI_SMAP2 = 0x1c,
172 } PCIVPBControlRegs;
173 
174 static void pci_vpb_reg_write(void *opaque, hwaddr addr,
175                               uint64_t val, unsigned size)
176 {
177     PCIVPBState *s = opaque;
178 
179     switch (addr) {
180     case PCI_IMAP0:
181     case PCI_IMAP1:
182     case PCI_IMAP2:
183     {
184         int win = (addr - PCI_IMAP0) >> 2;
185         s->imap[win] = val;
186         pci_vpb_update_window(s, win);
187         break;
188     }
189     case PCI_SELFID:
190         s->selfid = val;
191         break;
192     case PCI_FLAGS:
193         s->flags = val;
194         break;
195     case PCI_SMAP0:
196     case PCI_SMAP1:
197     case PCI_SMAP2:
198     {
199         int win = (addr - PCI_SMAP0) >> 2;
200         s->smap[win] = val;
201         break;
202     }
203     default:
204         qemu_log_mask(LOG_GUEST_ERROR,
205                       "pci_vpb_reg_write: Bad offset %x\n", (int)addr);
206         break;
207     }
208 }
209 
210 static uint64_t pci_vpb_reg_read(void *opaque, hwaddr addr,
211                                  unsigned size)
212 {
213     PCIVPBState *s = opaque;
214 
215     switch (addr) {
216     case PCI_IMAP0:
217     case PCI_IMAP1:
218     case PCI_IMAP2:
219     {
220         int win = (addr - PCI_IMAP0) >> 2;
221         return s->imap[win];
222     }
223     case PCI_SELFID:
224         return s->selfid;
225     case PCI_FLAGS:
226         return s->flags;
227     case PCI_SMAP0:
228     case PCI_SMAP1:
229     case PCI_SMAP2:
230     {
231         int win = (addr - PCI_SMAP0) >> 2;
232         return s->smap[win];
233     }
234     default:
235         qemu_log_mask(LOG_GUEST_ERROR,
236                       "pci_vpb_reg_read: Bad offset %x\n", (int)addr);
237         return 0;
238     }
239 }
240 
241 static const MemoryRegionOps pci_vpb_reg_ops = {
242     .read = pci_vpb_reg_read,
243     .write = pci_vpb_reg_write,
244     .endianness = DEVICE_NATIVE_ENDIAN,
245     .valid = {
246         .min_access_size = 4,
247         .max_access_size = 4,
248     },
249 };
250 
251 static int pci_vpb_broken_irq(int slot, int irq)
252 {
253     /* Determine whether this IRQ value for this slot represents a
254      * known broken Linux kernel behaviour for this slot.
255      * Return one of the PCI_VPB_IRQMAP_ constants:
256      *   BROKEN : if this definitely looks like a broken kernel
257      *   FORCE_OK : if this definitely looks good
258      *   ASSUME_OK : if we can't tell
259      */
260     slot %= PCI_NUM_PINS;
261 
262     if (irq == 27) {
263         if (slot == 2) {
264             /* Might be a Phase I kernel, or might be a fixed kernel,
265              * since slot 2 is where we expect this IRQ.
266              */
267             return PCI_VPB_IRQMAP_ASSUME_OK;
268         }
269         /* Phase I kernel */
270         return PCI_VPB_IRQMAP_BROKEN;
271     }
272     if (irq == slot + 27) {
273         /* Phase II kernel */
274         return PCI_VPB_IRQMAP_BROKEN;
275     }
276     if (irq == slot + 27 + 64) {
277         /* Phase III kernel */
278         return PCI_VPB_IRQMAP_BROKEN;
279     }
280     /* Anything else must be a fixed kernel, possibly using an
281      * arbitrary irq map.
282      */
283     return PCI_VPB_IRQMAP_FORCE_OK;
284 }
285 
286 static void pci_vpb_config_write(void *opaque, hwaddr addr,
287                                  uint64_t val, unsigned size)
288 {
289     PCIVPBState *s = opaque;
290     if (!s->realview && (addr & 0xff) == PCI_INTERRUPT_LINE
291         && s->irq_mapping == PCI_VPB_IRQMAP_ASSUME_OK) {
292         uint8_t devfn = addr >> 8;
293         s->irq_mapping = pci_vpb_broken_irq(PCI_SLOT(devfn), val);
294     }
295     pci_data_write(&s->pci_bus, addr, val, size);
296 }
297 
298 static uint64_t pci_vpb_config_read(void *opaque, hwaddr addr,
299                                     unsigned size)
300 {
301     PCIVPBState *s = opaque;
302     uint32_t val;
303     val = pci_data_read(&s->pci_bus, addr, size);
304     return val;
305 }
306 
307 static const MemoryRegionOps pci_vpb_config_ops = {
308     .read = pci_vpb_config_read,
309     .write = pci_vpb_config_write,
310     .endianness = DEVICE_NATIVE_ENDIAN,
311 };
312 
313 static int pci_vpb_map_irq(PCIDevice *d, int irq_num)
314 {
315     PCIVPBState *s = container_of(pci_get_bus(d), PCIVPBState, pci_bus);
316 
317     if (s->irq_mapping == PCI_VPB_IRQMAP_BROKEN) {
318         /* Legacy broken IRQ mapping for compatibility with old and
319          * buggy Linux guests
320          */
321         return irq_num;
322     }
323 
324     /* Slot to IRQ mapping for RealView Platform Baseboard 926 backplane
325      *      name    slot    IntA    IntB    IntC    IntD
326      *      A       31      IRQ28   IRQ29   IRQ30   IRQ27
327      *      B       30      IRQ27   IRQ28   IRQ29   IRQ30
328      *      C       29      IRQ30   IRQ27   IRQ28   IRQ29
329      * Slot C is for the host bridge; A and B the peripherals.
330      * Our output irqs 0..3 correspond to the baseboard's 27..30.
331      *
332      * This mapping function takes account of an oddity in the PB926
333      * board wiring, where the FPGA's P_nINTA input is connected to
334      * the INTB connection on the board PCI edge connector, P_nINTB
335      * is connected to INTC, and so on, so everything is one number
336      * further round from where you might expect.
337      */
338     return pci_swizzle_map_irq_fn(d, irq_num + 2);
339 }
340 
341 static int pci_vpb_rv_map_irq(PCIDevice *d, int irq_num)
342 {
343     /* Slot to IRQ mapping for RealView EB and PB1176 backplane
344      *      name    slot    IntA    IntB    IntC    IntD
345      *      A       31      IRQ50   IRQ51   IRQ48   IRQ49
346      *      B       30      IRQ49   IRQ50   IRQ51   IRQ48
347      *      C       29      IRQ48   IRQ49   IRQ50   IRQ51
348      * Slot C is for the host bridge; A and B the peripherals.
349      * Our output irqs 0..3 correspond to the baseboard's 48..51.
350      *
351      * The PB1176 and EB boards don't have the PB926 wiring oddity
352      * described above; P_nINTA connects to INTA, P_nINTB to INTB
353      * and so on, which is why this mapping function is different.
354      */
355     return pci_swizzle_map_irq_fn(d, irq_num + 3);
356 }
357 
358 static void pci_vpb_set_irq(void *opaque, int irq_num, int level)
359 {
360     qemu_irq *pic = opaque;
361 
362     qemu_set_irq(pic[irq_num], level);
363 }
364 
365 static void pci_vpb_reset(DeviceState *d)
366 {
367     PCIVPBState *s = PCI_VPB(d);
368 
369     s->imap[0] = 0;
370     s->imap[1] = 0;
371     s->imap[2] = 0;
372     s->smap[0] = 0;
373     s->smap[1] = 0;
374     s->smap[2] = 0;
375     s->selfid = 0;
376     s->flags = 0;
377     s->irq_mapping = s->irq_mapping_prop;
378 
379     pci_vpb_update_all_windows(s);
380 }
381 
382 static void pci_vpb_init(Object *obj)
383 {
384     PCIVPBState *s = PCI_VPB(obj);
385 
386     /* Window sizes for VersatilePB; realview_pci's init will override */
387     s->mem_win_size[0] = 0x0c000000;
388     s->mem_win_size[1] = 0x10000000;
389     s->mem_win_size[2] = 0x10000000;
390 }
391 
392 static void pci_vpb_realize(DeviceState *dev, Error **errp)
393 {
394     PCIVPBState *s = PCI_VPB(dev);
395     PCIHostState *h = PCI_HOST_BRIDGE(dev);
396     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
397     pci_map_irq_fn mapfn;
398     int i;
399 
400     memory_region_init(&s->pci_io_space, OBJECT(s), "pci_io", 1ULL << 32);
401     memory_region_init(&s->pci_mem_space, OBJECT(s), "pci_mem", 1ULL << 32);
402 
403     pci_root_bus_new_inplace(&s->pci_bus, sizeof(s->pci_bus), dev, "pci",
404                              &s->pci_mem_space, &s->pci_io_space,
405                              PCI_DEVFN(11, 0), TYPE_PCI_BUS);
406     h->bus = &s->pci_bus;
407 
408     object_initialize(&s->pci_dev, sizeof(s->pci_dev), TYPE_VERSATILE_PCI_HOST);
409     qdev_set_parent_bus(DEVICE(&s->pci_dev), BUS(&s->pci_bus));
410 
411     for (i = 0; i < 4; i++) {
412         sysbus_init_irq(sbd, &s->irq[i]);
413     }
414 
415     if (s->realview) {
416         mapfn = pci_vpb_rv_map_irq;
417     } else {
418         mapfn = pci_vpb_map_irq;
419     }
420 
421     pci_bus_irqs(&s->pci_bus, pci_vpb_set_irq, mapfn, s->irq, 4);
422 
423     /* Our memory regions are:
424      * 0 : our control registers
425      * 1 : PCI self config window
426      * 2 : PCI config window
427      * 3 : PCI IO window
428      * 4..6 : PCI memory windows
429      */
430     memory_region_init_io(&s->controlregs, OBJECT(s), &pci_vpb_reg_ops, s,
431                           "pci-vpb-regs", 0x1000);
432     sysbus_init_mmio(sbd, &s->controlregs);
433     memory_region_init_io(&s->mem_config, OBJECT(s), &pci_vpb_config_ops, s,
434                           "pci-vpb-selfconfig", 0x1000000);
435     sysbus_init_mmio(sbd, &s->mem_config);
436     memory_region_init_io(&s->mem_config2, OBJECT(s), &pci_vpb_config_ops, s,
437                           "pci-vpb-config", 0x1000000);
438     sysbus_init_mmio(sbd, &s->mem_config2);
439 
440     /* The window into I/O space is always into a fixed base address;
441      * its size is the same for both realview and versatile.
442      */
443     memory_region_init_alias(&s->pci_io_window, OBJECT(s), "pci-vbp-io-window",
444                              &s->pci_io_space, 0, 0x100000);
445 
446     sysbus_init_mmio(sbd, &s->pci_io_space);
447 
448     /* Create the alias regions corresponding to our three windows onto
449      * PCI memory space. The sizes vary from board to board; the base
450      * offsets are guest controllable via the IMAP registers.
451      */
452     for (i = 0; i < 3; i++) {
453         memory_region_init_alias(&s->pci_mem_window[i], OBJECT(s), "pci-vbp-window",
454                                  &s->pci_mem_space, 0, s->mem_win_size[i]);
455         sysbus_init_mmio(sbd, &s->pci_mem_window[i]);
456     }
457 
458     /* TODO Remove once realize propagates to child devices. */
459     object_property_set_bool(OBJECT(&s->pci_bus), true, "realized", errp);
460     object_property_set_bool(OBJECT(&s->pci_dev), true, "realized", errp);
461 }
462 
463 static void versatile_pci_host_realize(PCIDevice *d, Error **errp)
464 {
465     pci_set_word(d->config + PCI_STATUS,
466                  PCI_STATUS_66MHZ | PCI_STATUS_DEVSEL_MEDIUM);
467     pci_set_byte(d->config + PCI_LATENCY_TIMER, 0x10);
468 }
469 
470 static void versatile_pci_host_class_init(ObjectClass *klass, void *data)
471 {
472     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
473     DeviceClass *dc = DEVICE_CLASS(klass);
474 
475     k->realize = versatile_pci_host_realize;
476     k->vendor_id = PCI_VENDOR_ID_XILINX;
477     k->device_id = PCI_DEVICE_ID_XILINX_XC2VP30;
478     k->class_id = PCI_CLASS_PROCESSOR_CO;
479     /*
480      * PCI-facing part of the host bridge, not usable without the
481      * host-facing part, which can't be device_add'ed, yet.
482      */
483     dc->user_creatable = false;
484 }
485 
486 static const TypeInfo versatile_pci_host_info = {
487     .name          = TYPE_VERSATILE_PCI_HOST,
488     .parent        = TYPE_PCI_DEVICE,
489     .instance_size = sizeof(PCIDevice),
490     .class_init    = versatile_pci_host_class_init,
491     .interfaces = (InterfaceInfo[]) {
492         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
493         { },
494     },
495 };
496 
497 static Property pci_vpb_properties[] = {
498     DEFINE_PROP_UINT8("broken-irq-mapping", PCIVPBState, irq_mapping_prop,
499                       PCI_VPB_IRQMAP_ASSUME_OK),
500     DEFINE_PROP_END_OF_LIST()
501 };
502 
503 static void pci_vpb_class_init(ObjectClass *klass, void *data)
504 {
505     DeviceClass *dc = DEVICE_CLASS(klass);
506 
507     dc->realize = pci_vpb_realize;
508     dc->reset = pci_vpb_reset;
509     dc->vmsd = &pci_vpb_vmstate;
510     dc->props = pci_vpb_properties;
511 }
512 
513 static const TypeInfo pci_vpb_info = {
514     .name          = TYPE_VERSATILE_PCI,
515     .parent        = TYPE_PCI_HOST_BRIDGE,
516     .instance_size = sizeof(PCIVPBState),
517     .instance_init = pci_vpb_init,
518     .class_init    = pci_vpb_class_init,
519 };
520 
521 static void pci_realview_init(Object *obj)
522 {
523     PCIVPBState *s = PCI_VPB(obj);
524 
525     s->realview = 1;
526     /* The PCI window sizes are different on Realview boards */
527     s->mem_win_size[0] = 0x01000000;
528     s->mem_win_size[1] = 0x04000000;
529     s->mem_win_size[2] = 0x08000000;
530 }
531 
532 static const TypeInfo pci_realview_info = {
533     .name          = "realview_pci",
534     .parent        = TYPE_VERSATILE_PCI,
535     .instance_init = pci_realview_init,
536 };
537 
538 static void versatile_pci_register_types(void)
539 {
540     type_register_static(&pci_vpb_info);
541     type_register_static(&pci_realview_info);
542     type_register_static(&versatile_pci_host_info);
543 }
544 
545 type_init(versatile_pci_register_types)
546