1 /* 2 * SuperH on-chip PCIC emulation. 3 * 4 * Copyright (c) 2008 Takashi YOSHII 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/sysbus.h" 27 #include "hw/sh4/sh.h" 28 #include "hw/irq.h" 29 #include "hw/pci/pci_device.h" 30 #include "hw/pci/pci_host.h" 31 #include "qemu/module.h" 32 #include "qom/object.h" 33 34 #define TYPE_SH_PCI_HOST_BRIDGE "sh_pci" 35 36 OBJECT_DECLARE_SIMPLE_TYPE(SHPCIState, SH_PCI_HOST_BRIDGE) 37 38 struct SHPCIState { 39 PCIHostState parent_obj; 40 41 PCIDevice *dev; 42 qemu_irq irq[PCI_NUM_PINS]; 43 MemoryRegion memconfig_p4; 44 MemoryRegion memconfig_a7; 45 MemoryRegion isa; 46 uint32_t par; 47 uint32_t mbr; 48 uint32_t iobr; 49 }; 50 51 static void sh_pci_reg_write(void *p, hwaddr addr, uint64_t val, unsigned size) 52 { 53 SHPCIState *pcic = p; 54 PCIHostState *phb = PCI_HOST_BRIDGE(pcic); 55 56 switch (addr) { 57 case 0 ... 0xfc: 58 stl_le_p(pcic->dev->config + addr, val); 59 break; 60 case 0x1c0: 61 pcic->par = val; 62 break; 63 case 0x1c4: 64 pcic->mbr = val & 0xff000001; 65 break; 66 case 0x1c8: 67 pcic->iobr = val & 0xfffc0001; 68 memory_region_set_alias_offset(&pcic->isa, val & 0xfffc0000); 69 break; 70 case 0x220: 71 pci_data_write(phb->bus, pcic->par, val, 4); 72 break; 73 } 74 } 75 76 static uint64_t sh_pci_reg_read(void *p, hwaddr addr, unsigned size) 77 { 78 SHPCIState *pcic = p; 79 PCIHostState *phb = PCI_HOST_BRIDGE(pcic); 80 81 switch (addr) { 82 case 0 ... 0xfc: 83 return ldl_le_p(pcic->dev->config + addr); 84 case 0x1c0: 85 return pcic->par; 86 case 0x1c4: 87 return pcic->mbr; 88 case 0x1c8: 89 return pcic->iobr; 90 case 0x220: 91 return pci_data_read(phb->bus, pcic->par, 4); 92 } 93 return 0; 94 } 95 96 static const MemoryRegionOps sh_pci_reg_ops = { 97 .read = sh_pci_reg_read, 98 .write = sh_pci_reg_write, 99 .endianness = DEVICE_NATIVE_ENDIAN, 100 .valid = { 101 .min_access_size = 4, 102 .max_access_size = 4, 103 }, 104 }; 105 106 static int sh_pci_map_irq(PCIDevice *d, int irq_num) 107 { 108 return PCI_SLOT(d->devfn); 109 } 110 111 static void sh_pci_set_irq(void *opaque, int irq_num, int level) 112 { 113 qemu_irq *pic = opaque; 114 115 qemu_set_irq(pic[irq_num], level); 116 } 117 118 static void sh_pcic_host_realize(DeviceState *dev, Error **errp) 119 { 120 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 121 SHPCIState *s = SH_PCI_HOST_BRIDGE(dev); 122 PCIHostState *phb = PCI_HOST_BRIDGE(s); 123 int i; 124 125 for (i = 0; i < 4; i++) { 126 sysbus_init_irq(sbd, &s->irq[i]); 127 } 128 phb->bus = pci_register_root_bus(dev, "pci", 129 sh_pci_set_irq, sh_pci_map_irq, 130 s->irq, 131 get_system_memory(), 132 get_system_io(), 133 PCI_DEVFN(0, 0), PCI_NUM_PINS, 134 TYPE_PCI_BUS); 135 memory_region_init_io(&s->memconfig_p4, OBJECT(s), &sh_pci_reg_ops, s, 136 "sh_pci", 0x224); 137 memory_region_init_alias(&s->memconfig_a7, OBJECT(s), "sh_pci.2", 138 &s->memconfig_p4, 0, 0x224); 139 memory_region_init_alias(&s->isa, OBJECT(s), "sh_pci.isa", 140 get_system_io(), 0, 0x40000); 141 sysbus_init_mmio(sbd, &s->memconfig_p4); 142 sysbus_init_mmio(sbd, &s->memconfig_a7); 143 memory_region_add_subregion(get_system_memory(), 0xfe240000, &s->isa); 144 145 s->dev = pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "sh_pci_host"); 146 } 147 148 static void sh_pcic_pci_realize(PCIDevice *d, Error **errp) 149 { 150 pci_set_word(d->config + PCI_COMMAND, PCI_COMMAND_WAIT); 151 pci_set_word(d->config + PCI_STATUS, PCI_STATUS_CAP_LIST | 152 PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM); 153 } 154 155 static void sh_pcic_pci_class_init(ObjectClass *klass, const void *data) 156 { 157 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 158 DeviceClass *dc = DEVICE_CLASS(klass); 159 160 k->realize = sh_pcic_pci_realize; 161 k->vendor_id = PCI_VENDOR_ID_HITACHI; 162 k->device_id = PCI_DEVICE_ID_HITACHI_SH7751R; 163 /* 164 * PCI-facing part of the host bridge, not usable without the 165 * host-facing part, which can't be device_add'ed, yet. 166 */ 167 dc->user_creatable = false; 168 } 169 170 static void sh_pcic_host_class_init(ObjectClass *klass, const void *data) 171 { 172 DeviceClass *dc = DEVICE_CLASS(klass); 173 174 dc->realize = sh_pcic_host_realize; 175 } 176 177 static const TypeInfo sh_pcic_types[] = { 178 { 179 .name = TYPE_SH_PCI_HOST_BRIDGE, 180 .parent = TYPE_PCI_HOST_BRIDGE, 181 .instance_size = sizeof(SHPCIState), 182 .class_init = sh_pcic_host_class_init, 183 }, { 184 .name = "sh_pci_host", 185 .parent = TYPE_PCI_DEVICE, 186 .instance_size = sizeof(PCIDevice), 187 .class_init = sh_pcic_pci_class_init, 188 .interfaces = (const InterfaceInfo[]) { 189 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 190 { }, 191 }, 192 }, 193 }; 194 195 DEFINE_TYPES(sh_pcic_types) 196