1 /* 2 * QEMU Ultrasparc Sabre PCI host (PBM) 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * Copyright (c) 2012,2013 Artyom Tarasenko 6 * Copyright (c) 2018 Mark Cave-Ayland 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "hw/sysbus.h" 29 #include "hw/pci/pci.h" 30 #include "hw/pci/pci_host.h" 31 #include "hw/pci/pci_bridge.h" 32 #include "hw/pci/pci_bus.h" 33 #include "hw/pci-bridge/simba.h" 34 #include "hw/pci-host/sabre.h" 35 #include "sysemu/sysemu.h" 36 #include "exec/address-spaces.h" 37 #include "qapi/error.h" 38 #include "qemu/log.h" 39 40 /* debug sabre */ 41 //#define DEBUG_SABRE 42 43 #ifdef DEBUG_SABRE 44 #define SABRE_DPRINTF(fmt, ...) \ 45 do { printf("sabre: " fmt , ## __VA_ARGS__); } while (0) 46 #else 47 #define SABRE_DPRINTF(fmt, ...) 48 #endif 49 50 /* 51 * Chipset docs: 52 * PBM: "UltraSPARC IIi User's Manual", 53 * http://www.sun.com/processors/manuals/805-0087.pdf 54 */ 55 56 #define PBM_PCI_IMR_MASK 0x7fffffff 57 #define PBM_PCI_IMR_ENABLED 0x80000000 58 59 #define POR (1U << 31) 60 #define SOFT_POR (1U << 30) 61 #define SOFT_XIR (1U << 29) 62 #define BTN_POR (1U << 28) 63 #define BTN_XIR (1U << 27) 64 #define RESET_MASK 0xf8000000 65 #define RESET_WCMASK 0x98000000 66 #define RESET_WMASK 0x60000000 67 68 #define NO_IRQ_REQUEST (MAX_IVEC + 1) 69 70 static inline void sabre_set_request(SabreState *s, unsigned int irq_num) 71 { 72 SABRE_DPRINTF("%s: request irq %d\n", __func__, irq_num); 73 74 s->irq_request = irq_num; 75 qemu_set_irq(s->ivec_irqs[irq_num], 1); 76 } 77 78 static inline void sabre_check_irqs(SabreState *s) 79 { 80 unsigned int i; 81 82 /* Previous request is not acknowledged, resubmit */ 83 if (s->irq_request != NO_IRQ_REQUEST) { 84 sabre_set_request(s, s->irq_request); 85 return; 86 } 87 /* no request pending */ 88 if (s->pci_irq_in == 0ULL) { 89 return; 90 } 91 for (i = 0; i < 32; i++) { 92 if (s->pci_irq_in & (1ULL << i)) { 93 if (s->pci_irq_map[i >> 2] & PBM_PCI_IMR_ENABLED) { 94 sabre_set_request(s, i); 95 return; 96 } 97 } 98 } 99 for (i = 32; i < 64; i++) { 100 if (s->pci_irq_in & (1ULL << i)) { 101 if (s->obio_irq_map[i - 32] & PBM_PCI_IMR_ENABLED) { 102 sabre_set_request(s, i); 103 break; 104 } 105 } 106 } 107 } 108 109 static inline void sabre_clear_request(SabreState *s, unsigned int irq_num) 110 { 111 SABRE_DPRINTF("%s: clear request irq %d\n", __func__, irq_num); 112 qemu_set_irq(s->ivec_irqs[irq_num], 0); 113 s->irq_request = NO_IRQ_REQUEST; 114 } 115 116 static AddressSpace *sabre_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn) 117 { 118 IOMMUState *is = opaque; 119 120 return &is->iommu_as; 121 } 122 123 static void sabre_config_write(void *opaque, hwaddr addr, 124 uint64_t val, unsigned size) 125 { 126 SabreState *s = opaque; 127 128 SABRE_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func__, 129 addr, val); 130 131 switch (addr & 0xffff) { 132 case 0x30 ... 0x4f: /* DMA error registers */ 133 /* XXX: not implemented yet */ 134 break; 135 case 0xc00 ... 0xc3f: /* PCI interrupt control */ 136 if (addr & 4) { 137 unsigned int ino = (addr & 0x3f) >> 3; 138 s->pci_irq_map[ino] &= PBM_PCI_IMR_MASK; 139 s->pci_irq_map[ino] |= val & ~PBM_PCI_IMR_MASK; 140 if ((s->irq_request == ino) && !(val & ~PBM_PCI_IMR_MASK)) { 141 sabre_clear_request(s, ino); 142 } 143 sabre_check_irqs(s); 144 } 145 break; 146 case 0x1000 ... 0x107f: /* OBIO interrupt control */ 147 if (addr & 4) { 148 unsigned int ino = ((addr & 0xff) >> 3); 149 s->obio_irq_map[ino] &= PBM_PCI_IMR_MASK; 150 s->obio_irq_map[ino] |= val & ~PBM_PCI_IMR_MASK; 151 if ((s->irq_request == (ino | 0x20)) 152 && !(val & ~PBM_PCI_IMR_MASK)) { 153 sabre_clear_request(s, ino | 0x20); 154 } 155 sabre_check_irqs(s); 156 } 157 break; 158 case 0x1400 ... 0x14ff: /* PCI interrupt clear */ 159 if (addr & 4) { 160 unsigned int ino = (addr & 0xff) >> 5; 161 if ((s->irq_request / 4) == ino) { 162 sabre_clear_request(s, s->irq_request); 163 sabre_check_irqs(s); 164 } 165 } 166 break; 167 case 0x1800 ... 0x1860: /* OBIO interrupt clear */ 168 if (addr & 4) { 169 unsigned int ino = ((addr & 0xff) >> 3) | 0x20; 170 if (s->irq_request == ino) { 171 sabre_clear_request(s, ino); 172 sabre_check_irqs(s); 173 } 174 } 175 break; 176 case 0x2000 ... 0x202f: /* PCI control */ 177 s->pci_control[(addr & 0x3f) >> 2] = val; 178 break; 179 case 0xf020 ... 0xf027: /* Reset control */ 180 if (addr & 4) { 181 val &= RESET_MASK; 182 s->reset_control &= ~(val & RESET_WCMASK); 183 s->reset_control |= val & RESET_WMASK; 184 if (val & SOFT_POR) { 185 s->nr_resets = 0; 186 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 187 } else if (val & SOFT_XIR) { 188 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 189 } 190 } 191 break; 192 case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */ 193 case 0xa400 ... 0xa67f: /* IOMMU diagnostics */ 194 case 0xa800 ... 0xa80f: /* Interrupt diagnostics */ 195 case 0xf000 ... 0xf01f: /* FFB config, memory control */ 196 /* we don't care */ 197 default: 198 break; 199 } 200 } 201 202 static uint64_t sabre_config_read(void *opaque, 203 hwaddr addr, unsigned size) 204 { 205 SabreState *s = opaque; 206 uint32_t val; 207 208 switch (addr & 0xffff) { 209 case 0x30 ... 0x4f: /* DMA error registers */ 210 val = 0; 211 /* XXX: not implemented yet */ 212 break; 213 case 0xc00 ... 0xc3f: /* PCI interrupt control */ 214 if (addr & 4) { 215 val = s->pci_irq_map[(addr & 0x3f) >> 3]; 216 } else { 217 val = 0; 218 } 219 break; 220 case 0x1000 ... 0x107f: /* OBIO interrupt control */ 221 if (addr & 4) { 222 val = s->obio_irq_map[(addr & 0xff) >> 3]; 223 } else { 224 val = 0; 225 } 226 break; 227 case 0x1080 ... 0x108f: /* PCI bus error */ 228 if (addr & 4) { 229 val = s->pci_err_irq_map[(addr & 0xf) >> 3]; 230 } else { 231 val = 0; 232 } 233 break; 234 case 0x2000 ... 0x202f: /* PCI control */ 235 val = s->pci_control[(addr & 0x3f) >> 2]; 236 break; 237 case 0xf020 ... 0xf027: /* Reset control */ 238 if (addr & 4) { 239 val = s->reset_control; 240 } else { 241 val = 0; 242 } 243 break; 244 case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */ 245 case 0xa400 ... 0xa67f: /* IOMMU diagnostics */ 246 case 0xa800 ... 0xa80f: /* Interrupt diagnostics */ 247 case 0xf000 ... 0xf01f: /* FFB config, memory control */ 248 /* we don't care */ 249 default: 250 val = 0; 251 break; 252 } 253 SABRE_DPRINTF("%s: addr " TARGET_FMT_plx " -> %x\n", __func__, addr, val); 254 255 return val; 256 } 257 258 static const MemoryRegionOps sabre_config_ops = { 259 .read = sabre_config_read, 260 .write = sabre_config_write, 261 .endianness = DEVICE_BIG_ENDIAN, 262 }; 263 264 static void sabre_pci_config_write(void *opaque, hwaddr addr, 265 uint64_t val, unsigned size) 266 { 267 SabreState *s = opaque; 268 PCIHostState *phb = PCI_HOST_BRIDGE(s); 269 270 SABRE_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func__, 271 addr, val); 272 pci_data_write(phb->bus, addr, val, size); 273 } 274 275 static uint64_t sabre_pci_config_read(void *opaque, hwaddr addr, 276 unsigned size) 277 { 278 uint32_t ret; 279 SabreState *s = opaque; 280 PCIHostState *phb = PCI_HOST_BRIDGE(s); 281 282 ret = pci_data_read(phb->bus, addr, size); 283 SABRE_DPRINTF("%s: addr " TARGET_FMT_plx " -> %x\n", __func__, addr, ret); 284 return ret; 285 } 286 287 /* The sabre host has an IRQ line for each IRQ line of each slot. */ 288 static int pci_sabre_map_irq(PCIDevice *pci_dev, int irq_num) 289 { 290 /* Return the irq as swizzled by the PBM */ 291 return irq_num; 292 } 293 294 static int pci_simbaA_map_irq(PCIDevice *pci_dev, int irq_num) 295 { 296 /* The on-board devices have fixed (legacy) OBIO intnos */ 297 switch (PCI_SLOT(pci_dev->devfn)) { 298 case 1: 299 /* Onboard NIC */ 300 return OBIO_NIC_IRQ; 301 case 3: 302 /* Onboard IDE */ 303 return OBIO_HDD_IRQ; 304 default: 305 /* Normal intno, fall through */ 306 break; 307 } 308 309 return ((PCI_SLOT(pci_dev->devfn) << 2) + irq_num) & 0x1f; 310 } 311 312 static int pci_simbaB_map_irq(PCIDevice *pci_dev, int irq_num) 313 { 314 return (0x10 + (PCI_SLOT(pci_dev->devfn) << 2) + irq_num) & 0x1f; 315 } 316 317 static void pci_sabre_set_irq(void *opaque, int irq_num, int level) 318 { 319 SabreState *s = opaque; 320 321 SABRE_DPRINTF("%s: set irq_in %d level %d\n", __func__, irq_num, level); 322 /* PCI IRQ map onto the first 32 INO. */ 323 if (irq_num < 32) { 324 if (level) { 325 s->pci_irq_in |= 1ULL << irq_num; 326 if (s->pci_irq_map[irq_num >> 2] & PBM_PCI_IMR_ENABLED) { 327 sabre_set_request(s, irq_num); 328 } 329 } else { 330 s->pci_irq_in &= ~(1ULL << irq_num); 331 } 332 } else { 333 /* OBIO IRQ map onto the next 32 INO. */ 334 if (level) { 335 SABRE_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num, 336 level); 337 s->pci_irq_in |= 1ULL << irq_num; 338 if ((s->irq_request == NO_IRQ_REQUEST) 339 && (s->obio_irq_map[irq_num - 32] & PBM_PCI_IMR_ENABLED)) { 340 sabre_set_request(s, irq_num); 341 } 342 } else { 343 s->pci_irq_in &= ~(1ULL << irq_num); 344 } 345 } 346 } 347 348 static void sabre_reset(DeviceState *d) 349 { 350 SabreState *s = SABRE_DEVICE(d); 351 PCIDevice *pci_dev; 352 unsigned int i; 353 uint16_t cmd; 354 355 for (i = 0; i < 8; i++) { 356 s->pci_irq_map[i] &= PBM_PCI_IMR_MASK; 357 } 358 for (i = 0; i < 32; i++) { 359 s->obio_irq_map[i] &= PBM_PCI_IMR_MASK; 360 } 361 362 s->irq_request = NO_IRQ_REQUEST; 363 s->pci_irq_in = 0ULL; 364 365 if (s->nr_resets++ == 0) { 366 /* Power on reset */ 367 s->reset_control = POR; 368 } 369 370 /* As this is the busA PCI bridge which contains the on-board devices 371 * attached to the ebus, ensure that we initially allow IO transactions 372 * so that we get the early serial console until OpenBIOS can properly 373 * configure the PCI bridge itself */ 374 pci_dev = PCI_DEVICE(s->bridgeA); 375 cmd = pci_get_word(pci_dev->config + PCI_COMMAND); 376 pci_set_word(pci_dev->config + PCI_COMMAND, cmd | PCI_COMMAND_IO); 377 pci_bridge_update_mappings(PCI_BRIDGE(pci_dev)); 378 } 379 380 static const MemoryRegionOps pci_config_ops = { 381 .read = sabre_pci_config_read, 382 .write = sabre_pci_config_write, 383 .endianness = DEVICE_LITTLE_ENDIAN, 384 }; 385 386 static void sabre_realize(DeviceState *dev, Error **errp) 387 { 388 SabreState *s = SABRE_DEVICE(dev); 389 PCIHostState *phb = PCI_HOST_BRIDGE(dev); 390 SysBusDevice *sbd = SYS_BUS_DEVICE(s); 391 PCIDevice *pci_dev; 392 393 /* sabre_config */ 394 sysbus_mmio_map(sbd, 0, s->special_base); 395 /* PCI configuration space */ 396 sysbus_mmio_map(sbd, 1, s->special_base + 0x1000000ULL); 397 /* pci_ioport */ 398 sysbus_mmio_map(sbd, 2, s->special_base + 0x2000000ULL); 399 400 memory_region_init(&s->pci_mmio, OBJECT(s), "pci-mmio", 0x100000000ULL); 401 memory_region_add_subregion(get_system_memory(), s->mem_base, 402 &s->pci_mmio); 403 404 phb->bus = pci_register_root_bus(dev, "pci", 405 pci_sabre_set_irq, pci_sabre_map_irq, s, 406 &s->pci_mmio, 407 &s->pci_ioport, 408 0, 32, TYPE_PCI_BUS); 409 410 pci_create_simple(phb->bus, 0, TYPE_SABRE_PCI_DEVICE); 411 412 /* IOMMU */ 413 memory_region_add_subregion_overlap(&s->sabre_config, 0x200, 414 sysbus_mmio_get_region(SYS_BUS_DEVICE(s->iommu), 0), 1); 415 pci_setup_iommu(phb->bus, sabre_pci_dma_iommu, s->iommu); 416 417 /* APB secondary busses */ 418 pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 0), true, 419 TYPE_SIMBA_PCI_BRIDGE); 420 s->bridgeB = PCI_BRIDGE(pci_dev); 421 pci_bridge_map_irq(s->bridgeB, "pciB", pci_simbaB_map_irq); 422 qdev_init_nofail(&pci_dev->qdev); 423 424 pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 1), true, 425 TYPE_SIMBA_PCI_BRIDGE); 426 s->bridgeA = PCI_BRIDGE(pci_dev); 427 pci_bridge_map_irq(s->bridgeA, "pciA", pci_simbaA_map_irq); 428 qdev_init_nofail(&pci_dev->qdev); 429 } 430 431 static void sabre_init(Object *obj) 432 { 433 SabreState *s = SABRE_DEVICE(obj); 434 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 435 unsigned int i; 436 437 for (i = 0; i < 8; i++) { 438 s->pci_irq_map[i] = (0x1f << 6) | (i << 2); 439 } 440 for (i = 0; i < 2; i++) { 441 s->pci_err_irq_map[i] = (0x1f << 6) | 0x30; 442 } 443 for (i = 0; i < 32; i++) { 444 s->obio_irq_map[i] = ((0x1f << 6) | 0x20) + i; 445 } 446 qdev_init_gpio_in_named(DEVICE(s), pci_sabre_set_irq, "pbm-irq", MAX_IVEC); 447 qdev_init_gpio_out_named(DEVICE(s), s->ivec_irqs, "ivec-irq", MAX_IVEC); 448 s->irq_request = NO_IRQ_REQUEST; 449 s->pci_irq_in = 0ULL; 450 451 /* IOMMU */ 452 object_property_add_link(obj, "iommu", TYPE_SUN4U_IOMMU, 453 (Object **) &s->iommu, 454 qdev_prop_allow_set_link_before_realize, 455 0, NULL); 456 457 /* sabre_config */ 458 memory_region_init_io(&s->sabre_config, OBJECT(s), &sabre_config_ops, s, 459 "sabre-config", 0x10000); 460 /* at region 0 */ 461 sysbus_init_mmio(sbd, &s->sabre_config); 462 463 memory_region_init_io(&s->pci_config, OBJECT(s), &pci_config_ops, s, 464 "sabre-pci-config", 0x1000000); 465 /* at region 1 */ 466 sysbus_init_mmio(sbd, &s->pci_config); 467 468 /* pci_ioport */ 469 memory_region_init(&s->pci_ioport, OBJECT(s), "sabre-pci-ioport", 470 0x1000000); 471 472 /* at region 2 */ 473 sysbus_init_mmio(sbd, &s->pci_ioport); 474 } 475 476 static void sabre_pci_realize(PCIDevice *d, Error **errp) 477 { 478 pci_set_word(d->config + PCI_COMMAND, 479 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 480 pci_set_word(d->config + PCI_STATUS, 481 PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ | 482 PCI_STATUS_DEVSEL_MEDIUM); 483 } 484 485 static void sabre_pci_class_init(ObjectClass *klass, void *data) 486 { 487 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 488 DeviceClass *dc = DEVICE_CLASS(klass); 489 490 k->realize = sabre_pci_realize; 491 k->vendor_id = PCI_VENDOR_ID_SUN; 492 k->device_id = PCI_DEVICE_ID_SUN_SABRE; 493 k->class_id = PCI_CLASS_BRIDGE_HOST; 494 /* 495 * PCI-facing part of the host bridge, not usable without the 496 * host-facing part, which can't be device_add'ed, yet. 497 */ 498 dc->user_creatable = false; 499 } 500 501 static const TypeInfo sabre_pci_info = { 502 .name = TYPE_SABRE_PCI_DEVICE, 503 .parent = TYPE_PCI_DEVICE, 504 .instance_size = sizeof(SabrePCIState), 505 .class_init = sabre_pci_class_init, 506 .interfaces = (InterfaceInfo[]) { 507 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 508 { }, 509 }, 510 }; 511 512 static Property sabre_properties[] = { 513 DEFINE_PROP_UINT64("special-base", SabreState, special_base, 0), 514 DEFINE_PROP_UINT64("mem-base", SabreState, mem_base, 0), 515 DEFINE_PROP_END_OF_LIST(), 516 }; 517 518 static void sabre_class_init(ObjectClass *klass, void *data) 519 { 520 DeviceClass *dc = DEVICE_CLASS(klass); 521 522 dc->realize = sabre_realize; 523 dc->reset = sabre_reset; 524 dc->props = sabre_properties; 525 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 526 } 527 528 static const TypeInfo sabre_info = { 529 .name = TYPE_SABRE, 530 .parent = TYPE_PCI_HOST_BRIDGE, 531 .instance_size = sizeof(SabreState), 532 .instance_init = sabre_init, 533 .class_init = sabre_class_init, 534 }; 535 536 static void sabre_register_types(void) 537 { 538 type_register_static(&sabre_info); 539 type_register_static(&sabre_pci_info); 540 } 541 542 type_init(sabre_register_types) 543