1 /* 2 * QEMU Ultrasparc Sabre PCI host (PBM) 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * Copyright (c) 2012,2013 Artyom Tarasenko 6 * Copyright (c) 2018 Mark Cave-Ayland 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "hw/sysbus.h" 29 #include "hw/pci/pci.h" 30 #include "hw/pci/pci_host.h" 31 #include "hw/qdev-properties.h" 32 #include "hw/pci/pci_bridge.h" 33 #include "hw/pci/pci_bus.h" 34 #include "hw/irq.h" 35 #include "hw/pci-bridge/simba.h" 36 #include "hw/pci-host/sabre.h" 37 #include "exec/address-spaces.h" 38 #include "qapi/error.h" 39 #include "qemu/log.h" 40 #include "qemu/module.h" 41 #include "sysemu/runstate.h" 42 #include "trace.h" 43 44 /* 45 * Chipset docs: 46 * PBM: "UltraSPARC IIi User's Manual", 47 * http://www.sun.com/processors/manuals/805-0087.pdf 48 */ 49 50 #define PBM_PCI_IMR_MASK 0x7fffffff 51 #define PBM_PCI_IMR_ENABLED 0x80000000 52 53 #define POR (1U << 31) 54 #define SOFT_POR (1U << 30) 55 #define SOFT_XIR (1U << 29) 56 #define BTN_POR (1U << 28) 57 #define BTN_XIR (1U << 27) 58 #define RESET_MASK 0xf8000000 59 #define RESET_WCMASK 0x98000000 60 #define RESET_WMASK 0x60000000 61 62 #define NO_IRQ_REQUEST (MAX_IVEC + 1) 63 64 static inline void sabre_set_request(SabreState *s, unsigned int irq_num) 65 { 66 trace_sabre_set_request(irq_num); 67 s->irq_request = irq_num; 68 qemu_set_irq(s->ivec_irqs[irq_num], 1); 69 } 70 71 static inline void sabre_check_irqs(SabreState *s) 72 { 73 unsigned int i; 74 75 /* Previous request is not acknowledged, resubmit */ 76 if (s->irq_request != NO_IRQ_REQUEST) { 77 sabre_set_request(s, s->irq_request); 78 return; 79 } 80 /* no request pending */ 81 if (s->pci_irq_in == 0ULL) { 82 return; 83 } 84 for (i = 0; i < 32; i++) { 85 if (s->pci_irq_in & (1ULL << i)) { 86 if (s->pci_irq_map[i >> 2] & PBM_PCI_IMR_ENABLED) { 87 sabre_set_request(s, i); 88 return; 89 } 90 } 91 } 92 for (i = 32; i < 64; i++) { 93 if (s->pci_irq_in & (1ULL << i)) { 94 if (s->obio_irq_map[i - 32] & PBM_PCI_IMR_ENABLED) { 95 sabre_set_request(s, i); 96 break; 97 } 98 } 99 } 100 } 101 102 static inline void sabre_clear_request(SabreState *s, unsigned int irq_num) 103 { 104 trace_sabre_clear_request(irq_num); 105 qemu_set_irq(s->ivec_irqs[irq_num], 0); 106 s->irq_request = NO_IRQ_REQUEST; 107 } 108 109 static AddressSpace *sabre_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn) 110 { 111 IOMMUState *is = opaque; 112 113 return &is->iommu_as; 114 } 115 116 static void sabre_config_write(void *opaque, hwaddr addr, 117 uint64_t val, unsigned size) 118 { 119 SabreState *s = opaque; 120 121 trace_sabre_config_write(addr, val); 122 123 switch (addr & 0xffff) { 124 case 0x30 ... 0x4f: /* DMA error registers */ 125 /* XXX: not implemented yet */ 126 break; 127 case 0xc00 ... 0xc3f: /* PCI interrupt control */ 128 if (addr & 4) { 129 unsigned int ino = (addr & 0x3f) >> 3; 130 s->pci_irq_map[ino] &= PBM_PCI_IMR_MASK; 131 s->pci_irq_map[ino] |= val & ~PBM_PCI_IMR_MASK; 132 if ((s->irq_request == ino) && !(val & ~PBM_PCI_IMR_MASK)) { 133 sabre_clear_request(s, ino); 134 } 135 sabre_check_irqs(s); 136 } 137 break; 138 case 0x1000 ... 0x107f: /* OBIO interrupt control */ 139 if (addr & 4) { 140 unsigned int ino = ((addr & 0xff) >> 3); 141 s->obio_irq_map[ino] &= PBM_PCI_IMR_MASK; 142 s->obio_irq_map[ino] |= val & ~PBM_PCI_IMR_MASK; 143 if ((s->irq_request == (ino | 0x20)) 144 && !(val & ~PBM_PCI_IMR_MASK)) { 145 sabre_clear_request(s, ino | 0x20); 146 } 147 sabre_check_irqs(s); 148 } 149 break; 150 case 0x1400 ... 0x14ff: /* PCI interrupt clear */ 151 if (addr & 4) { 152 unsigned int ino = (addr & 0xff) >> 5; 153 if ((s->irq_request / 4) == ino) { 154 sabre_clear_request(s, s->irq_request); 155 sabre_check_irqs(s); 156 } 157 } 158 break; 159 case 0x1800 ... 0x1860: /* OBIO interrupt clear */ 160 if (addr & 4) { 161 unsigned int ino = ((addr & 0xff) >> 3) | 0x20; 162 if (s->irq_request == ino) { 163 sabre_clear_request(s, ino); 164 sabre_check_irqs(s); 165 } 166 } 167 break; 168 case 0x2000 ... 0x202f: /* PCI control */ 169 s->pci_control[(addr & 0x3f) >> 2] = val; 170 break; 171 case 0xf020 ... 0xf027: /* Reset control */ 172 if (addr & 4) { 173 val &= RESET_MASK; 174 s->reset_control &= ~(val & RESET_WCMASK); 175 s->reset_control |= val & RESET_WMASK; 176 if (val & SOFT_POR) { 177 s->nr_resets = 0; 178 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 179 } else if (val & SOFT_XIR) { 180 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 181 } 182 } 183 break; 184 case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */ 185 case 0xa400 ... 0xa67f: /* IOMMU diagnostics */ 186 case 0xa800 ... 0xa80f: /* Interrupt diagnostics */ 187 case 0xf000 ... 0xf01f: /* FFB config, memory control */ 188 /* we don't care */ 189 default: 190 break; 191 } 192 } 193 194 static uint64_t sabre_config_read(void *opaque, 195 hwaddr addr, unsigned size) 196 { 197 SabreState *s = opaque; 198 uint32_t val; 199 200 switch (addr & 0xffff) { 201 case 0x30 ... 0x4f: /* DMA error registers */ 202 val = 0; 203 /* XXX: not implemented yet */ 204 break; 205 case 0xc00 ... 0xc3f: /* PCI interrupt control */ 206 if (addr & 4) { 207 val = s->pci_irq_map[(addr & 0x3f) >> 3]; 208 } else { 209 val = 0; 210 } 211 break; 212 case 0x1000 ... 0x107f: /* OBIO interrupt control */ 213 if (addr & 4) { 214 val = s->obio_irq_map[(addr & 0xff) >> 3]; 215 } else { 216 val = 0; 217 } 218 break; 219 case 0x1080 ... 0x108f: /* PCI bus error */ 220 if (addr & 4) { 221 val = s->pci_err_irq_map[(addr & 0xf) >> 3]; 222 } else { 223 val = 0; 224 } 225 break; 226 case 0x2000 ... 0x202f: /* PCI control */ 227 val = s->pci_control[(addr & 0x3f) >> 2]; 228 break; 229 case 0xf020 ... 0xf027: /* Reset control */ 230 if (addr & 4) { 231 val = s->reset_control; 232 } else { 233 val = 0; 234 } 235 break; 236 case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */ 237 case 0xa400 ... 0xa67f: /* IOMMU diagnostics */ 238 case 0xa800 ... 0xa80f: /* Interrupt diagnostics */ 239 case 0xf000 ... 0xf01f: /* FFB config, memory control */ 240 /* we don't care */ 241 default: 242 val = 0; 243 break; 244 } 245 trace_sabre_config_read(addr, val); 246 247 return val; 248 } 249 250 static const MemoryRegionOps sabre_config_ops = { 251 .read = sabre_config_read, 252 .write = sabre_config_write, 253 .endianness = DEVICE_BIG_ENDIAN, 254 }; 255 256 static void sabre_pci_config_write(void *opaque, hwaddr addr, 257 uint64_t val, unsigned size) 258 { 259 SabreState *s = opaque; 260 PCIHostState *phb = PCI_HOST_BRIDGE(s); 261 262 trace_sabre_pci_config_write(addr, val); 263 pci_data_write(phb->bus, addr, val, size); 264 } 265 266 static uint64_t sabre_pci_config_read(void *opaque, hwaddr addr, 267 unsigned size) 268 { 269 uint32_t ret; 270 SabreState *s = opaque; 271 PCIHostState *phb = PCI_HOST_BRIDGE(s); 272 273 ret = pci_data_read(phb->bus, addr, size); 274 trace_sabre_pci_config_read(addr, ret); 275 return ret; 276 } 277 278 /* The sabre host has an IRQ line for each IRQ line of each slot. */ 279 static int pci_sabre_map_irq(PCIDevice *pci_dev, int irq_num) 280 { 281 /* Return the irq as swizzled by the PBM */ 282 return irq_num; 283 } 284 285 static int pci_simbaA_map_irq(PCIDevice *pci_dev, int irq_num) 286 { 287 /* The on-board devices have fixed (legacy) OBIO intnos */ 288 switch (PCI_SLOT(pci_dev->devfn)) { 289 case 1: 290 /* Onboard NIC */ 291 return OBIO_NIC_IRQ; 292 case 3: 293 /* Onboard IDE */ 294 return OBIO_HDD_IRQ; 295 default: 296 /* Normal intno, fall through */ 297 break; 298 } 299 300 return ((PCI_SLOT(pci_dev->devfn) << 2) + irq_num) & 0x1f; 301 } 302 303 static int pci_simbaB_map_irq(PCIDevice *pci_dev, int irq_num) 304 { 305 return (0x10 + (PCI_SLOT(pci_dev->devfn) << 2) + irq_num) & 0x1f; 306 } 307 308 static void pci_sabre_set_irq(void *opaque, int irq_num, int level) 309 { 310 SabreState *s = opaque; 311 312 trace_sabre_pci_set_irq(irq_num, level); 313 314 /* PCI IRQ map onto the first 32 INO. */ 315 if (irq_num < 32) { 316 if (level) { 317 s->pci_irq_in |= 1ULL << irq_num; 318 if (s->pci_irq_map[irq_num >> 2] & PBM_PCI_IMR_ENABLED) { 319 sabre_set_request(s, irq_num); 320 } 321 } else { 322 s->pci_irq_in &= ~(1ULL << irq_num); 323 } 324 } else { 325 /* OBIO IRQ map onto the next 32 INO. */ 326 if (level) { 327 trace_sabre_pci_set_obio_irq(irq_num, level); 328 s->pci_irq_in |= 1ULL << irq_num; 329 if ((s->irq_request == NO_IRQ_REQUEST) 330 && (s->obio_irq_map[irq_num - 32] & PBM_PCI_IMR_ENABLED)) { 331 sabre_set_request(s, irq_num); 332 } 333 } else { 334 s->pci_irq_in &= ~(1ULL << irq_num); 335 } 336 } 337 } 338 339 static void sabre_reset(DeviceState *d) 340 { 341 SabreState *s = SABRE_DEVICE(d); 342 PCIDevice *pci_dev; 343 unsigned int i; 344 uint16_t cmd; 345 346 for (i = 0; i < 8; i++) { 347 s->pci_irq_map[i] &= PBM_PCI_IMR_MASK; 348 } 349 for (i = 0; i < 32; i++) { 350 s->obio_irq_map[i] &= PBM_PCI_IMR_MASK; 351 } 352 353 s->irq_request = NO_IRQ_REQUEST; 354 s->pci_irq_in = 0ULL; 355 356 if (s->nr_resets++ == 0) { 357 /* Power on reset */ 358 s->reset_control = POR; 359 } 360 361 /* As this is the busA PCI bridge which contains the on-board devices 362 * attached to the ebus, ensure that we initially allow IO transactions 363 * so that we get the early serial console until OpenBIOS can properly 364 * configure the PCI bridge itself */ 365 pci_dev = PCI_DEVICE(s->bridgeA); 366 cmd = pci_get_word(pci_dev->config + PCI_COMMAND); 367 pci_set_word(pci_dev->config + PCI_COMMAND, cmd | PCI_COMMAND_IO); 368 pci_bridge_update_mappings(PCI_BRIDGE(pci_dev)); 369 } 370 371 static const MemoryRegionOps pci_config_ops = { 372 .read = sabre_pci_config_read, 373 .write = sabre_pci_config_write, 374 .endianness = DEVICE_LITTLE_ENDIAN, 375 }; 376 377 static void sabre_realize(DeviceState *dev, Error **errp) 378 { 379 SabreState *s = SABRE_DEVICE(dev); 380 PCIHostState *phb = PCI_HOST_BRIDGE(dev); 381 SysBusDevice *sbd = SYS_BUS_DEVICE(s); 382 PCIDevice *pci_dev; 383 384 /* sabre_config */ 385 sysbus_mmio_map(sbd, 0, s->special_base); 386 /* PCI configuration space */ 387 sysbus_mmio_map(sbd, 1, s->special_base + 0x1000000ULL); 388 /* pci_ioport */ 389 sysbus_mmio_map(sbd, 2, s->special_base + 0x2000000ULL); 390 391 memory_region_init(&s->pci_mmio, OBJECT(s), "pci-mmio", 0x100000000ULL); 392 memory_region_add_subregion(get_system_memory(), s->mem_base, 393 &s->pci_mmio); 394 395 phb->bus = pci_register_root_bus(dev, "pci", 396 pci_sabre_set_irq, pci_sabre_map_irq, s, 397 &s->pci_mmio, 398 &s->pci_ioport, 399 0, 32, TYPE_PCI_BUS); 400 401 pci_create_simple(phb->bus, 0, TYPE_SABRE_PCI_DEVICE); 402 403 /* IOMMU */ 404 memory_region_add_subregion_overlap(&s->sabre_config, 0x200, 405 sysbus_mmio_get_region(SYS_BUS_DEVICE(s->iommu), 0), 1); 406 pci_setup_iommu(phb->bus, sabre_pci_dma_iommu, s->iommu); 407 408 /* APB secondary busses */ 409 pci_dev = pci_new_multifunction(PCI_DEVFN(1, 0), true, 410 TYPE_SIMBA_PCI_BRIDGE); 411 s->bridgeB = PCI_BRIDGE(pci_dev); 412 pci_bridge_map_irq(s->bridgeB, "pciB", pci_simbaB_map_irq); 413 pci_realize_and_unref(pci_dev, phb->bus, &error_fatal); 414 415 pci_dev = pci_new_multifunction(PCI_DEVFN(1, 1), true, 416 TYPE_SIMBA_PCI_BRIDGE); 417 s->bridgeA = PCI_BRIDGE(pci_dev); 418 pci_bridge_map_irq(s->bridgeA, "pciA", pci_simbaA_map_irq); 419 pci_realize_and_unref(pci_dev, phb->bus, &error_fatal); 420 } 421 422 static void sabre_init(Object *obj) 423 { 424 SabreState *s = SABRE_DEVICE(obj); 425 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 426 unsigned int i; 427 428 for (i = 0; i < 8; i++) { 429 s->pci_irq_map[i] = (0x1f << 6) | (i << 2); 430 } 431 for (i = 0; i < 2; i++) { 432 s->pci_err_irq_map[i] = (0x1f << 6) | 0x30; 433 } 434 for (i = 0; i < 32; i++) { 435 s->obio_irq_map[i] = ((0x1f << 6) | 0x20) + i; 436 } 437 qdev_init_gpio_in_named(DEVICE(s), pci_sabre_set_irq, "pbm-irq", MAX_IVEC); 438 qdev_init_gpio_out_named(DEVICE(s), s->ivec_irqs, "ivec-irq", MAX_IVEC); 439 s->irq_request = NO_IRQ_REQUEST; 440 s->pci_irq_in = 0ULL; 441 442 /* IOMMU */ 443 object_property_add_link(obj, "iommu", TYPE_SUN4U_IOMMU, 444 (Object **) &s->iommu, 445 qdev_prop_allow_set_link_before_realize, 446 0); 447 448 /* sabre_config */ 449 memory_region_init_io(&s->sabre_config, OBJECT(s), &sabre_config_ops, s, 450 "sabre-config", 0x10000); 451 /* at region 0 */ 452 sysbus_init_mmio(sbd, &s->sabre_config); 453 454 memory_region_init_io(&s->pci_config, OBJECT(s), &pci_config_ops, s, 455 "sabre-pci-config", 0x1000000); 456 /* at region 1 */ 457 sysbus_init_mmio(sbd, &s->pci_config); 458 459 /* pci_ioport */ 460 memory_region_init(&s->pci_ioport, OBJECT(s), "sabre-pci-ioport", 461 0x1000000); 462 463 /* at region 2 */ 464 sysbus_init_mmio(sbd, &s->pci_ioport); 465 } 466 467 static void sabre_pci_realize(PCIDevice *d, Error **errp) 468 { 469 pci_set_word(d->config + PCI_COMMAND, 470 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 471 pci_set_word(d->config + PCI_STATUS, 472 PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ | 473 PCI_STATUS_DEVSEL_MEDIUM); 474 } 475 476 static void sabre_pci_class_init(ObjectClass *klass, void *data) 477 { 478 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 479 DeviceClass *dc = DEVICE_CLASS(klass); 480 481 k->realize = sabre_pci_realize; 482 k->vendor_id = PCI_VENDOR_ID_SUN; 483 k->device_id = PCI_DEVICE_ID_SUN_SABRE; 484 k->class_id = PCI_CLASS_BRIDGE_HOST; 485 /* 486 * PCI-facing part of the host bridge, not usable without the 487 * host-facing part, which can't be device_add'ed, yet. 488 */ 489 dc->user_creatable = false; 490 } 491 492 static const TypeInfo sabre_pci_info = { 493 .name = TYPE_SABRE_PCI_DEVICE, 494 .parent = TYPE_PCI_DEVICE, 495 .instance_size = sizeof(SabrePCIState), 496 .class_init = sabre_pci_class_init, 497 .interfaces = (InterfaceInfo[]) { 498 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 499 { }, 500 }, 501 }; 502 503 static char *sabre_ofw_unit_address(const SysBusDevice *dev) 504 { 505 SabreState *s = SABRE_DEVICE(dev); 506 507 return g_strdup_printf("%x,%x", 508 (uint32_t)((s->special_base >> 32) & 0xffffffff), 509 (uint32_t)(s->special_base & 0xffffffff)); 510 } 511 512 static Property sabre_properties[] = { 513 DEFINE_PROP_UINT64("special-base", SabreState, special_base, 0), 514 DEFINE_PROP_UINT64("mem-base", SabreState, mem_base, 0), 515 DEFINE_PROP_END_OF_LIST(), 516 }; 517 518 static void sabre_class_init(ObjectClass *klass, void *data) 519 { 520 DeviceClass *dc = DEVICE_CLASS(klass); 521 SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass); 522 523 dc->realize = sabre_realize; 524 dc->reset = sabre_reset; 525 device_class_set_props(dc, sabre_properties); 526 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 527 dc->fw_name = "pci"; 528 sbc->explicit_ofw_unit_address = sabre_ofw_unit_address; 529 } 530 531 static const TypeInfo sabre_info = { 532 .name = TYPE_SABRE, 533 .parent = TYPE_PCI_HOST_BRIDGE, 534 .instance_size = sizeof(SabreState), 535 .instance_init = sabre_init, 536 .class_init = sabre_class_init, 537 }; 538 539 static void sabre_register_types(void) 540 { 541 type_register_static(&sabre_info); 542 type_register_static(&sabre_pci_info); 543 } 544 545 type_init(sabre_register_types) 546