1 /* 2 * QEMU Ultrasparc Sabre PCI host (PBM) 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * Copyright (c) 2012,2013 Artyom Tarasenko 6 * Copyright (c) 2018 Mark Cave-Ayland 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "hw/sysbus.h" 29 #include "hw/pci/pci.h" 30 #include "hw/pci/pci_host.h" 31 #include "hw/pci/pci_bridge.h" 32 #include "hw/pci/pci_bus.h" 33 #include "hw/irq.h" 34 #include "hw/pci-bridge/simba.h" 35 #include "hw/pci-host/sabre.h" 36 #include "sysemu/sysemu.h" 37 #include "exec/address-spaces.h" 38 #include "qemu/log.h" 39 #include "qemu/module.h" 40 #include "trace.h" 41 42 /* 43 * Chipset docs: 44 * PBM: "UltraSPARC IIi User's Manual", 45 * http://www.sun.com/processors/manuals/805-0087.pdf 46 */ 47 48 #define PBM_PCI_IMR_MASK 0x7fffffff 49 #define PBM_PCI_IMR_ENABLED 0x80000000 50 51 #define POR (1U << 31) 52 #define SOFT_POR (1U << 30) 53 #define SOFT_XIR (1U << 29) 54 #define BTN_POR (1U << 28) 55 #define BTN_XIR (1U << 27) 56 #define RESET_MASK 0xf8000000 57 #define RESET_WCMASK 0x98000000 58 #define RESET_WMASK 0x60000000 59 60 #define NO_IRQ_REQUEST (MAX_IVEC + 1) 61 62 static inline void sabre_set_request(SabreState *s, unsigned int irq_num) 63 { 64 trace_sabre_set_request(irq_num); 65 s->irq_request = irq_num; 66 qemu_set_irq(s->ivec_irqs[irq_num], 1); 67 } 68 69 static inline void sabre_check_irqs(SabreState *s) 70 { 71 unsigned int i; 72 73 /* Previous request is not acknowledged, resubmit */ 74 if (s->irq_request != NO_IRQ_REQUEST) { 75 sabre_set_request(s, s->irq_request); 76 return; 77 } 78 /* no request pending */ 79 if (s->pci_irq_in == 0ULL) { 80 return; 81 } 82 for (i = 0; i < 32; i++) { 83 if (s->pci_irq_in & (1ULL << i)) { 84 if (s->pci_irq_map[i >> 2] & PBM_PCI_IMR_ENABLED) { 85 sabre_set_request(s, i); 86 return; 87 } 88 } 89 } 90 for (i = 32; i < 64; i++) { 91 if (s->pci_irq_in & (1ULL << i)) { 92 if (s->obio_irq_map[i - 32] & PBM_PCI_IMR_ENABLED) { 93 sabre_set_request(s, i); 94 break; 95 } 96 } 97 } 98 } 99 100 static inline void sabre_clear_request(SabreState *s, unsigned int irq_num) 101 { 102 trace_sabre_clear_request(irq_num); 103 qemu_set_irq(s->ivec_irqs[irq_num], 0); 104 s->irq_request = NO_IRQ_REQUEST; 105 } 106 107 static AddressSpace *sabre_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn) 108 { 109 IOMMUState *is = opaque; 110 111 return &is->iommu_as; 112 } 113 114 static void sabre_config_write(void *opaque, hwaddr addr, 115 uint64_t val, unsigned size) 116 { 117 SabreState *s = opaque; 118 119 trace_sabre_config_write(addr, val); 120 121 switch (addr & 0xffff) { 122 case 0x30 ... 0x4f: /* DMA error registers */ 123 /* XXX: not implemented yet */ 124 break; 125 case 0xc00 ... 0xc3f: /* PCI interrupt control */ 126 if (addr & 4) { 127 unsigned int ino = (addr & 0x3f) >> 3; 128 s->pci_irq_map[ino] &= PBM_PCI_IMR_MASK; 129 s->pci_irq_map[ino] |= val & ~PBM_PCI_IMR_MASK; 130 if ((s->irq_request == ino) && !(val & ~PBM_PCI_IMR_MASK)) { 131 sabre_clear_request(s, ino); 132 } 133 sabre_check_irqs(s); 134 } 135 break; 136 case 0x1000 ... 0x107f: /* OBIO interrupt control */ 137 if (addr & 4) { 138 unsigned int ino = ((addr & 0xff) >> 3); 139 s->obio_irq_map[ino] &= PBM_PCI_IMR_MASK; 140 s->obio_irq_map[ino] |= val & ~PBM_PCI_IMR_MASK; 141 if ((s->irq_request == (ino | 0x20)) 142 && !(val & ~PBM_PCI_IMR_MASK)) { 143 sabre_clear_request(s, ino | 0x20); 144 } 145 sabre_check_irqs(s); 146 } 147 break; 148 case 0x1400 ... 0x14ff: /* PCI interrupt clear */ 149 if (addr & 4) { 150 unsigned int ino = (addr & 0xff) >> 5; 151 if ((s->irq_request / 4) == ino) { 152 sabre_clear_request(s, s->irq_request); 153 sabre_check_irqs(s); 154 } 155 } 156 break; 157 case 0x1800 ... 0x1860: /* OBIO interrupt clear */ 158 if (addr & 4) { 159 unsigned int ino = ((addr & 0xff) >> 3) | 0x20; 160 if (s->irq_request == ino) { 161 sabre_clear_request(s, ino); 162 sabre_check_irqs(s); 163 } 164 } 165 break; 166 case 0x2000 ... 0x202f: /* PCI control */ 167 s->pci_control[(addr & 0x3f) >> 2] = val; 168 break; 169 case 0xf020 ... 0xf027: /* Reset control */ 170 if (addr & 4) { 171 val &= RESET_MASK; 172 s->reset_control &= ~(val & RESET_WCMASK); 173 s->reset_control |= val & RESET_WMASK; 174 if (val & SOFT_POR) { 175 s->nr_resets = 0; 176 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 177 } else if (val & SOFT_XIR) { 178 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 179 } 180 } 181 break; 182 case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */ 183 case 0xa400 ... 0xa67f: /* IOMMU diagnostics */ 184 case 0xa800 ... 0xa80f: /* Interrupt diagnostics */ 185 case 0xf000 ... 0xf01f: /* FFB config, memory control */ 186 /* we don't care */ 187 default: 188 break; 189 } 190 } 191 192 static uint64_t sabre_config_read(void *opaque, 193 hwaddr addr, unsigned size) 194 { 195 SabreState *s = opaque; 196 uint32_t val; 197 198 switch (addr & 0xffff) { 199 case 0x30 ... 0x4f: /* DMA error registers */ 200 val = 0; 201 /* XXX: not implemented yet */ 202 break; 203 case 0xc00 ... 0xc3f: /* PCI interrupt control */ 204 if (addr & 4) { 205 val = s->pci_irq_map[(addr & 0x3f) >> 3]; 206 } else { 207 val = 0; 208 } 209 break; 210 case 0x1000 ... 0x107f: /* OBIO interrupt control */ 211 if (addr & 4) { 212 val = s->obio_irq_map[(addr & 0xff) >> 3]; 213 } else { 214 val = 0; 215 } 216 break; 217 case 0x1080 ... 0x108f: /* PCI bus error */ 218 if (addr & 4) { 219 val = s->pci_err_irq_map[(addr & 0xf) >> 3]; 220 } else { 221 val = 0; 222 } 223 break; 224 case 0x2000 ... 0x202f: /* PCI control */ 225 val = s->pci_control[(addr & 0x3f) >> 2]; 226 break; 227 case 0xf020 ... 0xf027: /* Reset control */ 228 if (addr & 4) { 229 val = s->reset_control; 230 } else { 231 val = 0; 232 } 233 break; 234 case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */ 235 case 0xa400 ... 0xa67f: /* IOMMU diagnostics */ 236 case 0xa800 ... 0xa80f: /* Interrupt diagnostics */ 237 case 0xf000 ... 0xf01f: /* FFB config, memory control */ 238 /* we don't care */ 239 default: 240 val = 0; 241 break; 242 } 243 trace_sabre_config_read(addr, val); 244 245 return val; 246 } 247 248 static const MemoryRegionOps sabre_config_ops = { 249 .read = sabre_config_read, 250 .write = sabre_config_write, 251 .endianness = DEVICE_BIG_ENDIAN, 252 }; 253 254 static void sabre_pci_config_write(void *opaque, hwaddr addr, 255 uint64_t val, unsigned size) 256 { 257 SabreState *s = opaque; 258 PCIHostState *phb = PCI_HOST_BRIDGE(s); 259 260 trace_sabre_pci_config_write(addr, val); 261 pci_data_write(phb->bus, addr, val, size); 262 } 263 264 static uint64_t sabre_pci_config_read(void *opaque, hwaddr addr, 265 unsigned size) 266 { 267 uint32_t ret; 268 SabreState *s = opaque; 269 PCIHostState *phb = PCI_HOST_BRIDGE(s); 270 271 ret = pci_data_read(phb->bus, addr, size); 272 trace_sabre_pci_config_read(addr, ret); 273 return ret; 274 } 275 276 /* The sabre host has an IRQ line for each IRQ line of each slot. */ 277 static int pci_sabre_map_irq(PCIDevice *pci_dev, int irq_num) 278 { 279 /* Return the irq as swizzled by the PBM */ 280 return irq_num; 281 } 282 283 static int pci_simbaA_map_irq(PCIDevice *pci_dev, int irq_num) 284 { 285 /* The on-board devices have fixed (legacy) OBIO intnos */ 286 switch (PCI_SLOT(pci_dev->devfn)) { 287 case 1: 288 /* Onboard NIC */ 289 return OBIO_NIC_IRQ; 290 case 3: 291 /* Onboard IDE */ 292 return OBIO_HDD_IRQ; 293 default: 294 /* Normal intno, fall through */ 295 break; 296 } 297 298 return ((PCI_SLOT(pci_dev->devfn) << 2) + irq_num) & 0x1f; 299 } 300 301 static int pci_simbaB_map_irq(PCIDevice *pci_dev, int irq_num) 302 { 303 return (0x10 + (PCI_SLOT(pci_dev->devfn) << 2) + irq_num) & 0x1f; 304 } 305 306 static void pci_sabre_set_irq(void *opaque, int irq_num, int level) 307 { 308 SabreState *s = opaque; 309 310 trace_sabre_pci_set_irq(irq_num, level); 311 312 /* PCI IRQ map onto the first 32 INO. */ 313 if (irq_num < 32) { 314 if (level) { 315 s->pci_irq_in |= 1ULL << irq_num; 316 if (s->pci_irq_map[irq_num >> 2] & PBM_PCI_IMR_ENABLED) { 317 sabre_set_request(s, irq_num); 318 } 319 } else { 320 s->pci_irq_in &= ~(1ULL << irq_num); 321 } 322 } else { 323 /* OBIO IRQ map onto the next 32 INO. */ 324 if (level) { 325 trace_sabre_pci_set_obio_irq(irq_num, level); 326 s->pci_irq_in |= 1ULL << irq_num; 327 if ((s->irq_request == NO_IRQ_REQUEST) 328 && (s->obio_irq_map[irq_num - 32] & PBM_PCI_IMR_ENABLED)) { 329 sabre_set_request(s, irq_num); 330 } 331 } else { 332 s->pci_irq_in &= ~(1ULL << irq_num); 333 } 334 } 335 } 336 337 static void sabre_reset(DeviceState *d) 338 { 339 SabreState *s = SABRE_DEVICE(d); 340 PCIDevice *pci_dev; 341 unsigned int i; 342 uint16_t cmd; 343 344 for (i = 0; i < 8; i++) { 345 s->pci_irq_map[i] &= PBM_PCI_IMR_MASK; 346 } 347 for (i = 0; i < 32; i++) { 348 s->obio_irq_map[i] &= PBM_PCI_IMR_MASK; 349 } 350 351 s->irq_request = NO_IRQ_REQUEST; 352 s->pci_irq_in = 0ULL; 353 354 if (s->nr_resets++ == 0) { 355 /* Power on reset */ 356 s->reset_control = POR; 357 } 358 359 /* As this is the busA PCI bridge which contains the on-board devices 360 * attached to the ebus, ensure that we initially allow IO transactions 361 * so that we get the early serial console until OpenBIOS can properly 362 * configure the PCI bridge itself */ 363 pci_dev = PCI_DEVICE(s->bridgeA); 364 cmd = pci_get_word(pci_dev->config + PCI_COMMAND); 365 pci_set_word(pci_dev->config + PCI_COMMAND, cmd | PCI_COMMAND_IO); 366 pci_bridge_update_mappings(PCI_BRIDGE(pci_dev)); 367 } 368 369 static const MemoryRegionOps pci_config_ops = { 370 .read = sabre_pci_config_read, 371 .write = sabre_pci_config_write, 372 .endianness = DEVICE_LITTLE_ENDIAN, 373 }; 374 375 static void sabre_realize(DeviceState *dev, Error **errp) 376 { 377 SabreState *s = SABRE_DEVICE(dev); 378 PCIHostState *phb = PCI_HOST_BRIDGE(dev); 379 SysBusDevice *sbd = SYS_BUS_DEVICE(s); 380 PCIDevice *pci_dev; 381 382 /* sabre_config */ 383 sysbus_mmio_map(sbd, 0, s->special_base); 384 /* PCI configuration space */ 385 sysbus_mmio_map(sbd, 1, s->special_base + 0x1000000ULL); 386 /* pci_ioport */ 387 sysbus_mmio_map(sbd, 2, s->special_base + 0x2000000ULL); 388 389 memory_region_init(&s->pci_mmio, OBJECT(s), "pci-mmio", 0x100000000ULL); 390 memory_region_add_subregion(get_system_memory(), s->mem_base, 391 &s->pci_mmio); 392 393 phb->bus = pci_register_root_bus(dev, "pci", 394 pci_sabre_set_irq, pci_sabre_map_irq, s, 395 &s->pci_mmio, 396 &s->pci_ioport, 397 0, 32, TYPE_PCI_BUS); 398 399 pci_create_simple(phb->bus, 0, TYPE_SABRE_PCI_DEVICE); 400 401 /* IOMMU */ 402 memory_region_add_subregion_overlap(&s->sabre_config, 0x200, 403 sysbus_mmio_get_region(SYS_BUS_DEVICE(s->iommu), 0), 1); 404 pci_setup_iommu(phb->bus, sabre_pci_dma_iommu, s->iommu); 405 406 /* APB secondary busses */ 407 pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 0), true, 408 TYPE_SIMBA_PCI_BRIDGE); 409 s->bridgeB = PCI_BRIDGE(pci_dev); 410 pci_bridge_map_irq(s->bridgeB, "pciB", pci_simbaB_map_irq); 411 qdev_init_nofail(&pci_dev->qdev); 412 413 pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 1), true, 414 TYPE_SIMBA_PCI_BRIDGE); 415 s->bridgeA = PCI_BRIDGE(pci_dev); 416 pci_bridge_map_irq(s->bridgeA, "pciA", pci_simbaA_map_irq); 417 qdev_init_nofail(&pci_dev->qdev); 418 } 419 420 static void sabre_init(Object *obj) 421 { 422 SabreState *s = SABRE_DEVICE(obj); 423 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 424 unsigned int i; 425 426 for (i = 0; i < 8; i++) { 427 s->pci_irq_map[i] = (0x1f << 6) | (i << 2); 428 } 429 for (i = 0; i < 2; i++) { 430 s->pci_err_irq_map[i] = (0x1f << 6) | 0x30; 431 } 432 for (i = 0; i < 32; i++) { 433 s->obio_irq_map[i] = ((0x1f << 6) | 0x20) + i; 434 } 435 qdev_init_gpio_in_named(DEVICE(s), pci_sabre_set_irq, "pbm-irq", MAX_IVEC); 436 qdev_init_gpio_out_named(DEVICE(s), s->ivec_irqs, "ivec-irq", MAX_IVEC); 437 s->irq_request = NO_IRQ_REQUEST; 438 s->pci_irq_in = 0ULL; 439 440 /* IOMMU */ 441 object_property_add_link(obj, "iommu", TYPE_SUN4U_IOMMU, 442 (Object **) &s->iommu, 443 qdev_prop_allow_set_link_before_realize, 444 0, NULL); 445 446 /* sabre_config */ 447 memory_region_init_io(&s->sabre_config, OBJECT(s), &sabre_config_ops, s, 448 "sabre-config", 0x10000); 449 /* at region 0 */ 450 sysbus_init_mmio(sbd, &s->sabre_config); 451 452 memory_region_init_io(&s->pci_config, OBJECT(s), &pci_config_ops, s, 453 "sabre-pci-config", 0x1000000); 454 /* at region 1 */ 455 sysbus_init_mmio(sbd, &s->pci_config); 456 457 /* pci_ioport */ 458 memory_region_init(&s->pci_ioport, OBJECT(s), "sabre-pci-ioport", 459 0x1000000); 460 461 /* at region 2 */ 462 sysbus_init_mmio(sbd, &s->pci_ioport); 463 } 464 465 static void sabre_pci_realize(PCIDevice *d, Error **errp) 466 { 467 pci_set_word(d->config + PCI_COMMAND, 468 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 469 pci_set_word(d->config + PCI_STATUS, 470 PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ | 471 PCI_STATUS_DEVSEL_MEDIUM); 472 } 473 474 static void sabre_pci_class_init(ObjectClass *klass, void *data) 475 { 476 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 477 DeviceClass *dc = DEVICE_CLASS(klass); 478 479 k->realize = sabre_pci_realize; 480 k->vendor_id = PCI_VENDOR_ID_SUN; 481 k->device_id = PCI_DEVICE_ID_SUN_SABRE; 482 k->class_id = PCI_CLASS_BRIDGE_HOST; 483 /* 484 * PCI-facing part of the host bridge, not usable without the 485 * host-facing part, which can't be device_add'ed, yet. 486 */ 487 dc->user_creatable = false; 488 } 489 490 static const TypeInfo sabre_pci_info = { 491 .name = TYPE_SABRE_PCI_DEVICE, 492 .parent = TYPE_PCI_DEVICE, 493 .instance_size = sizeof(SabrePCIState), 494 .class_init = sabre_pci_class_init, 495 .interfaces = (InterfaceInfo[]) { 496 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 497 { }, 498 }, 499 }; 500 501 static char *sabre_ofw_unit_address(const SysBusDevice *dev) 502 { 503 SabreState *s = SABRE_DEVICE(dev); 504 505 return g_strdup_printf("%x,%x", 506 (uint32_t)((s->special_base >> 32) & 0xffffffff), 507 (uint32_t)(s->special_base & 0xffffffff)); 508 } 509 510 static Property sabre_properties[] = { 511 DEFINE_PROP_UINT64("special-base", SabreState, special_base, 0), 512 DEFINE_PROP_UINT64("mem-base", SabreState, mem_base, 0), 513 DEFINE_PROP_END_OF_LIST(), 514 }; 515 516 static void sabre_class_init(ObjectClass *klass, void *data) 517 { 518 DeviceClass *dc = DEVICE_CLASS(klass); 519 SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass); 520 521 dc->realize = sabre_realize; 522 dc->reset = sabre_reset; 523 dc->props = sabre_properties; 524 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 525 dc->fw_name = "pci"; 526 sbc->explicit_ofw_unit_address = sabre_ofw_unit_address; 527 } 528 529 static const TypeInfo sabre_info = { 530 .name = TYPE_SABRE, 531 .parent = TYPE_PCI_HOST_BRIDGE, 532 .instance_size = sizeof(SabreState), 533 .instance_init = sabre_init, 534 .class_init = sabre_class_init, 535 }; 536 537 static void sabre_register_types(void) 538 { 539 type_register_static(&sabre_info); 540 type_register_static(&sabre_pci_info); 541 } 542 543 type_init(sabre_register_types) 544