1 /* 2 * QEMU PREP PCI host 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * Copyright (c) 2011-2013 Andreas Färber 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "qemu/datadir.h" 28 #include "qemu/units.h" 29 #include "qemu/log.h" 30 #include "qapi/error.h" 31 #include "hw/pci/pci_device.h" 32 #include "hw/pci/pci_bus.h" 33 #include "hw/pci/pci_host.h" 34 #include "hw/qdev-properties.h" 35 #include "migration/vmstate.h" 36 #include "hw/intc/i8259.h" 37 #include "hw/irq.h" 38 #include "hw/loader.h" 39 #include "hw/or-irq.h" 40 #include "elf.h" 41 #include "qom/object.h" 42 43 #define TYPE_RAVEN_PCI_DEVICE "raven" 44 #define TYPE_RAVEN_PCI_HOST_BRIDGE "raven-pcihost" 45 46 OBJECT_DECLARE_SIMPLE_TYPE(RavenPCIState, RAVEN_PCI_DEVICE) 47 48 struct RavenPCIState { 49 PCIDevice dev; 50 51 uint32_t elf_machine; 52 char *bios_name; 53 MemoryRegion bios; 54 }; 55 56 typedef struct PRePPCIState PREPPCIState; 57 DECLARE_INSTANCE_CHECKER(PREPPCIState, RAVEN_PCI_HOST_BRIDGE, 58 TYPE_RAVEN_PCI_HOST_BRIDGE) 59 60 struct PRePPCIState { 61 PCIHostState parent_obj; 62 63 OrIRQState *or_irq; 64 qemu_irq pci_irqs[PCI_NUM_PINS]; 65 PCIBus pci_bus; 66 AddressSpace pci_io_as; 67 MemoryRegion pci_io; 68 MemoryRegion pci_io_non_contiguous; 69 MemoryRegion pci_memory; 70 MemoryRegion pci_intack; 71 MemoryRegion bm; 72 MemoryRegion bm_ram_alias; 73 MemoryRegion bm_pci_memory_alias; 74 AddressSpace bm_as; 75 RavenPCIState pci_dev; 76 77 int contiguous_map; 78 }; 79 80 #define BIOS_SIZE (1 * MiB) 81 82 #define PCI_IO_BASE_ADDR 0x80000000 /* Physical address on main bus */ 83 84 static inline uint32_t raven_pci_io_config(hwaddr addr) 85 { 86 int i; 87 88 for (i = 0; i < 11; i++) { 89 if ((addr & (1 << (11 + i))) != 0) { 90 break; 91 } 92 } 93 return (addr & 0x7ff) | (i << 11); 94 } 95 96 static void raven_pci_io_write(void *opaque, hwaddr addr, 97 uint64_t val, unsigned int size) 98 { 99 PREPPCIState *s = opaque; 100 PCIHostState *phb = PCI_HOST_BRIDGE(s); 101 pci_data_write(phb->bus, raven_pci_io_config(addr), val, size); 102 } 103 104 static uint64_t raven_pci_io_read(void *opaque, hwaddr addr, 105 unsigned int size) 106 { 107 PREPPCIState *s = opaque; 108 PCIHostState *phb = PCI_HOST_BRIDGE(s); 109 return pci_data_read(phb->bus, raven_pci_io_config(addr), size); 110 } 111 112 static const MemoryRegionOps raven_pci_io_ops = { 113 .read = raven_pci_io_read, 114 .write = raven_pci_io_write, 115 .endianness = DEVICE_LITTLE_ENDIAN, 116 }; 117 118 static uint64_t raven_intack_read(void *opaque, hwaddr addr, 119 unsigned int size) 120 { 121 return pic_read_irq(isa_pic); 122 } 123 124 static void raven_intack_write(void *opaque, hwaddr addr, 125 uint64_t data, unsigned size) 126 { 127 qemu_log_mask(LOG_UNIMP, "%s not implemented\n", __func__); 128 } 129 130 static const MemoryRegionOps raven_intack_ops = { 131 .read = raven_intack_read, 132 .write = raven_intack_write, 133 .valid = { 134 .max_access_size = 1, 135 }, 136 }; 137 138 static inline hwaddr raven_io_address(PREPPCIState *s, 139 hwaddr addr) 140 { 141 if (s->contiguous_map == 0) { 142 /* 64 KB contiguous space for IOs */ 143 addr &= 0xFFFF; 144 } else { 145 /* 8 MB non-contiguous space for IOs */ 146 addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7); 147 } 148 149 /* FIXME: handle endianness switch */ 150 151 return addr; 152 } 153 154 static uint64_t raven_io_read(void *opaque, hwaddr addr, 155 unsigned int size) 156 { 157 PREPPCIState *s = opaque; 158 uint8_t buf[4]; 159 160 addr = raven_io_address(s, addr); 161 address_space_read(&s->pci_io_as, addr + PCI_IO_BASE_ADDR, 162 MEMTXATTRS_UNSPECIFIED, buf, size); 163 164 if (size == 1) { 165 return buf[0]; 166 } else if (size == 2) { 167 return lduw_le_p(buf); 168 } else if (size == 4) { 169 return ldl_le_p(buf); 170 } else { 171 g_assert_not_reached(); 172 } 173 } 174 175 static void raven_io_write(void *opaque, hwaddr addr, 176 uint64_t val, unsigned int size) 177 { 178 PREPPCIState *s = opaque; 179 uint8_t buf[4]; 180 181 addr = raven_io_address(s, addr); 182 183 if (size == 1) { 184 buf[0] = val; 185 } else if (size == 2) { 186 stw_le_p(buf, val); 187 } else if (size == 4) { 188 stl_le_p(buf, val); 189 } else { 190 g_assert_not_reached(); 191 } 192 193 address_space_write(&s->pci_io_as, addr + PCI_IO_BASE_ADDR, 194 MEMTXATTRS_UNSPECIFIED, buf, size); 195 } 196 197 static const MemoryRegionOps raven_io_ops = { 198 .read = raven_io_read, 199 .write = raven_io_write, 200 .endianness = DEVICE_LITTLE_ENDIAN, 201 .impl.max_access_size = 4, 202 .impl.unaligned = true, 203 .valid.unaligned = true, 204 }; 205 206 static int raven_map_irq(PCIDevice *pci_dev, int irq_num) 207 { 208 return (irq_num + (pci_dev->devfn >> 3)) & 1; 209 } 210 211 static void raven_set_irq(void *opaque, int irq_num, int level) 212 { 213 PREPPCIState *s = opaque; 214 215 qemu_set_irq(s->pci_irqs[irq_num], level); 216 } 217 218 static AddressSpace *raven_pcihost_set_iommu(PCIBus *bus, void *opaque, 219 int devfn) 220 { 221 PREPPCIState *s = opaque; 222 223 return &s->bm_as; 224 } 225 226 static const PCIIOMMUOps raven_iommu_ops = { 227 .get_address_space = raven_pcihost_set_iommu, 228 }; 229 230 static void raven_change_gpio(void *opaque, int n, int level) 231 { 232 PREPPCIState *s = opaque; 233 234 s->contiguous_map = level; 235 } 236 237 static void raven_pcihost_realizefn(DeviceState *d, Error **errp) 238 { 239 SysBusDevice *dev = SYS_BUS_DEVICE(d); 240 PCIHostState *h = PCI_HOST_BRIDGE(dev); 241 PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(dev); 242 MemoryRegion *address_space_mem = get_system_memory(); 243 int i; 244 245 /* 246 * According to PReP specification section 6.1.6 "System Interrupt 247 * Assignments", all PCI interrupts are routed via IRQ 15 248 */ 249 s->or_irq = OR_IRQ(object_new(TYPE_OR_IRQ)); 250 object_property_set_int(OBJECT(s->or_irq), "num-lines", PCI_NUM_PINS, 251 &error_fatal); 252 qdev_realize(DEVICE(s->or_irq), NULL, &error_fatal); 253 sysbus_init_irq(dev, &s->or_irq->out_irq); 254 255 for (i = 0; i < PCI_NUM_PINS; i++) { 256 s->pci_irqs[i] = qdev_get_gpio_in(DEVICE(s->or_irq), i); 257 } 258 259 qdev_init_gpio_in(d, raven_change_gpio, 1); 260 261 pci_bus_irqs(&s->pci_bus, raven_set_irq, s, PCI_NUM_PINS); 262 pci_bus_map_irqs(&s->pci_bus, raven_map_irq); 263 264 memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops, s, 265 "pci-conf-idx", 4); 266 memory_region_add_subregion(&s->pci_io, 0xcf8, &h->conf_mem); 267 268 memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops, s, 269 "pci-conf-data", 4); 270 memory_region_add_subregion(&s->pci_io, 0xcfc, &h->data_mem); 271 272 memory_region_init_io(&h->mmcfg, OBJECT(s), &raven_pci_io_ops, s, 273 "pciio", 0x00400000); 274 memory_region_add_subregion(address_space_mem, 0x80800000, &h->mmcfg); 275 276 memory_region_init_io(&s->pci_intack, OBJECT(s), &raven_intack_ops, s, 277 "pci-intack", 1); 278 memory_region_add_subregion(address_space_mem, 0xbffffff0, &s->pci_intack); 279 280 /* TODO Remove once realize propagates to child devices. */ 281 qdev_realize(DEVICE(&s->pci_dev), BUS(&s->pci_bus), errp); 282 } 283 284 static void raven_pcihost_initfn(Object *obj) 285 { 286 PCIHostState *h = PCI_HOST_BRIDGE(obj); 287 PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(obj); 288 MemoryRegion *address_space_mem = get_system_memory(); 289 DeviceState *pci_dev; 290 291 memory_region_init(&s->pci_io, obj, "pci-io", 0x3f800000); 292 memory_region_init_io(&s->pci_io_non_contiguous, obj, &raven_io_ops, s, 293 "pci-io-non-contiguous", 0x00800000); 294 memory_region_init(&s->pci_memory, obj, "pci-memory", 0x3f000000); 295 address_space_init(&s->pci_io_as, &s->pci_io, "raven-io"); 296 297 /* 298 * Raven's raven_io_ops use the address-space API to access pci-conf-idx 299 * (which is also owned by the raven device). As such, mark the 300 * pci_io_non_contiguous as re-entrancy safe. 301 */ 302 s->pci_io_non_contiguous.disable_reentrancy_guard = true; 303 304 /* CPU address space */ 305 memory_region_add_subregion(address_space_mem, PCI_IO_BASE_ADDR, 306 &s->pci_io); 307 memory_region_add_subregion_overlap(address_space_mem, PCI_IO_BASE_ADDR, 308 &s->pci_io_non_contiguous, 1); 309 memory_region_add_subregion(address_space_mem, 0xc0000000, &s->pci_memory); 310 pci_root_bus_init(&s->pci_bus, sizeof(s->pci_bus), DEVICE(obj), NULL, 311 &s->pci_memory, &s->pci_io, 0, TYPE_PCI_BUS); 312 313 /* Bus master address space */ 314 memory_region_init(&s->bm, obj, "bm-raven", 4 * GiB); 315 memory_region_init_alias(&s->bm_pci_memory_alias, obj, "bm-pci-memory", 316 &s->pci_memory, 0, 317 memory_region_size(&s->pci_memory)); 318 memory_region_init_alias(&s->bm_ram_alias, obj, "bm-system", 319 get_system_memory(), 0, 0x80000000); 320 memory_region_add_subregion(&s->bm, 0 , &s->bm_pci_memory_alias); 321 memory_region_add_subregion(&s->bm, 0x80000000, &s->bm_ram_alias); 322 address_space_init(&s->bm_as, &s->bm, "raven-bm"); 323 pci_setup_iommu(&s->pci_bus, &raven_iommu_ops, s); 324 325 h->bus = &s->pci_bus; 326 327 object_initialize(&s->pci_dev, sizeof(s->pci_dev), TYPE_RAVEN_PCI_DEVICE); 328 pci_dev = DEVICE(&s->pci_dev); 329 object_property_set_int(OBJECT(&s->pci_dev), "addr", PCI_DEVFN(0, 0), 330 NULL); 331 qdev_prop_set_bit(pci_dev, "multifunction", false); 332 } 333 334 static void raven_realize(PCIDevice *d, Error **errp) 335 { 336 RavenPCIState *s = RAVEN_PCI_DEVICE(d); 337 char *filename; 338 int bios_size = -1; 339 340 d->config[PCI_CACHE_LINE_SIZE] = 0x08; 341 d->config[PCI_LATENCY_TIMER] = 0x10; 342 d->config[PCI_CAPABILITY_LIST] = 0x00; 343 344 if (!memory_region_init_rom_nomigrate(&s->bios, OBJECT(s), "bios", 345 BIOS_SIZE, errp)) { 346 return; 347 } 348 memory_region_add_subregion(get_system_memory(), (uint32_t)(-BIOS_SIZE), 349 &s->bios); 350 if (s->bios_name) { 351 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, s->bios_name); 352 if (filename) { 353 if (s->elf_machine != EM_NONE) { 354 bios_size = load_elf(filename, NULL, NULL, NULL, NULL, 355 NULL, NULL, NULL, 356 ELFDATA2MSB, s->elf_machine, 0, 0); 357 } 358 if (bios_size < 0) { 359 bios_size = get_image_size(filename); 360 if (bios_size > 0 && bios_size <= BIOS_SIZE) { 361 hwaddr bios_addr; 362 bios_size = (bios_size + 0xfff) & ~0xfff; 363 bios_addr = (uint32_t)(-BIOS_SIZE); 364 bios_size = load_image_targphys(filename, bios_addr, 365 bios_size); 366 } 367 } 368 } 369 g_free(filename); 370 if (bios_size < 0 || bios_size > BIOS_SIZE) { 371 memory_region_del_subregion(get_system_memory(), &s->bios); 372 error_setg(errp, "Could not load bios image '%s'", s->bios_name); 373 return; 374 } 375 } 376 377 vmstate_register_ram_global(&s->bios); 378 } 379 380 static const VMStateDescription vmstate_raven = { 381 .name = "raven", 382 .version_id = 0, 383 .minimum_version_id = 0, 384 .fields = (const VMStateField[]) { 385 VMSTATE_PCI_DEVICE(dev, RavenPCIState), 386 VMSTATE_END_OF_LIST() 387 }, 388 }; 389 390 static void raven_class_init(ObjectClass *klass, const void *data) 391 { 392 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 393 DeviceClass *dc = DEVICE_CLASS(klass); 394 395 k->realize = raven_realize; 396 k->vendor_id = PCI_VENDOR_ID_MOTOROLA; 397 k->device_id = PCI_DEVICE_ID_MOTOROLA_RAVEN; 398 k->revision = 0x00; 399 k->class_id = PCI_CLASS_BRIDGE_HOST; 400 dc->desc = "PReP Host Bridge - Motorola Raven"; 401 dc->vmsd = &vmstate_raven; 402 /* 403 * Reason: PCI-facing part of the host bridge, not usable without 404 * the host-facing part, which can't be device_add'ed, yet. 405 */ 406 dc->user_creatable = false; 407 } 408 409 static const TypeInfo raven_info = { 410 .name = TYPE_RAVEN_PCI_DEVICE, 411 .parent = TYPE_PCI_DEVICE, 412 .instance_size = sizeof(RavenPCIState), 413 .class_init = raven_class_init, 414 .interfaces = (const InterfaceInfo[]) { 415 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 416 { }, 417 }, 418 }; 419 420 static const Property raven_pcihost_properties[] = { 421 DEFINE_PROP_UINT32("elf-machine", PREPPCIState, pci_dev.elf_machine, 422 EM_NONE), 423 DEFINE_PROP_STRING("bios-name", PREPPCIState, pci_dev.bios_name), 424 }; 425 426 static void raven_pcihost_class_init(ObjectClass *klass, const void *data) 427 { 428 DeviceClass *dc = DEVICE_CLASS(klass); 429 430 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 431 dc->realize = raven_pcihost_realizefn; 432 device_class_set_props(dc, raven_pcihost_properties); 433 dc->fw_name = "pci"; 434 } 435 436 static const TypeInfo raven_pcihost_info = { 437 .name = TYPE_RAVEN_PCI_HOST_BRIDGE, 438 .parent = TYPE_PCI_HOST_BRIDGE, 439 .instance_size = sizeof(PREPPCIState), 440 .instance_init = raven_pcihost_initfn, 441 .class_init = raven_pcihost_class_init, 442 }; 443 444 static void raven_register_types(void) 445 { 446 type_register_static(&raven_pcihost_info); 447 type_register_static(&raven_info); 448 } 449 450 type_init(raven_register_types) 451