1 /* 2 * QEMU PREP PCI host 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * Copyright (c) 2011-2013 Andreas Färber 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "qemu/datadir.h" 28 #include "qemu/units.h" 29 #include "qemu/log.h" 30 #include "qapi/error.h" 31 #include "hw/pci/pci_device.h" 32 #include "hw/pci/pci_bus.h" 33 #include "hw/pci/pci_host.h" 34 #include "hw/qdev-properties.h" 35 #include "migration/vmstate.h" 36 #include "hw/intc/i8259.h" 37 #include "hw/irq.h" 38 #include "hw/loader.h" 39 #include "hw/or-irq.h" 40 #include "elf.h" 41 #include "qom/object.h" 42 43 #define TYPE_RAVEN_PCI_DEVICE "raven" 44 #define TYPE_RAVEN_PCI_HOST_BRIDGE "raven-pcihost" 45 46 OBJECT_DECLARE_SIMPLE_TYPE(RavenPCIState, RAVEN_PCI_DEVICE) 47 48 struct RavenPCIState { 49 PCIDevice dev; 50 51 uint32_t elf_machine; 52 char *bios_name; 53 MemoryRegion bios; 54 }; 55 56 typedef struct PRePPCIState PREPPCIState; 57 DECLARE_INSTANCE_CHECKER(PREPPCIState, RAVEN_PCI_HOST_BRIDGE, 58 TYPE_RAVEN_PCI_HOST_BRIDGE) 59 60 struct PRePPCIState { 61 PCIHostState parent_obj; 62 63 OrIRQState *or_irq; 64 qemu_irq pci_irqs[PCI_NUM_PINS]; 65 PCIBus pci_bus; 66 AddressSpace pci_io_as; 67 MemoryRegion pci_io; 68 MemoryRegion pci_io_non_contiguous; 69 MemoryRegion pci_memory; 70 MemoryRegion pci_intack; 71 MemoryRegion bm; 72 MemoryRegion bm_ram_alias; 73 MemoryRegion bm_pci_memory_alias; 74 AddressSpace bm_as; 75 RavenPCIState pci_dev; 76 77 int contiguous_map; 78 bool is_legacy_prep; 79 }; 80 81 #define BIOS_SIZE (1 * MiB) 82 83 #define PCI_IO_BASE_ADDR 0x80000000 /* Physical address on main bus */ 84 85 static inline uint32_t raven_pci_io_config(hwaddr addr) 86 { 87 int i; 88 89 for (i = 0; i < 11; i++) { 90 if ((addr & (1 << (11 + i))) != 0) { 91 break; 92 } 93 } 94 return (addr & 0x7ff) | (i << 11); 95 } 96 97 static void raven_pci_io_write(void *opaque, hwaddr addr, 98 uint64_t val, unsigned int size) 99 { 100 PREPPCIState *s = opaque; 101 PCIHostState *phb = PCI_HOST_BRIDGE(s); 102 pci_data_write(phb->bus, raven_pci_io_config(addr), val, size); 103 } 104 105 static uint64_t raven_pci_io_read(void *opaque, hwaddr addr, 106 unsigned int size) 107 { 108 PREPPCIState *s = opaque; 109 PCIHostState *phb = PCI_HOST_BRIDGE(s); 110 return pci_data_read(phb->bus, raven_pci_io_config(addr), size); 111 } 112 113 static const MemoryRegionOps raven_pci_io_ops = { 114 .read = raven_pci_io_read, 115 .write = raven_pci_io_write, 116 .endianness = DEVICE_LITTLE_ENDIAN, 117 }; 118 119 static uint64_t raven_intack_read(void *opaque, hwaddr addr, 120 unsigned int size) 121 { 122 return pic_read_irq(isa_pic); 123 } 124 125 static void raven_intack_write(void *opaque, hwaddr addr, 126 uint64_t data, unsigned size) 127 { 128 qemu_log_mask(LOG_UNIMP, "%s not implemented\n", __func__); 129 } 130 131 static const MemoryRegionOps raven_intack_ops = { 132 .read = raven_intack_read, 133 .write = raven_intack_write, 134 .valid = { 135 .max_access_size = 1, 136 }, 137 }; 138 139 static inline hwaddr raven_io_address(PREPPCIState *s, 140 hwaddr addr) 141 { 142 if (s->contiguous_map == 0) { 143 /* 64 KB contiguous space for IOs */ 144 addr &= 0xFFFF; 145 } else { 146 /* 8 MB non-contiguous space for IOs */ 147 addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7); 148 } 149 150 /* FIXME: handle endianness switch */ 151 152 return addr; 153 } 154 155 static uint64_t raven_io_read(void *opaque, hwaddr addr, 156 unsigned int size) 157 { 158 PREPPCIState *s = opaque; 159 uint8_t buf[4]; 160 161 addr = raven_io_address(s, addr); 162 address_space_read(&s->pci_io_as, addr + PCI_IO_BASE_ADDR, 163 MEMTXATTRS_UNSPECIFIED, buf, size); 164 165 if (size == 1) { 166 return buf[0]; 167 } else if (size == 2) { 168 return lduw_le_p(buf); 169 } else if (size == 4) { 170 return ldl_le_p(buf); 171 } else { 172 g_assert_not_reached(); 173 } 174 } 175 176 static void raven_io_write(void *opaque, hwaddr addr, 177 uint64_t val, unsigned int size) 178 { 179 PREPPCIState *s = opaque; 180 uint8_t buf[4]; 181 182 addr = raven_io_address(s, addr); 183 184 if (size == 1) { 185 buf[0] = val; 186 } else if (size == 2) { 187 stw_le_p(buf, val); 188 } else if (size == 4) { 189 stl_le_p(buf, val); 190 } else { 191 g_assert_not_reached(); 192 } 193 194 address_space_write(&s->pci_io_as, addr + PCI_IO_BASE_ADDR, 195 MEMTXATTRS_UNSPECIFIED, buf, size); 196 } 197 198 static const MemoryRegionOps raven_io_ops = { 199 .read = raven_io_read, 200 .write = raven_io_write, 201 .endianness = DEVICE_LITTLE_ENDIAN, 202 .impl.max_access_size = 4, 203 .impl.unaligned = true, 204 .valid.unaligned = true, 205 }; 206 207 static int raven_map_irq(PCIDevice *pci_dev, int irq_num) 208 { 209 return (irq_num + (pci_dev->devfn >> 3)) & 1; 210 } 211 212 static void raven_set_irq(void *opaque, int irq_num, int level) 213 { 214 PREPPCIState *s = opaque; 215 216 qemu_set_irq(s->pci_irqs[irq_num], level); 217 } 218 219 static AddressSpace *raven_pcihost_set_iommu(PCIBus *bus, void *opaque, 220 int devfn) 221 { 222 PREPPCIState *s = opaque; 223 224 return &s->bm_as; 225 } 226 227 static const PCIIOMMUOps raven_iommu_ops = { 228 .get_address_space = raven_pcihost_set_iommu, 229 }; 230 231 static void raven_change_gpio(void *opaque, int n, int level) 232 { 233 PREPPCIState *s = opaque; 234 235 s->contiguous_map = level; 236 } 237 238 static void raven_pcihost_realizefn(DeviceState *d, Error **errp) 239 { 240 SysBusDevice *dev = SYS_BUS_DEVICE(d); 241 PCIHostState *h = PCI_HOST_BRIDGE(dev); 242 PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(dev); 243 MemoryRegion *address_space_mem = get_system_memory(); 244 int i; 245 246 if (s->is_legacy_prep) { 247 for (i = 0; i < PCI_NUM_PINS; i++) { 248 sysbus_init_irq(dev, &s->pci_irqs[i]); 249 } 250 } else { 251 /* According to PReP specification section 6.1.6 "System Interrupt 252 * Assignments", all PCI interrupts are routed via IRQ 15 */ 253 s->or_irq = OR_IRQ(object_new(TYPE_OR_IRQ)); 254 object_property_set_int(OBJECT(s->or_irq), "num-lines", PCI_NUM_PINS, 255 &error_fatal); 256 qdev_realize(DEVICE(s->or_irq), NULL, &error_fatal); 257 sysbus_init_irq(dev, &s->or_irq->out_irq); 258 259 for (i = 0; i < PCI_NUM_PINS; i++) { 260 s->pci_irqs[i] = qdev_get_gpio_in(DEVICE(s->or_irq), i); 261 } 262 } 263 264 qdev_init_gpio_in(d, raven_change_gpio, 1); 265 266 pci_bus_irqs(&s->pci_bus, raven_set_irq, s, PCI_NUM_PINS); 267 pci_bus_map_irqs(&s->pci_bus, raven_map_irq); 268 269 memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops, s, 270 "pci-conf-idx", 4); 271 memory_region_add_subregion(&s->pci_io, 0xcf8, &h->conf_mem); 272 273 memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops, s, 274 "pci-conf-data", 4); 275 memory_region_add_subregion(&s->pci_io, 0xcfc, &h->data_mem); 276 277 memory_region_init_io(&h->mmcfg, OBJECT(s), &raven_pci_io_ops, s, 278 "pciio", 0x00400000); 279 memory_region_add_subregion(address_space_mem, 0x80800000, &h->mmcfg); 280 281 memory_region_init_io(&s->pci_intack, OBJECT(s), &raven_intack_ops, s, 282 "pci-intack", 1); 283 memory_region_add_subregion(address_space_mem, 0xbffffff0, &s->pci_intack); 284 285 /* TODO Remove once realize propagates to child devices. */ 286 qdev_realize(DEVICE(&s->pci_dev), BUS(&s->pci_bus), errp); 287 } 288 289 static void raven_pcihost_initfn(Object *obj) 290 { 291 PCIHostState *h = PCI_HOST_BRIDGE(obj); 292 PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(obj); 293 MemoryRegion *address_space_mem = get_system_memory(); 294 DeviceState *pci_dev; 295 296 memory_region_init(&s->pci_io, obj, "pci-io", 0x3f800000); 297 memory_region_init_io(&s->pci_io_non_contiguous, obj, &raven_io_ops, s, 298 "pci-io-non-contiguous", 0x00800000); 299 memory_region_init(&s->pci_memory, obj, "pci-memory", 0x3f000000); 300 address_space_init(&s->pci_io_as, &s->pci_io, "raven-io"); 301 302 /* 303 * Raven's raven_io_ops use the address-space API to access pci-conf-idx 304 * (which is also owned by the raven device). As such, mark the 305 * pci_io_non_contiguous as re-entrancy safe. 306 */ 307 s->pci_io_non_contiguous.disable_reentrancy_guard = true; 308 309 /* CPU address space */ 310 memory_region_add_subregion(address_space_mem, PCI_IO_BASE_ADDR, 311 &s->pci_io); 312 memory_region_add_subregion_overlap(address_space_mem, PCI_IO_BASE_ADDR, 313 &s->pci_io_non_contiguous, 1); 314 memory_region_add_subregion(address_space_mem, 0xc0000000, &s->pci_memory); 315 pci_root_bus_init(&s->pci_bus, sizeof(s->pci_bus), DEVICE(obj), NULL, 316 &s->pci_memory, &s->pci_io, 0, TYPE_PCI_BUS); 317 318 /* Bus master address space */ 319 memory_region_init(&s->bm, obj, "bm-raven", 4 * GiB); 320 memory_region_init_alias(&s->bm_pci_memory_alias, obj, "bm-pci-memory", 321 &s->pci_memory, 0, 322 memory_region_size(&s->pci_memory)); 323 memory_region_init_alias(&s->bm_ram_alias, obj, "bm-system", 324 get_system_memory(), 0, 0x80000000); 325 memory_region_add_subregion(&s->bm, 0 , &s->bm_pci_memory_alias); 326 memory_region_add_subregion(&s->bm, 0x80000000, &s->bm_ram_alias); 327 address_space_init(&s->bm_as, &s->bm, "raven-bm"); 328 pci_setup_iommu(&s->pci_bus, &raven_iommu_ops, s); 329 330 h->bus = &s->pci_bus; 331 332 object_initialize(&s->pci_dev, sizeof(s->pci_dev), TYPE_RAVEN_PCI_DEVICE); 333 pci_dev = DEVICE(&s->pci_dev); 334 object_property_set_int(OBJECT(&s->pci_dev), "addr", PCI_DEVFN(0, 0), 335 NULL); 336 qdev_prop_set_bit(pci_dev, "multifunction", false); 337 } 338 339 static void raven_realize(PCIDevice *d, Error **errp) 340 { 341 RavenPCIState *s = RAVEN_PCI_DEVICE(d); 342 char *filename; 343 int bios_size = -1; 344 345 d->config[PCI_CACHE_LINE_SIZE] = 0x08; 346 d->config[PCI_LATENCY_TIMER] = 0x10; 347 d->config[PCI_CAPABILITY_LIST] = 0x00; 348 349 if (!memory_region_init_rom_nomigrate(&s->bios, OBJECT(s), "bios", 350 BIOS_SIZE, errp)) { 351 return; 352 } 353 memory_region_add_subregion(get_system_memory(), (uint32_t)(-BIOS_SIZE), 354 &s->bios); 355 if (s->bios_name) { 356 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, s->bios_name); 357 if (filename) { 358 if (s->elf_machine != EM_NONE) { 359 bios_size = load_elf(filename, NULL, NULL, NULL, NULL, 360 NULL, NULL, NULL, 1, s->elf_machine, 361 0, 0); 362 } 363 if (bios_size < 0) { 364 bios_size = get_image_size(filename); 365 if (bios_size > 0 && bios_size <= BIOS_SIZE) { 366 hwaddr bios_addr; 367 bios_size = (bios_size + 0xfff) & ~0xfff; 368 bios_addr = (uint32_t)(-BIOS_SIZE); 369 bios_size = load_image_targphys(filename, bios_addr, 370 bios_size); 371 } 372 } 373 } 374 g_free(filename); 375 if (bios_size < 0 || bios_size > BIOS_SIZE) { 376 memory_region_del_subregion(get_system_memory(), &s->bios); 377 error_setg(errp, "Could not load bios image '%s'", s->bios_name); 378 return; 379 } 380 } 381 382 vmstate_register_ram_global(&s->bios); 383 } 384 385 static const VMStateDescription vmstate_raven = { 386 .name = "raven", 387 .version_id = 0, 388 .minimum_version_id = 0, 389 .fields = (const VMStateField[]) { 390 VMSTATE_PCI_DEVICE(dev, RavenPCIState), 391 VMSTATE_END_OF_LIST() 392 }, 393 }; 394 395 static void raven_class_init(ObjectClass *klass, void *data) 396 { 397 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 398 DeviceClass *dc = DEVICE_CLASS(klass); 399 400 k->realize = raven_realize; 401 k->vendor_id = PCI_VENDOR_ID_MOTOROLA; 402 k->device_id = PCI_DEVICE_ID_MOTOROLA_RAVEN; 403 k->revision = 0x00; 404 k->class_id = PCI_CLASS_BRIDGE_HOST; 405 dc->desc = "PReP Host Bridge - Motorola Raven"; 406 dc->vmsd = &vmstate_raven; 407 /* 408 * Reason: PCI-facing part of the host bridge, not usable without 409 * the host-facing part, which can't be device_add'ed, yet. 410 */ 411 dc->user_creatable = false; 412 } 413 414 static const TypeInfo raven_info = { 415 .name = TYPE_RAVEN_PCI_DEVICE, 416 .parent = TYPE_PCI_DEVICE, 417 .instance_size = sizeof(RavenPCIState), 418 .class_init = raven_class_init, 419 .interfaces = (InterfaceInfo[]) { 420 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 421 { }, 422 }, 423 }; 424 425 static Property raven_pcihost_properties[] = { 426 DEFINE_PROP_UINT32("elf-machine", PREPPCIState, pci_dev.elf_machine, 427 EM_NONE), 428 DEFINE_PROP_STRING("bios-name", PREPPCIState, pci_dev.bios_name), 429 /* Temporary workaround until legacy prep machine is removed */ 430 DEFINE_PROP_BOOL("is-legacy-prep", PREPPCIState, is_legacy_prep, 431 false), 432 DEFINE_PROP_END_OF_LIST() 433 }; 434 435 static void raven_pcihost_class_init(ObjectClass *klass, void *data) 436 { 437 DeviceClass *dc = DEVICE_CLASS(klass); 438 439 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 440 dc->realize = raven_pcihost_realizefn; 441 device_class_set_props(dc, raven_pcihost_properties); 442 dc->fw_name = "pci"; 443 } 444 445 static const TypeInfo raven_pcihost_info = { 446 .name = TYPE_RAVEN_PCI_HOST_BRIDGE, 447 .parent = TYPE_PCI_HOST_BRIDGE, 448 .instance_size = sizeof(PREPPCIState), 449 .instance_init = raven_pcihost_initfn, 450 .class_init = raven_pcihost_class_init, 451 }; 452 453 static void raven_register_types(void) 454 { 455 type_register_static(&raven_pcihost_info); 456 type_register_static(&raven_info); 457 } 458 459 type_init(raven_register_types) 460