1 /* 2 * QEMU MCH/ICH9 PCI Bridge Emulation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * Copyright (c) 2009, 2010, 2011 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on piix.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 #include "qemu/osdep.h" 31 #include "hw/hw.h" 32 #include "hw/pci-host/q35.h" 33 #include "qapi/error.h" 34 #include "qapi/visitor.h" 35 36 /**************************************************************************** 37 * Q35 host 38 */ 39 40 #define Q35_PCI_HOST_HOLE64_SIZE_DEFAULT (1ULL << 35) 41 42 static void q35_host_realize(DeviceState *dev, Error **errp) 43 { 44 PCIHostState *pci = PCI_HOST_BRIDGE(dev); 45 Q35PCIHost *s = Q35_HOST_DEVICE(dev); 46 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 47 48 sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem); 49 sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, 4); 50 51 sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem); 52 sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, 4); 53 54 pci->bus = pci_bus_new(DEVICE(s), "pcie.0", 55 s->mch.pci_address_space, s->mch.address_space_io, 56 0, TYPE_PCIE_BUS); 57 PC_MACHINE(qdev_get_machine())->bus = pci->bus; 58 qdev_set_parent_bus(DEVICE(&s->mch), BUS(pci->bus)); 59 qdev_init_nofail(DEVICE(&s->mch)); 60 } 61 62 static const char *q35_host_root_bus_path(PCIHostState *host_bridge, 63 PCIBus *rootbus) 64 { 65 Q35PCIHost *s = Q35_HOST_DEVICE(host_bridge); 66 67 /* For backwards compat with old device paths */ 68 if (s->mch.short_root_bus) { 69 return "0000"; 70 } 71 return "0000:00"; 72 } 73 74 static void q35_host_get_pci_hole_start(Object *obj, Visitor *v, 75 const char *name, void *opaque, 76 Error **errp) 77 { 78 Q35PCIHost *s = Q35_HOST_DEVICE(obj); 79 uint64_t val64; 80 uint32_t value; 81 82 val64 = range_is_empty(&s->mch.pci_hole) 83 ? 0 : range_lob(&s->mch.pci_hole); 84 value = val64; 85 assert(value == val64); 86 visit_type_uint32(v, name, &value, errp); 87 } 88 89 static void q35_host_get_pci_hole_end(Object *obj, Visitor *v, 90 const char *name, void *opaque, 91 Error **errp) 92 { 93 Q35PCIHost *s = Q35_HOST_DEVICE(obj); 94 uint64_t val64; 95 uint32_t value; 96 97 val64 = range_is_empty(&s->mch.pci_hole) 98 ? 0 : range_upb(&s->mch.pci_hole) + 1; 99 value = val64; 100 assert(value == val64); 101 visit_type_uint32(v, name, &value, errp); 102 } 103 104 /* 105 * The 64bit PCI hole start is set by the Guest firmware 106 * as the address of the first 64bit PCI MEM resource. 107 * If no PCI device has resources on the 64bit area, 108 * the 64bit PCI hole will start after "over 4G RAM" and the 109 * reserved space for memory hotplug if any. 110 */ 111 static void q35_host_get_pci_hole64_start(Object *obj, Visitor *v, 112 const char *name, void *opaque, 113 Error **errp) 114 { 115 PCIHostState *h = PCI_HOST_BRIDGE(obj); 116 Q35PCIHost *s = Q35_HOST_DEVICE(obj); 117 Range w64; 118 uint64_t value; 119 120 pci_bus_get_w64_range(h->bus, &w64); 121 value = range_is_empty(&w64) ? 0 : range_lob(&w64); 122 if (!value && s->pci_hole64_fix) { 123 value = pc_pci_hole64_start(); 124 } 125 visit_type_uint64(v, name, &value, errp); 126 } 127 128 /* 129 * The 64bit PCI hole end is set by the Guest firmware 130 * as the address of the last 64bit PCI MEM resource. 131 * Then it is expanded to the PCI_HOST_PROP_PCI_HOLE64_SIZE 132 * that can be configured by the user. 133 */ 134 static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v, 135 const char *name, void *opaque, 136 Error **errp) 137 { 138 PCIHostState *h = PCI_HOST_BRIDGE(obj); 139 Q35PCIHost *s = Q35_HOST_DEVICE(obj); 140 uint64_t hole64_start = pc_pci_hole64_start(); 141 Range w64; 142 uint64_t value, hole64_end; 143 144 pci_bus_get_w64_range(h->bus, &w64); 145 value = range_is_empty(&w64) ? 0 : range_upb(&w64) + 1; 146 hole64_end = ROUND_UP(hole64_start + s->mch.pci_hole64_size, 1ULL << 30); 147 if (s->pci_hole64_fix && value < hole64_end) { 148 value = hole64_end; 149 } 150 visit_type_uint64(v, name, &value, errp); 151 } 152 153 static void q35_host_get_mmcfg_size(Object *obj, Visitor *v, const char *name, 154 void *opaque, Error **errp) 155 { 156 PCIExpressHost *e = PCIE_HOST_BRIDGE(obj); 157 158 visit_type_uint64(v, name, &e->size, errp); 159 } 160 161 /* 162 * NOTE: setting defaults for the mch.* fields in this table 163 * doesn't work, because mch is a separate QOM object that is 164 * zeroed by the object_initialize(&s->mch, ...) call inside 165 * q35_host_initfn(). The default values for those 166 * properties need to be initialized manually by 167 * q35_host_initfn() after the object_initialize() call. 168 */ 169 static Property q35_host_props[] = { 170 DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, Q35PCIHost, parent_obj.base_addr, 171 MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT), 172 DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, Q35PCIHost, 173 mch.pci_hole64_size, Q35_PCI_HOST_HOLE64_SIZE_DEFAULT), 174 DEFINE_PROP_UINT32("short_root_bus", Q35PCIHost, mch.short_root_bus, 0), 175 DEFINE_PROP_SIZE(PCI_HOST_BELOW_4G_MEM_SIZE, Q35PCIHost, 176 mch.below_4g_mem_size, 0), 177 DEFINE_PROP_SIZE(PCI_HOST_ABOVE_4G_MEM_SIZE, Q35PCIHost, 178 mch.above_4g_mem_size, 0), 179 DEFINE_PROP_BOOL("x-pci-hole64-fix", Q35PCIHost, pci_hole64_fix, true), 180 DEFINE_PROP_END_OF_LIST(), 181 }; 182 183 static void q35_host_class_init(ObjectClass *klass, void *data) 184 { 185 DeviceClass *dc = DEVICE_CLASS(klass); 186 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); 187 188 hc->root_bus_path = q35_host_root_bus_path; 189 dc->realize = q35_host_realize; 190 dc->props = q35_host_props; 191 /* Reason: needs to be wired up by pc_q35_init */ 192 dc->user_creatable = false; 193 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 194 dc->fw_name = "pci"; 195 } 196 197 static void q35_host_initfn(Object *obj) 198 { 199 Q35PCIHost *s = Q35_HOST_DEVICE(obj); 200 PCIHostState *phb = PCI_HOST_BRIDGE(obj); 201 202 memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, phb, 203 "pci-conf-idx", 4); 204 memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, phb, 205 "pci-conf-data", 4); 206 207 object_initialize(&s->mch, sizeof(s->mch), TYPE_MCH_PCI_DEVICE); 208 object_property_add_child(OBJECT(s), "mch", OBJECT(&s->mch), NULL); 209 qdev_prop_set_int32(DEVICE(&s->mch), "addr", PCI_DEVFN(0, 0)); 210 qdev_prop_set_bit(DEVICE(&s->mch), "multifunction", false); 211 /* mch's object_initialize resets the default value, set it again */ 212 qdev_prop_set_uint64(DEVICE(s), PCI_HOST_PROP_PCI_HOLE64_SIZE, 213 Q35_PCI_HOST_HOLE64_SIZE_DEFAULT); 214 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "uint32", 215 q35_host_get_pci_hole_start, 216 NULL, NULL, NULL, NULL); 217 218 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "uint32", 219 q35_host_get_pci_hole_end, 220 NULL, NULL, NULL, NULL); 221 222 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "uint64", 223 q35_host_get_pci_hole64_start, 224 NULL, NULL, NULL, NULL); 225 226 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "uint64", 227 q35_host_get_pci_hole64_end, 228 NULL, NULL, NULL, NULL); 229 230 object_property_add(obj, PCIE_HOST_MCFG_SIZE, "uint64", 231 q35_host_get_mmcfg_size, 232 NULL, NULL, NULL, NULL); 233 234 object_property_add_link(obj, MCH_HOST_PROP_RAM_MEM, TYPE_MEMORY_REGION, 235 (Object **) &s->mch.ram_memory, 236 qdev_prop_allow_set_link_before_realize, 0, NULL); 237 238 object_property_add_link(obj, MCH_HOST_PROP_PCI_MEM, TYPE_MEMORY_REGION, 239 (Object **) &s->mch.pci_address_space, 240 qdev_prop_allow_set_link_before_realize, 0, NULL); 241 242 object_property_add_link(obj, MCH_HOST_PROP_SYSTEM_MEM, TYPE_MEMORY_REGION, 243 (Object **) &s->mch.system_memory, 244 qdev_prop_allow_set_link_before_realize, 0, NULL); 245 246 object_property_add_link(obj, MCH_HOST_PROP_IO_MEM, TYPE_MEMORY_REGION, 247 (Object **) &s->mch.address_space_io, 248 qdev_prop_allow_set_link_before_realize, 0, NULL); 249 250 /* Leave enough space for the biggest MCFG BAR */ 251 /* TODO: this matches current bios behaviour, but 252 * it's not a power of two, which means an MTRR 253 * can't cover it exactly. 254 */ 255 range_set_bounds(&s->mch.pci_hole, 256 MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT + MCH_HOST_BRIDGE_PCIEXBAR_MAX, 257 IO_APIC_DEFAULT_ADDRESS - 1); 258 } 259 260 static const TypeInfo q35_host_info = { 261 .name = TYPE_Q35_HOST_DEVICE, 262 .parent = TYPE_PCIE_HOST_BRIDGE, 263 .instance_size = sizeof(Q35PCIHost), 264 .instance_init = q35_host_initfn, 265 .class_init = q35_host_class_init, 266 }; 267 268 /**************************************************************************** 269 * MCH D0:F0 270 */ 271 272 static uint64_t tseg_blackhole_read(void *ptr, hwaddr reg, unsigned size) 273 { 274 return 0xffffffff; 275 } 276 277 static void tseg_blackhole_write(void *opaque, hwaddr addr, uint64_t val, 278 unsigned width) 279 { 280 /* nothing */ 281 } 282 283 static const MemoryRegionOps tseg_blackhole_ops = { 284 .read = tseg_blackhole_read, 285 .write = tseg_blackhole_write, 286 .endianness = DEVICE_NATIVE_ENDIAN, 287 .valid.min_access_size = 1, 288 .valid.max_access_size = 4, 289 .impl.min_access_size = 4, 290 .impl.max_access_size = 4, 291 .endianness = DEVICE_LITTLE_ENDIAN, 292 }; 293 294 /* PCIe MMCFG */ 295 static void mch_update_pciexbar(MCHPCIState *mch) 296 { 297 PCIDevice *pci_dev = PCI_DEVICE(mch); 298 BusState *bus = qdev_get_parent_bus(DEVICE(mch)); 299 PCIExpressHost *pehb = PCIE_HOST_BRIDGE(bus->parent); 300 301 uint64_t pciexbar; 302 int enable; 303 uint64_t addr; 304 uint64_t addr_mask; 305 uint32_t length; 306 307 pciexbar = pci_get_quad(pci_dev->config + MCH_HOST_BRIDGE_PCIEXBAR); 308 enable = pciexbar & MCH_HOST_BRIDGE_PCIEXBAREN; 309 addr_mask = MCH_HOST_BRIDGE_PCIEXBAR_ADMSK; 310 switch (pciexbar & MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) { 311 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M: 312 length = 256 * 1024 * 1024; 313 break; 314 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M: 315 length = 128 * 1024 * 1024; 316 addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK | 317 MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; 318 break; 319 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M: 320 length = 64 * 1024 * 1024; 321 addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; 322 break; 323 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD: 324 default: 325 abort(); 326 } 327 addr = pciexbar & addr_mask; 328 pcie_host_mmcfg_update(pehb, enable, addr, length); 329 /* Leave enough space for the MCFG BAR */ 330 /* 331 * TODO: this matches current bios behaviour, but it's not a power of two, 332 * which means an MTRR can't cover it exactly. 333 */ 334 if (enable) { 335 range_set_bounds(&mch->pci_hole, 336 addr + length, 337 IO_APIC_DEFAULT_ADDRESS - 1); 338 } else { 339 range_set_bounds(&mch->pci_hole, 340 MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT, 341 IO_APIC_DEFAULT_ADDRESS - 1); 342 } 343 } 344 345 /* PAM */ 346 static void mch_update_pam(MCHPCIState *mch) 347 { 348 PCIDevice *pd = PCI_DEVICE(mch); 349 int i; 350 351 memory_region_transaction_begin(); 352 for (i = 0; i < 13; i++) { 353 pam_update(&mch->pam_regions[i], i, 354 pd->config[MCH_HOST_BRIDGE_PAM0 + (DIV_ROUND_UP(i, 2))]); 355 } 356 memory_region_transaction_commit(); 357 } 358 359 /* SMRAM */ 360 static void mch_update_smram(MCHPCIState *mch) 361 { 362 PCIDevice *pd = PCI_DEVICE(mch); 363 bool h_smrame = (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME); 364 uint32_t tseg_size; 365 366 /* implement SMRAM.D_LCK */ 367 if (pd->config[MCH_HOST_BRIDGE_SMRAM] & MCH_HOST_BRIDGE_SMRAM_D_LCK) { 368 pd->config[MCH_HOST_BRIDGE_SMRAM] &= ~MCH_HOST_BRIDGE_SMRAM_D_OPEN; 369 pd->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK_LCK; 370 pd->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK_LCK; 371 } 372 373 memory_region_transaction_begin(); 374 375 if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_D_OPEN) { 376 /* Hide (!) low SMRAM if H_SMRAME = 1 */ 377 memory_region_set_enabled(&mch->smram_region, h_smrame); 378 /* Show high SMRAM if H_SMRAME = 1 */ 379 memory_region_set_enabled(&mch->open_high_smram, h_smrame); 380 } else { 381 /* Hide high SMRAM and low SMRAM */ 382 memory_region_set_enabled(&mch->smram_region, true); 383 memory_region_set_enabled(&mch->open_high_smram, false); 384 } 385 386 if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_G_SMRAME) { 387 memory_region_set_enabled(&mch->low_smram, !h_smrame); 388 memory_region_set_enabled(&mch->high_smram, h_smrame); 389 } else { 390 memory_region_set_enabled(&mch->low_smram, false); 391 memory_region_set_enabled(&mch->high_smram, false); 392 } 393 394 if (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_T_EN) { 395 switch (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & 396 MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK) { 397 case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB: 398 tseg_size = 1024 * 1024; 399 break; 400 case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB: 401 tseg_size = 1024 * 1024 * 2; 402 break; 403 case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB: 404 tseg_size = 1024 * 1024 * 8; 405 break; 406 default: 407 tseg_size = 1024 * 1024 * (uint32_t)mch->ext_tseg_mbytes; 408 break; 409 } 410 } else { 411 tseg_size = 0; 412 } 413 memory_region_del_subregion(mch->system_memory, &mch->tseg_blackhole); 414 memory_region_set_enabled(&mch->tseg_blackhole, tseg_size); 415 memory_region_set_size(&mch->tseg_blackhole, tseg_size); 416 memory_region_add_subregion_overlap(mch->system_memory, 417 mch->below_4g_mem_size - tseg_size, 418 &mch->tseg_blackhole, 1); 419 420 memory_region_set_enabled(&mch->tseg_window, tseg_size); 421 memory_region_set_size(&mch->tseg_window, tseg_size); 422 memory_region_set_address(&mch->tseg_window, 423 mch->below_4g_mem_size - tseg_size); 424 memory_region_set_alias_offset(&mch->tseg_window, 425 mch->below_4g_mem_size - tseg_size); 426 427 memory_region_transaction_commit(); 428 } 429 430 static void mch_update_ext_tseg_mbytes(MCHPCIState *mch) 431 { 432 PCIDevice *pd = PCI_DEVICE(mch); 433 uint8_t *reg = pd->config + MCH_HOST_BRIDGE_EXT_TSEG_MBYTES; 434 435 if (mch->ext_tseg_mbytes > 0 && 436 pci_get_word(reg) == MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY) { 437 pci_set_word(reg, mch->ext_tseg_mbytes); 438 } 439 } 440 441 static void mch_write_config(PCIDevice *d, 442 uint32_t address, uint32_t val, int len) 443 { 444 MCHPCIState *mch = MCH_PCI_DEVICE(d); 445 446 pci_default_write_config(d, address, val, len); 447 448 if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PAM0, 449 MCH_HOST_BRIDGE_PAM_SIZE)) { 450 mch_update_pam(mch); 451 } 452 453 if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PCIEXBAR, 454 MCH_HOST_BRIDGE_PCIEXBAR_SIZE)) { 455 mch_update_pciexbar(mch); 456 } 457 458 if (ranges_overlap(address, len, MCH_HOST_BRIDGE_SMRAM, 459 MCH_HOST_BRIDGE_SMRAM_SIZE)) { 460 mch_update_smram(mch); 461 } 462 463 if (ranges_overlap(address, len, MCH_HOST_BRIDGE_EXT_TSEG_MBYTES, 464 MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_SIZE)) { 465 mch_update_ext_tseg_mbytes(mch); 466 } 467 } 468 469 static void mch_update(MCHPCIState *mch) 470 { 471 mch_update_pciexbar(mch); 472 mch_update_pam(mch); 473 mch_update_smram(mch); 474 mch_update_ext_tseg_mbytes(mch); 475 } 476 477 static int mch_post_load(void *opaque, int version_id) 478 { 479 MCHPCIState *mch = opaque; 480 mch_update(mch); 481 return 0; 482 } 483 484 static const VMStateDescription vmstate_mch = { 485 .name = "mch", 486 .version_id = 1, 487 .minimum_version_id = 1, 488 .post_load = mch_post_load, 489 .fields = (VMStateField[]) { 490 VMSTATE_PCI_DEVICE(parent_obj, MCHPCIState), 491 /* Used to be smm_enabled, which was basically always zero because 492 * SeaBIOS hardly uses SMM. SMRAM is now handled by CPU code. 493 */ 494 VMSTATE_UNUSED(1), 495 VMSTATE_END_OF_LIST() 496 } 497 }; 498 499 static void mch_reset(DeviceState *qdev) 500 { 501 PCIDevice *d = PCI_DEVICE(qdev); 502 MCHPCIState *mch = MCH_PCI_DEVICE(d); 503 504 pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR, 505 MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT); 506 507 d->config[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT; 508 d->config[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_DEFAULT; 509 d->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK; 510 d->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK; 511 512 if (mch->ext_tseg_mbytes > 0) { 513 pci_set_word(d->config + MCH_HOST_BRIDGE_EXT_TSEG_MBYTES, 514 MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY); 515 } 516 517 mch_update(mch); 518 } 519 520 static void mch_realize(PCIDevice *d, Error **errp) 521 { 522 int i; 523 MCHPCIState *mch = MCH_PCI_DEVICE(d); 524 525 if (mch->ext_tseg_mbytes > MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_MAX) { 526 error_setg(errp, "invalid extended-tseg-mbytes value: %" PRIu16, 527 mch->ext_tseg_mbytes); 528 return; 529 } 530 531 /* setup pci memory mapping */ 532 pc_pci_as_mapping_init(OBJECT(mch), mch->system_memory, 533 mch->pci_address_space); 534 535 /* if *disabled* show SMRAM to all CPUs */ 536 memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-region", 537 mch->pci_address_space, 0xa0000, 0x20000); 538 memory_region_add_subregion_overlap(mch->system_memory, 0xa0000, 539 &mch->smram_region, 1); 540 memory_region_set_enabled(&mch->smram_region, true); 541 542 memory_region_init_alias(&mch->open_high_smram, OBJECT(mch), "smram-open-high", 543 mch->ram_memory, 0xa0000, 0x20000); 544 memory_region_add_subregion_overlap(mch->system_memory, 0xfeda0000, 545 &mch->open_high_smram, 1); 546 memory_region_set_enabled(&mch->open_high_smram, false); 547 548 /* smram, as seen by SMM CPUs */ 549 memory_region_init(&mch->smram, OBJECT(mch), "smram", 1ull << 32); 550 memory_region_set_enabled(&mch->smram, true); 551 memory_region_init_alias(&mch->low_smram, OBJECT(mch), "smram-low", 552 mch->ram_memory, 0xa0000, 0x20000); 553 memory_region_set_enabled(&mch->low_smram, true); 554 memory_region_add_subregion(&mch->smram, 0xa0000, &mch->low_smram); 555 memory_region_init_alias(&mch->high_smram, OBJECT(mch), "smram-high", 556 mch->ram_memory, 0xa0000, 0x20000); 557 memory_region_set_enabled(&mch->high_smram, true); 558 memory_region_add_subregion(&mch->smram, 0xfeda0000, &mch->high_smram); 559 560 memory_region_init_io(&mch->tseg_blackhole, OBJECT(mch), 561 &tseg_blackhole_ops, NULL, 562 "tseg-blackhole", 0); 563 memory_region_set_enabled(&mch->tseg_blackhole, false); 564 memory_region_add_subregion_overlap(mch->system_memory, 565 mch->below_4g_mem_size, 566 &mch->tseg_blackhole, 1); 567 568 memory_region_init_alias(&mch->tseg_window, OBJECT(mch), "tseg-window", 569 mch->ram_memory, mch->below_4g_mem_size, 0); 570 memory_region_set_enabled(&mch->tseg_window, false); 571 memory_region_add_subregion(&mch->smram, mch->below_4g_mem_size, 572 &mch->tseg_window); 573 object_property_add_const_link(qdev_get_machine(), "smram", 574 OBJECT(&mch->smram), &error_abort); 575 576 init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, 577 mch->pci_address_space, &mch->pam_regions[0], 578 PAM_BIOS_BASE, PAM_BIOS_SIZE); 579 for (i = 0; i < 12; ++i) { 580 init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, 581 mch->pci_address_space, &mch->pam_regions[i+1], 582 PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE); 583 } 584 } 585 586 uint64_t mch_mcfg_base(void) 587 { 588 bool ambiguous; 589 Object *o = object_resolve_path_type("", TYPE_MCH_PCI_DEVICE, &ambiguous); 590 if (!o) { 591 return 0; 592 } 593 return MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT; 594 } 595 596 static Property mch_props[] = { 597 DEFINE_PROP_UINT16("extended-tseg-mbytes", MCHPCIState, ext_tseg_mbytes, 598 16), 599 DEFINE_PROP_END_OF_LIST(), 600 }; 601 602 static void mch_class_init(ObjectClass *klass, void *data) 603 { 604 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 605 DeviceClass *dc = DEVICE_CLASS(klass); 606 607 k->realize = mch_realize; 608 k->config_write = mch_write_config; 609 dc->reset = mch_reset; 610 dc->props = mch_props; 611 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 612 dc->desc = "Host bridge"; 613 dc->vmsd = &vmstate_mch; 614 k->vendor_id = PCI_VENDOR_ID_INTEL; 615 k->device_id = PCI_DEVICE_ID_INTEL_Q35_MCH; 616 k->revision = MCH_HOST_BRIDGE_REVISION_DEFAULT; 617 k->class_id = PCI_CLASS_BRIDGE_HOST; 618 /* 619 * PCI-facing part of the host bridge, not usable without the 620 * host-facing part, which can't be device_add'ed, yet. 621 */ 622 dc->user_creatable = false; 623 } 624 625 static const TypeInfo mch_info = { 626 .name = TYPE_MCH_PCI_DEVICE, 627 .parent = TYPE_PCI_DEVICE, 628 .instance_size = sizeof(MCHPCIState), 629 .class_init = mch_class_init, 630 .interfaces = (InterfaceInfo[]) { 631 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 632 { }, 633 }, 634 }; 635 636 static void q35_register(void) 637 { 638 type_register_static(&mch_info); 639 type_register_static(&q35_host_info); 640 } 641 642 type_init(q35_register); 643